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Merge branch 'bugfix/sign_compare_warning_in_soc_component' into 'release/v4.1'

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fix sign compare warning in soc component

See merge request espressif/esp-idf!11434
This commit is contained in:
Angus Gratton
2021-02-09 11:05:12 +08:00
parent e508a64ae9 ec2817a285
commit 42b126e4dd
8 changed files with 12 additions and 12 deletions
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4
components/soc/esp32/emac_hal.c
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@@ -457,7 +457,7 @@ uint32_t emac_hal_transmit_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t
eth_dma_tx_descriptor_t *desc_iter = hal->tx_desc;
/* A frame is transmitted in multiple descriptor */
for (int i = 0; i < bufcount; i++) {
for (uint32_t i = 0; i < bufcount; i++) {
/* Check if the descriptor is owned by the Ethernet DMA (when 1) or CPU (when 0) */
if (desc_iter->TDES0.Own != EMAC_DMADESC_OWNER_CPU) {
goto err;
@@ -492,7 +492,7 @@ uint32_t emac_hal_transmit_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t
}
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
for (int i = 0; i < bufcount; i++) {
for (uint32_t i = 0; i < bufcount; i++) {
hal->tx_desc->TDES0.Own = EMAC_DMADESC_OWNER_DMA;
hal->tx_desc = (eth_dma_tx_descriptor_t *)(hal->tx_desc->Buffer2NextDescAddr);
}

2
components/soc/esp32/include/hal/spi_flash_ll.h
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@@ -141,7 +141,7 @@ static inline void spi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, ui
} else {
// Otherwise, slow(er) path copies word by word
int copy_len = read_len;
for (int i = 0; i < (read_len + 3) / 4; i++) {
for (uint32_t i = 0; i < (read_len + 3) / 4; i++) {
int word_len = MIN(sizeof(uint32_t), copy_len);
uint32_t word = dev->data_buf[i];
memcpy(buffer, &word, word_len);

4
components/soc/esp32/include/hal/spi_ll.h
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@@ -165,7 +165,7 @@ static inline void spi_ll_txdma_start(spi_dev_t *hw, lldesc_t *addr)
*/
static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_send, size_t bitlen)
{
for (int x = 0; x < bitlen; x += 32) {
for (size_t x = 0; x < bitlen; x += 32) {
//Use memcpy to get around alignment issues for txdata
uint32_t word;
memcpy(&word, &buffer_to_send[x / 8], 4);
@@ -182,7 +182,7 @@ static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_s
*/
static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, size_t bitlen)
{
for (int x = 0; x < bitlen; x += 32) {
for (size_t x = 0; x < bitlen; x += 32) {
//Do a memcpy to get around possible alignment issues in rx_buffer
uint32_t word = hw->data_buf[x / 32];
int len = bitlen - x;

4
components/soc/esp32/include/hal/uart_ll.h
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@@ -165,7 +165,7 @@ FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_
{
//Get the UART APB fifo addr. Read fifo, we use APB address
uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_REG(0) : (hw == &UART1) ? UART_FIFO_REG(1) : UART_FIFO_REG(2);
for(int i = 0; i < rd_len; i++) {
for(uint32_t i = 0; i < rd_len; i++) {
buf[i] = READ_PERI_REG(fifo_addr);
}
}
@@ -183,7 +183,7 @@ FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf,
{
//Get the UART AHB fifo addr, Write fifo, we use AHB address
uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_AHB_REG(0) : (hw == &UART1) ? UART_FIFO_AHB_REG(1) : UART_FIFO_AHB_REG(2);
for(int i = 0; i < wr_len; i++) {
for(uint32_t i = 0; i < wr_len; i++) {
WRITE_PERI_REG(fifo_addr, buf[i]);
}
}

2
components/soc/esp32/include/soc/cpu.h
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@@ -74,7 +74,7 @@ static inline void cpu_init_memctl(void)
static inline void cpu_configure_region_protection(void)
{
const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000};
for (int i = 0; i < sizeof(pages_to_protect)/sizeof(pages_to_protect[0]); ++i) {
for (size_t i = 0; i < sizeof(pages_to_protect)/sizeof(pages_to_protect[0]); ++i) {
cpu_write_dtlb(pages_to_protect[i], 0xf);
cpu_write_itlb(pages_to_protect[i], 0xf);
}

2
components/soc/esp32/rtc_clk.c
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@@ -106,7 +106,7 @@ static void rtc_clk_bbpll_enable(void);
static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz);
// Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled.
static int s_cur_pll_freq;
static size_t s_cur_pll_freq;
static const char* TAG = "rtc_clk";

4
components/soc/src/hal/adc_hal.c
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@@ -36,14 +36,14 @@ void adc_hal_dig_controller_config(const adc_hal_dig_config_t *cfg)
if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_1) {
adc_ll_set_controller(ADC_NUM_1, ADC_CTRL_DIG);
adc_ll_set_pattern_table_len(ADC_NUM_1, cfg->adc1_pattern_len);
for (int i = 0; i < cfg->adc1_pattern_len; i++) {
for (uint32_t i = 0; i < cfg->adc1_pattern_len; i++) {
adc_ll_set_pattern_table(ADC_NUM_1, i, cfg->adc1_pattern[i]);
}
}
if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_2) {
adc_ll_set_controller(ADC_NUM_2, ADC_CTRL_DIG);
adc_ll_set_pattern_table_len(ADC_NUM_2, cfg->adc2_pattern_len);
for (int i = 0; i < cfg->adc2_pattern_len; i++) {
for (uint32_t i = 0; i < cfg->adc2_pattern_len; i++) {
adc_ll_set_pattern_table(ADC_NUM_2, i, cfg->adc2_pattern[i]);
}
}

2
components/soc/src/hal/sdio_slave_hal.c
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@@ -127,7 +127,7 @@ static inline esp_err_t sdio_ringbuf_recv(sdio_ringbuf_t *buf, uint8_t **start,
static inline int sdio_ringbuf_return(sdio_ringbuf_t* buf, uint8_t *ptr)
{
assert(sdio_ringbuf_offset_ptr(buf, RINGBUF_FREE_PTR, SDIO_SLAVE_SEND_DESC_SIZE) == ptr);
int size = (buf->read_ptr + buf->size - buf->free_ptr) % buf->size;
size_t size = (buf->read_ptr + buf->size - buf->free_ptr) % buf->size;
int count = size / SDIO_SLAVE_SEND_DESC_SIZE;
assert(count * SDIO_SLAVE_SEND_DESC_SIZE==size);
buf->free_ptr = buf->read_ptr;