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fix(ble): fix rtc freq div error on esp32c61

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(cherry picked from commit b7571dd711)

Co-authored-by: cjin <jinchen@espressif.com>
This commit is contained in:
Jin Chen
2025-01-24 12:12:01 +08:00
parent 649f9a72ae
commit 4300c344ca
1 changed files with 4 additions and 0 deletions
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4
components/bt/controller/esp32c6/bt.c
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@ -522,12 +522,16 @@ void esp_bt_rtc_slow_clk_select(uint8_t slow_clk_src)
switch (slow_clk_src) {
case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using main XTAL as clock source");
#if SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND
uint32_t chip_version = efuse_hal_chip_revision();
if (chip_version == 0) {
modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (400 - 1));
} else{
modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (5 - 1));
}
#else
modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (400 - 1));
#endif // SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND
break;
case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using 136 kHz RC as clock source, can only run legacy ADV or SCAN due to low clock accuracy!");