Merge branch 'bugfix/update_esp32c2_soc_memory_addr' into 'master'

soc: update memory address for esp32c2

See merge request espressif/esp-idf!17085
This commit is contained in:
Jiang Guang Ming
2022-02-22 10:23:35 +00:00
3 changed files with 8 additions and 12 deletions

View File

@@ -159,13 +159,13 @@
/* Overall memory map */
#define SOC_DROM_LOW 0x3C000000
#define SOC_DROM_HIGH 0x3C800000
#define SOC_DROM_HIGH 0x3C400000
#define SOC_IROM_LOW 0x42000000
#define SOC_IROM_HIGH 0x42400000
#define SOC_IROM_MASK_LOW 0x40000000
#define SOC_IROM_MASK_HIGH 0x40060000
#define SOC_IROM_MASK_HIGH 0x40090000
#define SOC_DROM_MASK_LOW 0x3FF00000
#define SOC_DROM_MASK_HIGH 0x3FF20000
#define SOC_DROM_MASK_HIGH 0x3FF50000
#define SOC_IRAM_LOW 0x4037C000
#define SOC_IRAM_HIGH 0x403C0000
#define SOC_DRAM_LOW 0x3FCA0000

View File

@@ -1,21 +1,17 @@
# Data_type:
# copy from ESP32-C3
# primary_address: value
# length: value or equation
# secondary_address: value if exist
DRAM:
primary_address: 0x3FC80000
length: 0x60000
primary_address: 0x3FCA0000
length: 0x40000
secondary_address: 0x40380000
IRAM:
primary_address: 0x4037C000
length: 0x4000
CACHE_I:
primary_address: 0x42000000
length: 0x800000
length: 0x400000
CACHE_D:
primary_address: 0x3C000000
length: 0x800000
RTC_SLOW_D:
primary_address: 0x50000000
length: 0x2000
length: 0x400000