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Merge branch 'contrib/github_pr_10165' into 'master'

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Clarify GPIO Mask Comment (GitHub PR)

Closes IDFGH-8724

See merge request espressif/esp-idf!21068
This commit is contained in:
morris
2022-11-17 20:03:49 +08:00
parent 96585abb17 0c89ab3b58
commit 454fc4034c
3 changed files with 3 additions and 3 deletions
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2
components/soc/esp32/include/soc/soc_caps.h
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@@ -160,7 +160,7 @@
// set pullup/down/capability via RTC register. On ESP32-S2, Digital IOs have their own registers to
// control pullup/down/capability, independent with RTC registers.
// 0~39 except from 24, 28~31 are valid
// 0~39 valid except 24, 28~31
#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFULL & ~(0ULL | BIT24 | BIT28 | BIT29 | BIT30 | BIT31))
// GPIO >= 34 are input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT34 | BIT35 | BIT36 | BIT37 | BIT38 | BIT39))

2
components/soc/esp32s2/include/soc/soc_caps.h
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@@ -143,7 +143,7 @@
// Force hold is a new function of ESP32-S2
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// 0~46 except from 22~25 are valid
// 0~46 valid except 22~25
#define SOC_GPIO_VALID_GPIO_MASK (0x7FFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
// GPIO 46 is input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46))

2
components/soc/esp32s3/include/soc/soc_caps.h
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@@ -150,7 +150,7 @@
// Force hold is a new function of ESP32-S3
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// 0~48 except from 22~25 are valid
// 0~48 valid except 22~25
#define SOC_GPIO_VALID_GPIO_MASK (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
// No GPIO is input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK)