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refactor(ledc): remove deprecated LEDC_USE_RTC8M_CLK macro for v6.0

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This commit is contained in:
Song Ruo Jing
2025-07-29 21:43:42 +08:00
parent f61e780f60
commit 48233e0e7e
58 changed files with 492 additions and 506 deletions
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8
components/esp_hw_support/port/esp32/include/soc/rtc.h
View File

@@ -392,21 +392,21 @@ uint32_t rtc_clk_apb_freq_get(void);
* the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal.
*
* @param cali_clk_sel clock to be measured
* @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out
*/
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slow_clk_cycles);
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/**
* @brief Measure ratio between XTAL frequency and RTC slow clock frequency
* @param cali_clk_sel slow clock to be measured
* @param cal_clk_sel slow clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average ratio between XTAL frequency and slow clock frequency,
* Q13.19 fixed point format, or 0 if calibration has timed out.
*/
uint32_t rtc_clk_cal_ratio(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slow_clk_cycles);
uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

32
components/esp_hw_support/port/esp32/rtc_time.c
View File

@@ -30,38 +30,38 @@ static const char *TAG = "rtc_time";
/**
* @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
* @param cali_clk_sel which clock to calibrate
* @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count. Max value is 32766.
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
assert(slowclk_cycles < 32767);
/* Enable requested clock (rtc slow clock is always on) */
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable();
}
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled();
if (cali_clk_sel == CLK_CAL_RC_FAST_D256) {
if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
rtc_clk_8m_enable(true, true);
clk_ll_rc_fast_d256_digi_enable();
}
/* Prepare calibration */
clk_ll_calibration_set_target(cali_clk_sel);
clk_ll_freq_calulation_set_target(cal_clk_sel);
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
/* Figure out how long to wait for calibration to finish */
uint32_t expected_freq;
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (cali_clk_sel == CLK_CAL_32K_XTAL ||
(cali_clk_sel == CLK_CAL_RTC_SLOW && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K)) {
if (cal_clk_sel == CLK_CAL_32K_XTAL ||
(cal_clk_sel == CLK_CAL_RTC_SLOW && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K)) {
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; /* standard 32k XTAL */
} else if (cali_clk_sel == CLK_CAL_RC_FAST_D256 ||
(cali_clk_sel == CLK_CAL_RTC_SLOW && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256)) {
} else if (cal_clk_sel == CLK_CAL_RC_FAST_D256 ||
(cal_clk_sel == CLK_CAL_RTC_SLOW && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256)) {
expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX;
} else {
expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; /* 150k internal oscillator */
@@ -95,11 +95,11 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
}
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable();
}
if (cali_clk_sel == CLK_CAL_RC_FAST_D256) {
if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
clk_ll_rc_fast_d256_digi_disable();
rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled);
}
@@ -111,10 +111,10 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
return REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE);
}
uint32_t rtc_clk_cal_ratio(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
assert(slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cali_clk_sel, slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles;
uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX);
return ratio;
@@ -127,13 +127,13 @@ static inline bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cy
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
}
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cali_clk_sel, slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if ((cali_clk_sel == CLK_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
if ((cal_clk_sel == CLK_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0;
}

8
components/esp_hw_support/port/esp32c2/include/soc/rtc.h
View File

@@ -415,21 +415,21 @@ uint32_t rtc_clk_apb_freq_get(void);
* the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal.
*
* @param cali_clk_sel clock to be measured
* @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out
*/
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slow_clk_cycles);
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/**
* @brief Measure ratio between XTAL frequency and RTC slow clock frequency
* @param cali_clk_sel slow clock to be measured
* @param cal_clk_sel slow clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average ratio between XTAL frequency and slow clock frequency,
* Q13.19 fixed point format, or 0 if calibration has timed out.
*/
uint32_t rtc_clk_cal_ratio(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slow_clk_cycles);
uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

36
components/esp_hw_support/port/esp32c2/rtc_time.c
View File

@@ -29,32 +29,32 @@
/**
* @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
* @param cali_clk_sel which clock to calibrate
* @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
if (cali_clk_sel == CLK_CAL_RTC_SLOW) {
if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
cali_clk_sel = CLK_CAL_RC_SLOW;
cal_clk_sel = CLK_CAL_RC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
cali_clk_sel = CLK_CAL_32K_OSC_SLOW;
cal_clk_sel = CLK_CAL_32K_OSC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
cali_clk_sel = CLK_CAL_RC_FAST_D256;
cal_clk_sel = CLK_CAL_RC_FAST_D256;
}
}
/* Enable requested clock (150k clock is always on) */
bool dig_ext_clk_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_32K_OSC_SLOW && !dig_ext_clk_enabled) {
if (cal_clk_sel == CLK_CAL_32K_OSC_SLOW && !dig_ext_clk_enabled) {
clk_ll_xtal32k_digi_enable();
}
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled();
if (cali_clk_sel == CLK_CAL_RC_FAST_D256) {
if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
rtc_clk_8m_enable(true, true);
clk_ll_rc_fast_d256_digi_enable();
}
@@ -72,17 +72,17 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
}
/* Prepare calibration */
clk_ll_calibration_set_target(cali_clk_sel);
clk_ll_freq_calulation_set_target(cal_clk_sel);
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
/* Figure out how long to wait for calibration to finish */
/* Set timeout reg and expect time delay*/
uint32_t expected_freq;
if (cali_clk_sel == CLK_CAL_32K_OSC_SLOW) {
if (cal_clk_sel == CLK_CAL_32K_OSC_SLOW) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_OSC_SLOW_FREQ_APPROX;
} else if (cali_clk_sel == CLK_CAL_RC_FAST_D256) {
} else if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX;
} else {
@@ -110,11 +110,11 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
/* if dig_ext_clk was originally off and enabled due to calibration, then set back to off state */
if (cali_clk_sel == CLK_CAL_32K_OSC_SLOW && !dig_ext_clk_enabled) {
if (cal_clk_sel == CLK_CAL_32K_OSC_SLOW && !dig_ext_clk_enabled) {
clk_ll_xtal32k_digi_disable();
}
if (cali_clk_sel == CLK_CAL_RC_FAST_D256) {
if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
clk_ll_rc_fast_d256_digi_disable();
rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled);
}
@@ -122,10 +122,10 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
return cal_val;
}
uint32_t rtc_clk_cal_ratio(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
assert(slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cali_clk_sel, slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles;
uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX);
return ratio;
@@ -138,13 +138,13 @@ static inline bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cy
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
}
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cali_clk_sel, slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if ((cali_clk_sel == CLK_CAL_32K_OSC_SLOW) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
if ((cal_clk_sel == CLK_CAL_32K_OSC_SLOW) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0;
}

8
components/esp_hw_support/port/esp32c3/include/soc/rtc.h
View File

@@ -445,21 +445,21 @@ uint32_t rtc_clk_apb_freq_get(void);
* the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal.
*
* @param cali_clk_sel clock to be measured
* @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out
*/
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slow_clk_cycles);
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/**
* @brief Measure ratio between XTAL frequency and RTC slow clock frequency
* @param cali_clk_sel slow clock to be measured
* @param cal_clk_sel slow clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average ratio between XTAL frequency and slow clock frequency,
* Q13.19 fixed point format, or 0 if calibration has timed out.
*/
uint32_t rtc_clk_cal_ratio(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slow_clk_cycles);
uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

36
components/esp_hw_support/port/esp32c3/rtc_time.c
View File

@@ -29,32 +29,32 @@
/**
* @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
* @param cali_clk_sel which clock to calibrate
* @param cal_clk_sel which clock to calibrate
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
if (cali_clk_sel == CLK_CAL_RTC_SLOW) {
if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
cali_clk_sel = CLK_CAL_RC_SLOW;
cal_clk_sel = CLK_CAL_RC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cali_clk_sel = CLK_CAL_32K_XTAL;
cal_clk_sel = CLK_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
cali_clk_sel = CLK_CAL_RC_FAST_D256;
cal_clk_sel = CLK_CAL_RC_FAST_D256;
}
}
/* Enable requested clock (150k clock is always on) */
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable();
}
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled();
if (cali_clk_sel == CLK_CAL_RC_FAST_D256) {
if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
rtc_clk_8m_enable(true, true);
clk_ll_rc_fast_d256_digi_enable();
}
@@ -72,17 +72,17 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
}
/* Prepare calibration */
clk_ll_calibration_set_target(cali_clk_sel);
clk_ll_freq_calulation_set_target(cal_clk_sel);
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
/* Figure out how long to wait for calibration to finish */
/* Set timeout reg and expect time delay*/
uint32_t expected_freq;
if (cali_clk_sel == CLK_CAL_32K_XTAL) {
if (cal_clk_sel == CLK_CAL_32K_XTAL) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
} else if (cali_clk_sel == CLK_CAL_RC_FAST_D256) {
} else if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX;
} else {
@@ -110,11 +110,11 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable();
}
if (cali_clk_sel == CLK_CAL_RC_FAST_D256) {
if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
clk_ll_rc_fast_d256_digi_disable();
rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled);
}
@@ -122,10 +122,10 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
return cal_val;
}
uint32_t rtc_clk_cal_ratio(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
assert(slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cali_clk_sel, slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles;
uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX);
return ratio;
@@ -138,13 +138,13 @@ static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, u
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
}
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cali_clk_sel, slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if ((cali_clk_sel == CLK_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
if ((cal_clk_sel == CLK_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0;
}

4
components/esp_hw_support/port/esp32c5/include/soc/rtc.h
View File

@@ -344,12 +344,12 @@ uint32_t rtc_clk_apb_freq_get(void);
* the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal.
*
* @param cali_clk_sel clock to be measured
* @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out
*/
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slow_clk_cycles);
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

46
components/esp_hw_support/port/esp32c5/rtc_time.c
View File

@@ -19,31 +19,31 @@
__attribute__((unused)) static const char *TAG = "rtc_time";
#define CLK_CAL_TIMEOUT_THRES(cali_clk_sel, cycles) ((cali_clk_sel == CLK_CAL_32K_XTAL || cali_clk_sel == CLK_CAL_32K_OSC_SLOW) ? (cycles << 12) : (cycles << 10))
#define CLK_CAL_TIMEOUT_THRES(cal_clk_sel, cycles) ((cal_clk_sel == CLK_CAL_32K_XTAL || cal_clk_sel == CLK_CAL_32K_OSC_SLOW) ? (cycles << 12) : (cycles << 10))
/**
* @brief Clock calibration function used by rtc_clk_cal
* @brief Clock frequency calculation function used by rtc_clk_cal
*
* Calibration of clock frequency is performed using a special feature of TIMG0.
* Calculation of clock frequency is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* clock cycles.
*
* @param cali_clk_sel which clock to calibrate
* @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V);
if (cali_clk_sel == CLK_CAL_RTC_SLOW) {
if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
cali_clk_sel = CLK_CAL_RC_SLOW;
cal_clk_sel = CLK_CAL_RC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cali_clk_sel = CLK_CAL_32K_XTAL;
cal_clk_sel = CLK_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
cali_clk_sel = CLK_CAL_32K_OSC_SLOW;
cal_clk_sel = CLK_CAL_32K_OSC_SLOW;
}
}
@@ -52,13 +52,13 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
// Only enable if originally was disabled, and set back to the disable state after calibration is done
// If the clock is already on, then do nothing
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable();
}
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!rc_fast_enabled) {
rtc_clk_8m_enable(true);
}
@@ -81,8 +81,8 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
}
/* Prepare calibration */
clk_ll_calibration_set_target(cali_clk_sel);
if (cali_clk_sel == CLK_CAL_RC_FAST) {
clk_ll_freq_calulation_set_target(cal_clk_sel);
if (cal_clk_sel == CLK_CAL_RC_FAST) {
clk_ll_rc_fast_tick_conf();
}
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
@@ -90,11 +90,11 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
/* Figure out how long to wait for calibration to finish */
/* Set timeout reg and expect time delay*/
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, CLK_CAL_TIMEOUT_THRES(cali_clk_sel, slowclk_cycles));
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, CLK_CAL_TIMEOUT_THRES(cal_clk_sel, slowclk_cycles));
uint32_t expected_freq;
if (cali_clk_sel == CLK_CAL_32K_XTAL || cali_clk_sel == CLK_CAL_32K_OSC_SLOW) {
if (cal_clk_sel == CLK_CAL_32K_XTAL || cal_clk_sel == CLK_CAL_32K_OSC_SLOW) {
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
} else if (cali_clk_sel == CLK_CAL_RC_FAST) {
} else if (cal_clk_sel == CLK_CAL_RC_FAST) {
expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
} else {
expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX;
@@ -113,7 +113,7 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
/*The Fosc CLK of calibration circuit is divided by a factor, k.
So we need to multiply the frequency of the FOSC by k times.*/
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
}
break;
@@ -127,11 +127,11 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
clk_ll_enable_timergroup_rtc_calibration_clock(false);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable();
}
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!dig_rc_fast_enabled) {
rtc_dig_clk8m_disable();
}
@@ -150,19 +150,19 @@ static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, u
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
}
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
/*The Fosc CLK of calibration circuit is divided by a factor, k.
So we need to divide the calibrate cycles of the FOSC by k to
avoid excessive calibration time.*/
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
}
assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cali_clk_sel, slowclk_cycles);
if (cali_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if (cal_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0;
}

4
components/esp_hw_support/port/esp32c6/include/soc/rtc.h
View File

@@ -371,12 +371,12 @@ uint32_t rtc_clk_apb_freq_get(void);
* the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal.
*
* @param cali_clk_sel clock to be measured
* @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out
*/
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slow_clk_cycles);
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

48
components/esp_hw_support/port/esp32c6/rtc_time.c
View File

@@ -21,9 +21,9 @@
__attribute__((unused)) static const char *TAG = "rtc_time";
/**
* @brief Clock calibration function used by rtc_clk_cal
* @brief Clock frequency calculation function used by rtc_clk_cal
*
* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* Calculation of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* RTC_SLOW_CLK cycles.
*
@@ -34,24 +34,24 @@ __attribute__((unused)) static const char *TAG = "rtc_time";
* once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
* enabled using TIMG_RTC_CALI_START bit.
*
* @param cali_clk_sel which clock to calibrate
* @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V);
if (cali_clk_sel == CLK_CAL_RTC_SLOW) {
if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
cali_clk_sel = CLK_CAL_RC_SLOW;
cal_clk_sel = CLK_CAL_RC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
cali_clk_sel = CLK_CAL_32K_OSC_SLOW;
cal_clk_sel = CLK_CAL_32K_OSC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cali_clk_sel = CLK_CAL_32K_XTAL;
cal_clk_sel = CLK_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
cali_clk_sel = CLK_CAL_RC32K;
cal_clk_sel = CLK_CAL_RC32K;
}
}
@@ -60,13 +60,13 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
// Only enable if originally was disabled, and set back to the disable state after calibration is done
// If the clock is already on, then do nothing
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable();
}
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!rc_fast_enabled) {
rtc_clk_8m_enable(true);
}
@@ -77,7 +77,7 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
bool rc32k_enabled = clk_ll_rc32k_is_enabled();
bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_RC32K) {
if (cal_clk_sel == CLK_CAL_RC32K) {
if (!rc32k_enabled) {
rtc_clk_rc32k_enable(true);
}
@@ -100,8 +100,8 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
}
/* Prepare calibration */
clk_ll_calibration_set_target(cali_clk_sel);
if (cali_clk_sel == CLK_CAL_RC_FAST) {
clk_ll_freq_calulation_set_target(cal_clk_sel);
if (cal_clk_sel == CLK_CAL_RC_FAST) {
clk_ll_rc_fast_tick_conf();
}
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
@@ -110,10 +110,10 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
/* Set timeout reg and expect time delay*/
uint32_t expected_freq;
if (cali_clk_sel == CLK_CAL_32K_XTAL || cali_clk_sel == CLK_CAL_32K_OSC_SLOW || cali_clk_sel == CLK_CAL_RC32K) {
if (cal_clk_sel == CLK_CAL_32K_XTAL || cal_clk_sel == CLK_CAL_32K_OSC_SLOW || cal_clk_sel == CLK_CAL_RC32K) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
} else if (cali_clk_sel == CLK_CAL_RC_FAST) {
} else if (cal_clk_sel == CLK_CAL_RC_FAST) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX;
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
@@ -141,7 +141,7 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
And the 32-divider belongs to REF_TICK module, so we need to enable its clock during
calibration. */
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
CLEAR_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
}
@@ -156,11 +156,11 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable();
}
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!dig_rc_fast_enabled) {
rtc_dig_clk8m_disable();
}
@@ -169,7 +169,7 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
}
}
if (cali_clk_sel == CLK_CAL_RC32K) {
if (cal_clk_sel == CLK_CAL_RC32K) {
if (!dig_rc32k_enabled) {
clk_ll_rc32k_digi_disable();
}
@@ -188,7 +188,7 @@ static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, u
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
}
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
@@ -197,15 +197,15 @@ uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slow
So we need to divide the calibrate cycles of the FOSC for ECO1 and above chips by 32 to
avoid excessive calibration time.*/
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
SET_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
}
}
uint64_t xtal_cycles = rtc_clk_cal_internal(cali_clk_sel, slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if (cali_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0;
}

4
components/esp_hw_support/port/esp32c61/include/soc/rtc.h
View File

@@ -342,12 +342,12 @@ uint32_t rtc_clk_apb_freq_get(void);
* the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal.
*
* @param cali_clk_sel clock to be measured
* @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out
*/
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slow_clk_cycles);
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

46
components/esp_hw_support/port/esp32c61/rtc_time.c
View File

@@ -18,31 +18,31 @@
__attribute__((unused)) static const char *TAG = "rtc_time";
#define CLK_CAL_TIMEOUT_THRES(cali_clk_sel, cycles) ((cali_clk_sel == CLK_CAL_32K_XTAL || cali_clk_sel == CLK_CAL_32K_OSC_SLOW) ? (cycles << 12) : (cycles << 10))
#define CLK_CAL_TIMEOUT_THRES(cal_clk_sel, cycles) ((cal_clk_sel == CLK_CAL_32K_XTAL || cal_clk_sel == CLK_CAL_32K_OSC_SLOW) ? (cycles << 12) : (cycles << 10))
/**
* @brief Clock calibration function used by rtc_clk_cal
* @brief Clock frequency calculation function used by rtc_clk_cal
*
* Calibration of clock frequency is performed using a special feature of TIMG0.
* Calculation of clock frequency is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* clock cycles.
*
* @param cali_clk_sel which clock to calibrate
* @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V);
if (cali_clk_sel == CLK_CAL_RTC_SLOW) {
if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
cali_clk_sel = CLK_CAL_RC_SLOW;
cal_clk_sel = CLK_CAL_RC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cali_clk_sel = CLK_CAL_32K_XTAL;
cal_clk_sel = CLK_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
cali_clk_sel = CLK_CAL_32K_OSC_SLOW;
cal_clk_sel = CLK_CAL_32K_OSC_SLOW;
}
}
@@ -51,13 +51,13 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
// Only enable if originally was disabled, and set back to the disable state after calibration is done
// If the clock is already on, then do nothing
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable();
}
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!rc_fast_enabled) {
rtc_clk_8m_enable(true);
}
@@ -80,8 +80,8 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
}
/* Prepare calibration */
clk_ll_calibration_set_target(cali_clk_sel);
if (cali_clk_sel == CLK_CAL_RC_FAST) {
clk_ll_freq_calulation_set_target(cal_clk_sel);
if (cal_clk_sel == CLK_CAL_RC_FAST) {
clk_ll_rc_fast_tick_conf();
}
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
@@ -89,11 +89,11 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
/* Figure out how long to wait for calibration to finish */
/* Set timeout reg and expect time delay*/
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, CLK_CAL_TIMEOUT_THRES(cali_clk_sel, slowclk_cycles));
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, CLK_CAL_TIMEOUT_THRES(cal_clk_sel, slowclk_cycles));
uint32_t expected_freq;
if (cali_clk_sel == CLK_CAL_32K_XTAL || cali_clk_sel == CLK_CAL_32K_OSC_SLOW) {
if (cal_clk_sel == CLK_CAL_32K_XTAL || cal_clk_sel == CLK_CAL_32K_OSC_SLOW) {
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
} else if (cali_clk_sel == CLK_CAL_RC_FAST) {
} else if (cal_clk_sel == CLK_CAL_RC_FAST) {
expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
} else {
expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX;
@@ -112,7 +112,7 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
/*The Fosc CLK of calibration circuit is divided by a factor, k.
So we need to multiply the frequency of the FOSC by k times.*/
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
}
break;
@@ -125,11 +125,11 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable();
}
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!dig_rc_fast_enabled) {
rtc_dig_clk8m_disable();
}
@@ -148,20 +148,20 @@ static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, u
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
}
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
/*The Fosc CLK of calibration circuit is divided by a factor, k.
So we need to divide the calibrate cycles of the FOSC by k to
avoid excessive calibration time.*/
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
}
assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cali_clk_sel, slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if (cali_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0;
}

4
components/esp_hw_support/port/esp32h2/include/soc/rtc.h
View File

@@ -370,12 +370,12 @@ uint32_t rtc_clk_apb_freq_get(void);
* 32k XTAL is being calibrated, but the oscillator has not started up (due to
* incorrect loading capacitance, board design issue, or lack of 32 XTAL on board).
*
* @param cali_clk_sel clock to be measured
* @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out
*/
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slow_clk_cycles);
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

48
components/esp_hw_support/port/esp32h2/rtc_time.c
View File

@@ -21,9 +21,9 @@
__attribute__((unused)) static const char *TAG = "rtc_time";
/**
* @brief Clock calibration function used by rtc_clk_cal
* @brief Clock frequency calculation function used by rtc_clk_cal
*
* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* Calculation of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* RTC_SLOW_CLK cycles.
*
@@ -34,24 +34,24 @@ __attribute__((unused)) static const char *TAG = "rtc_time";
* once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
* enabled using TIMG_RTC_CALI_START bit.
*
* @param cali_clk_sel which clock to calibrate
* @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V);
if (cali_clk_sel == CLK_CAL_RTC_SLOW) {
if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
cali_clk_sel = CLK_CAL_RC_SLOW;
cal_clk_sel = CLK_CAL_RC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
cali_clk_sel = CLK_CAL_32K_OSC_SLOW;
cal_clk_sel = CLK_CAL_32K_OSC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cali_clk_sel = CLK_CAL_32K_XTAL;
cal_clk_sel = CLK_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
cali_clk_sel = CLK_CAL_RC32K;
cal_clk_sel = CLK_CAL_RC32K;
}
}
@@ -60,13 +60,13 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
// Only enable if originally was disabled, and set back to the disable state after calibration is done
// If the clock is already on, then do nothing
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable();
}
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!rc_fast_enabled) {
rtc_clk_8m_enable(true);
}
@@ -77,7 +77,7 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
bool rc32k_enabled = clk_ll_rc32k_is_enabled();
bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_RC32K) {
if (cal_clk_sel == CLK_CAL_RC32K) {
if (!rc32k_enabled) {
rtc_clk_rc32k_enable(true);
}
@@ -100,8 +100,8 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
}
/* Prepare calibration */
clk_ll_calibration_set_target(cali_clk_sel);
if (cali_clk_sel == CLK_CAL_RC_FAST) {
clk_ll_freq_calulation_set_target(cal_clk_sel);
if (cal_clk_sel == CLK_CAL_RC_FAST) {
clk_ll_rc_fast_tick_conf();
}
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
@@ -110,10 +110,10 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
/* Set timeout reg and expect time delay*/
uint32_t expected_freq;
if (cali_clk_sel == CLK_CAL_32K_XTAL || cali_clk_sel == CLK_CAL_32K_OSC_SLOW || cali_clk_sel == CLK_CAL_RC32K) {
if (cal_clk_sel == CLK_CAL_32K_XTAL || cal_clk_sel == CLK_CAL_32K_OSC_SLOW || cal_clk_sel == CLK_CAL_RC32K) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
} else if (cali_clk_sel == CLK_CAL_RC_FAST) {
} else if (cal_clk_sel == CLK_CAL_RC_FAST) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_8M_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX;
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) {
@@ -141,7 +141,7 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
And the 32-divider belongs to REF_TICK module, so we need to enable its clock during
calibration. */
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) {
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
CLEAR_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
}
@@ -156,11 +156,11 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable();
}
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!dig_rc_fast_enabled) {
rtc_dig_clk8m_disable();
}
@@ -169,7 +169,7 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
}
}
if (cali_clk_sel == CLK_CAL_RC32K) {
if (cal_clk_sel == CLK_CAL_RC32K) {
if (!dig_rc32k_enabled) {
clk_ll_rc32k_digi_disable();
}
@@ -188,7 +188,7 @@ static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, u
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
}
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
@@ -197,15 +197,15 @@ uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slow
So we need to divide the calibrate cycles of the FOSC for ECO1 and above chips by 32 to
avoid excessive calibration time.*/
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) {
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
SET_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
}
}
uint64_t xtal_cycles = rtc_clk_cal_internal(cali_clk_sel, slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if (cali_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0;
}

4
components/esp_hw_support/port/esp32h21/include/soc/rtc.h
View File

@@ -314,12 +314,12 @@ uint32_t rtc_clk_apb_freq_get(void);
* the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal.
*
* @param cali_clk_sel clock to be measured
* @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out
*/
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slow_clk_cycles);
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

48
components/esp_hw_support/port/esp32h21/rtc_time.c
View File

@@ -23,33 +23,33 @@ __attribute__((unused)) static const char *TAG = "rtc_time";
#define RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(cycles) (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value
/**
* @brief Clock calibration function used by rtc_clk_cal
* @brief Clock frequency calculation function used by rtc_clk_cal
*
* Calibration of clock frequency is performed using a special feature of TIMG0.
* Calculation of clock frequency is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* clock cycles.
*
* @param cali_clk_sel which clock to calibrate
* @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V);
bool is_cali_clk_rtc_slow = false;
bool is_cal_clk_rtc_slow = false;
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (cali_clk_sel == CLK_CAL_RTC_SLOW) {
is_cali_clk_rtc_slow = true;
if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
is_cal_clk_rtc_slow = true;
switch (slow_clk_src) {
case SOC_RTC_SLOW_CLK_SRC_RC_SLOW_D4:
cali_clk_sel = CLK_CAL_RC_SLOW;
cal_clk_sel = CLK_CAL_RC_SLOW;
break;
case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
cali_clk_sel = CLK_CAL_32K_XTAL;
cal_clk_sel = CLK_CAL_32K_XTAL;
break;
case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW:
cali_clk_sel = CLK_CAL_32K_OSC_SLOW;
cal_clk_sel = CLK_CAL_32K_OSC_SLOW;
break;
default:
ESP_EARLY_LOGE(TAG, "clock not supported to be calibrated");
@@ -62,13 +62,13 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
// Only enable if originally was disabled, and set back to the disable state after calibration is done
// If the clock is already on, then do nothing
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable();
}
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!rc_fast_enabled) {
rtc_clk_8m_enable(true);
}
@@ -91,8 +91,8 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
}
/* Prepare calibration */
clk_ll_calibration_set_target(cali_clk_sel);
if (cali_clk_sel == CLK_CAL_RC_FAST) {
clk_ll_freq_calulation_set_target(cal_clk_sel);
if (cal_clk_sel == CLK_CAL_RC_FAST) {
clk_ll_rc_fast_tick_conf();
}
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
@@ -101,10 +101,10 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
/* Set timeout reg and expect time delay*/
uint32_t expected_freq;
if (cali_clk_sel == CLK_CAL_32K_XTAL || cali_clk_sel == CLK_CAL_32K_OSC_SLOW) {
if (cal_clk_sel == CLK_CAL_32K_XTAL || cal_clk_sel == CLK_CAL_32K_OSC_SLOW) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
} else if (cali_clk_sel == CLK_CAL_RC_FAST) {
} else if (cal_clk_sel == CLK_CAL_RC_FAST) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
} else {
@@ -125,7 +125,7 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
/* The Fosc CLK of calibration circuit is divided by a factor, k.
So we need to multiply the frequency of the FOSC by k times. */
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
cal_val = cal_val >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
}
break;
@@ -138,11 +138,11 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable();
}
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!dig_rc_fast_enabled) {
rtc_dig_clk8m_disable();
}
@@ -151,7 +151,7 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
}
}
if (is_cali_clk_rtc_slow && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW_D4) {
if (is_cal_clk_rtc_slow && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW_D4) {
// calibration was done on RC_SLOW clock, but rtc_slow_clk src is RC_SLOW_D4, so we need to multiply the cal_val by 4
cal_val *= 4;
}
@@ -166,20 +166,20 @@ static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, u
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
}
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
/* The Fosc CLK of calibration circuit is divided by a factor, k.
So we need to divide the calibrate cycles of the FOSC by k to
avoid excessive calibration time. */
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
slowclk_cycles = slowclk_cycles >> CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS;
}
assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cali_clk_sel, slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if (cali_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0;
}

4
components/esp_hw_support/port/esp32h4/include/soc/rtc.h
View File

@@ -327,12 +327,12 @@ uint32_t rtc_clk_apb_freq_get(void);
* the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal.
*
* @param cali_clk_sel clock to be measured
* @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out
*/
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slow_clk_cycles);
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

56
components/esp_hw_support/port/esp32h4/rtc_time.c
View File

@@ -23,37 +23,37 @@ static const char *TAG = "rtc_time";
// Calibration can only be performed on relatively slow speed clock signal. Therefore, for high-speed clocks,
// calibration is performed on their DIV_CLKs. The divider is configurable. We set:
#define CLK_CAL_DIV_VAL(cali_clk_sel) \
((cali_clk_sel == CLK_CAL_RC_FAST) ? 32 : 1)
#define CLK_CAL_DIV_VAL(cal_clk_sel) \
((cal_clk_sel == CLK_CAL_RC_FAST) ? 32 : 1)
/**
* @brief Clock calibration function used by rtc_clk_cal
* @brief Clock frequency calculation function used by rtc_clk_cal
*
* Calibration of clock frequency is performed using a special feature of TIMG0.
* Calculation of clock frequency is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* clock cycles.
*
* @param cali_clk_sel which clock to calibrate
* @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V);
bool is_cali_clk_rtc_slow = false;
bool is_cal_clk_rtc_slow = false;
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (cali_clk_sel == CLK_CAL_RTC_SLOW) {
is_cali_clk_rtc_slow = true;
if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
is_cal_clk_rtc_slow = true;
switch (slow_clk_src) {
case SOC_RTC_SLOW_CLK_SRC_RC_SLOW_D4:
cali_clk_sel = CLK_CAL_RC_SLOW;
cal_clk_sel = CLK_CAL_RC_SLOW;
break;
case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
cali_clk_sel = CLK_CAL_32K_XTAL;
cal_clk_sel = CLK_CAL_32K_XTAL;
break;
case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW:
cali_clk_sel = CLK_CAL_32K_OSC_SLOW;
cal_clk_sel = CLK_CAL_32K_OSC_SLOW;
break;
default:
ESP_EARLY_LOGE(TAG, "clock not supported to be calibrated");
@@ -61,7 +61,7 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
}
}
if (cali_clk_sel != CLK_CAL_RC_SLOW && cali_clk_sel != CLK_CAL_32K_XTAL && cali_clk_sel != CLK_CAL_32K_OSC_SLOW && cali_clk_sel != CLK_CAL_RC_FAST) {
if (cal_clk_sel != CLK_CAL_RC_SLOW && cal_clk_sel != CLK_CAL_32K_XTAL && cal_clk_sel != CLK_CAL_32K_OSC_SLOW && cal_clk_sel != CLK_CAL_RC_FAST) {
ESP_EARLY_LOGE(TAG, "calibration not yet supported for this clock");
return 0;
}
@@ -71,13 +71,13 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
// Only enable if originally was disabled, and set back to the disable state after calibration is done
// If the clock is already on, then do nothing
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable();
}
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!rc_fast_enabled) {
rtc_clk_8m_enable(true);
}
@@ -100,19 +100,19 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
}
/* Prepare calibration */
clk_ll_calibration_set_target(cali_clk_sel);
uint32_t clk_cal_divider = CLK_CAL_DIV_VAL(cali_clk_sel);
clk_ll_calibration_set_divider(clk_cal_divider);
clk_ll_freq_calulation_set_target(cal_clk_sel);
uint32_t clk_cal_divider = CLK_CAL_DIV_VAL(cal_clk_sel);
clk_ll_freq_calculation_set_divider(clk_cal_divider);
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
/* Figure out how long to wait for calibration to finish */
/* Set timeout reg and expect time delay*/
uint32_t expected_freq;
if (cali_clk_sel == CLK_CAL_32K_XTAL || cali_clk_sel == CLK_CAL_32K_OSC_SLOW) {
if (cal_clk_sel == CLK_CAL_32K_XTAL || cal_clk_sel == CLK_CAL_32K_OSC_SLOW) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
} else if (cali_clk_sel == CLK_CAL_RC_FAST) {
} else if (cal_clk_sel == CLK_CAL_RC_FAST) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX;
} else {
@@ -140,14 +140,14 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
}
}
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
clk_ll_calibration_set_divider(1);
clk_ll_freq_calculation_set_divider(1);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable();
}
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!dig_rc_fast_enabled) {
rtc_dig_clk8m_disable();
}
@@ -156,7 +156,7 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
}
}
if (is_cali_clk_rtc_slow && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW_D4) {
if (is_cal_clk_rtc_slow && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW_D4) {
// calibration was done on RC_SLOW clock, but rtc_slow_clk src is RC_SLOW_D4, so we need to multiply the cal_val by 4
cal_val *= 4;
}
@@ -171,14 +171,14 @@ static bool rtc_clk_cal_32k_valid(soc_xtal_freq_t xtal_freq, uint32_t slowclk_cy
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
}
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
slowclk_cycles /= (cali_clk_sel == CLK_CAL_RTC_SLOW) ? 1 : CLK_CAL_DIV_VAL(cali_clk_sel);
slowclk_cycles /= (cal_clk_sel == CLK_CAL_RTC_SLOW) ? 1 : CLK_CAL_DIV_VAL(cal_clk_sel);
assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cali_clk_sel, slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if (cali_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0;
}

4
components/esp_hw_support/port/esp32p4/include/soc/rtc.h
View File

@@ -396,12 +396,12 @@ uint32_t rtc_clk_apb_freq_get(void);
* the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal.
*
* @param cali_clk_sel clock to be measured
* @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out
*/
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slow_clk_cycles);
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

86
components/esp_hw_support/port/esp32p4/rtc_time.c
View File

@@ -18,54 +18,54 @@
__attribute__((unused)) static const char *TAG = "rtc_time";
#define CLK_CAL_TIMEOUT_THRES(cali_clk_sel, cycles) ((cali_clk_sel == CLK_CAL_RC32K || cali_clk_sel == CLK_CAL_32K_XTAL) ? (cycles << 12) : (cycles << 10))
#define CLK_CAL_TIMEOUT_THRES(cal_clk_sel, cycles) ((cal_clk_sel == CLK_CAL_RC32K || cal_clk_sel == CLK_CAL_32K_XTAL) ? (cycles << 12) : (cycles << 10))
// Calibration can only be performed on relatively slow speed clock signal. Therefore, for high-speed clocks,
// calibration is performed on their DIV_CLKs. The divider is configurable. We set:
#define CLK_CAL_DIV_VAL(cali_clk_sel) \
((cali_clk_sel == CLK_CAL_RC_SLOW || cali_clk_sel == CLK_CAL_RC32K || cali_clk_sel == CLK_CAL_32K_XTAL) ? 1 : \
(cali_clk_sel == CLK_CAL_LP_PLL) ? 25 : \
(cali_clk_sel == CLK_CAL_RC_FAST) ? 50 : \
(cali_clk_sel == CLK_CAL_APLL) ? 200 : \
// Calculation can only be performed on relatively slow speed clock signal. Therefore, for high-speed clocks,
// calculation is performed on their DIV_CLKs. The divider is configurable. We set:
#define CLK_CAL_DIV_VAL(cal_clk_sel) \
((cal_clk_sel == CLK_CAL_RC_SLOW || cal_clk_sel == CLK_CAL_RC32K || cal_clk_sel == CLK_CAL_32K_XTAL) ? 1 : \
(cal_clk_sel == CLK_CAL_LP_PLL) ? 25 : \
(cal_clk_sel == CLK_CAL_RC_FAST) ? 50 : \
(cal_clk_sel == CLK_CAL_APLL) ? 200 : \
4000)
// CLK_CAL_FREQ_APPROX = CLK_FREQ_APPROX / CLK_CAL_DIV_VAL
#define CLK_CAL_FREQ_APPROX(cali_clk_sel) \
((cali_clk_sel == CLK_CAL_MPLL) ? (CLK_LL_PLL_500M_FREQ_MHZ * MHZ / 4000) : \
(cali_clk_sel == CLK_CAL_SPLL) ? (CLK_LL_PLL_480M_FREQ_MHZ * MHZ / 4000) : \
(cali_clk_sel == CLK_CAL_CPLL) ? (CLK_LL_PLL_400M_FREQ_MHZ * MHZ / 4000) : \
(cali_clk_sel == CLK_CAL_APLL) ? (105 * MHZ / 200) : \
(cali_clk_sel == CLK_CAL_SDIO_PLL0 || cali_clk_sel == CLK_CAL_SDIO_PLL1 || cali_clk_sel == CLK_CAL_SDIO_PLL2) ? (200 * MHZ / 4000) : \
(cali_clk_sel == CLK_CAL_RC_FAST) ? (SOC_CLK_RC_FAST_FREQ_APPROX / 50) : \
(cali_clk_sel == CLK_CAL_RC_SLOW) ? (SOC_CLK_RC_SLOW_FREQ_APPROX) : \
(cali_clk_sel == CLK_CAL_RC32K) ? (SOC_CLK_RC32K_FREQ_APPROX) : \
(cali_clk_sel == CLK_CAL_32K_XTAL) ? (SOC_CLK_XTAL32K_FREQ_APPROX) : \
(cali_clk_sel == CLK_CAL_LP_PLL) ? (CLK_LL_PLL_8M_FREQ_MHZ * MHZ / 25) : \
#define CLK_CAL_FREQ_APPROX(cal_clk_sel) \
((cal_clk_sel == CLK_CAL_MPLL) ? (CLK_LL_PLL_500M_FREQ_MHZ * MHZ / 4000) : \
(cal_clk_sel == CLK_CAL_SPLL) ? (CLK_LL_PLL_480M_FREQ_MHZ * MHZ / 4000) : \
(cal_clk_sel == CLK_CAL_CPLL) ? (CLK_LL_PLL_400M_FREQ_MHZ * MHZ / 4000) : \
(cal_clk_sel == CLK_CAL_APLL) ? (105 * MHZ / 200) : \
(cal_clk_sel == CLK_CAL_SDIO_PLL0 || cal_clk_sel == CLK_CAL_SDIO_PLL1 || cal_clk_sel == CLK_CAL_SDIO_PLL2) ? (200 * MHZ / 4000) : \
(cal_clk_sel == CLK_CAL_RC_FAST) ? (SOC_CLK_RC_FAST_FREQ_APPROX / 50) : \
(cal_clk_sel == CLK_CAL_RC_SLOW) ? (SOC_CLK_RC_SLOW_FREQ_APPROX) : \
(cal_clk_sel == CLK_CAL_RC32K) ? (SOC_CLK_RC32K_FREQ_APPROX) : \
(cal_clk_sel == CLK_CAL_32K_XTAL) ? (SOC_CLK_XTAL32K_FREQ_APPROX) : \
(cal_clk_sel == CLK_CAL_LP_PLL) ? (CLK_LL_PLL_8M_FREQ_MHZ * MHZ / 25) : \
0)
/**
* @brief Clock calibration function used by rtc_clk_cal
* @brief Clock frequency calculation function used by rtc_clk_cal
*
* Calibration of clock frequency is performed using a special feature of TIMG0.
* Calculation of clock frequency is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* clock cycles.
*
* @param cali_clk_sel which clock to calibrate
* @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V);
if (cali_clk_sel == CLK_CAL_RTC_SLOW) {
if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
cali_clk_sel = CLK_CAL_RC_SLOW;
cal_clk_sel = CLK_CAL_RC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cali_clk_sel = CLK_CAL_32K_XTAL;
cal_clk_sel = CLK_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
cali_clk_sel = CLK_CAL_RC32K;
cal_clk_sel = CLK_CAL_RC32K;
}
}
@@ -74,13 +74,13 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
// Only enable if originally was disabled, and set back to the disable state after calibration is done
// If the clock is already on, then do nothing
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable();
}
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!rc_fast_enabled) {
rtc_clk_8m_enable(true);
}
@@ -91,7 +91,7 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
bool rc32k_enabled = clk_ll_rc32k_is_enabled();
bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_RC32K) {
if (cal_clk_sel == CLK_CAL_RC32K) {
if (!rc32k_enabled) {
rtc_clk_rc32k_enable(true);
}
@@ -114,16 +114,16 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
}
/* Prepare calibration */
clk_ll_calibration_set_target(cali_clk_sel);
uint32_t clk_cal_divider = CLK_CAL_DIV_VAL(cali_clk_sel);
clk_ll_calibration_set_divider(clk_cal_divider);
clk_ll_freq_calulation_set_target(cal_clk_sel);
uint32_t clk_cal_divider = CLK_CAL_DIV_VAL(cal_clk_sel);
clk_ll_freq_calculation_set_divider(clk_cal_divider);
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
/* Figure out how long to wait for calibration to finish */
/* Set timeout reg and expect time delay*/
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, CLK_CAL_TIMEOUT_THRES(cali_clk_sel, slowclk_cycles));
uint32_t expected_freq = CLK_CAL_FREQ_APPROX(cali_clk_sel);
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, CLK_CAL_TIMEOUT_THRES(cal_clk_sel, slowclk_cycles));
uint32_t expected_freq = CLK_CAL_FREQ_APPROX(cal_clk_sel);
assert(expected_freq);
uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq);
/* Start calibration */
@@ -145,14 +145,14 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
}
}
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
clk_ll_calibration_set_divider(1);
clk_ll_freq_calculation_set_divider(1);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable();
}
if (cali_clk_sel == CLK_CAL_RC_FAST) {
if (cal_clk_sel == CLK_CAL_RC_FAST) {
if (!dig_rc_fast_enabled) {
rtc_dig_clk8m_disable();
}
@@ -161,7 +161,7 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
}
}
if (cali_clk_sel == CLK_CAL_RC32K) {
if (cal_clk_sel == CLK_CAL_RC32K) {
if (!dig_rc32k_enabled) {
clk_ll_rc32k_digi_disable();
}
@@ -180,14 +180,14 @@ static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, u
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
}
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
slowclk_cycles /= (cali_clk_sel == CLK_CAL_RTC_SLOW) ? 1 : CLK_CAL_DIV_VAL(cali_clk_sel);
slowclk_cycles /= (cal_clk_sel == CLK_CAL_RTC_SLOW) ? 1 : CLK_CAL_DIV_VAL(cal_clk_sel);
assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cali_clk_sel, slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if (cali_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0;
}

12
components/esp_hw_support/port/esp32s2/include/soc/rtc.h
View File

@@ -478,21 +478,21 @@ uint32_t rtc_clk_apb_freq_get(void);
* the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal.
*
* @param cali_clk_sel clock to be measured
* @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out
*/
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slow_clk_cycles);
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/**
* @brief Measure ratio between XTAL frequency and RTC slow clock frequency
* @param cali_clk_sel slow clock to be measured
* @param cal_clk_sel slow clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average ratio between XTAL frequency and slow clock frequency,
* Q13.19 fixed point format, or 0 if calibration has timed out.
*/
uint32_t rtc_clk_cal_ratio(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slow_clk_cycles);
uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles
@@ -841,10 +841,10 @@ void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);
/**
* Using valid hardware calibration value to calibrate slowclk
* If there is no hardware calibration in process, start hardware calibration and wait for calibration finished
* @param cali_clk_sel clock to be measured
* @param cal_clk_sel clock to be measured
* @param slowclk_cycles if no hardware calibration in process, use this amount of slow cycles to calibrate slowclk.
*/
uint32_t rtc_clk_cal_cycling(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles);
uint32_t rtc_clk_cal_cycling(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles);
// -------------------------- CLOCK TREE DEFS ALIAS ----------------------------

62
components/esp_hw_support/port/esp32s2/rtc_time.c
View File

@@ -14,11 +14,11 @@
#include "soc/timer_group_reg.h"
#include "esp_private/periph_ctrl.h"
/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
/* Calculation of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* RTC_SLOW_CLK cycles.
*
* Slow clock calibration feature has two modes of operation: one-off and cycling.
* Slow clock frequency calculation feature has two modes of operation: one-off and cycling.
* In cycling mode (which is enabled by default on SoC reset), counting of XTAL
* cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
* using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
@@ -28,11 +28,11 @@
/**
* @brief One-off clock calibration function used by rtc_clk_cal_internal
* @param cali_clk_sel which clock to calibrate
* @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
static uint32_t rtc_clk_cal_internal_oneoff(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
static uint32_t rtc_clk_cal_internal_oneoff(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
/* There may be another calibration process already running during we call this function,
* so we should wait the last process is done.
@@ -48,17 +48,17 @@ static uint32_t rtc_clk_cal_internal_oneoff(soc_timg0_calibration_clk_src_t cali
}
/* Prepare calibration */
clk_ll_calibration_set_target(cali_clk_sel);
clk_ll_freq_calulation_set_target(cal_clk_sel);
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
/* Figure out how long to wait for calibration to finish */
/* Set timeout reg and expect time delay*/
uint32_t expected_freq;
if (cali_clk_sel == CLK_CAL_32K_XTAL) {
if (cal_clk_sel == CLK_CAL_32K_XTAL) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
} else if (cali_clk_sel == CLK_CAL_RC_FAST_D256) {
} else if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX;
} else {
@@ -89,19 +89,19 @@ static uint32_t rtc_clk_cal_internal_oneoff(soc_timg0_calibration_clk_src_t cali
/**
* @brief Cycling clock calibration function used by rtc_clk_cal_internal
* @param cali_clk_sel which clock to calibrate
* @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
static uint32_t rtc_clk_cal_internal_cycling(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
static uint32_t rtc_clk_cal_internal_cycling(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
/* Get which slowclk is in calibration and max cali cycles */
soc_timg0_calibration_clk_src_t in_calibration_clk = REG_GET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL);
soc_clk_freq_calculation_src_t in_calibration_clk = REG_GET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL);
uint32_t cali_slowclk_cycles = REG_GET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX);
/* If no calibration in process or calibration period equal to 0, use slowclk_cycles cycles to calibrate slowclk */
if (cali_slowclk_cycles == 0 || !GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING) || in_calibration_clk != cali_clk_sel) {
if (cali_slowclk_cycles == 0 || !GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING) || in_calibration_clk != cal_clk_sel) {
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
clk_ll_calibration_set_target(cali_clk_sel);
clk_ll_freq_calulation_set_target(cal_clk_sel);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
cali_slowclk_cycles = slowclk_cycles;
@@ -132,51 +132,51 @@ static uint32_t rtc_clk_xtal_to_slowclk(uint64_t xtal_cycles, uint32_t slowclk_c
/**
* @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
* @param cali_clk_sel which clock to calibrate
* @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles, uint32_t cal_mode)
static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles, uint32_t cal_mode)
{
if (cali_clk_sel == CLK_CAL_RTC_SLOW) {
if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
cali_clk_sel = CLK_CAL_RC_SLOW;
cal_clk_sel = CLK_CAL_RC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cali_clk_sel = CLK_CAL_32K_XTAL;
cal_clk_sel = CLK_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
cali_clk_sel = CLK_CAL_RC_FAST_D256;
cal_clk_sel = CLK_CAL_RC_FAST_D256;
}
}
/* Enable requested clock (90k clock is always on) */
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable();
}
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled();
if (cali_clk_sel == CLK_CAL_RC_FAST_D256) {
if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
rtc_clk_8m_enable(true, true);
clk_ll_rc_fast_d256_digi_enable();
}
uint32_t cal_val;
if (cal_mode == RTC_TIME_CAL_ONEOFF_MODE) {
cal_val = rtc_clk_cal_internal_oneoff(cali_clk_sel, slowclk_cycles);
cal_val = rtc_clk_cal_internal_oneoff(cal_clk_sel, slowclk_cycles);
} else {
cal_val = rtc_clk_cal_internal_cycling(cali_clk_sel, slowclk_cycles);
cal_val = rtc_clk_cal_internal_cycling(cal_clk_sel, slowclk_cycles);
}
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable();
}
if (cali_clk_sel == CLK_CAL_RC_FAST_D256) {
if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
clk_ll_rc_fast_d256_digi_disable();
rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled);
}
@@ -184,10 +184,10 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
return cal_val;
}
uint32_t rtc_clk_cal_ratio(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
assert(slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cali_clk_sel, slowclk_cycles, RTC_TIME_CAL_ONEOFF_MODE);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles, RTC_TIME_CAL_ONEOFF_MODE);
uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles;
uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX);
return ratio;
@@ -200,20 +200,20 @@ static inline bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cy
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
}
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
uint64_t xtal_cycles = rtc_clk_cal_internal(cali_clk_sel, slowclk_cycles, RTC_TIME_CAL_ONEOFF_MODE);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles, RTC_TIME_CAL_ONEOFF_MODE);
if ((cali_clk_sel == CLK_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)rtc_clk_xtal_freq_get(), slowclk_cycles, xtal_cycles)) {
if ((cal_clk_sel == CLK_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)rtc_clk_xtal_freq_get(), slowclk_cycles, xtal_cycles)) {
return 0;
}
return rtc_clk_xtal_to_slowclk(xtal_cycles, slowclk_cycles);
}
uint32_t rtc_clk_cal_cycling(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
uint32_t rtc_clk_cal_cycling(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
uint64_t xtal_cycles = rtc_clk_cal_internal(cali_clk_sel, slowclk_cycles, RTC_TIME_CAL_CYCLING_MODE);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles, RTC_TIME_CAL_CYCLING_MODE);
uint32_t period = rtc_clk_xtal_to_slowclk(xtal_cycles, slowclk_cycles);
return period;
}

8
components/esp_hw_support/port/esp32s3/include/soc/rtc.h
View File

@@ -456,21 +456,21 @@ uint32_t rtc_clk_apb_freq_get(void);
* the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal.
*
* @param cali_clk_sel clock to be measured
* @param cal_clk_sel clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out
*/
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slow_clk_cycles);
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/**
* @brief Measure ratio between XTAL frequency and RTC slow clock frequency
* @param cali_clk_sel slow clock to be measured
* @param cal_clk_sel slow clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average ratio between XTAL frequency and slow clock frequency,
* Q13.19 fixed point format, or 0 if calibration has timed out.
*/
uint32_t rtc_clk_cal_ratio(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slow_clk_cycles);
uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slow_clk_cycles);
/**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles

42
components/esp_hw_support/port/esp32s3/rtc_time.c
View File

@@ -14,11 +14,11 @@
#include "soc/timer_group_reg.h"
#include "esp_private/periph_ctrl.h"
/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
/* Calculation of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* RTC_SLOW_CLK cycles.
*
* Slow clock calibration feature has two modes of operation: one-off and cycling.
* Slow clock frequency calculation feature has two modes of operation: one-off and cycling.
* In cycling mode (which is enabled by default on SoC reset), counting of XTAL
* cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
* using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
@@ -27,33 +27,33 @@
*/
/**
* @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
* @param cali_clk_sel which clock to calibrate
* @brief Clock frequency calculation function used by rtc_clk_cal and rtc_clk_cal_ratio
* @param cal_clk_sel which clock to calculate frequency
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
static uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
if (cali_clk_sel == CLK_CAL_RTC_SLOW) {
if (cal_clk_sel == CLK_CAL_RTC_SLOW) {
soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
cali_clk_sel = CLK_CAL_RC_SLOW;
cal_clk_sel = CLK_CAL_RC_SLOW;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
cali_clk_sel = CLK_CAL_32K_XTAL;
cal_clk_sel = CLK_CAL_32K_XTAL;
} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
cali_clk_sel = CLK_CAL_RC_FAST_D256;
cal_clk_sel = CLK_CAL_RC_FAST_D256;
}
}
/* Enable requested clock (150k clock is always on) */
bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_enable();
}
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled();
if (cali_clk_sel == CLK_CAL_RC_FAST_D256) {
if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
rtc_clk_8m_enable(true, true);
clk_ll_rc_fast_d256_digi_enable();
}
@@ -71,17 +71,17 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
}
/* Prepare calibration */
clk_ll_calibration_set_target(cali_clk_sel);
clk_ll_freq_calulation_set_target(cal_clk_sel);
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
/* Figure out how long to wait for calibration to finish */
/* Set timeout reg and expect time delay*/
uint32_t expected_freq;
if (cali_clk_sel == CLK_CAL_32K_XTAL) {
if (cal_clk_sel == CLK_CAL_32K_XTAL) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
} else if (cali_clk_sel == CLK_CAL_RC_FAST_D256) {
} else if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles));
expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX;
} else {
@@ -109,11 +109,11 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
if (cali_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
clk_ll_xtal32k_digi_disable();
}
if (cali_clk_sel == CLK_CAL_RC_FAST_D256) {
if (cal_clk_sel == CLK_CAL_RC_FAST_D256) {
clk_ll_rc_fast_d256_digi_disable();
rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled);
}
@@ -121,10 +121,10 @@ static uint32_t rtc_clk_cal_internal(soc_timg0_calibration_clk_src_t cali_clk_se
return cal_val;
}
uint32_t rtc_clk_cal_ratio(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
uint32_t rtc_clk_cal_ratio(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
assert(slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cali_clk_sel, slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles;
uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX);
return ratio;
@@ -137,13 +137,13 @@ static inline bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cy
return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
}
uint32_t rtc_clk_cal(soc_timg0_calibration_clk_src_t cali_clk_sel, uint32_t slowclk_cycles)
uint32_t rtc_clk_cal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32_t slowclk_cycles)
{
assert(slowclk_cycles);
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cali_clk_sel, slowclk_cycles);
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk_sel, slowclk_cycles);
if ((cali_clk_sel == CLK_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
if ((cal_clk_sel == CLK_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
return 0;
}

2
components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c
View File

@@ -31,7 +31,7 @@
#define CALIBRATE_ONE(cali_clk) calibrate_one(cali_clk, #cali_clk)
static uint32_t calibrate_one(soc_timg0_calibration_clk_src_t cal_clk, const char* name)
static uint32_t calibrate_one(soc_clk_freq_calculation_src_t cal_clk, const char* name)
{
const uint32_t cal_count = 1000;
const float factor = (1 << 19) * 1000.0f;

2
components/esp_system/port/soc/esp32c5/clk.c
View File

@@ -177,7 +177,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
* will time out, returning 0.
*/
ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
soc_timg0_calibration_clk_src_t cal_sel = -1;
soc_clk_freq_calculation_src_t cal_sel = -1;
if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(true);
cal_sel = CLK_CAL_32K_XTAL;

2
components/esp_system/port/soc/esp32c6/clk.c
View File

@@ -156,7 +156,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
* will time out, returning 0.
*/
ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
soc_timg0_calibration_clk_src_t cal_sel = -1;
soc_clk_freq_calculation_src_t cal_sel = -1;
if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(true);
cal_sel = CLK_CAL_32K_XTAL;

2
components/esp_system/port/soc/esp32c61/clk.c
View File

@@ -127,7 +127,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
* will time out, returning 0.
*/
ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
soc_timg0_calibration_clk_src_t cal_sel = -1;
soc_clk_freq_calculation_src_t cal_sel = -1;
if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(true);
cal_sel = CLK_CAL_32K_XTAL;

2
components/esp_system/port/soc/esp32h2/clk.c
View File

@@ -160,7 +160,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
* will time out, returning 0.
*/
ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
soc_timg0_calibration_clk_src_t cal_sel = -1;
soc_clk_freq_calculation_src_t cal_sel = -1;
if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(true);
cal_sel = CLK_CAL_32K_XTAL;

2
components/esp_system/port/soc/esp32h21/clk.c
View File

@@ -130,7 +130,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
* will time out, returning 0.
*/
ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
soc_timg0_calibration_clk_src_t cal_sel = -1;
soc_clk_freq_calculation_src_t cal_sel = -1;
if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(true);
cal_sel = CLK_CAL_32K_XTAL;

2
components/esp_system/port/soc/esp32h4/clk.c
View File

@@ -126,7 +126,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
* will time out, returning 0.
*/
ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
soc_timg0_calibration_clk_src_t cal_sel = -1;
soc_clk_freq_calculation_src_t cal_sel = -1;
if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(true);
cal_sel = CLK_CAL_32K_XTAL;

2
components/esp_system/port/soc/esp32p4/clk.c
View File

@@ -172,7 +172,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
* will time out, returning 0.
*/
ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
soc_timg0_calibration_clk_src_t cal_sel = -1;
soc_clk_freq_calculation_src_t cal_sel = -1;
if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(true);
cal_sel = CLK_CAL_32K_XTAL;

6
components/hal/esp32/include/hal/clk_tree_ll.h
View File

@@ -704,11 +704,11 @@ static inline __attribute__((always_inline)) void clk_ll_ref_tick_set_divider(so
}
/**
* @brief Select the calibration clock source for timergroup0
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_timg0_calibration_clk_src_t
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(soc_timg0_calibration_clk_src_t clk_sel)
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
switch (clk_sel) {
case CLK_CAL_RTC_SLOW:

6
components/hal/esp32c2/include/hal/clk_tree_ll.h
View File

@@ -388,11 +388,11 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi
}
/**
* @brief Select the calibration clock source for timergroup0
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_timg0_calibration_clk_src_t
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(soc_timg0_calibration_clk_src_t clk_sel)
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
switch (clk_sel) {
case CLK_CAL_RC_SLOW:

6
components/hal/esp32c3/include/hal/clk_tree_ll.h
View File

@@ -496,11 +496,11 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi
}
/**
* @brief Select the calibration clock source for timergroup0
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_timg0_calibration_clk_src_t
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(soc_timg0_calibration_clk_src_t clk_sel)
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
switch (clk_sel) {
case CLK_CAL_RC_SLOW:

6
components/hal/esp32c5/include/hal/clk_tree_ll.h
View File

@@ -451,11 +451,11 @@ static inline __attribute__((always_inline)) void clk_ll_enable_timergroup_rtc_c
}
/**
* @brief Select the calibration clock source for timergroup0
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_timg0_calibration_clk_src_t
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(soc_timg0_calibration_clk_src_t clk_sel)
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
int timg_cali_clk_sel = -1;

6
components/hal/esp32c6/include/hal/clk_tree_ll.h
View File

@@ -578,11 +578,11 @@ static inline __attribute__((always_inline)) void clk_ll_mspi_fast_set_ls_divide
}
/**
* @brief Select the calibration clock source for timergroup0
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_timg0_calibration_clk_src_t
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(soc_timg0_calibration_clk_src_t clk_sel)
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
int timg_cali_clk_sel = -1;
int clk_32k_sel = -1;

6
components/hal/esp32c61/include/hal/clk_tree_ll.h
View File

@@ -397,11 +397,11 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi
}
/**
* @brief Select the calibration clock source for timergroup0
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_timg0_calibration_clk_src_t
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(soc_timg0_calibration_clk_src_t clk_sel)
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
int timg_cali_clk_sel = -1;

6
components/hal/esp32h2/include/hal/clk_tree_ll.h
View File

@@ -459,11 +459,11 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi
}
/**
* @brief Select the calibration clock source for timergroup0
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_timg0_calibration_clk_src_t
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(soc_timg0_calibration_clk_src_t clk_sel)
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
int timg_cali_clk_sel = -1;
int clk_32k_sel = -1;

6
components/hal/esp32h21/include/hal/clk_tree_ll.h
View File

@@ -411,11 +411,11 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi
}
/**
* @brief Select the calibration clock source for timergroup0
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_timg0_calibration_clk_src_t
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(soc_timg0_calibration_clk_src_t clk_sel)
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
int timg_cali_clk_sel = -1;
int clk_32k_sel = -1;

10
components/hal/esp32h4/include/hal/clk_tree_ll.h
View File

@@ -420,11 +420,11 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi
}
/**
* @brief Select the calibration clock source for timergroup0
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_timg0_calibration_clk_src_t
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(soc_timg0_calibration_clk_src_t clk_sel)
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
int timg_cali_clk_sel = -1;
int timg_secure_clk_sel = -1;
@@ -501,11 +501,11 @@ static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(
}
/**
* @brief Set a divider for the clock to be calibrated by timergroup0
* @brief Set a divider for the clock to be frequency calculated by timergroup0
*
* @param divider Divider. PRE_DIV_CNT = divider - 1.
*/
static inline __attribute__((always_inline)) void clk_ll_calibration_set_divider(uint32_t divider)
static inline __attribute__((always_inline)) void clk_ll_freq_calculation_set_divider(uint32_t divider)
{
HAL_ASSERT(divider >= 1);
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.timg_cali_clk_conf, timg_secure_clk_div_num, divider - 1);

10
components/hal/esp32p4/include/hal/clk_tree_ll.h
View File

@@ -726,11 +726,11 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_pll_f20m_get_divide
}
/**
* @brief Select the calibration clock source for timergroup0
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_timg0_calibration_clk_src_t
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(soc_timg0_calibration_clk_src_t clk_sel)
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
int timg_cali_clk_sel = -1;
@@ -782,11 +782,11 @@ static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(
}
/**
* @brief Set a divider for the clock to be calibrated by timergroup0
* @brief Set a divider for the clock to be frequency calculated by timergroup0
*
* @param divider Divider. PRE_DIV_CNT = divider - 1.
*/
static inline __attribute__((always_inline)) void clk_ll_calibration_set_divider(uint32_t divider)
static inline __attribute__((always_inline)) void clk_ll_freq_calculation_set_divider(uint32_t divider)
{
HAL_ASSERT(divider >= 1);
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl21, reg_timergrp0_tgrt_clk_div_num, divider - 1);

6
components/hal/esp32s2/include/hal/clk_tree_ll.h
View File

@@ -620,11 +620,11 @@ static inline __attribute__((always_inline)) void clk_ll_ref_tick_set_divider(so
}
/**
* @brief Select the calibration clock source for timergroup0
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_timg0_calibration_clk_src_t
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(soc_timg0_calibration_clk_src_t clk_sel)
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
switch (clk_sel) {
case CLK_CAL_RC_SLOW:

6
components/hal/esp32s3/include/hal/clk_tree_ll.h
View File

@@ -496,11 +496,11 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi
}
/**
* @brief Select the calibration clock source for timergroup0
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_timg0_calibration_clk_src_t
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(soc_timg0_calibration_clk_src_t clk_sel)
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
switch (clk_sel) {
case CLK_CAL_RC_SLOW:

14
components/soc/esp32/include/soc/clk_tree_defs.h
View File

@@ -451,8 +451,6 @@ typedef enum {
LEDC_USE_APB_CLK = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_REF_TICK = SOC_MOD_CLK_REF_TICK, /*!< Select REF_TICK as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////////SDMMC///////////////////////////////////////////////////////////////
@@ -484,15 +482,15 @@ typedef enum {
CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t;
////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calibration source selection
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW, /*!< Select to calibrate RTC_SLOW_CLK */
CLK_CAL_RC_FAST_D256, /*!< Select to calibrate RC_FAST_D256_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calibrate XTAL32K_CLK */
} soc_timg0_calibration_clk_src_t;
CLK_CAL_RTC_SLOW, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_FAST_D256, /*!< Select to calculate frequency of RC_FAST_D256_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus
}

16
components/soc/esp32c2/include/soc/clk_tree_defs.h
View File

@@ -311,8 +311,6 @@ typedef enum {
LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F60M, /*!< Select PLL_F60M as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
@@ -325,16 +323,16 @@ typedef enum {
CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t;
////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calibration source selection
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calibrate RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calibrate RC_SLOW_CLK */
CLK_CAL_RC_FAST_D256, /*!< Select to calibrate RC_FAST_D256_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calibrate OSC_SLOW_CLK (external slow clock) */
} soc_timg0_calibration_clk_src_t;
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_RC_FAST_D256, /*!< Select to calculate frequency of RC_FAST_D256_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calculate frequency of OSC_SLOW_CLK (external slow clock) */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus
}

16
components/soc/esp32c3/include/soc/clk_tree_defs.h
View File

@@ -380,8 +380,6 @@ typedef enum {
LEDC_USE_APB_CLK = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
@@ -394,16 +392,16 @@ typedef enum {
CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t;
////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calibration source selection
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calibrate RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calibrate RC_SLOW_CLK */
CLK_CAL_RC_FAST_D256, /*!< Select to calibrate RC_FAST_D256_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calibrate XTAL32K_CLK */
} soc_timg0_calibration_clk_src_t;
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_RC_FAST_D256, /*!< Select to calculate frequency of RC_FAST_D256_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus
}

18
components/soc/esp32c5/include/soc/clk_tree_defs.h
View File

@@ -500,8 +500,6 @@ typedef enum {
LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////////PARLIO////////////////////////////////////////////////////////////////
@@ -558,17 +556,17 @@ typedef enum {
CLKOUT_SIG_RC_SLOW = 0x19, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
} soc_clkout_sig_id_t;
////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calibration source selection
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calibrate RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calibrate RC_SLOW_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calibrate XTAL32K_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calibrate OSC_SLOW_CLK (external slow clock) */
CLK_CAL_RC_FAST, /*!< Select to calibrate RC_FAST_CLK */
} soc_timg0_calibration_clk_src_t;
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calculate frequency of OSC_SLOW_CLK (external slow clock) */
CLK_CAL_RC_FAST, /*!< Select to calculate frequency of RC_FAST_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus
}

20
components/soc/esp32c6/include/soc/clk_tree_defs.h
View File

@@ -478,8 +478,6 @@ typedef enum {
LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////////PARLIO////////////////////////////////////////////////////////////////
@@ -516,18 +514,18 @@ typedef enum {
CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t;
////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calibration source selection
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calibrate RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calibrate RC_SLOW_CLK */
CLK_CAL_RC32K, /*!< Select to calibrate RC32K_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calibrate XTAL32K_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calibrate OSC_SLOW_CLK (external slow clock) */
CLK_CAL_RC_FAST, /*!< Select to calibrate RC_FAST_CLK */
} soc_timg0_calibration_clk_src_t;
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_RC32K, /*!< Select to calculate frequency of RC32K_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calculate frequency of OSC_SLOW_CLK (external slow clock) */
CLK_CAL_RC_FAST, /*!< Select to calculate frequency of RC_FAST_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus
}

18
components/soc/esp32c61/include/soc/clk_tree_defs.h
View File

@@ -356,8 +356,6 @@ typedef enum {
LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////////FLASH///////////////////////////////////////////////////////////////////
@@ -396,17 +394,17 @@ typedef enum {
CLKOUT_SIG_RC_SLOW = 0x19, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
} soc_clkout_sig_id_t;
////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calibration source selection
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calibrate RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calibrate RC_SLOW_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calibrate XTAL32K_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calibrate OSC_SLOW_CLK (external slow clock) */
CLK_CAL_RC_FAST, /*!< Select to calibrate RC_FAST_CLK */
} soc_timg0_calibration_clk_src_t;
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calculate frequency of OSC_SLOW_CLK (external slow clock) */
CLK_CAL_RC_FAST, /*!< Select to calculate frequency of RC_FAST_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus
}

20
components/soc/esp32h2/include/soc/clk_tree_defs.h
View File

@@ -472,8 +472,6 @@ typedef enum {
LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M clock as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////////PARLIO////////////////////////////////////////////////////////////////
@@ -525,18 +523,18 @@ typedef enum {
CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t;
////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calibration source selection
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calibrate RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calibrate RC_SLOW_CLK */
CLK_CAL_RC32K, /*!< Select to calibrate RC32K_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calibrate XTAL32K_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calibrate OSC_SLOW_CLK (external slow clock) */
CLK_CAL_RC_FAST, /*!< Select to calibrate RC_FAST_CLK */
} soc_timg0_calibration_clk_src_t;
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_RC32K, /*!< Select to calculate frequency of RC32K_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calculate frequency of OSC_SLOW_CLK (external slow clock) */
CLK_CAL_RC_FAST, /*!< Select to calculate frequency of RC_FAST_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus
}

16
components/soc/esp32h21/include/soc/clk_tree_defs.h
View File

@@ -338,17 +338,17 @@ typedef enum {
FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
} soc_periph_flash_clk_src_t;
////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calibration source selection
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calibrate RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calibrate RC_SLOW_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calibrate XTAL32K_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calibrate OSC_SLOW_CLK (external slow clock) */
CLK_CAL_RC_FAST, /*!< Select to calibrate RC_FAST_CLK */
} soc_timg0_calibration_clk_src_t;
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calculate frequency of OSC_SLOW_CLK (external slow clock) */
CLK_CAL_RC_FAST, /*!< Select to calculate frequency of RC_FAST_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus
}

38
components/soc/esp32h4/include/soc/clk_tree_defs.h
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@@ -286,28 +286,28 @@ typedef enum {
FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
} soc_periph_flash_clk_src_t;
////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calibration source selection
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calibrate RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calibrate RC_SLOW_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calibrate XTAL32K_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calibrate OSC_SLOW_CLK (external slow clock) */
CLK_CAL_RC_FAST, /*!< Select to calibrate RC_FAST_CLK */
CLK_CAL_CPU, /*!< Select to calibrate CPU_CLK */
CLK_CAL_AHB, /*!< Select to calibrate AHB_CLK */
CLK_CAL_APB, /*!< Select to calibrate APB_CLK */
CLK_CAL_SEC, /*!< Select to calibrate SEC_CLK */
CLK_CAL_MSPI, /*!< Select to calibrate MSPI_CLK */
CLK_CAL_IOMUX, /*!< Select to calibrate IOMUX_CLK */
CLK_CAL_PARLIO_RX, /*!< Select to calibrate PARLIO_RX_CLK */
CLK_CAL_PARLIO_TX, /*!< Select to calibrate PARLIO_TX_CLK */
CLK_CAL_GPSPI3_MST, /*!< Select to calibrate GPSPI3_MST_CLK */
CLK_CAL_GPSPI2_MST, /*!< Select to calibrate GPSPI2_MST_CLK */
CLK_CAL_EXT_IO, /*!< Select to calibrate an external clock from an IO */
} soc_timg0_calibration_clk_src_t;
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calculate frequency of OSC_SLOW_CLK (external slow clock) */
CLK_CAL_RC_FAST, /*!< Select to calculate frequency of RC_FAST_CLK */
CLK_CAL_CPU, /*!< Select to calculate frequency of CPU_CLK */
CLK_CAL_AHB, /*!< Select to calculate frequency of AHB_CLK */
CLK_CAL_APB, /*!< Select to calculate frequency of APB_CLK */
CLK_CAL_SEC, /*!< Select to calculate frequency of SEC_CLK */
CLK_CAL_MSPI, /*!< Select to calculate frequency of MSPI_CLK */
CLK_CAL_IOMUX, /*!< Select to calculate frequency of IOMUX_CLK */
CLK_CAL_PARLIO_RX, /*!< Select to calculate frequency of PARLIO_RX_CLK */
CLK_CAL_PARLIO_TX, /*!< Select to calculate frequency of PARLIO_TX_CLK */
CLK_CAL_GPSPI3_MST, /*!< Select to calculate frequency of GPSPI3_MST_CLK */
CLK_CAL_GPSPI2_MST, /*!< Select to calculate frequency of GPSPI2_MST_CLK */
CLK_CAL_EXT_IO, /*!< Select to calculate frequency of an external clock from an IO */
} soc_clk_freq_calculation_src_t;
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////

32
components/soc/esp32p4/include/soc/clk_tree_defs.h
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@@ -797,25 +797,25 @@ typedef enum {
CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t;
////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calibration source selection
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calibrate RTC_SLOW_CLK */
CLK_CAL_MPLL, /*!< Select to calibrate MPLL_CLK */
CLK_CAL_SPLL, /*!< Select to calibrate SPLL_CLK */
CLK_CAL_CPLL, /*!< Select to calibrate CPLL_CLK */
CLK_CAL_APLL, /*!< Select to calibrate APLL_CLK */
CLK_CAL_SDIO_PLL0, /*!< Select to calibrate SDIO_PLL0_CLK */
CLK_CAL_SDIO_PLL1, /*!< Select to calibrate SDIO_PLL1_CLK */
CLK_CAL_SDIO_PLL2, /*!< Select to calibrate SDIO_PLL2_CLK */
CLK_CAL_RC_FAST, /*!< Select to calibrate RC_FAST_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calibrate RC_SLOW_CLK */
CLK_CAL_RC32K, /*!< Select to calibrate RC32K_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calibrate XTAL32K_CLK */
CLK_CAL_LP_PLL, /*!< Select to calibrate LP_PLL_CLK */
} soc_timg0_calibration_clk_src_t;
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_MPLL, /*!< Select to calculate frequency of MPLL_CLK */
CLK_CAL_SPLL, /*!< Select to calculate frequency of SPLL_CLK */
CLK_CAL_CPLL, /*!< Select to calculate frequency of CPLL_CLK */
CLK_CAL_APLL, /*!< Select to calculate frequency of APLL_CLK */
CLK_CAL_SDIO_PLL0, /*!< Select to calculate frequency of SDIO_PLL0_CLK */
CLK_CAL_SDIO_PLL1, /*!< Select to calculate frequency of SDIO_PLL1_CLK */
CLK_CAL_SDIO_PLL2, /*!< Select to calculate frequency of SDIO_PLL2_CLK */
CLK_CAL_RC_FAST, /*!< Select to calculate frequency of RC_FAST_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_RC32K, /*!< Select to calculate frequency of RC32K_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
CLK_CAL_LP_PLL, /*!< Select to calculate frequency of LP_PLL_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus
}

16
components/soc/esp32s2/include/soc/clk_tree_defs.h
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@@ -438,8 +438,6 @@ typedef enum {
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_REF_TICK = SOC_MOD_CLK_REF_TICK, /*!< Select REF_TICK as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
@@ -454,16 +452,16 @@ typedef enum {
CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t;
////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calibration source selection
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calibrate RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calibrate RC_SLOW_CLK */
CLK_CAL_RC_FAST_D256, /*!< Select to calibrate RC_FAST_D256_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calibrate XTAL32K_CLK */
} soc_timg0_calibration_clk_src_t;
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_RC_FAST_D256, /*!< Select to calculate frequency of RC_FAST_D256_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus
}

16
components/soc/esp32s3/include/soc/clk_tree_defs.h
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@@ -469,8 +469,6 @@ typedef enum {
LEDC_USE_APB_CLK = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////////SDMMC///////////////////////////////////////////////////////////////
@@ -499,16 +497,16 @@ typedef enum {
CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t;
////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
//////////////////////////////////////CLOCK FREQUENCY CALCULATION////////////////////////////////////////////////////
/**
* @brief Clock frequency calibration source selection
* @brief Clock frequency calculation source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW = -1, /*!< Select to calibrate RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calibrate RC_SLOW_CLK */
CLK_CAL_RC_FAST_D256, /*!< Select to calibrate RC_FAST_D256_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calibrate XTAL32K_CLK */
} soc_timg0_calibration_clk_src_t;
CLK_CAL_RTC_SLOW = -1, /*!< Select to calculate frequency of RTC_SLOW_CLK */
CLK_CAL_RC_SLOW, /*!< Select to calculate frequency of RC_SLOW_CLK */
CLK_CAL_RC_FAST_D256, /*!< Select to calculate frequency of RC_FAST_D256_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calculate frequency of XTAL32K_CLK */
} soc_clk_freq_calculation_src_t;
#ifdef __cplusplus
}

2
docs/en/migration-guides/release-6.x/6.0/peripherals.rst
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@@ -62,6 +62,8 @@ LEDC
- :cpp:member:`ledc_channel_config_t::intr_type` has been deprecated. `LEDC_INTR_FADE_END` interrupt enable / disable control is handled by the driver internally. Users can still register a callback for this interrupt by :cpp:func:`ledc_cb_register`.
- :cpp:enumerator:`soc_periph_ledc_clk_src_legacy_t::LEDC_USE_RTC8M_CLK` has been removed. Please use ``LEDC_USE_RC_FAST_CLK`` instead.
I2C
---

2
docs/zh_CN/migration-guides/release-6.x/6.0/peripherals.rst
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@@ -62,6 +62,8 @@ LEDC
- :cpp:member:`ledc_channel_config_t::intr_type` 已被弃用。`LEDC_INTR_FADE_END` 中断使能/禁用控制由驱动内部处理。用户仍可以通过 :cpp:func:`ledc_cb_register` 注册该中断的回调。
- :cpp:enumerator:`soc_periph_ledc_clk_src_legacy_t::LEDC_USE_RTC8M_CLK` 已被移除。请使用 ``LEDC_USE_RC_FAST_CLK`` 代替。
I2C
---