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clk_tree: Update clock tree programming guide for esp32c6
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@@ -37,8 +37,8 @@ extern "C" {
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*
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*
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* 6) External Slow Clock (optional): OSC_SLOW
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* 6) External Slow Clock (optional): OSC_SLOW
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*
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*
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* A clock signal generated by an external circuit with frequency ~32kHz can be connected to GPIO0
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* A slow clock signal generated by an external circuit can be connected to GPIO0 to be the clock source for the
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* to be the clock source for the RTC_SLOW_CLK.
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* RTC_SLOW_CLK.
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*
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*
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* OSC_SLOW_CLK can also be calibrated to get its exact frequency.
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* OSC_SLOW_CLK can also be calibrated to get its exact frequency.
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*/
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*/
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@@ -95,7 +95,7 @@ typedef enum {
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*/
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*/
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typedef enum {
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typedef enum {
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SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
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SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
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SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
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} soc_rtc_fast_clk_src_t;
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} soc_rtc_fast_clk_src_t;
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@@ -98,7 +98,6 @@ api-reference/peripherals/dac
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api-reference/peripherals/touch_element
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api-reference/peripherals/touch_element
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api-reference/peripherals/secure_element
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api-reference/peripherals/secure_element
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api-reference/peripherals/sdio_slave
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api-reference/peripherals/sdio_slave
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api-reference/peripherals/clk_tree
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api-reference/peripherals/touch_pad
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api-reference/peripherals/touch_pad
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api-reference/peripherals/adc_calibration
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api-reference/peripherals/adc_calibration
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api-reference/peripherals/ds
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api-reference/peripherals/ds
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@@ -1,11 +1,11 @@
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Clock Tree
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Clock Tree
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==========
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==========
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{IDF_TARGET_RC_FAST_VAGUE_FREQ: default="8", esp32="8", esp32s2="8", esp32c3="17.5", esp32s3="17.5", esp32c2="17.5", esp32h4="8"}
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{IDF_TARGET_RC_FAST_VAGUE_FREQ: default="8", esp32="8", esp32s2="8", esp32c3="17.5", esp32s3="17.5", esp32c2="17.5", esp32c6="17.5", esp32h4="8"}
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{IDF_TARGET_RC_FAST_ADJUSTED_FREQ: default="8.5", esp32="8.5", esp32s2="8.5", esp32c3="17.5", esp32s3="17.5", esp32c2="17.5", esp32h4="8.5"}
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{IDF_TARGET_RC_FAST_ADJUSTED_FREQ: default="8.5", esp32="8.5", esp32s2="8.5", esp32c3="17.5", esp32s3="17.5", esp32c2="17.5", esp32c6="17.5", esp32h4="8.5"}
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{IDF_TARGET_XTAL_FREQ: default="40", esp32="2~40", esp32s2="40", esp32c3="40", esp32s3="40", esp32c2="40", esp32h4="32"}
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{IDF_TARGET_XTAL_FREQ: default="40", esp32="2~40", esp32c2="40/26", esp32h4="32"}
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{IDF_TARGET_RC_SLOW_VAGUE_FREQ: default="136", esp32="150", esp32s2="90"}
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{IDF_TARGET_RC_SLOW_VAGUE_FREQ: default="136", esp32="150", esp32s2="90"}
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@@ -31,13 +31,17 @@ Root clocks generate reliable clock signals. These clock signals then pass throu
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This RC oscillator generates a ~{IDF_TARGET_RC_FAST_ADJUSTED_FREQ}MHz clock signal output as the RC_FAST_CLK.
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This RC oscillator generates a ~{IDF_TARGET_RC_FAST_ADJUSTED_FREQ}MHz clock signal output as the RC_FAST_CLK.
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.. only:: not esp32h4
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.. only:: SOC_CLK_RC_FAST_D256_SUPPORTED
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The ~{IDF_TARGET_RC_FAST_ADJUSTED_FREQ}MHz signal output is also passed into a configurable divider, which by default divides the input clock frequency by 256, to generate a RC_FAST_D256_CLK.
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The ~{IDF_TARGET_RC_FAST_ADJUSTED_FREQ}MHz signal output is also passed into a configurable divider, which by default divides the input clock frequency by 256, to generate a RC_FAST_D256_CLK.
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The exact frequency of RC_FAST_CLK can be computed in runtime through calibration on the RC_FAST_D256_CLK.
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The exact frequency of RC_FAST_CLK can be computed in runtime through calibration on the RC_FAST_D256_CLK.
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.. only:: not SOC_CLK_RC_FAST_D256_SUPPORTED and SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
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.. only:: esp32h4
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The exact frequency of RC_FAST_CLK can be computed in runtime through calibration.
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.. only:: not SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
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The exact frequency of RC_FAST_CLK cannot be computed in runtime through calibration, but it is still possible to get its frequency through an oscillscope or a logic analyzer by routing the clock signal to a GPIO pin.
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The exact frequency of RC_FAST_CLK cannot be computed in runtime through calibration, but it is still possible to get its frequency through an oscillscope or a logic analyzer by routing the clock signal to a GPIO pin.
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@@ -47,7 +51,7 @@ Root clocks generate reliable clock signals. These clock signals then pass throu
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This RC oscillator generates a ~{IDF_TARGET_RC_SLOW_VAGUE_FREQ}kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock can be computed in runtime through calibration.
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This RC oscillator generates a ~{IDF_TARGET_RC_SLOW_VAGUE_FREQ}kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock can be computed in runtime through calibration.
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.. only:: not esp32c2
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.. only:: SOC_CLK_XTAL32K_SUPPORTED
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- External 32kHz Crystal - optional (XTAL32K)
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- External 32kHz Crystal - optional (XTAL32K)
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@@ -61,13 +65,13 @@ Root clocks generate reliable clock signals. These clock signals then pass throu
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XTAL32K_CLK can also be calibrated to get its exact frequency.
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XTAL32K_CLK can also be calibrated to get its exact frequency.
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.. only:: esp32c2
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.. only:: SOC_CLK_OSC_SLOW_SUPPORTED
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- External Slow Clock - optional (OSC_SLOW)
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- External Slow Clock - optional (OSC_SLOW)
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A clock signal generated by an external circuit can be connected to pin0 to be the clock source for the RTC_SLOW_CLK. This clock can also be calibrated to get its exact frequency.
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A clock signal generated by an external circuit can be connected to pin0 to be the clock source for the RTC_SLOW_CLK. This clock can also be calibrated to get its exact frequency.
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.. only:: esp32h4
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.. only:: SOC_CLK_RC32K_SUPPORTED
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- Internal 32kHz RC Oscillator (RC32K)
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- Internal 32kHz RC Oscillator (RC32K)
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