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soc/esp32s3: merge gpio caps into soc_caps.h

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This commit is contained in:
Michael (XIAO Xufeng)
2022-02-15 02:09:16 +08:00
parent 4995e24199
commit 4efab0d0ff
4 changed files with 22 additions and 63 deletions
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2
components/hal/esp32s3/include/hal/rtc_io_ll.h
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@ -18,6 +18,8 @@
#include "hal/rtc_io_types.h" #include "hal/rtc_io_types.h"
#include "hal/gpio_types.h" #include "hal/gpio_types.h"
#define RTCIO_LL_PIN_FUNC 0
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif

40
components/soc/esp32s3/include/soc/gpio_caps.h
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@ -1,40 +0,0 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
// ESP32-S3 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define SOC_GPIO_PIN_COUNT (49)
// On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP32-S3
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// 0~48 except from 22~25 are valid
#define SOC_GPIO_VALID_GPIO_MASK (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
// No GPIO is input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK)
// Support to configure slept status
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
#ifdef __cplusplus
}
#endif

21
components/soc/esp32s3/include/soc/rtc_io_caps.h
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@ -1,21 +0,0 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_RTCIO_PIN_COUNT 22
#define RTCIO_LL_PIN_FUNC 0
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
#define SOC_RTCIO_HOLD_SUPPORTED 1
#define SOC_RTCIO_WAKE_SUPPORTED 1

22
components/soc/esp32s3/include/soc/soc_caps.h
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@ -95,7 +95,22 @@
#define SOC_GDMA_PSRAM_MIN_ALIGN (16) // Minimal alignment for PSRAM transaction #define SOC_GDMA_PSRAM_MIN_ALIGN (16) // Minimal alignment for PSRAM transaction
/*-------------------------- GPIO CAPS ---------------------------------------*/ /*-------------------------- GPIO CAPS ---------------------------------------*/
#include "gpio_caps.h" // ESP32-S3 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1U)
#define SOC_GPIO_PIN_COUNT (49)
// On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP32-S3
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// 0~48 except from 22~25 are valid
#define SOC_GPIO_VALID_GPIO_MASK (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
// No GPIO is input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK)
// Support to configure slept status
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/ /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
@ -175,7 +190,10 @@
#define SOC_RTC_CNTL_TAGMEM_PD_DMA_ADDR_ALIGN (SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH >> 3) #define SOC_RTC_CNTL_TAGMEM_PD_DMA_ADDR_ALIGN (SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH >> 3)
/*-------------------------- RTCIO CAPS --------------------------------------*/ /*-------------------------- RTCIO CAPS --------------------------------------*/
#include "rtc_io_caps.h" #define SOC_RTCIO_PIN_COUNT 22
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
#define SOC_RTCIO_HOLD_SUPPORTED 1
#define SOC_RTCIO_WAKE_SUPPORTED 1
/*-------------------------- SIGMA DELTA CAPS --------------------------------*/ /*-------------------------- SIGMA DELTA CAPS --------------------------------*/
#define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral #define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral