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Merge branch 'bugfix/esp32_u4wdh_quad_io_v4.2' into 'release/v4.2'

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bootloader: Fix selection of Quad I/O modes on ESP32-U4WDH chip (v4.2)

See merge request espressif/esp-idf!13877
This commit is contained in:
Angus Gratton
2021-06-23 05:37:51 +00:00
parent 007bb3f9ed f23c9d94ae
commit 54ac548cd4
2 changed files with 3 additions and 2 deletions
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2
components/bootloader_support/src/bootloader_flash_config_esp32.c
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@@ -178,9 +178,9 @@ int bootloader_flash_get_wp_pin(void)
uint8_t chip_ver; uint8_t chip_ver;
uint32_t pkg_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG); uint32_t pkg_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
switch(pkg_ver) { switch(pkg_ver) {
case EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH:
case EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5: case EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5:
return ESP32_D2WD_WP_GPIO; return ESP32_D2WD_WP_GPIO;
case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2:
case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4: case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4:
/* Same package IDs are used for ESP32-PICO-V3 and ESP32-PICO-D4, silicon version differentiates */ /* Same package IDs are used for ESP32-PICO-V3 and ESP32-PICO-D4, silicon version differentiates */
chip_ver = bootloader_common_get_chip_revision(); chip_ver = bootloader_common_get_chip_revision();

3
components/soc/soc/esp32/include/soc/efuse_reg.h
View File

@@ -112,7 +112,8 @@
#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0 #define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0
#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1 #define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1
#define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2 #define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2
#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4 #define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4 /* Deprecated: this chip was never mass produced */
#define EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH 4
#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5 #define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5
#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302 6 #define EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302 6
/* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */ /* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */