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Merge branch 'refactor/improve_adc_power_maintanance_v4.4' into 'release/v4.4'

Browse Source 
adc: improve power logic (v4.4)

See merge request espressif/esp-idf!23275
This commit is contained in:
morris
2023-06-20 10:52:46 +08:00
parent ea9d916f2a 2a0a4fadd9
commit 564e20dd6b
35 changed files with 1272 additions and 137 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
components/driver/adc.c
View File

@@ -42,6 +42,7 @@
#include "soc/i2s_periph.h"
#include "esp_private/i2s_platform.h"
#endif
#include "esp_private/sar_periph_ctrl.h"
static const char *ADC_TAG = "ADC";
@@ -365,7 +366,7 @@ esp_err_t adc_digi_start(void)
ESP_LOGE(ADC_TAG, "The driver is already started");
return ESP_ERR_INVALID_STATE;
}
adc_power_acquire();
sar_periph_ctrl_adc_continuous_power_acquire();
//reset flags
s_adc_digi_ctx->ringbuf_overflow_flag = 0;
s_adc_digi_ctx->driver_start_flag = 1;
@@ -454,7 +455,7 @@ esp_err_t adc_digi_stop(void)
if (s_adc_digi_ctx->use_adc2) {
SAR_ADC2_LOCK_RELEASE();
}
adc_power_release();
sar_periph_ctrl_adc_continuous_power_release();
}
#if CONFIG_IDF_TARGET_ESP32S2
else {
@@ -662,7 +663,7 @@ esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio)
}
}
adc_power_acquire();
sar_periph_ctrl_adc_oneshot_power_acquire();
if (adc_unit & ADC_UNIT_1) {
ADC_ENTER_CRITICAL();
adc_hal_vref_output(ADC_NUM_1, channel, true);
@@ -707,7 +708,7 @@ int adc1_get_raw(adc1_channel_t channel)
int raw_out = 0;
periph_module_enable(PERIPH_SARADC_MODULE);
adc_power_acquire();
sar_periph_ctrl_adc_oneshot_power_acquire();
SAR_ADC1_LOCK_ACQUIRE();
adc_ll_digi_clk_sel(0);
@@ -723,7 +724,7 @@ int adc1_get_raw(adc1_channel_t channel)
SAR_ADC1_LOCK_RELEASE();
adc_power_release();
sar_periph_ctrl_adc_oneshot_power_release();
periph_module_disable(PERIPH_SARADC_MODULE);
return raw_out;
@@ -758,7 +759,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
esp_err_t ret = ESP_OK;
periph_module_enable(PERIPH_SARADC_MODULE);
adc_power_acquire();
sar_periph_ctrl_adc_oneshot_power_acquire();
SAR_ADC2_LOCK_ACQUIRE();
adc_ll_digi_clk_sel(0);
@@ -777,7 +778,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
SAR_ADC2_LOCK_RELEASE();
adc_power_release();
sar_periph_ctrl_adc_oneshot_power_release();
periph_module_disable(PERIPH_SARADC_MODULE);
return ret;
@@ -879,12 +880,12 @@ uint32_t adc_get_calibration_offset(adc_ll_num_t adc_n, adc_channel_t channel, a
} else {
ESP_LOGD(ADC_TAG, "Calibration eFuse is not configured, use self-calibration for ICode");
adc_power_acquire();
sar_periph_ctrl_adc_oneshot_power_acquire();
ADC_ENTER_CRITICAL();
const bool internal_gnd = true;
init_code = adc_hal_self_calibration(adc_n, channel, atten, internal_gnd);
ADC_EXIT_CRITICAL();
adc_power_release();
sar_periph_ctrl_adc_oneshot_power_release();
}
s_adc_cali_param[adc_n][atten] = init_code;

67
components/driver/adc_common.c
View File

@@ -21,6 +21,7 @@
#include "hal/adc_types.h"
#include "hal/adc_hal.h"
#include "hal/adc_hal_conf.h"
#include "esp_private/sar_periph_ctrl.h"
#if SOC_DAC_SUPPORTED
#include "driver/dac.h"
@@ -132,64 +133,28 @@ static esp_pm_lock_handle_t s_adc2_arbiter_lock;
ADC Common
---------------------------------------------------------------*/
// ADC Power
// This gets incremented when adc_power_acquire() is called, and decremented when
// adc_power_release() is called. ADC is powered down when the value reaches zero.
// Should be modified within critical section (ADC_ENTER/EXIT_CRITICAL).
static int s_adc_power_on_cnt;
static void adc_power_on_internal(void)
{
/* Set the power always on to increase precision. */
adc_hal_set_power_manage(ADC_POWER_SW_ON);
}
void adc_power_acquire(void)
{
ADC_POWER_ENTER();
s_adc_power_on_cnt++;
if (s_adc_power_on_cnt == 1) {
adc_power_on_internal();
}
ADC_POWER_EXIT();
sar_periph_ctrl_adc_oneshot_power_acquire();
sar_periph_ctrl_adc_continuous_power_acquire();
}
void adc_power_on(void)
{
ADC_POWER_ENTER();
adc_power_on_internal();
ADC_POWER_EXIT();
}
static void adc_power_off_internal(void)
{
#if CONFIG_IDF_TARGET_ESP32
adc_hal_set_power_manage(ADC_POWER_SW_OFF);
#else
adc_hal_set_power_manage(ADC_POWER_BY_FSM);
#endif
sar_periph_ctrl_adc_oneshot_power_acquire();
sar_periph_ctrl_adc_continuous_power_acquire();
}
void adc_power_release(void)
{
ADC_POWER_ENTER();
s_adc_power_on_cnt--;
/* Sanity check */
if (s_adc_power_on_cnt < 0) {
ADC_POWER_EXIT();
ESP_LOGE(ADC_TAG, "%s called, but s_adc_power_on_cnt == 0", __func__);
abort();
} else if (s_adc_power_on_cnt == 0) {
adc_power_off_internal();
}
ADC_POWER_EXIT();
sar_periph_ctrl_adc_continuous_power_release();
sar_periph_ctrl_adc_oneshot_power_release();
}
void adc_power_off(void)
{
ADC_POWER_ENTER();
adc_power_off_internal();
ADC_POWER_EXIT();
sar_periph_ctrl_adc_continuous_power_release();
sar_periph_ctrl_adc_oneshot_power_release();
}
esp_err_t adc1_pad_get_io_num(adc1_channel_t channel, gpio_num_t *gpio_num)
@@ -389,7 +354,7 @@ esp_err_t adc1_dma_mode_acquire(void)
SARADC1_ACQUIRE();
ESP_LOGD( ADC_TAG, "dma mode takes adc1 lock." );
adc_power_acquire();
sar_periph_ctrl_adc_continuous_power_acquire();
SARADC1_ENTER();
/* switch SARADC into DIG channel */
@@ -404,7 +369,7 @@ esp_err_t adc1_rtc_mode_acquire(void)
/* Use locks to avoid digtal and RTC controller conflicts.
for adc1, block until acquire the lock. */
SARADC1_ACQUIRE();
adc_power_acquire();
sar_periph_ctrl_adc_oneshot_power_acquire();
SARADC1_ENTER();
/* switch SARADC into RTC channel. */
@@ -419,7 +384,7 @@ esp_err_t adc1_lock_release(void)
ADC_CHECK((uint32_t *)adc1_dma_lock != NULL, "adc1 lock release called before acquire", ESP_ERR_INVALID_STATE );
/* Use locks to avoid digtal and RTC controller conflicts. for adc1, block until acquire the lock. */
adc_power_release();
sar_periph_ctrl_adc_oneshot_power_release();
SARADC1_RELEASE();
return ESP_OK;
}
@@ -460,7 +425,7 @@ int adc1_get_voltage(adc1_channel_t channel) //Deprecated. Use adc1_get_raw()
#if SOC_ULP_SUPPORTED
void adc1_ulp_enable(void)
{
adc_power_acquire();
sar_periph_ctrl_adc_oneshot_power_acquire();
SARADC1_ENTER();
adc_ll_set_controller(ADC_NUM_1, ADC_LL_CTRL_ULP);
@@ -583,7 +548,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
//try the lock, return if failed (wifi using).
return ESP_ERR_TIMEOUT;
}
adc_power_acquire(); //in critical section with whole rtc module
sar_periph_ctrl_adc_oneshot_power_acquire(); //in critical section with whole rtc module
//avoid collision with other tasks
adc2_init(); // in critical section with whole rtc module. because the PWDET use the same registers, place it here.
@@ -628,7 +593,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
#endif //CONFIG_IDF_TARGET_ESP32
SARADC2_EXIT();
adc_power_release();
sar_periph_ctrl_adc_oneshot_power_release();
SARADC2_RELEASE();
*raw_out = adc_value;
@@ -659,7 +624,7 @@ esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio)
return ESP_ERR_INVALID_ARG;
}
adc_power_acquire();
sar_periph_ctrl_adc_oneshot_power_acquire();
if (adc_unit & ADC_UNIT_1) {
VREF_ENTER(1);
adc_hal_vref_output(ADC_NUM_1, ch, true);

5
components/driver/esp32/adc.c
View File

@@ -21,6 +21,7 @@
#include "driver/rtc_cntl.h"
#include "driver/gpio.h"
#include "driver/adc.h"
#include "esp_private/sar_periph_ctrl.h"
#ifndef NDEBUG
// Enable built-in checks in queue.h in debug builds
@@ -47,7 +48,7 @@ static int hall_sensor_get_value(void) //hall sensor without LNA
{
int hall_value;
adc_power_acquire();
sar_periph_ctrl_adc_oneshot_power_acquire();
ADC_ENTER_CRITICAL();
/* disable other peripherals. */
@@ -59,7 +60,7 @@ static int hall_sensor_get_value(void) //hall sensor without LNA
adc_ll_hall_disable();
ADC_EXIT_CRITICAL();
adc_power_release();
sar_periph_ctrl_adc_oneshot_power_release();
return hall_value;
}

3
components/driver/i2s.c
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@@ -39,6 +39,7 @@
#include "esp_efuse.h"
#include "esp_rom_gpio.h"
#include "esp_private/i2s_platform.h"
#include "esp_private/sar_periph_ctrl.h"
#include "sdkconfig.h"
@@ -1995,7 +1996,7 @@ esp_err_t i2s_driver_install(i2s_port_t i2s_num, const i2s_config_t *i2s_config,
#if SOC_I2S_SUPPORTS_ADC
/* If using built-in ADC, we need to enable ADC power manerge*/
if (pre_alloc_i2s_obj->hal_cfg.mode & I2S_MODE_ADC_BUILT_IN) {
adc_power_acquire();
sar_periph_ctrl_adc_continuous_power_acquire();
}
#endif
/* Enable module clock */

3
components/esp_hw_support/component.mk
View File

@@ -17,7 +17,8 @@ COMPONENT_OBJEXCLUDE += clk_ctrl_os.o \
port/$(IDF_TARGET)/cache_sram_mmu.o \
port/$(IDF_TARGET)/esp_himem.o \
port/$(IDF_TARGET)/spiram.o \
port/$(IDF_TARGET)/spiram_psram.o
port/$(IDF_TARGET)/spiram_psram.o \
port/$(IDF_TARGET)/sar_periph_ctrl.o
endif
ifdef CONFIG_IDF_TARGET_ESP32

77
components/esp_hw_support/include/esp_private/sar_periph_ctrl.h Normal file
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@@ -0,0 +1,77 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent. This file
* provides a united control to these registers, as multiple
* components require these controls.
*
* See target/sar_periph_ctrl.c to know involved peripherals
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
* Initialise SAR related peripheral register settings
* Should only be used when running into app stage
*/
void sar_periph_ctrl_init(void);
/*------------------------------------------------------------------------------
* ADC Power
*----------------------------------------------------------------------------*/
/**
* @brief Acquire the ADC oneshot mode power
*/
void sar_periph_ctrl_adc_oneshot_power_acquire(void);
/**
* @brief Release the ADC oneshot mode power
*/
void sar_periph_ctrl_adc_oneshot_power_release(void);
/**
* @brief Acquire the ADC continuous mode power
*/
void sar_periph_ctrl_adc_continuous_power_acquire(void);
/**
* @brief Release the ADC ADC continuous mode power
*/
void sar_periph_ctrl_adc_continuous_power_release(void);
/*------------------------------------------------------------------------------
* PWDET Power
*----------------------------------------------------------------------------*/
/**
* @brief Acquire the PWDET Power
*/
void sar_periph_ctrl_pwdet_power_acquire(void);
/**
* @brief Release the PWDET Power
*/
void sar_periph_ctrl_pwdet_power_release(void);
/**
* @brief Enable SAR power when system wakes up
*/
void sar_periph_ctrl_power_enable(void);
/**
* @brief Disable SAR power when system goes to sleep
*/
void sar_periph_ctrl_power_disable(void);
#ifdef __cplusplus
}
#endif

3
components/esp_hw_support/port/esp32/CMakeLists.txt
View File

@@ -16,7 +16,8 @@ if(NOT BOOTLOADER_BUILD)
"dport_access.c"
"esp_himem.c"
"spiram.c"
"spiram_psram.c")
"spiram_psram.c"
"sar_periph_ctrl.c")
endif()
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")

8
components/esp_hw_support/port/esp32/rtc_init.c
View File

@@ -13,6 +13,9 @@
#include "soc/efuse_periph.h"
#include "hal/efuse_ll.h"
#include "soc/gpio_periph.h"
#ifndef BOOTLOADER_BUILD
#include "esp_private/sar_periph_ctrl.h"
#endif
void rtc_init(rtc_config_t cfg)
@@ -95,6 +98,11 @@ void rtc_init(rtc_config_t cfg)
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
#ifndef BOOTLOADER_BUILD
//initialise SAR related peripheral register settings
sar_periph_ctrl_init();
#endif
}
rtc_vddsdio_config_t rtc_vddsdio_get_config(void)

117
components/esp_hw_support/port/esp32/sar_periph_ctrl.c Normal file
View File

@@ -0,0 +1,117 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent. This file
* provides a united control to these registers, as multiple
* components require these controls.
*
* Related peripherals are:
* - ADC
* - PWDET
*/
#include "sdkconfig.h"
#include "esp_log.h"
#include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h"
#include "hal/sar_ctrl_ll.h"
static const char *TAG = "sar_periph_ctrl";
extern portMUX_TYPE rtc_spinlock;
void sar_periph_ctrl_init(void)
{
//Put SAR control mux to ON state
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_ON);
//Add other periph power control initialisation here
}
void sar_periph_ctrl_power_enable(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_ON);
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
void sar_periph_ctrl_power_disable(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
/**
* This gets incremented when s_sar_power_acquire() is called,
* and decremented when s_sar_power_release() is called.
* PWDET is powered down when the value reaches zero.
* Should be modified within critical section.
*/
static int s_sar_power_on_cnt;
static void s_sar_power_acquire(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_sar_power_on_cnt++;
if (s_sar_power_on_cnt == 1) {
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_ON);
}
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
static void s_sar_power_release(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_sar_power_on_cnt--;
if (s_sar_power_on_cnt < 0) {
portEXIT_CRITICAL(&rtc_spinlock);
ESP_LOGE(TAG, "%s called, but s_sar_power_on_cnt == 0", __func__);
abort();
} else if (s_sar_power_on_cnt == 0) {
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
}
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
/*------------------------------------------------------------------------------
* PWDET Power
*----------------------------------------------------------------------------*/
void sar_periph_ctrl_pwdet_power_acquire(void)
{
s_sar_power_acquire();
}
void sar_periph_ctrl_pwdet_power_release(void)
{
s_sar_power_release();
}
/*------------------------------------------------------------------------------
* ADC Power
*----------------------------------------------------------------------------*/
void sar_periph_ctrl_adc_oneshot_power_acquire(void)
{
s_sar_power_acquire();
}
void sar_periph_ctrl_adc_oneshot_power_release(void)
{
s_sar_power_release();
}
void sar_periph_ctrl_adc_continuous_power_acquire(void)
{
s_sar_power_acquire();
}
void sar_periph_ctrl_adc_continuous_power_release(void)
{
s_sar_power_release();
}

130
components/esp_hw_support/port/esp32c2/sar_periph_ctrl.c Normal file
View File

@@ -0,0 +1,130 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent. This file
* provides a united control to these registers, as multiple
* components require these controls.
*
* Related peripherals are:
* - ADC
* - PWDET
* - Temp Sensor
*/
#include "sdkconfig.h"
#include "esp_log.h"
#include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h"
#include "hal/sar_ctrl_ll.h"
#include "hal/adc_ll.h"
static const char *TAG = "sar_periph_ctrl";
extern portMUX_TYPE rtc_spinlock;
void sar_periph_ctrl_init(void)
{
//Put SAR control mux to FSM state
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
//Add other periph power control initialisation here
}
void sar_periph_ctrl_power_enable(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
void sar_periph_ctrl_power_disable(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
/*------------------------------------------------------------------------------
* PWDET Power
*----------------------------------------------------------------------------*/
static int s_pwdet_power_on_cnt;
void sar_periph_ctrl_pwdet_power_acquire(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_pwdet_power_on_cnt++;
if (s_pwdet_power_on_cnt == 1) {
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON);
}
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
void sar_periph_ctrl_pwdet_power_release(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_pwdet_power_on_cnt--;
/* Sanity check */
if (s_pwdet_power_on_cnt < 0) {
portEXIT_CRITICAL(&rtc_spinlock);
ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__);
abort();
} else if (s_pwdet_power_on_cnt == 0) {
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
}
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
/*------------------------------------------------------------------------------
* ADC Power
*----------------------------------------------------------------------------*/
static int s_saradc_power_on_cnt;
static void s_sar_adc_power_acquire(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_saradc_power_on_cnt++;
if (s_saradc_power_on_cnt == 1) {
adc_ll_digi_set_power_manage(ADC_POWER_SW_ON);
}
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
static void s_sar_adc_power_release(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_saradc_power_on_cnt--;
if (s_saradc_power_on_cnt < 0) {
portEXIT_CRITICAL(&rtc_spinlock);
ESP_LOGE(TAG, "%s called, but s_saradc_power_on_cnt == 0", __func__);
abort();
} else if (s_saradc_power_on_cnt == 0) {
adc_ll_digi_set_power_manage(ADC_POWER_BY_FSM);
}
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
void sar_periph_ctrl_adc_oneshot_power_acquire(void)
{
s_sar_adc_power_acquire();
}
void sar_periph_ctrl_adc_oneshot_power_release(void)
{
s_sar_adc_power_release();
}
void sar_periph_ctrl_adc_continuous_power_acquire(void)
{
abort(); //c2 not supported, should never reach here
}
void sar_periph_ctrl_adc_continuous_power_release(void)
{
abort(); //c2 not supported, should never reach here
}

3
components/esp_hw_support/port/esp32c3/CMakeLists.txt
View File

@@ -13,7 +13,8 @@ if(NOT BOOTLOADER_BUILD)
"esp_hmac.c"
"esp_crypto_lock.c"
"esp_ds.c"
"dport_access.c")
"dport_access.c"
"sar_periph_ctrl.c")
if(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE)
list(APPEND srcs "esp_memprot.c" "../esp_memprot_conv.c")

8
components/esp_hw_support/port/esp32c3/rtc_init.c
View File

@@ -19,6 +19,9 @@
#include "soc_log.h"
#include "esp_efuse.h"
#include "esp_efuse_table.h"
#ifndef BOOTLOADER_BUILD
#include "esp_private/sar_periph_ctrl.h"
#endif
static const char *TAG = "rtc_init";
@@ -154,6 +157,11 @@ void rtc_init(rtc_config_t cfg)
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 1);
#ifndef BOOTLOADER_BUILD
//initialise SAR related peripheral register settings
sar_periph_ctrl_init();
#endif
}
rtc_vddsdio_config_t rtc_vddsdio_get_config(void)

130
components/esp_hw_support/port/esp32c3/sar_periph_ctrl.c Normal file
View File

@@ -0,0 +1,130 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent. This file
* provides a united control to these registers, as multiple
* components require these controls.
*
* Related peripherals are:
* - ADC
* - PWDET
* - Temp Sensor
*/
#include "sdkconfig.h"
#include "esp_log.h"
#include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h"
#include "hal/sar_ctrl_ll.h"
#include "hal/adc_ll.h"
static const char *TAG = "sar_periph_ctrl";
extern portMUX_TYPE rtc_spinlock;
void sar_periph_ctrl_init(void)
{
//Put SAR control mux to FSM state
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
//Add other periph power control initialisation here
}
void sar_periph_ctrl_power_enable(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
void sar_periph_ctrl_power_disable(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
/*------------------------------------------------------------------------------
* PWDET Power
*----------------------------------------------------------------------------*/
static int s_pwdet_power_on_cnt;
void sar_periph_ctrl_pwdet_power_acquire(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_pwdet_power_on_cnt++;
if (s_pwdet_power_on_cnt == 1) {
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON);
}
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
void sar_periph_ctrl_pwdet_power_release(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_pwdet_power_on_cnt--;
/* Sanity check */
if (s_pwdet_power_on_cnt < 0) {
portEXIT_CRITICAL(&rtc_spinlock);
ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__);
abort();
} else if (s_pwdet_power_on_cnt == 0) {
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
}
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
/*------------------------------------------------------------------------------
* ADC Power
*----------------------------------------------------------------------------*/
static int s_saradc_power_on_cnt;
static void s_sar_adc_power_acquire(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_saradc_power_on_cnt++;
if (s_saradc_power_on_cnt == 1) {
adc_ll_digi_set_power_manage(ADC_POWER_SW_ON);
}
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
static void s_sar_adc_power_release(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_saradc_power_on_cnt--;
if (s_saradc_power_on_cnt < 0) {
portEXIT_CRITICAL(&rtc_spinlock);
ESP_LOGE(TAG, "%s called, but s_saradc_power_on_cnt == 0", __func__);
abort();
} else if (s_saradc_power_on_cnt == 0) {
adc_ll_digi_set_power_manage(ADC_POWER_BY_FSM);
}
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
void sar_periph_ctrl_adc_oneshot_power_acquire(void)
{
s_sar_adc_power_acquire();
}
void sar_periph_ctrl_adc_oneshot_power_release(void)
{
s_sar_adc_power_release();
}
void sar_periph_ctrl_adc_continuous_power_acquire(void)
{
s_sar_adc_power_acquire();
}
void sar_periph_ctrl_adc_continuous_power_release(void)
{
s_sar_adc_power_release();
}

3
components/esp_hw_support/port/esp32h2/CMakeLists.txt
View File

@@ -13,7 +13,8 @@ if(NOT BOOTLOADER_BUILD)
"esp_hmac.c"
"esp_crypto_lock.c"
"esp_ds.c"
"dport_access.c")
"dport_access.c"
"sar_periph_ctrl.c")
if(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE)
list(APPEND srcs "esp_memprot.c" "../esp_memprot_conv.c")

8
components/esp_hw_support/port/esp32h2/rtc_init.c
View File

@@ -22,6 +22,9 @@
#include "esp_efuse_table.h"
#include "i2c_pmu.h"
#include "soc/clkrst_reg.h"
#ifndef BOOTLOADER_BUILD
#include "esp_private/sar_periph_ctrl.h"
#endif
void pmu_ctl(void);
void dcdc_ctl(uint32_t mode);
@@ -132,6 +135,11 @@ void rtc_init(rtc_config_t cfg)
}
/* config dcdc frequency */
REG_SET_FIELD(RTC_CNTL_DCDC_CTRL0_REG, RTC_CNTL_FSW_DCDC, RTC_CNTL_DCDC_FREQ_DEFAULT);
#ifndef BOOTLOADER_BUILD
//initialise SAR related peripheral register settings
sar_periph_ctrl_init();
#endif
}
void pmu_ctl(void)

110
components/esp_hw_support/port/esp32h2/sar_periph_ctrl.c Normal file
View File

@@ -0,0 +1,110 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent. This file
* provides a united control to these registers, as multiple
* components require these controls.
*
* Related peripherals are:
* - ADC
* - PWDET
*/
#include "sdkconfig.h"
#include "esp_log.h"
#include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h"
#include "hal/sar_ctrl_ll.h"
static const char *TAG = "sar_periph_ctrl";
extern portMUX_TYPE rtc_spinlock;
void sar_periph_ctrl_init(void)
{
//TODO: IDF-6123
}
void sar_periph_ctrl_power_enable(void)
{
//TODO: IDF-6123
}
void sar_periph_ctrl_power_disable(void)
{
//TODO: IDF-6123
}
/**
* This gets incremented when s_sar_power_acquire() is called,
* and decremented when s_sar_power_release() is called.
* PWDET is powered down when the value reaches zero.
* Should be modified within critical section.
*/
static int s_pwdet_power_on_cnt;
static void s_sar_power_acquire(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_pwdet_power_on_cnt++;
if (s_pwdet_power_on_cnt == 1) {
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON);
}
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
static void s_sar_power_release(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_pwdet_power_on_cnt--;
if (s_pwdet_power_on_cnt < 0) {
portEXIT_CRITICAL(&rtc_spinlock);
ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__);
abort();
} else if (s_pwdet_power_on_cnt == 0) {
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
}
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
/*------------------------------------------------------------------------------
* PWDET Power
*----------------------------------------------------------------------------*/
void sar_periph_ctrl_pwdet_power_acquire(void)
{
s_sar_power_acquire();
}
void sar_periph_ctrl_pwdet_power_release(void)
{
s_sar_power_release();
}
/*------------------------------------------------------------------------------
* ADC Power
*----------------------------------------------------------------------------*/
void sar_periph_ctrl_adc_oneshot_power_acquire(void)
{
s_sar_power_acquire();
}
void sar_periph_ctrl_adc_oneshot_power_release(void)
{
s_sar_power_release();
}
void sar_periph_ctrl_adc_continuous_power_acquire(void)
{
s_sar_power_acquire();
}
void sar_periph_ctrl_adc_continuous_power_release(void)
{
s_sar_power_release();
}

3
components/esp_hw_support/port/esp32s2/CMakeLists.txt
View File

@@ -21,7 +21,8 @@ if(NOT BOOTLOADER_BUILD)
"esp_ds.c"
"dport_access.c"
"spiram.c"
"spiram_psram.c")
"spiram_psram.c"
"sar_periph_ctrl.c")
endif()
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")

8
components/esp_hw_support/port/esp32s2/rtc_init.c
View File

@@ -18,6 +18,9 @@
#include "soc_log.h"
#include "esp_efuse.h"
#include "esp_efuse_table.h"
#ifndef BOOTLOADER_BUILD
#include "esp_private/sar_periph_ctrl.h"
#endif
__attribute__((unused)) static const char *TAG = "rtc_init";
@@ -163,6 +166,11 @@ void rtc_init(rtc_config_t cfg)
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
#ifndef BOOTLOADER_BUILD
//initialise SAR related peripheral register settings
sar_periph_ctrl_init();
#endif
}
rtc_vddsdio_config_t rtc_vddsdio_get_config(void)

104
components/esp_hw_support/port/esp32s2/sar_periph_ctrl.c Normal file
View File

@@ -0,0 +1,104 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent. This file
* provides a united control to these registers, as multiple
* components require these controls.
*
* Related peripherals are:
* - ADC
* - PWDET
* - Temp Sensor
*/
#include "sdkconfig.h"
#include "esp_log.h"
#include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h"
#include "hal/sar_ctrl_ll.h"
#include "hal/adc_ll.h"
static const char *TAG = "sar_periph_ctrl";
extern portMUX_TYPE rtc_spinlock;
void sar_periph_ctrl_init(void)
{
//Put SAR control mux to FSM state
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
//Add other periph power control initialisation here
}
void sar_periph_ctrl_power_enable(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
void sar_periph_ctrl_power_disable(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
/*------------------------------------------------------------------------------
* PWDET Power
*----------------------------------------------------------------------------*/
static int s_pwdet_power_on_cnt;
void sar_periph_ctrl_pwdet_power_acquire(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_pwdet_power_on_cnt++;
if (s_pwdet_power_on_cnt == 1) {
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON);
}
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
void sar_periph_ctrl_pwdet_power_release(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_pwdet_power_on_cnt--;
/* Sanity check */
if (s_pwdet_power_on_cnt < 0) {
portEXIT_CRITICAL(&rtc_spinlock);
ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__);
abort();
} else if (s_pwdet_power_on_cnt == 0) {
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
}
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
/*------------------------------------------------------------------------------
* ADC Power
*----------------------------------------------------------------------------*/
void sar_periph_ctrl_adc_oneshot_power_acquire(void)
{
//Keep oneshot mode power controlled by HW, leave this function for compatibility
}
void sar_periph_ctrl_adc_oneshot_power_release(void)
{
//Keep oneshot mode power controlled by HW, leave this function for compatibility
}
void sar_periph_ctrl_adc_continuous_power_acquire(void)
{
adc_ll_digi_set_power_manage(ADC_POWER_SW_ON);
}
void sar_periph_ctrl_adc_continuous_power_release(void)
{
adc_ll_digi_set_power_manage(ADC_POWER_BY_FSM);
}

3
components/esp_hw_support/port/esp32s3/CMakeLists.txt
View File

@@ -18,7 +18,8 @@ if(NOT BOOTLOADER_BUILD)
"esp_hmac.c"
"esp_ds.c"
"esp_crypto_lock.c"
"spiram.c")
"spiram.c"
"sar_periph_ctrl.c")
if(CONFIG_SPIRAM_MODE_QUAD)
list(APPEND srcs "spiram_psram.c")

8
components/esp_hw_support/port/esp32s3/rtc_init.c
View File

@@ -22,6 +22,9 @@
#include "esp_efuse.h"
#include "esp_efuse_table.h"
#include "esp_private/spi_flash_os.h"
#ifndef BOOTLOADER_BUILD
#include "esp_private/sar_periph_ctrl.h"
#endif
#define RTC_CNTL_MEM_FORCE_NOISO (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO)
@@ -194,6 +197,11 @@ void rtc_init(rtc_config_t cfg)
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
#ifndef BOOTLOADER_BUILD
//initialise SAR related peripheral register settings
sar_periph_ctrl_init();
#endif
}
rtc_vddsdio_config_t rtc_vddsdio_get_config(void)

119
components/esp_hw_support/port/esp32s3/sar_periph_ctrl.c Normal file
View File

@@ -0,0 +1,119 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent. This file
* provides a united control to these registers, as multiple
* components require these controls.
*
* Related peripherals are:
* - ADC
* - PWDET
* - Temp Sensor
*/
#include "sdkconfig.h"
#include "esp_log.h"
#include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h"
#include "hal/sar_ctrl_ll.h"
#include "hal/adc_ll.h"
static const char *TAG = "sar_periph_ctrl";
extern portMUX_TYPE rtc_spinlock;
void sar_periph_ctrl_init(void)
{
//Put SAR control mux to FSM state
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_ON);
//Add other periph power control initialisation here
}
void sar_periph_ctrl_power_enable(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
void sar_periph_ctrl_power_disable(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
/**
* This gets incremented when s_sar_power_acquire() is called,
* and decremented when s_sar_power_release() is called.
* PWDET is powered down when the value reaches zero.
* Should be modified within critical section.
*/
static int s_sar_power_on_cnt;
static void s_sar_power_acquire(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_sar_power_on_cnt++;
if (s_sar_power_on_cnt == 1) {
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_ON);
}
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
static void s_sar_power_release(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
s_sar_power_on_cnt--;
if (s_sar_power_on_cnt < 0) {
portEXIT_CRITICAL(&rtc_spinlock);
ESP_LOGE(TAG, "%s called, but s_sar_power_on_cnt == 0", __func__);
abort();
} else if (s_sar_power_on_cnt == 0) {
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
}
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
/*------------------------------------------------------------------------------
* PWDET Power
*----------------------------------------------------------------------------*/
void sar_periph_ctrl_pwdet_power_acquire(void)
{
s_sar_power_acquire();
}
void sar_periph_ctrl_pwdet_power_release(void)
{
s_sar_power_release();
}
/*------------------------------------------------------------------------------
* ADC Power
*----------------------------------------------------------------------------*/
void sar_periph_ctrl_adc_oneshot_power_acquire(void)
{
s_sar_power_acquire();
}
void sar_periph_ctrl_adc_oneshot_power_release(void)
{
s_sar_power_release();
}
void sar_periph_ctrl_adc_continuous_power_acquire(void)
{
s_sar_power_acquire();
}
void sar_periph_ctrl_adc_continuous_power_release(void)
{
s_sar_power_release();
}

9
components/esp_hw_support/sleep_modes.c
View File

@@ -46,6 +46,7 @@
#include "esp_rom_sys.h"
#include "brownout.h"
#include "esp_private/sleep_retention.h"
#include "esp_private/sar_periph_ctrl.h"
#ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/cache.h"
@@ -336,7 +337,7 @@ static void IRAM_ATTR resume_uarts(uint32_t uarts_resume_bmap)
/**
* These save-restore workaround should be moved to lower layer
*/
inline static void IRAM_ATTR misc_modules_sleep_prepare(void)
inline static void IRAM_ATTR misc_modules_sleep_prepare(bool deep_sleep)
{
#if CONFIG_MAC_BB_PD
mac_bb_power_down_cb_execute();
@@ -350,6 +351,9 @@ inline static void IRAM_ATTR misc_modules_sleep_prepare(void)
#if REGI2C_ANA_CALI_PD_WORKAROUND
regi2c_analog_cali_reg_read();
#endif
if (!(deep_sleep && s_adc_tsen_enabled)){
sar_periph_ctrl_power_disable();
}
}
/**
@@ -357,6 +361,7 @@ inline static void IRAM_ATTR misc_modules_sleep_prepare(void)
*/
inline static void IRAM_ATTR misc_modules_wake_prepare(void)
{
sar_periph_ctrl_power_enable();
#if SOC_PM_SUPPORT_CPU_PD || SOC_PM_SUPPORT_TAGMEM_PD
sleep_disable_memory_retention();
#endif
@@ -449,7 +454,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
#endif
}
} else {
misc_modules_sleep_prepare();
misc_modules_sleep_prepare(deep_sleep);
}
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3

16
components/esp_phy/src/phy_override.c
View File

@@ -5,8 +5,9 @@
*/
#include <stdbool.h>
#include "esp_attr.h"
#include "regi2c_ctrl.h"
#include "driver/adc.h"
#include "esp_private/sar_periph_ctrl.h"
/*
* This file is used to override the hooks provided by the PHY lib for some system features.
@@ -32,9 +33,9 @@ void set_xpd_sar(bool en)
s_wifi_adc_xpd_flag = en;
if (en) {
adc_power_acquire();
sar_periph_ctrl_pwdet_power_acquire();
} else {
adc_power_release();
sar_periph_ctrl_pwdet_power_release();
}
}
@@ -48,3 +49,12 @@ IRAM_ATTR void phy_i2c_exit_critical(void)
{
regi2c_exit_critical();
}
void phy_set_pwdet_power(bool en)
{
if (en) {
sar_periph_ctrl_pwdet_power_acquire();
} else {
sar_periph_ctrl_pwdet_power_release();
}
}

25
components/hal/esp32/include/hal/adc_ll.h
View File

@@ -25,13 +25,6 @@ typedef enum {
ADC_NUM_MAX,
} adc_ll_num_t;
typedef enum {
ADC_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */
ADC_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */
ADC_POWER_SW_OFF, /*!< ADC XPD controlled by SW. power off. */
ADC_POWER_MAX, /*!< For parameter check. */
} adc_ll_power_t;
typedef enum {
ADC_RTC_DATA_OK = 0,
} adc_ll_rtc_raw_data_t;
@@ -503,24 +496,6 @@ static inline adc_atten_t adc_ll_get_atten(adc_ll_num_t adc_n, adc_channel_t cha
/*---------------------------------------------------------------
Common setting
---------------------------------------------------------------*/
/**
* Set ADC module power management.
*
* @param manage Set ADC power status.
*/
static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
{
/* Bit1 0:Fsm 1: SW mode
Bit0 0:SW mode power down 1: SW mode power on */
if (manage == ADC_POWER_SW_ON) {
SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_PU;
} else if (manage == ADC_POWER_BY_FSM) {
SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_FSM;
} else if (manage == ADC_POWER_SW_OFF) {
SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_PD;
}
}
/**
* Set ADC module controller.
* There are five SAR ADC controllers:

56
components/hal/esp32/include/hal/sar_ctrl_ll.h Normal file
View File

@@ -0,0 +1,56 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent.
* Related peripherals are:
* - ADC
* - PWDET
*
* All of above peripherals require SAR to work correctly.
* As SAR has some registers that will influence above mentioned peripherals.
* This file gives an abstraction for such registers
*/
#pragma once
#include <stdlib.h>
#include "soc/sens_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM
SAR_CTRL_LL_POWER_ON, //SAR power on
SAR_CTRL_LL_POWER_OFF, //SAR power off
} sar_ctrl_ll_power_t;
/*---------------------------------------------------------------
SAR power control
---------------------------------------------------------------*/
/**
* Set SAR power mode
*
* @param mode See `sar_ctrl_ll_power_t`
*/
static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode)
{
if (mode == SAR_CTRL_LL_POWER_FSM) {
SENS.sar_meas_wait2.force_xpd_sar = 0x0;
} else if (mode == SAR_CTRL_LL_POWER_ON) {
SENS.sar_meas_wait2.force_xpd_sar = 0x3;
} else {
SENS.sar_meas_wait2.force_xpd_sar = 0x2;
}
}
#ifdef __cplusplus
}
#endif

2
components/hal/esp32c3/include/hal/adc_ll.h
View File

@@ -510,7 +510,7 @@ static inline adc_ll_rtc_raw_data_t adc_ll_analysis_raw_data(adc_ll_num_t adc_n,
*
* @param manage Set ADC power status.
*/
static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
static inline void adc_ll_digi_set_power_manage(adc_ll_power_t manage)
{
/* Bit1 0:Fsm 1: SW mode
Bit0 0:SW mode power down 1: SW mode power on */

80
components/hal/esp32c3/include/hal/sar_ctrl_ll.h Normal file
View File

@@ -0,0 +1,80 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent.
* Related peripherals are:
* - ADC
* - PWDET
* - Temp Sensor
*
* All of above peripherals require SAR to work correctly.
* As SAR has some registers that will influence above mentioned peripherals.
* This file gives an abstraction for such registers
*/
#pragma once
#include <stdlib.h>
#include "soc/soc.h"
#include "soc/rtc_cntl_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PWDET_CONF_REG 0x6000E060
#define PWDET_SAR_POWER_FORCE BIT(7)
#define PWDET_SAR_POWER_CNTL BIT(6)
typedef enum {
SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM
SAR_CTRL_LL_POWER_ON, //SAR power on
SAR_CTRL_LL_POWER_OFF, //SAR power off
} sar_ctrl_ll_power_t;
/*---------------------------------------------------------------
SAR power control
---------------------------------------------------------------*/
/**
* Set SAR power mode
*
* @param mode See `sar_ctrl_ll_power_t`
*/
static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode)
{
if (mode == SAR_CTRL_LL_POWER_FSM) {
RTCCNTL.sensor_ctrl.force_xpd_sar = 0x0;
} else if (mode == SAR_CTRL_LL_POWER_ON) {
RTCCNTL.sensor_ctrl.force_xpd_sar = 0x3;
} else {
RTCCNTL.sensor_ctrl.force_xpd_sar = 0x2;
}
}
/**
* @brief Set SAR power mode when controlled by PWDET
*
* @param[in] mode See `sar_ctrl_ll_power_t`
*/
static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode)
{
if (mode == SAR_CTRL_LL_POWER_FSM) {
REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
} else if (mode == SAR_CTRL_LL_POWER_ON) {
REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
} else if (mode == SAR_CTRL_LL_POWER_OFF) {
REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
}
}
#ifdef __cplusplus
}
#endif

14
components/hal/esp32h2/include/hal/adc_ll.h
View File

@@ -512,18 +512,8 @@ static inline adc_ll_rtc_raw_data_t adc_ll_analysis_raw_data(adc_ll_num_t adc_n,
*/
static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
{
/* Bit1 0:Fsm 1: SW mode
Bit0 0:SW mode power down 1: SW mode power on */
if (manage == ADC_POWER_SW_ON) {
APB_SARADC.ctrl.sar_clk_gated = 1;
APB_SARADC.ctrl.xpd_sar_force = 3;
} else if (manage == ADC_POWER_BY_FSM) {
APB_SARADC.ctrl.sar_clk_gated = 1;
APB_SARADC.ctrl.xpd_sar_force = 0;
} else if (manage == ADC_POWER_SW_OFF) {
APB_SARADC.ctrl.sar_clk_gated = 0;
APB_SARADC.ctrl.xpd_sar_force = 2;
}
//HW bug, use `sar_ctrl_ll_set_power_mode_from_pwdet` instead, `APB_SARADC.ctrl.xpd_sar_force` doesn not effect
//Leave here for a record
}
static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t ctrl)

63
components/hal/esp32h2/include/hal/sar_ctrl_ll.h Normal file
View File

@@ -0,0 +1,63 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent.
* Related peripherals are:
* - ADC
* - PWDET
* - Temp Sensor
*
* All of above peripherals require SAR to work correctly.
* As SAR has some registers that will influence above mentioned peripherals.
* This file gives an abstraction for such registers
*/
#pragma once
#include <stdlib.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PWDET_CONF_REG 0x600A8010
#define PWDET_SAR_POWER_FORCE BIT(24)
#define PWDET_SAR_POWER_CNTL BIT(23)
typedef enum {
SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM
SAR_CTRL_LL_POWER_ON, //SAR power on
SAR_CTRL_LL_POWER_OFF, //SAR power off
} sar_ctrl_ll_power_t;
/*---------------------------------------------------------------
SAR power control
---------------------------------------------------------------*/
/**
* @brief Set SAR power mode when controlled by PWDET
*
* @param[in] mode See `sar_ctrl_ll_power_t`
*/
static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode)
{
if (mode == SAR_CTRL_LL_POWER_FSM) {
REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
} else if (mode == SAR_CTRL_LL_POWER_ON) {
REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
} else if (mode == SAR_CTRL_LL_POWER_OFF) {
REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
}
}
#ifdef __cplusplus
}
#endif

16
components/hal/esp32s2/include/hal/adc_ll.h
View File

@@ -852,19 +852,17 @@ static inline adc_atten_t adc_ll_get_atten(adc_ll_num_t adc_n, adc_channel_t cha
*
* @param manage Set ADC power status.
*/
static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
static inline void adc_ll_digi_set_power_manage(adc_ll_power_t manage)
{
/* Bit1 0:Fsm 1: SW mode
Bit0 0:SW mode power down 1: SW mode power on */
if (manage == ADC_POWER_SW_ON) {
SENS.sar_meas1_ctrl1.rtc_saradc_clkgate_en = 1;
SENS.sar_power_xpd_sar.force_xpd_sar = SENS_FORCE_XPD_SAR_PU;
APB_SARADC.ctrl.sar_clk_gated = 1;
APB_SARADC.ctrl.xpd_sar_force = 0x3;
} else if (manage == ADC_POWER_BY_FSM) {
SENS.sar_meas1_ctrl1.rtc_saradc_clkgate_en = 1;
SENS.sar_power_xpd_sar.force_xpd_sar = SENS_FORCE_XPD_SAR_FSM;
APB_SARADC.ctrl.sar_clk_gated = 1;
APB_SARADC.ctrl.xpd_sar_force = 0x0;
} else if (manage == ADC_POWER_SW_OFF) {
SENS.sar_power_xpd_sar.force_xpd_sar = SENS_FORCE_XPD_SAR_PD;
SENS.sar_meas1_ctrl1.rtc_saradc_clkgate_en = 0;
APB_SARADC.ctrl.sar_clk_gated = 0;
APB_SARADC.ctrl.xpd_sar_force = 0x2;
}
}

83
components/hal/esp32s2/include/hal/sar_ctrl_ll.h Normal file
View File

@@ -0,0 +1,83 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent.
* Related peripherals are:
* - ADC
* - PWDET
* - Temp Sensor
*
* All of above peripherals require SAR to work correctly.
* As SAR has some registers that will influence above mentioned peripherals.
* This file gives an abstraction for such registers
*/
#pragma once
#include <stdlib.h>
#include "soc/soc.h"
#include "soc/sens_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PWDET_CONF_REG 0x6000E060
#define PWDET_SAR_POWER_FORCE BIT(7)
#define PWDET_SAR_POWER_CNTL BIT(6)
typedef enum {
SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM
SAR_CTRL_LL_POWER_ON, //SAR power on
SAR_CTRL_LL_POWER_OFF, //SAR power off
} sar_ctrl_ll_power_t;
/*---------------------------------------------------------------
SAR power control
---------------------------------------------------------------*/
/**
* Set SAR power mode
*
* @param mode See `sar_ctrl_ll_power_t`
*/
static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode)
{
if (mode == SAR_CTRL_LL_POWER_FSM) {
SENS.sar_meas1_ctrl1.rtc_saradc_clkgate_en = 1;
SENS.sar_power_xpd_sar.force_xpd_sar = 0x0;
} else if (mode == SAR_CTRL_LL_POWER_ON) {
SENS.sar_meas1_ctrl1.rtc_saradc_clkgate_en = 1;
SENS.sar_power_xpd_sar.force_xpd_sar = 0x3;
} else {
SENS.sar_meas1_ctrl1.rtc_saradc_clkgate_en = 0;
SENS.sar_power_xpd_sar.force_xpd_sar = 0x2;
}
}
/**
* @brief Set SAR power mode when controlled by PWDET
*
* @param[in] mode See `sar_ctrl_ll_power_t`
*/
static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode)
{
if (mode == SAR_CTRL_LL_POWER_FSM) {
REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
} else if (mode == SAR_CTRL_LL_POWER_ON) {
REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
} else if (mode == SAR_CTRL_LL_POWER_OFF) {
REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
}
}
#ifdef __cplusplus
}
#endif

16
components/hal/esp32s3/include/hal/adc_ll.h
View File

@@ -530,19 +530,17 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
*
* @param manage Set ADC power status.
*/
static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
static inline void adc_ll_digi_set_power_manage(adc_ll_power_t manage)
{
/* Bit1 0:Fsm 1: SW mode
Bit0 0:SW mode power down 1: SW mode power on */
if (manage == ADC_POWER_SW_ON) {
SENS.sar_peri_clk_gate_conf.saradc_clk_en = 1;
SENS.sar_power_xpd_sar.force_xpd_sar = 3; //SENS_FORCE_XPD_SAR_PU;
APB_SARADC.ctrl.sar_clk_gated = 1;
APB_SARADC.ctrl.xpd_sar_force = 0x3;
} else if (manage == ADC_POWER_BY_FSM) {
SENS.sar_peri_clk_gate_conf.saradc_clk_en = 1;
SENS.sar_power_xpd_sar.force_xpd_sar = 0; //SENS_FORCE_XPD_SAR_FSM;
APB_SARADC.ctrl.sar_clk_gated = 1;
APB_SARADC.ctrl.xpd_sar_force = 0x0;
} else if (manage == ADC_POWER_SW_OFF) {
SENS.sar_power_xpd_sar.force_xpd_sar = 2; //SENS_FORCE_XPD_SAR_PD;
SENS.sar_peri_clk_gate_conf.saradc_clk_en = 0;
APB_SARADC.ctrl.sar_clk_gated = 0;
APB_SARADC.ctrl.xpd_sar_force = 0x2;
}
}

83
components/hal/esp32s3/include/hal/sar_ctrl_ll.h Normal file
View File

@@ -0,0 +1,83 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent.
* Related peripherals are:
* - ADC
* - PWDET
* - Temp Sensor
*
* All of above peripherals require SAR to work correctly.
* As SAR has some registers that will influence above mentioned peripherals.
* This file gives an abstraction for such registers
*/
#pragma once
#include <stdlib.h>
#include "soc/soc.h"
#include "soc/sens_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PWDET_CONF_REG 0x6000E060
#define PWDET_SAR_POWER_FORCE BIT(7)
#define PWDET_SAR_POWER_CNTL BIT(6)
typedef enum {
SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM
SAR_CTRL_LL_POWER_ON, //SAR power on
SAR_CTRL_LL_POWER_OFF, //SAR power off
} sar_ctrl_ll_power_t;
/*---------------------------------------------------------------
SAR power control
---------------------------------------------------------------*/
/**
* Set SAR power mode
*
* @param mode See `sar_ctrl_ll_power_t`
*/
static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode)
{
if (mode == SAR_CTRL_LL_POWER_FSM) {
SENS.sar_peri_clk_gate_conf.saradc_clk_en = 1;
SENS.sar_power_xpd_sar.force_xpd_sar = 0x0;
} else if (mode == SAR_CTRL_LL_POWER_ON) {
SENS.sar_peri_clk_gate_conf.saradc_clk_en = 1;
SENS.sar_power_xpd_sar.force_xpd_sar = 0x3;
} else {
SENS.sar_peri_clk_gate_conf.saradc_clk_en = 0;
SENS.sar_power_xpd_sar.force_xpd_sar = 0x2;
}
}
/**
* @brief Set SAR power mode when controlled by PWDET
*
* @param[in] mode See `sar_ctrl_ll_power_t`
*/
static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode)
{
if (mode == SAR_CTRL_LL_POWER_FSM) {
REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
} else if (mode == SAR_CTRL_LL_POWER_ON) {
REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
} else if (mode == SAR_CTRL_LL_POWER_OFF) {
REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
}
}
#ifdef __cplusplus
}
#endif

7
components/hal/include/hal/adc_hal.h
View File

@@ -94,13 +94,6 @@ typedef struct adc_hal_digi_ctrlr_cfg_t {
/*---------------------------------------------------------------
Common setting
---------------------------------------------------------------*/
/**
* Set ADC module power management.
*
* @prarm manage Set ADC power status.
*/
#define adc_hal_set_power_manage(manage) adc_ll_set_power_manage(manage)
void adc_hal_set_controller(adc_ll_num_t unit, adc_hal_work_mode_t work_mode);
#if SOC_ADC_ARBITER_SUPPORTED