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Merge branch 'fix/fix_psram_mode_reg_wrong_timing_v5.2' into 'release/v5.2'

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psram: fixed mode reg read bad timing on octal and hex psrams (v5.2)

See merge request espressif/esp-idf!35950
This commit is contained in:
morris
2024-12-25 14:13:13 +08:00
parent 9d1b0c2df7 137cee80d2
commit 610b334c26
2 changed files with 9 additions and 6 deletions
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8
components/esp_psram/device/esp_psram_impl_ap_hex.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -26,6 +26,8 @@
#define AP_HEX_PSRAM_WR_CMD_BITLEN 16
#define AP_HEX_PSRAM_ADDR_BITLEN 32
#define AP_HEX_PSRAM_RD_DUMMY_BITLEN (2*(10-1))
#define AP_HEX_PSRAM_RD_REG_DUMMY_BITLEN (2*(5-1))
#define AP_HEX_PSRAM_RD_REG_DUMMY_BITLEN (2*(5-1))
#define AP_HEX_PSRAM_WR_DUMMY_BITLEN (2*(5-1))
#define AP_HEX_PSRAM_VENDOR_ID 0xD
@ -118,7 +120,7 @@ static void s_init_psram_mode_reg(int spi_num, hex_psram_mode_reg_t *mode_reg_co
int cmd_len = 16;
uint32_t addr = 0x0;
int addr_bit_len = 32;
int dummy = AP_HEX_PSRAM_RD_DUMMY_BITLEN;
int dummy = AP_HEX_PSRAM_RD_REG_DUMMY_BITLEN;
hex_psram_mode_reg_t mode_reg = {0};
int data_bit_len = 16;
@ -176,7 +178,7 @@ static void s_get_psram_mode_reg(int spi_num, hex_psram_mode_reg_t *out_reg)
{
int cmd_len = 16;
int addr_bit_len = 32;
int dummy = AP_HEX_PSRAM_RD_DUMMY_BITLEN;
int dummy = AP_HEX_PSRAM_RD_REG_DUMMY_BITLEN;
int data_bit_len = 16;
//Read MR0~1 register

7
components/esp_psram/esp32s3/esp_psram_impl_octal.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -31,6 +31,7 @@
#define OCT_PSRAM_WR_CMD_BITLEN 16
#define OCT_PSRAM_ADDR_BITLEN 32
#define OCT_PSRAM_RD_DUMMY_BITLEN (2*(10-1))
#define OCT_PSRAM_RD_REG_DUMMY_BITLEN (2*(5-1))
#define OCT_PSRAM_WR_DUMMY_BITLEN (2*(5-1))
#define OCT_PSRAM_CS1_IO SPI_CS1_GPIO_NUM
#define OCT_PSRAM_VENDOR_ID 0xD
@ -115,7 +116,7 @@ static void s_init_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *mode_reg_co
int cmd_len = 16;
uint32_t addr = 0x0; //0x0 is the MR0 register
int addr_bit_len = 32;
int dummy = OCT_PSRAM_RD_DUMMY_BITLEN;
int dummy = OCT_PSRAM_RD_REG_DUMMY_BITLEN;
opi_psram_mode_reg_t mode_reg = {0};
int data_bit_len = 16;
@ -178,7 +179,7 @@ static void s_get_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *out_reg)
esp_rom_spiflash_read_mode_t mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE;
int cmd_len = 16;
int addr_bit_len = 32;
int dummy = OCT_PSRAM_RD_DUMMY_BITLEN;
int dummy = OCT_PSRAM_RD_REG_DUMMY_BITLEN;
int data_bit_len = 16;
//Read MR0~1 register