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Merge branch 'ci/backport_i2s_ci_fix_to_v5.4' into 'release/v5.4'

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ci(i2s): backport i2s ci fix (v5.4)

See merge request espressif/esp-idf!34586
This commit is contained in:
morris
2024-11-15 10:53:39 +08:00
parent af18afd279 76d87acd59
commit 63ef26e9ee
9 changed files with 171 additions and 51 deletions
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21
components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c
View File

@ -114,7 +114,7 @@ static void test_i2s_tdm_master(uint32_t sample_rate, i2s_data_bit_width_t bit_w
if (i2s_channel_read(i2s_tdm_rx_handle, rx_buffer, buf_size, &bytes_read, 1000) != ESP_OK) {
continue;
}
for (int i = 0; i < buf_size && count < TEST_I2S_MAX_DATA; i++) {
for (int i = 0; i < buf_size / sizeof(uint32_t) && count < TEST_I2S_MAX_DATA; i++) {
if (rx_buffer[i] == count) {
count++;
} else if (count != 1) {
@ -240,8 +240,9 @@ TEST_CASE_MULTIPLE_DEVICES("I2S_TDM_full_duplex_test_in_48k_8bits_4slots", "[I2S
test_i2s_tdm_master_48k_8bits_4slots, test_i2s_tdm_slave_48k_8bits_4slots);
/* The I2S source clock can only reach 96Mhz on ESP32H2,
and the max clock source APLL on P4 is 125M,
which can't satisfy the following configurations in slave mode */
#if !CONFIG_IDF_TARGET_ESP32H2
#if !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4
static void test_i2s_tdm_master_48k_16bits_8slots(void)
{
test_i2s_tdm_master(48000, I2S_DATA_BIT_WIDTH_16BIT, I2S_TDM_SLOT0 | I2S_TDM_SLOT1 | I2S_TDM_SLOT2 | I2S_TDM_SLOT3 |
@ -257,8 +258,6 @@ static void test_i2s_tdm_slave_48k_16bits_8slots(void)
TEST_CASE_MULTIPLE_DEVICES("I2S_TDM_full_duplex_test_in_48k_16bits_8slots", "[I2S_TDM]",
test_i2s_tdm_master_48k_16bits_8slots, test_i2s_tdm_slave_48k_16bits_8slots);
// The max clock source APLL on P4 is 125M which can't satisfy the following config in slave mode
#if !CONFIG_IDF_TARGET_ESP32P4
static void test_i2s_tdm_master_96k_16bits_4slots(void)
{
test_i2s_tdm_master(96000, I2S_DATA_BIT_WIDTH_16BIT, I2S_TDM_SLOT0 | I2S_TDM_SLOT1 | I2S_TDM_SLOT2 | I2S_TDM_SLOT3);
@ -271,8 +270,7 @@ static void test_i2s_tdm_slave_96k_16bits_4slots(void)
TEST_CASE_MULTIPLE_DEVICES("I2S_TDM_full_duplex_test_in_96k_16bits_4slots", "[I2S_TDM]",
test_i2s_tdm_master_96k_16bits_4slots, test_i2s_tdm_slave_96k_16bits_4slots);
#endif // !CONFIG_IDF_TARGET_ESP32P4
#endif // !CONFIG_IDF_TARGET_ESP32H2
#endif // !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4
static void test_i2s_external_clk_src(bool is_master, bool is_external)
{
@ -285,22 +283,15 @@ static void test_i2s_external_clk_src(bool is_master, bool is_external)
.slot_cfg = I2S_STD_MSB_SLOT_DEFAULT_CONFIG(16, I2S_SLOT_MODE_STEREO),
.gpio_cfg = TEST_I2S_DEFAULT_GPIO(TEST_I2S_MCK_IO, is_master),
};
std_cfg.clk_cfg.mclk_multiple = I2S_MCLK_MULTIPLE_512;
if (is_external) {
std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_EXTERNAL;
std_cfg.clk_cfg.ext_clk_freq_hz = 11289600;
std_cfg.clk_cfg.ext_clk_freq_hz = 22579200;
}
TEST_ESP_OK(i2s_channel_init_std_mode(tx_handle, &std_cfg));
if (is_master && !is_external) {
i2s_std_slot_config_t slot_cfg = I2S_STD_PHILIPS_SLOT_DEFAULT_CONFIG(16, I2S_SLOT_MODE_STEREO);
memcpy(&std_cfg.slot_cfg, &slot_cfg, sizeof(i2s_std_slot_config_t));
}
TEST_ESP_OK(i2s_channel_init_std_mode(rx_handle, &std_cfg));
if (is_master) {
if (!is_external) {
// Delay bclk to get compensate the data delay
I2S0.rx_timing.rx_bck_out_dm = 1;
}
uint8_t mst_tx_data[4] = {0x12, 0x34, 0x56, 0x78};
size_t w_bytes = 4;
while (w_bytes == 4) {

3
components/hal/esp32c5/include/hal/i2s_ll.h
View File

@ -13,7 +13,6 @@
#pragma once
#include <stdbool.h>
#include "sdkconfig.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/i2s_periph.h"
@ -154,7 +153,7 @@ static inline void i2s_ll_rx_disable_clock(i2s_dev_t *hw)
static inline void i2s_ll_mclk_bind_to_tx_clk(i2s_dev_t *hw)
{
(void)hw;
PCR.i2s_rx_clkm_conf.i2s_mclk_sel = 0; // TODO: need check
PCR.i2s_rx_clkm_conf.i2s_mclk_sel = 0;
}
/**

2
components/hal/esp32c61/include/hal/etm_ll.h
View File

@ -18,6 +18,8 @@
extern "C" {
#endif
#define ETM_LL_SUPPORT_STATUS 1 // Support to get and clear the status of the ETM event and task
/**
* @brief Enable the clock for ETM register
*

146
components/hal/esp32c61/include/hal/i2s_ll.h
View File

@ -18,6 +18,7 @@
#include "soc/i2s_periph.h"
#include "soc/i2s_struct.h"
#include "soc/pcr_struct.h"
#include "soc/soc_etm_struct.h"
#include "soc/soc_etm_source.h"
#include "hal/i2s_types.h"
#include "hal/hal_utils.h"
@ -28,16 +29,16 @@ extern "C" {
#endif
#define I2S_LL_GET_HW(num) (((num) == 0)? (&I2S0) : NULL)
#define I2S_LL_GET_ID(hw) (((hw) == &I2S0)? 0 : -1)
#define I2S_LL_TDM_CH_MASK (0xffff)
#define I2S_LL_PDM_BCK_FACTOR (64)
#define I2S_LL_CLK_FRAC_DIV_N_MAX 256 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the N register is 8 bit-width
#define I2S_LL_CLK_FRAC_DIV_AB_MAX 512 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 9 bit-width
#define I2S_LL_CLK_FRAC_DIV_N_MAX 256 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the N register is 8 bit-width
#define I2S_LL_CLK_FRAC_DIV_AB_MAX 512 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 9 bit-width
#define I2S_LL_PLL_F120M_CLK_FREQ (120 * 1000000) // PLL_F160M_CLK: 120MHz
#define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz
#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
#define I2S_LL_ETM_EVENT_TABLE(i2s_port, chan_dir, event) \
(uint32_t[SOC_I2S_NUM][2][I2S_ETM_EVENT_MAX]){{ \
@ -64,6 +65,7 @@ extern "C" {
#define I2S_LL_ETM_MAX_THRESH_NUM (0x3FFUL)
/**
* @brief Enable the bus clock for I2S module
*
* @param i2s_id The port id of I2S
* @param enable Set true to enable the buf clock
@ -313,13 +315,21 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
{
(void)hw;
/* Workaround for the double division issue.
* The division coefficients must be set in particular sequence.
* And it has to switch to a small division first before setting the target division. */
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_tx_clkm_conf, i2s_tx_clkm_div_num, 2);
PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_yn1 = 0;
PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_y = 1;
PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_z = 0;
PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_x = 0;
/* Set the target mclk division coefficients */
PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_yn1 = yn1;
PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_z = z;
PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_y = y;
PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_x = x;
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_tx_clkm_conf, i2s_tx_clkm_div_num, div_int);
typeof(PCR.i2s_tx_clkm_div_conf) div = {};
div.i2s_tx_clkm_div_x = x;
div.i2s_tx_clkm_div_y = y;
div.i2s_tx_clkm_div_z = z;
div.i2s_tx_clkm_div_yn1 = yn1;
PCR.i2s_tx_clkm_div_conf.val = div.val;
}
/**
@ -335,13 +345,21 @@ static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, ui
static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
{
(void)hw;
/* Workaround for the double division issue.
* The division coefficients must be set in particular sequence.
* And it has to switch to a small division first before setting the target division. */
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_rx_clkm_conf, i2s_rx_clkm_div_num, 2);
PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_yn1 = 0;
PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_y = 1;
PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_z = 0;
PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_x = 0;
/* Set the target mclk division coefficients */
PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_yn1 = yn1;
PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_z = z;
PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_y = y;
PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_x = x;
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_rx_clkm_conf, i2s_rx_clkm_div_num, div_int);
typeof(PCR.i2s_rx_clkm_div_conf) div = {};
div.i2s_rx_clkm_div_x = x;
div.i2s_rx_clkm_div_y = y;
div.i2s_rx_clkm_div_z = z;
div.i2s_rx_clkm_div_yn1 = yn1;
PCR.i2s_rx_clkm_div_conf.val = div.val;
}
/**
@ -352,12 +370,6 @@ static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, ui
*/
static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const hal_utils_clk_div_t *mclk_div)
{
/* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
* Set to particular coefficients first then update to the target coefficients,
* otherwise the clock division might be inaccurate.
* the general idea is to set a value that impossible to calculate from the regular decimal */
i2s_ll_tx_set_raw_clk_div(hw, 7, 317, 7, 3, 0);
uint32_t div_x = 0;
uint32_t div_y = 0;
uint32_t div_z = 0;
@ -392,12 +404,6 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const hal_utils_clk_div_t *mclk_div)
{
/* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
* Set to particular coefficients first then update to the target coefficients,
* otherwise the clock division might be inaccurate.
* the general idea is to set a value that impossible to calculate from the regular decimal */
i2s_ll_rx_set_raw_clk_div(hw, 7, 317, 7, 3, 0);
uint32_t div_x = 0;
uint32_t div_y = 0;
uint32_t div_z = 0;
@ -525,7 +531,7 @@ static inline void i2s_ll_rx_set_sample_bit(i2s_dev_t *hw, uint8_t chan_bit, int
*/
static inline void i2s_ll_tx_set_half_sample_bit(i2s_dev_t *hw, int half_sample_bits)
{
hw->tx_conf1.tx_half_sample_bits = half_sample_bits - 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_conf1, tx_half_sample_bits, half_sample_bits - 1);
}
/**
@ -536,7 +542,7 @@ static inline void i2s_ll_tx_set_half_sample_bit(i2s_dev_t *hw, int half_sample_
*/
static inline void i2s_ll_rx_set_half_sample_bit(i2s_dev_t *hw, int half_sample_bits)
{
hw->rx_conf1.rx_half_sample_bits = half_sample_bits - 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_conf1, rx_half_sample_bits, half_sample_bits - 1);
}
/**
@ -1218,7 +1224,7 @@ static inline uint32_t i2s_ll_tx_get_bclk_sync_count(i2s_dev_t *hw)
* @brief Set the TX ETM threshold of REACH_THRESH event
*
* @param hw Peripheral I2S hardware instance address.
* @param thresh The threshold that send
* @param thresh The threshold that send, in words (4 bytes)
*/
static inline void i2s_ll_tx_set_etm_threshold(i2s_dev_t *hw, uint32_t thresh)
{
@ -1229,13 +1235,89 @@ static inline void i2s_ll_tx_set_etm_threshold(i2s_dev_t *hw, uint32_t thresh)
* @brief Set the RX ETM threshold of REACH_THRESH event
*
* @param hw Peripheral I2S hardware instance address.
* @param thresh The threshold that received
* @param thresh The threshold that received, in words (4 bytes)
*/
static inline void i2s_ll_rx_set_etm_threshold(i2s_dev_t *hw, uint32_t thresh)
{
hw->etm_conf.etm_rx_receive_word_num = thresh;
}
/**
* @brief Get I2S ETM TX done event status
*
* @param hw Peripheral I2S hardware instance address.
* @return
* - true TX done event triggered
* - false TX done event not triggered
*/
static inline bool i2s_ll_get_etm_tx_done_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st2.i2s0_evt_tx_done_st;
default:
HAL_ASSERT(false);
}
}
/**
* @brief Get I2S ETM TX done event status
*
* @param hw Peripheral I2S hardware instance address.
* @return
* - true TX done event triggered
* - false TX done event not triggered
*/
static inline bool i2s_ll_get_etm_rx_done_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st2.i2s0_evt_rx_done_st;
default:
HAL_ASSERT(false);
}
}
/**
* @brief Get I2S ETM TX done event status
*
* @param hw Peripheral I2S hardware instance address.
* @return
* - true TX done event triggered
* - false TX done event not triggered
*/
static inline bool i2s_ll_get_etm_tx_threshold_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st2.i2s0_evt_x_words_sent_st;
default:
HAL_ASSERT(false);
}
}
/**
* @brief Get I2S ETM TX done event status
*
* @param hw Peripheral I2S hardware instance address.
* @return
* - true TX done event triggered
* - false TX done event not triggered
*/
static inline bool i2s_ll_get_etm_rx_threshold_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st2.i2s0_evt_x_words_received_st;
default:
HAL_ASSERT(false);
}
}
#ifdef __cplusplus
}
#endif

1
components/soc/esp32c5/include/soc/soc_caps.h
View File

@ -279,7 +279,6 @@
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_ETM (1)
#define SOC_I2S_SUPPORTS_TX_SYNC_CNT (1)
// #define SOC_I2S_SUPPORTS_RX_RECOMB (1) //TODO[C5] IDF-9966
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PLL_F160M (1)
#define SOC_I2S_SUPPORTS_PLL_F240M (1)

39
components/soc/esp32c61/i2s_periph.c
View File

@ -5,6 +5,7 @@
*/
#include "soc/i2s_periph.h"
#include "soc/i2s_reg.h"
#include "soc/gpio_sig_map.h"
/*
@ -32,3 +33,41 @@ const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
.irq = ETS_I2S0_INTR_SOURCE,
}
};
/**
* I2S Registers to be saved during sleep retention
* - I2S_RX_CONF_REG
* - I2S_TX_CONF_REG
* - I2S_RX_CONF1_REG
* - I2S_TX_CONF1_REG
* - I2S_TX_PCM2PDM_CONF_REG
* - I2S_TX_PCM2PDM_CONF1_REG
* - I2S_RX_TDM_CTRL_REG
* - I2S_TX_TDM_CTRL_REG
* - I2S_RXEOF_NUM_REG
* - I2S_ETM_CONF_REG
*/
#define I2S_RETENTION_REGS_CNT 10
#define I2S_RETENTION_REGS_BASE(i) I2S_RX_CONF_REG
static const uint32_t i2s_regs_map[4] = {0x12360f, 0x0, 0x0, 0x0};
#define I2S_SLEEP_RETENTION_ENTRIES(i2s_port) { \
/* Save/restore the register values */ \
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT( \
REGDMA_I2S_LINK(0x00), \
I2S_RETENTION_REGS_BASE(i2s_port), \
I2S_RETENTION_REGS_BASE(i2s_port), \
I2S_RETENTION_REGS_CNT, 0, 0, \
i2s_regs_map[0], i2s_regs_map[1], \
i2s_regs_map[2], i2s_regs_map[3]), \
.owner = ENTRY(0) | ENTRY(2)}, \
};
static const regdma_entries_config_t i2s0_regs_retention[] = I2S_SLEEP_RETENTION_ENTRIES(0);
const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_NUM] = {
[0] = {
.retention_module = SLEEP_RETENTION_MODULE_I2S0,
.entry_array = i2s0_regs_retention,
.array_size = ARRAY_SIZE(i2s0_regs_retention)
},
};

4
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
View File

@ -495,6 +495,10 @@ config SOC_I2S_SUPPORTS_TDM
bool
default y
config SOC_I2S_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
bool
default y

5
components/soc/esp32c61/include/soc/retention_periph_defs.h
View File

@ -37,6 +37,7 @@ typedef enum periph_retention_module {
SLEEP_RETENTION_MODULE_ETM0 = 16,
SLEEP_RETENTION_MODULE_GPSPI2 = 17,
SLEEP_RETENTION_MODULE_LEDC = 18,
SLEEP_RETENTION_MODULE_I2S0 = 19,
/* Modem module, which includes WiFi, BLE and 802.15.4 */
SLEEP_RETENTION_MODULE_WIFI_MAC = 26,
@ -71,6 +72,7 @@ typedef enum periph_retention_module_bitmap {
SLEEP_RETENTION_MODULE_BM_ETM0 = BIT(SLEEP_RETENTION_MODULE_ETM0),
SLEEP_RETENTION_MODULE_BM_GPSPI2 = BIT(SLEEP_RETENTION_MODULE_GPSPI2),
SLEEP_RETENTION_MODULE_BM_LEDC = BIT(SLEEP_RETENTION_MODULE_LEDC),
SLEEP_RETENTION_MODULE_BM_I2S0 = BIT(SLEEP_RETENTION_MODULE_I2S0),
/* modem module, which includes WiFi, BLE and 802.15.4 */
SLEEP_RETENTION_MODULE_BM_WIFI_MAC = BIT(SLEEP_RETENTION_MODULE_WIFI_MAC),
SLEEP_RETENTION_MODULE_BM_WIFI_BB = BIT(SLEEP_RETENTION_MODULE_WIFI_BB),
@ -93,7 +95,8 @@ typedef enum periph_retention_module_bitmap {
| SLEEP_RETENTION_MODULE_BM_ETM0 \
| SLEEP_RETENTION_MODULE_BM_GPSPI2 \
| SLEEP_RETENTION_MODULE_BM_LEDC \
| SLEEP_RETENTION_MODULE_BM_NULL \
| SLEEP_RETENTION_MODULE_BM_I2S0 \
| SLEEP_RETENTION_MODULE_BM_NULL \
)
#ifdef __cplusplus

1
components/soc/esp32c61/include/soc/soc_caps.h
View File

@ -244,6 +244,7 @@
#define SOC_I2S_SUPPORTS_PDM_TX (1)
#define SOC_I2S_PDM_MAX_TX_LINES (2)
#define SOC_I2S_SUPPORTS_TDM (1)
#define SOC_I2S_SUPPORT_SLEEP_RETENTION (1)
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)