espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-10-01 17:40:57 +02:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'feat/support_esp32h4_sleep_feature' into 'master'

Browse Source 
change(esp_hw_support): support sleep features for esp32h4mp

Closes IDF-13838

See merge request espressif/esp-idf!41951
This commit is contained in:
Li Shuai
2025-09-25 10:05:51 +08:00
parent f3dba4f778 c30ecd8777
commit 661898c90a
6 changed files with 4807 additions and 3111 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3766
components/soc/esp32h4/register/hw_ver_beta5/soc/pmu_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

0
components/soc/esp32h4/register/soc/pmu_struct.h → components/soc/esp32h4/register/hw_ver_beta5/soc/pmu_struct.h
View File

222
components/soc/esp32h4/register/hw_ver_mp/soc/interrupt_matrix_reg.h
View File

@@ -10,10 +10,12 @@
extern "C" { extern "C" {
#endif #endif
#define DR_REG_INTERRUPT_BASE(i) (DR_REG_INTMTX0_BASE + (i) * 0x1000)
/** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG register /** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG register
* WIFI_MAC_INTR mapping register * WIFI_MAC_INTR mapping register
*/ */
#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0) #define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x0)
/** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -32,7 +34,7 @@ extern "C" {
/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG register /** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG register
* WIFI_MAC_NMI mapping register * WIFI_MAC_NMI mapping register
*/ */
#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4) #define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x4)
/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -51,7 +53,7 @@ extern "C" {
/** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG register /** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG register
* WIFI_PWR_INTR mapping register * WIFI_PWR_INTR mapping register
*/ */
#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8) #define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x8)
/** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -70,7 +72,7 @@ extern "C" {
/** INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG register /** INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG register
* WIFI_BB_INTR mapping register * WIFI_BB_INTR mapping register
*/ */
#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc) #define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xc)
/** INTERRUPT_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -89,7 +91,7 @@ extern "C" {
/** INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG register /** INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG register
* BT_MAC_INTR mapping register * BT_MAC_INTR mapping register
*/ */
#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10) #define INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x10)
/** INTERRUPT_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -108,7 +110,7 @@ extern "C" {
/** INTERRUPT_CORE0_BT_BB_INTR_MAP_REG register /** INTERRUPT_CORE0_BT_BB_INTR_MAP_REG register
* BT_BB_INTR mapping register * BT_BB_INTR mapping register
*/ */
#define INTERRUPT_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14) #define INTERRUPT_CORE0_BT_BB_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x14)
/** INTERRUPT_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -127,7 +129,7 @@ extern "C" {
/** INTERRUPT_CORE0_BT_BB_NMI_MAP_REG register /** INTERRUPT_CORE0_BT_BB_NMI_MAP_REG register
* BT_BB_NMI mapping register * BT_BB_NMI mapping register
*/ */
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18) #define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x18)
/** INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -146,7 +148,7 @@ extern "C" {
/** INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG register /** INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG register
* LP_TIMER_INTR mapping register * LP_TIMER_INTR mapping register
*/ */
#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c) #define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x1c)
/** INTERRUPT_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -165,7 +167,7 @@ extern "C" {
/** INTERRUPT_CORE0_COEX_INTR_MAP_REG register /** INTERRUPT_CORE0_COEX_INTR_MAP_REG register
* COEX_INTR mapping register * COEX_INTR mapping register
*/ */
#define INTERRUPT_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20) #define INTERRUPT_CORE0_COEX_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x20)
/** INTERRUPT_CORE0_COEX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_COEX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -184,7 +186,7 @@ extern "C" {
/** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG register /** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG register
* BLE_TIMER_INTR mapping register * BLE_TIMER_INTR mapping register
*/ */
#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24) #define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x24)
/** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -203,7 +205,7 @@ extern "C" {
/** INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG register /** INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG register
* BLE_SEC_INTR mapping register * BLE_SEC_INTR mapping register
*/ */
#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28) #define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x28)
/** INTERRUPT_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -222,7 +224,7 @@ extern "C" {
/** INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG register /** INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG register
* I2C_MST_INTR mapping register * I2C_MST_INTR mapping register
*/ */
#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c) #define INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x2c)
/** INTERRUPT_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -241,7 +243,7 @@ extern "C" {
/** INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG register /** INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG register
* ZB_MAC_INTR mapping register * ZB_MAC_INTR mapping register
*/ */
#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30) #define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x30)
/** INTERRUPT_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -260,7 +262,7 @@ extern "C" {
/** INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_REG register /** INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_REG register
* MODEM_APB_TIMEOUT_INTR mapping register * MODEM_APB_TIMEOUT_INTR mapping register
*/ */
#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34) #define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x34)
/** INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -279,7 +281,7 @@ extern "C" {
/** INTERRUPT_CORE0_BT_MAC_INT1_MAP_REG register /** INTERRUPT_CORE0_BT_MAC_INT1_MAP_REG register
* BT_MAC_INT1 mapping register * BT_MAC_INT1 mapping register
*/ */
#define INTERRUPT_CORE0_BT_MAC_INT1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38) #define INTERRUPT_CORE0_BT_MAC_INT1_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x38)
/** INTERRUPT_CORE0_BT_MAC_INT1_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_BT_MAC_INT1_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -298,7 +300,7 @@ extern "C" {
/** INTERRUPT_CORE0_PMU_INTR_MAP_REG register /** INTERRUPT_CORE0_PMU_INTR_MAP_REG register
* PMU_INTR mapping register * PMU_INTR mapping register
*/ */
#define INTERRUPT_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3c) #define INTERRUPT_CORE0_PMU_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x3c)
/** INTERRUPT_CORE0_PMU_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_PMU_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -317,7 +319,7 @@ extern "C" {
/** INTERRUPT_CORE0_EFUSE_INTR_MAP_REG register /** INTERRUPT_CORE0_EFUSE_INTR_MAP_REG register
* EFUSE_INTR mapping register * EFUSE_INTR mapping register
*/ */
#define INTERRUPT_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40) #define INTERRUPT_CORE0_EFUSE_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x40)
/** INTERRUPT_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -336,7 +338,7 @@ extern "C" {
/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG register /** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG register
* LP_RTC_TIMER_INTR mapping register * LP_RTC_TIMER_INTR mapping register
*/ */
#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44) #define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x44)
/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -355,7 +357,7 @@ extern "C" {
/** INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_REG register /** INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_REG register
* LP_RTC_BLE_TIMER_INTR mapping register * LP_RTC_BLE_TIMER_INTR mapping register
*/ */
#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48) #define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x48)
/** INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -374,7 +376,7 @@ extern "C" {
/** INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG register /** INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG register
* LP_WDT_INTR mapping register * LP_WDT_INTR mapping register
*/ */
#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4c) #define INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x4c)
/** INTERRUPT_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -393,7 +395,7 @@ extern "C" {
/** INTERRUPT_CORE0_TOUCH_INTR_MAP_REG register /** INTERRUPT_CORE0_TOUCH_INTR_MAP_REG register
* TOUCH_INTR mapping register * TOUCH_INTR mapping register
*/ */
#define INTERRUPT_CORE0_TOUCH_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50) #define INTERRUPT_CORE0_TOUCH_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x50)
/** INTERRUPT_CORE0_TOUCH_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_TOUCH_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -412,7 +414,7 @@ extern "C" {
/** INTERRUPT_CORE0_HUK_INTR_MAP_REG register /** INTERRUPT_CORE0_HUK_INTR_MAP_REG register
* HUK_INTR mapping register * HUK_INTR mapping register
*/ */
#define INTERRUPT_CORE0_HUK_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54) #define INTERRUPT_CORE0_HUK_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x54)
/** INTERRUPT_CORE0_HUK_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_HUK_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -431,7 +433,7 @@ extern "C" {
/** INTERRUPT_CORE0_LP_PERI_PMS_INTR_MAP_REG register /** INTERRUPT_CORE0_LP_PERI_PMS_INTR_MAP_REG register
* LP_PERI_PMS_INTR mapping register * LP_PERI_PMS_INTR mapping register
*/ */
#define INTERRUPT_CORE0_LP_PERI_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58) #define INTERRUPT_CORE0_LP_PERI_PMS_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x58)
/** INTERRUPT_CORE0_LP_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_LP_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -450,7 +452,7 @@ extern "C" {
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register
* CPU_INTR_FROM_CPU_0 mapping register * CPU_INTR_FROM_CPU_0 mapping register
*/ */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5c) #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x5c)
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -469,7 +471,7 @@ extern "C" {
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register
* CPU_INTR_FROM_CPU_1 mapping register * CPU_INTR_FROM_CPU_1 mapping register
*/ */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60) #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x60)
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -488,7 +490,7 @@ extern "C" {
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register
* CPU_INTR_FROM_CPU_2 mapping register * CPU_INTR_FROM_CPU_2 mapping register
*/ */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64) #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x64)
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -507,7 +509,7 @@ extern "C" {
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register
* CPU_INTR_FROM_CPU_3 mapping register * CPU_INTR_FROM_CPU_3 mapping register
*/ */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68) #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x68)
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -526,7 +528,7 @@ extern "C" {
/** INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_REG register /** INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_REG register
* BUS_MONITOR_INTR mapping register * BUS_MONITOR_INTR mapping register
*/ */
#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c) #define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x6c)
/** INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -545,7 +547,7 @@ extern "C" {
/** INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_REG register /** INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_REG register
* CORE0_TRACE_INTR mapping register * CORE0_TRACE_INTR mapping register
*/ */
#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70) #define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x70)
/** INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -564,7 +566,7 @@ extern "C" {
/** INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_REG register /** INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_REG register
* CORE1_TRACE_INTR mapping register * CORE1_TRACE_INTR mapping register
*/ */
#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74) #define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x74)
/** INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -583,7 +585,7 @@ extern "C" {
/** INTERRUPT_CORE0_CACHE_INTR_MAP_REG register /** INTERRUPT_CORE0_CACHE_INTR_MAP_REG register
* CACHE_INTR mapping register * CACHE_INTR mapping register
*/ */
#define INTERRUPT_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78) #define INTERRUPT_CORE0_CACHE_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x78)
/** INTERRUPT_CORE0_CACHE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_CACHE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -602,7 +604,7 @@ extern "C" {
/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register /** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register
* CPU_PERI_TIMEOUT_INTR mapping register * CPU_PERI_TIMEOUT_INTR mapping register
*/ */
#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7c) #define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x7c)
/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -621,7 +623,7 @@ extern "C" {
/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register /** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register
* GPIO_INTERRUPT_PRO mapping register * GPIO_INTERRUPT_PRO mapping register
*/ */
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80) #define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x80)
/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -640,7 +642,7 @@ extern "C" {
/** INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_REG register /** INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_REG register
* GPIO_INTERRUPT_2 mapping register * GPIO_INTERRUPT_2 mapping register
*/ */
#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84) #define INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x84)
/** INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -659,7 +661,7 @@ extern "C" {
/** INTERRUPT_CORE0_PAU_INTR_MAP_REG register /** INTERRUPT_CORE0_PAU_INTR_MAP_REG register
* PAU_INTR mapping register * PAU_INTR mapping register
*/ */
#define INTERRUPT_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88) #define INTERRUPT_CORE0_PAU_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x88)
/** INTERRUPT_CORE0_PAU_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_PAU_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -678,7 +680,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register /** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register
* HP_PERI_TIMEOUT_INTR mapping register * HP_PERI_TIMEOUT_INTR mapping register
*/ */
#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c) #define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x8c)
/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -697,7 +699,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG register /** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG register
* HP_APM_M0_INTR mapping register * HP_APM_M0_INTR mapping register
*/ */
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90) #define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x90)
/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -716,7 +718,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG register /** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG register
* HP_APM_M1_INTR mapping register * HP_APM_M1_INTR mapping register
*/ */
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94) #define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x94)
/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -735,7 +737,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG register /** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG register
* HP_APM_M2_INTR mapping register * HP_APM_M2_INTR mapping register
*/ */
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98) #define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x98)
/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -754,7 +756,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG register /** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG register
* HP_APM_M3_INTR mapping register * HP_APM_M3_INTR mapping register
*/ */
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c) #define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x9c)
/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -773,7 +775,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG register /** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG register
* HP_APM_M4_INTR mapping register * HP_APM_M4_INTR mapping register
*/ */
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0) #define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xa0)
/** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -792,7 +794,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_REG register /** INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_REG register
* HP_MEM_APM_M0_INTR mapping register * HP_MEM_APM_M0_INTR mapping register
*/ */
#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa4) #define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xa4)
/** INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -811,7 +813,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_REG register /** INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_REG register
* HP_MEM_APM_M1_INTR mapping register * HP_MEM_APM_M1_INTR mapping register
*/ */
#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8) #define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xa8)
/** INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -830,7 +832,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_REG register /** INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_REG register
* HP_MEM_APM_M2_INTR mapping register * HP_MEM_APM_M2_INTR mapping register
*/ */
#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac) #define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xac)
/** INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -849,7 +851,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_REG register /** INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_REG register
* HP_MEM_APM_M3_INTR mapping register * HP_MEM_APM_M3_INTR mapping register
*/ */
#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0) #define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xb0)
/** INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -868,7 +870,7 @@ extern "C" {
/** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG register /** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG register
* CPU_APM_M0_INTR mapping register * CPU_APM_M0_INTR mapping register
*/ */
#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4) #define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xb4)
/** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -887,7 +889,7 @@ extern "C" {
/** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG register /** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG register
* CPU_APM_M1_INTR mapping register * CPU_APM_M1_INTR mapping register
*/ */
#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8) #define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xb8)
/** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -906,7 +908,7 @@ extern "C" {
/** INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_REG register /** INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_REG register
* CPU_APM_M2_INTR mapping register * CPU_APM_M2_INTR mapping register
*/ */
#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc) #define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xbc)
/** INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -925,7 +927,7 @@ extern "C" {
/** INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_REG register /** INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_REG register
* CPU_APM_M3_INTR mapping register * CPU_APM_M3_INTR mapping register
*/ */
#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0) #define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xc0)
/** INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -944,7 +946,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_PERI_PMS_INTR_MAP_REG register /** INTERRUPT_CORE0_HP_PERI_PMS_INTR_MAP_REG register
* HP_PERI_PMS_INTR mapping register * HP_PERI_PMS_INTR mapping register
*/ */
#define INTERRUPT_CORE0_HP_PERI_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4) #define INTERRUPT_CORE0_HP_PERI_PMS_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xc4)
/** INTERRUPT_CORE0_HP_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_HP_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -963,7 +965,7 @@ extern "C" {
/** INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_MAP_REG register /** INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_MAP_REG register
* MODEM_PERI_PMS_INTR mapping register * MODEM_PERI_PMS_INTR mapping register
*/ */
#define INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8) #define INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xc8)
/** INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -982,7 +984,7 @@ extern "C" {
/** INTERRUPT_CORE0_CPU_PERI_PMS_INTR_MAP_REG register /** INTERRUPT_CORE0_CPU_PERI_PMS_INTR_MAP_REG register
* CPU_PERI_PMS_INTR mapping register * CPU_PERI_PMS_INTR mapping register
*/ */
#define INTERRUPT_CORE0_CPU_PERI_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc) #define INTERRUPT_CORE0_CPU_PERI_PMS_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xcc)
/** INTERRUPT_CORE0_CPU_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_CPU_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1001,7 +1003,7 @@ extern "C" {
/** INTERRUPT_CORE0_MSPI_INTR_MAP_REG register /** INTERRUPT_CORE0_MSPI_INTR_MAP_REG register
* MSPI_INTR mapping register * MSPI_INTR mapping register
*/ */
#define INTERRUPT_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0) #define INTERRUPT_CORE0_MSPI_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xd0)
/** INTERRUPT_CORE0_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1020,7 +1022,7 @@ extern "C" {
/** INTERRUPT_CORE0_I2S_INTR_MAP_REG register /** INTERRUPT_CORE0_I2S_INTR_MAP_REG register
* I2S_INTR mapping register * I2S_INTR mapping register
*/ */
#define INTERRUPT_CORE0_I2S_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4) #define INTERRUPT_CORE0_I2S_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xd4)
/** INTERRUPT_CORE0_I2S_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_I2S_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1039,7 +1041,7 @@ extern "C" {
/** INTERRUPT_CORE0_UHCI0_INTR_MAP_REG register /** INTERRUPT_CORE0_UHCI0_INTR_MAP_REG register
* UHCI0_INTR mapping register * UHCI0_INTR mapping register
*/ */
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8) #define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xd8)
/** INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1058,7 +1060,7 @@ extern "C" {
/** INTERRUPT_CORE0_UART0_INTR_MAP_REG register /** INTERRUPT_CORE0_UART0_INTR_MAP_REG register
* UART0_INTR mapping register * UART0_INTR mapping register
*/ */
#define INTERRUPT_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc) #define INTERRUPT_CORE0_UART0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xdc)
/** INTERRUPT_CORE0_UART0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_UART0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1077,7 +1079,7 @@ extern "C" {
/** INTERRUPT_CORE0_UART1_INTR_MAP_REG register /** INTERRUPT_CORE0_UART1_INTR_MAP_REG register
* UART1_INTR mapping register * UART1_INTR mapping register
*/ */
#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0) #define INTERRUPT_CORE0_UART1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xe0)
/** INTERRUPT_CORE0_UART1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_UART1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1096,7 +1098,7 @@ extern "C" {
/** INTERRUPT_CORE0_LEDC_INTR_MAP_REG register /** INTERRUPT_CORE0_LEDC_INTR_MAP_REG register
* LEDC_INTR mapping register * LEDC_INTR mapping register
*/ */
#define INTERRUPT_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4) #define INTERRUPT_CORE0_LEDC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xe4)
/** INTERRUPT_CORE0_LEDC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_LEDC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1115,7 +1117,7 @@ extern "C" {
/** INTERRUPT_CORE0_CAN0_INTR_MAP_REG register /** INTERRUPT_CORE0_CAN0_INTR_MAP_REG register
* CAN0_INTR mapping register * CAN0_INTR mapping register
*/ */
#define INTERRUPT_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8) #define INTERRUPT_CORE0_CAN0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xe8)
/** INTERRUPT_CORE0_CAN0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_CAN0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1134,7 +1136,7 @@ extern "C" {
/** INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_REG register /** INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_REG register
* CAN0_TIMER_INTR mapping register * CAN0_TIMER_INTR mapping register
*/ */
#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec) #define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xec)
/** INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1153,7 +1155,7 @@ extern "C" {
/** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG register /** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG register
* USB_SERIAL_JTAG_INTR mapping register * USB_SERIAL_JTAG_INTR mapping register
*/ */
#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0) #define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xf0)
/** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1172,7 +1174,7 @@ extern "C" {
/** INTERRUPT_CORE0_RMT_INTR_MAP_REG register /** INTERRUPT_CORE0_RMT_INTR_MAP_REG register
* RMT_INTR mapping register * RMT_INTR mapping register
*/ */
#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4) #define INTERRUPT_CORE0_RMT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xf4)
/** INTERRUPT_CORE0_RMT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_RMT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1191,7 +1193,7 @@ extern "C" {
/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG register /** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG register
* I2C_EXT0_INTR mapping register * I2C_EXT0_INTR mapping register
*/ */
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8) #define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xf8)
/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1210,7 +1212,7 @@ extern "C" {
/** INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_REG register /** INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_REG register
* I2C_EXT1_INTR mapping register * I2C_EXT1_INTR mapping register
*/ */
#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc) #define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0xfc)
/** INTERRUPT_CORE0_I2C_EXT1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_I2C_EXT1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1229,7 +1231,7 @@ extern "C" {
/** INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG register /** INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG register
* TG0_T0_INTR mapping register * TG0_T0_INTR mapping register
*/ */
#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) #define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x100)
/** INTERRUPT_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1248,7 +1250,7 @@ extern "C" {
/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG register /** INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG register
* TG0_WDT_INTR mapping register * TG0_WDT_INTR mapping register
*/ */
#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104) #define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x104)
/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1267,7 +1269,7 @@ extern "C" {
/** INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG register /** INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG register
* TG1_T0_INTR mapping register * TG1_T0_INTR mapping register
*/ */
#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108) #define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x108)
/** INTERRUPT_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1286,7 +1288,7 @@ extern "C" {
/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG register /** INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG register
* TG1_WDT_INTR mapping register * TG1_WDT_INTR mapping register
*/ */
#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c) #define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x10c)
/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1305,7 +1307,7 @@ extern "C" {
/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register /** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register
* SYSTIMER_TARGET0_INTR mapping register * SYSTIMER_TARGET0_INTR mapping register
*/ */
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110) #define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x110)
/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1324,7 +1326,7 @@ extern "C" {
/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register /** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register
* SYSTIMER_TARGET1_INTR mapping register * SYSTIMER_TARGET1_INTR mapping register
*/ */
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114) #define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x114)
/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1343,7 +1345,7 @@ extern "C" {
/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register /** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register
* SYSTIMER_TARGET2_INTR mapping register * SYSTIMER_TARGET2_INTR mapping register
*/ */
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118) #define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x118)
/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1362,7 +1364,7 @@ extern "C" {
/** INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG register /** INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG register
* APB_ADC_INTR mapping register * APB_ADC_INTR mapping register
*/ */
#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c) #define INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x11c)
/** INTERRUPT_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1381,7 +1383,7 @@ extern "C" {
/** INTERRUPT_CORE0_PWM0_INTR_MAP_REG register /** INTERRUPT_CORE0_PWM0_INTR_MAP_REG register
* PWM0_INTR mapping register * PWM0_INTR mapping register
*/ */
#define INTERRUPT_CORE0_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120) #define INTERRUPT_CORE0_PWM0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x120)
/** INTERRUPT_CORE0_PWM0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_PWM0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1400,7 +1402,7 @@ extern "C" {
/** INTERRUPT_CORE0_PWM1_INTR_MAP_REG register /** INTERRUPT_CORE0_PWM1_INTR_MAP_REG register
* PWM1_INTR mapping register * PWM1_INTR mapping register
*/ */
#define INTERRUPT_CORE0_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124) #define INTERRUPT_CORE0_PWM1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x124)
/** INTERRUPT_CORE0_PWM1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_PWM1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1419,7 +1421,7 @@ extern "C" {
/** INTERRUPT_CORE0_PCNT_INTR_MAP_REG register /** INTERRUPT_CORE0_PCNT_INTR_MAP_REG register
* PCNT_INTR mapping register * PCNT_INTR mapping register
*/ */
#define INTERRUPT_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128) #define INTERRUPT_CORE0_PCNT_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x128)
/** INTERRUPT_CORE0_PCNT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_PCNT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1438,7 +1440,7 @@ extern "C" {
/** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG register /** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG register
* PARL_IO_TX_INTR mapping register * PARL_IO_TX_INTR mapping register
*/ */
#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c) #define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x12c)
/** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1457,7 +1459,7 @@ extern "C" {
/** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG register /** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG register
* PARL_IO_RX_INTR mapping register * PARL_IO_RX_INTR mapping register
*/ */
#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130) #define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x130)
/** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1476,7 +1478,7 @@ extern "C" {
/** INTERRUPT_CORE0_USB_OTG11_INTR_MAP_REG register /** INTERRUPT_CORE0_USB_OTG11_INTR_MAP_REG register
* USB_OTG11_INTR mapping register * USB_OTG11_INTR mapping register
*/ */
#define INTERRUPT_CORE0_USB_OTG11_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134) #define INTERRUPT_CORE0_USB_OTG11_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x134)
/** INTERRUPT_CORE0_USB_OTG11_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_USB_OTG11_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1495,7 +1497,7 @@ extern "C" {
/** INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_REG register /** INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_REG register
* ASRC_CHNL0_INTR mapping register * ASRC_CHNL0_INTR mapping register
*/ */
#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138) #define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x138)
/** INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1514,7 +1516,7 @@ extern "C" {
/** INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_REG register /** INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_REG register
* ASRC_CHNL1_INTR mapping register * ASRC_CHNL1_INTR mapping register
*/ */
#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c) #define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x13c)
/** INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1533,7 +1535,7 @@ extern "C" {
/** INTERRUPT_CORE0_ZERO_DET_INTR_MAP_REG register /** INTERRUPT_CORE0_ZERO_DET_INTR_MAP_REG register
* ZERO_DET_INTR mapping register * ZERO_DET_INTR mapping register
*/ */
#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140) #define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x140)
/** INTERRUPT_CORE0_ZERO_DET_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_ZERO_DET_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1552,7 +1554,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG register /** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG register
* DMA_IN_CH0_INTR mapping register * DMA_IN_CH0_INTR mapping register
*/ */
#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144) #define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x144)
/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1571,7 +1573,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG register /** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG register
* DMA_IN_CH1_INTR mapping register * DMA_IN_CH1_INTR mapping register
*/ */
#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148) #define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x148)
/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1590,7 +1592,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG register /** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG register
* DMA_IN_CH2_INTR mapping register * DMA_IN_CH2_INTR mapping register
*/ */
#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c) #define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x14c)
/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1609,7 +1611,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_REG register /** INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_REG register
* DMA_IN_CH3_INTR mapping register * DMA_IN_CH3_INTR mapping register
*/ */
#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150) #define INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x150)
/** INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1628,7 +1630,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_REG register /** INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_REG register
* DMA_IN_CH4_INTR mapping register * DMA_IN_CH4_INTR mapping register
*/ */
#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154) #define INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x154)
/** INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1647,7 +1649,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG register /** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG register
* DMA_OUT_CH0_INTR mapping register * DMA_OUT_CH0_INTR mapping register
*/ */
#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158) #define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x158)
/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1666,7 +1668,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG register /** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG register
* DMA_OUT_CH1_INTR mapping register * DMA_OUT_CH1_INTR mapping register
*/ */
#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15c) #define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x15c)
/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1685,7 +1687,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG register /** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG register
* DMA_OUT_CH2_INTR mapping register * DMA_OUT_CH2_INTR mapping register
*/ */
#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160) #define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x160)
/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1704,7 +1706,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_REG register /** INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_REG register
* DMA_OUT_CH3_INTR mapping register * DMA_OUT_CH3_INTR mapping register
*/ */
#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164) #define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x164)
/** INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1723,7 +1725,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_REG register /** INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_REG register
* DMA_OUT_CH4_INTR mapping register * DMA_OUT_CH4_INTR mapping register
*/ */
#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168) #define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x168)
/** INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1742,7 +1744,7 @@ extern "C" {
/** INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG register /** INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG register
* GPSPI2_INTR mapping register * GPSPI2_INTR mapping register
*/ */
#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16c) #define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x16c)
/** INTERRUPT_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1761,7 +1763,7 @@ extern "C" {
/** INTERRUPT_CORE0_GPSPI3_INTR_MAP_REG register /** INTERRUPT_CORE0_GPSPI3_INTR_MAP_REG register
* GPSPI3_INTR mapping register * GPSPI3_INTR mapping register
*/ */
#define INTERRUPT_CORE0_GPSPI3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170) #define INTERRUPT_CORE0_GPSPI3_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x170)
/** INTERRUPT_CORE0_GPSPI3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_GPSPI3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1780,7 +1782,7 @@ extern "C" {
/** INTERRUPT_CORE0_AES_INTR_MAP_REG register /** INTERRUPT_CORE0_AES_INTR_MAP_REG register
* AES_INTR mapping register * AES_INTR mapping register
*/ */
#define INTERRUPT_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174) #define INTERRUPT_CORE0_AES_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x174)
/** INTERRUPT_CORE0_AES_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_AES_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1799,7 +1801,7 @@ extern "C" {
/** INTERRUPT_CORE0_SHA_INTR_MAP_REG register /** INTERRUPT_CORE0_SHA_INTR_MAP_REG register
* SHA_INTR mapping register * SHA_INTR mapping register
*/ */
#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178) #define INTERRUPT_CORE0_SHA_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x178)
/** INTERRUPT_CORE0_SHA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_SHA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1818,7 +1820,7 @@ extern "C" {
/** INTERRUPT_CORE0_ECC_INTR_MAP_REG register /** INTERRUPT_CORE0_ECC_INTR_MAP_REG register
* ECC_INTR mapping register * ECC_INTR mapping register
*/ */
#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17c) #define INTERRUPT_CORE0_ECC_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x17c)
/** INTERRUPT_CORE0_ECC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_ECC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1837,7 +1839,7 @@ extern "C" {
/** INTERRUPT_CORE0_ECDSA_INTR_MAP_REG register /** INTERRUPT_CORE0_ECDSA_INTR_MAP_REG register
* ECDSA_INTR mapping register * ECDSA_INTR mapping register
*/ */
#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180) #define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x180)
/** INTERRUPT_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1856,7 +1858,7 @@ extern "C" {
/** INTERRUPT_CORE0_KM_INTR_MAP_REG register /** INTERRUPT_CORE0_KM_INTR_MAP_REG register
* KM_INTR mapping register * KM_INTR mapping register
*/ */
#define INTERRUPT_CORE0_KM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184) #define INTERRUPT_CORE0_KM_INTR_MAP_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x184)
/** INTERRUPT_CORE0_KM_INTR_MAP : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_KM_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt. * Configures the interrupt source into one CPU interrupt.
*/ */
@@ -1875,7 +1877,7 @@ extern "C" {
/** INTERRUPT_CORE0_INT_STATUS_REG_0_REG register /** INTERRUPT_CORE0_INT_STATUS_REG_0_REG register
* Status register for interrupt sources 0 ~ 31 * Status register for interrupt sources 0 ~ 31
*/ */
#define INTERRUPT_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188) #define INTERRUPT_CORE0_INT_STATUS_REG_0_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x188)
/** INTERRUPT_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0; /** INTERRUPT_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
* Represents the status of the interrupt sources within interrupt-index-range 0 ~ 31. * Represents the status of the interrupt sources within interrupt-index-range 0 ~ 31.
* Each bit corresponds to one interrupt source * Each bit corresponds to one interrupt source
@@ -1890,7 +1892,7 @@ extern "C" {
/** INTERRUPT_CORE0_INT_STATUS_REG_1_REG register /** INTERRUPT_CORE0_INT_STATUS_REG_1_REG register
* Status register for interrupt sources 32 ~ 63 * Status register for interrupt sources 32 ~ 63
*/ */
#define INTERRUPT_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18c) #define INTERRUPT_CORE0_INT_STATUS_REG_1_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x18c)
/** INTERRUPT_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0; /** INTERRUPT_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
* Represents the status of the interrupt sources within interrupt-index-range 32 ~ * Represents the status of the interrupt sources within interrupt-index-range 32 ~
* 63. Each bit corresponds to one interrupt source * 63. Each bit corresponds to one interrupt source
@@ -1905,7 +1907,7 @@ extern "C" {
/** INTERRUPT_CORE0_INT_STATUS_REG_2_REG register /** INTERRUPT_CORE0_INT_STATUS_REG_2_REG register
* Status register for interrupt sources 64 ~ 95 * Status register for interrupt sources 64 ~ 95
*/ */
#define INTERRUPT_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190) #define INTERRUPT_CORE0_INT_STATUS_REG_2_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x190)
/** INTERRUPT_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0; /** INTERRUPT_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0;
* Represents the status of the interrupt sources within interrupt-index-range 64 ~ * Represents the status of the interrupt sources within interrupt-index-range 64 ~
* 95. Each bit corresponds to one interrupt source * 95. Each bit corresponds to one interrupt source
@@ -1920,7 +1922,7 @@ extern "C" {
/** INTERRUPT_CORE0_INT_STATUS_REG_3_REG register /** INTERRUPT_CORE0_INT_STATUS_REG_3_REG register
* Status register for interrupt sources 96 ~ 97 * Status register for interrupt sources 96 ~ 97
*/ */
#define INTERRUPT_CORE0_INT_STATUS_REG_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194) #define INTERRUPT_CORE0_INT_STATUS_REG_3_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x194)
/** INTERRUPT_CORE0_INT_STATUS_3 : RO; bitpos: [1:0]; default: 0; /** INTERRUPT_CORE0_INT_STATUS_3 : RO; bitpos: [1:0]; default: 0;
* Represents the status of the interrupt sources within interrupt-index-range 96 ~ * Represents the status of the interrupt sources within interrupt-index-range 96 ~
* 97. Each bit corresponds to one interrupt source * 97. Each bit corresponds to one interrupt source
@@ -1935,7 +1937,7 @@ extern "C" {
/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_0_REG register /** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_0_REG register
* PASS_IN_SEC status register for interrupt sources 0 ~ 31 * PASS_IN_SEC status register for interrupt sources 0 ~ 31
*/ */
#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x198) #define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_0_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x198)
/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0 : RO; bitpos: [31:0]; default: 0; /** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0 : RO; bitpos: [31:0]; default: 0;
* Represents the PASS_IN_SEC status of the interrupt sources within * Represents the PASS_IN_SEC status of the interrupt sources within
* interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source * interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source
@@ -1950,7 +1952,7 @@ extern "C" {
/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_1_REG register /** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_1_REG register
* PASS_IN_SEC status register for interrupt sources 32 ~ 63 * PASS_IN_SEC status register for interrupt sources 32 ~ 63
*/ */
#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19c) #define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_1_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x19c)
/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1 : RO; bitpos: [31:0]; default: 0; /** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1 : RO; bitpos: [31:0]; default: 0;
* Represents the PASS_IN_SEC status of the interrupt sources within * Represents the PASS_IN_SEC status of the interrupt sources within
* interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source * interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source
@@ -1965,7 +1967,7 @@ extern "C" {
/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_2_REG register /** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_2_REG register
* PASS_IN_SEC status register for interrupt sources 64 ~ 95 * PASS_IN_SEC status register for interrupt sources 64 ~ 95
*/ */
#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a0) #define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_2_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x1a0)
/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2 : RO; bitpos: [31:0]; default: 0; /** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2 : RO; bitpos: [31:0]; default: 0;
* Represents the PASS_IN_SEC status of the interrupt sources within * Represents the PASS_IN_SEC status of the interrupt sources within
* interrupt-index-range 64 ~ 95. Each bit corresponds to one interrupt source * interrupt-index-range 64 ~ 95. Each bit corresponds to one interrupt source
@@ -1980,7 +1982,7 @@ extern "C" {
/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_3_REG register /** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_3_REG register
* PASS_IN_SEC status register for interrupt sources 96 ~ 97 * PASS_IN_SEC status register for interrupt sources 96 ~ 97
*/ */
#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a4) #define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_3_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x1a4)
/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_3 : RO; bitpos: [1:0]; default: 0; /** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_3 : RO; bitpos: [1:0]; default: 0;
* Represents the PASS_IN_SEC status of the interrupt sources with * Represents the PASS_IN_SEC status of the interrupt sources with
* interrupt-index-range 96 ~ 97. Each bit corresponds to one interrupt source * interrupt-index-range 96 ~ 97. Each bit corresponds to one interrupt source
@@ -1995,7 +1997,7 @@ extern "C" {
/** INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG register /** INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG register
* reserved * reserved
*/ */
#define INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a8) #define INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x1a8)
/** INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC : R/W; bitpos: [5:0]; default: 0; /** INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC : R/W; bitpos: [5:0]; default: 0;
* reserved * reserved
*/ */
@@ -2007,7 +2009,7 @@ extern "C" {
/** INTERRUPT_CORE0_SECURE_STATUS_REG register /** INTERRUPT_CORE0_SECURE_STATUS_REG register
* reserved * reserved
*/ */
#define INTERRUPT_CORE0_SECURE_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1ac) #define INTERRUPT_CORE0_SECURE_STATUS_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x1ac)
/** INTERRUPT_CORE0_INT_SECURE_STATUS : RO; bitpos: [31:0]; default: 0; /** INTERRUPT_CORE0_INT_SECURE_STATUS : RO; bitpos: [31:0]; default: 0;
* reserved * reserved
*/ */
@@ -2019,7 +2021,7 @@ extern "C" {
/** INTERRUPT_CORE0_CLOCK_GATE_REG register /** INTERRUPT_CORE0_CLOCK_GATE_REG register
* Interrupt clock gating configure register * Interrupt clock gating configure register
*/ */
#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b0) #define INTERRUPT_CORE0_CLOCK_GATE_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x1b0)
/** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 0; /** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
* Interrupt clock gating configure register * Interrupt clock gating configure register
*/ */
@@ -2031,7 +2033,7 @@ extern "C" {
/** INTERRUPT_CORE0_INTERRUPT_DATE_REG register /** INTERRUPT_CORE0_INTERRUPT_DATE_REG register
* Version control register * Version control register
*/ */
#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7fc) #define INTERRUPT_CORE0_INTERRUPT_DATE_REG(i) (DR_REG_INTERRUPT_BASE(i) + 0x7fc)
/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 38813760; /** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 38813760;
* Version control register * Version control register
*/ */

0
components/soc/esp32h4/register/soc/pmu_reg.h → components/soc/esp32h4/register/hw_ver_mp/soc/pmu_reg.h
View File

929
components/soc/esp32h4/register/hw_ver_mp/soc/pmu_struct.h Normal file
View File

@@ -0,0 +1,929 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stddef.h>
#ifdef __cplusplus
extern "C"
{
#endif
typedef union {
struct {
uint32_t reserved0 : 18;
uint32_t vdd_flash_mode: 4;
uint32_t mem_dslp : 1;
uint32_t mem_pd_en : 4;
uint32_t wifi_pd_en : 1;
uint32_t peri_pd_en : 1;
uint32_t cpu_pd_en : 1;
uint32_t aon_pd_en : 1;
uint32_t top_pd_en : 1;
};
uint32_t val;
} pmu_hp_dig_power_reg_t;
typedef union {
struct {
uint32_t reserved0: 30;
uint32_t code : 2;
};
uint32_t val;
} pmu_hp_icg_modem_reg_t;
typedef union {
struct {
uint32_t reserved0 : 24;
uint32_t uart_wakeup_en : 1;
uint32_t lp_pad_hold_all: 1;
uint32_t hp_pad_hold_all: 1;
uint32_t dig_pad_slp_sel: 1;
uint32_t dig_pause_wdt : 1;
uint32_t dig_cpu_stall : 1;
uint32_t reserved1 : 2;
};
uint32_t val;
} pmu_hp_sys_cntl_reg_t;
typedef union {
struct {
uint32_t reserved0 : 26;
uint32_t i2c_iso_en : 1;
uint32_t i2c_retention: 1;
uint32_t xpd_bb_i2c : 1;
uint32_t xpd_bbpll_i2c: 1;
uint32_t xpd_bbpll : 1;
uint32_t reserved1 : 1;
};
uint32_t val;
} pmu_hp_clk_power_reg_t;
typedef union {
struct {
uint32_t reserved0 : 9;
uint32_t dcdc_ccm_enb : 1;
uint32_t dcdc_clear_rdy : 1;
uint32_t dig_reg_dpcur_bias: 2;
uint32_t dig_reg_dsfmos : 4;
uint32_t dcm_vset : 5;
uint32_t dcm_mode : 2;
uint32_t xpd_trx : 1;
uint32_t xpd_bias : 1;
uint32_t reserved1 : 3;
uint32_t discnnt_dig_rtc : 1;
uint32_t pd_cur : 1;
uint32_t bias_sleep : 1;
};
uint32_t val;
} pmu_hp_bias_reg_t;
typedef union {
struct { /* HP: Active State */
uint32_t reserved0 : 4;
uint32_t hp_sleep2active_backup_modem_clk_code: 2;
uint32_t hp_modem2active_backup_modem_clk_code: 2;
uint32_t reserved1 : 6;
uint32_t hp_sleep2active_backup_clk_sel : 2;
uint32_t hp_modem2active_backup_clk_sel : 2;
uint32_t hp_sleep2active_backup_mode : 5;
uint32_t hp_modem2active_backup_mode : 5;
uint32_t reserved3 : 1;
uint32_t hp_sleep2active_backup_en : 1;
uint32_t hp_modem2active_backup_en : 1;
uint32_t reserved4 : 1;
};
struct { /* HP: Modem State */
uint32_t reserved5 : 4;
uint32_t hp_sleep2modem_backup_modem_clk_code : 2;
uint32_t reserved6 : 8;
uint32_t hp_sleep2modem_backup_clk_sel : 2;
uint32_t reserved8 : 4;
uint32_t hp_sleep2modem_backup_mode : 5;
uint32_t reserved9 : 4;
uint32_t hp_sleep2modem_backup_en : 1;
uint32_t reserved10 : 2;
};
struct { /* HP: Sleep State */
uint32_t reserved11 : 6;
uint32_t hp_modem2sleep_backup_modem_clk_code : 2;
uint32_t hp_active2sleep_backup_modem_clk_code: 2;
uint32_t reserved12 : 6;
uint32_t hp_modem2sleep_backup_clk_sel : 2;
uint32_t hp_active2sleep_backup_clk_sel : 2;
uint32_t hp_modem2sleep_backup_mode : 5;
uint32_t hp_active2sleep_backup_mode : 5;
uint32_t hp_modem2sleep_backup_en : 1;
uint32_t hp_active2sleep_backup_en : 1;
};
uint32_t val;
} pmu_hp_backup_reg_t;
typedef union {
struct {
uint32_t reserved0 : 26;
uint32_t dig_sysclk_nodiv: 1;
uint32_t icg_sysclk_en : 1;
uint32_t sysclk_slp_sel : 1;
uint32_t icg_slp_sel : 1;
uint32_t dig_sysclk_sel : 2;
};
uint32_t val;
} pmu_hp_sysclk_reg_t;
typedef union {
struct {
uint32_t power_det_bypass: 1;
uint32_t reserved0 : 3;
uint32_t lp_dbias_vol : 5; /* Only HP_ACTIVE mode under hp system is valid */
uint32_t hp_dbias_vol : 5; /* Only HP_ACTIVE mode under hp system is valid */
uint32_t dbias_sel : 1; /* Only HP_ACTIVE mode under hp system is valid */
uint32_t dbias_init : 1; /* Only HP_ACTIVE mode under hp system is valid */
uint32_t slp_mem_xpd : 1;
uint32_t slp_logic_xpd : 1;
uint32_t xpd : 1;
uint32_t slp_mem_dbias : 4;
uint32_t slp_logic_dbias : 4;
uint32_t dbias : 5;
};
uint32_t val;
} pmu_hp_regulator0_reg_t;
typedef union {
struct {
uint32_t reserved0: 8;
uint32_t drv_b : 24;
};
uint32_t val;
} pmu_hp_regulator1_reg_t;
typedef union {
struct {
uint32_t reserved0 : 30;
uint32_t xpd_xtalx2: 1;
uint32_t xpd_xtal : 1;
};
uint32_t val;
} pmu_hp_xtal_reg_t;
typedef struct pmu_hp_hw_regmap {
pmu_hp_dig_power_reg_t dig_power;
uint32_t icg_func;
uint32_t icg_apb;
pmu_hp_icg_modem_reg_t icg_modem;
pmu_hp_sys_cntl_reg_t syscntl;
pmu_hp_clk_power_reg_t clk_power;
pmu_hp_bias_reg_t bias;
pmu_hp_backup_reg_t backup;
uint32_t backup_clk;
pmu_hp_sysclk_reg_t sysclk;
pmu_hp_regulator0_reg_t regulator0;
pmu_hp_regulator1_reg_t regulator1;
pmu_hp_xtal_reg_t xtal;
} pmu_hp_hw_regmap_t;
typedef union {
struct {
uint32_t reserved0: 21;
uint32_t slp_xpd : 1;
uint32_t xpd : 1;
uint32_t slp_dbias: 4;
uint32_t dbias : 5;
};
uint32_t val;
} pmu_lp_regulator0_reg_t;
typedef union {
struct {
uint32_t reserved0: 28;
uint32_t drv_b : 4;
};
uint32_t val;
} pmu_lp_regulator1_reg_t;
typedef union {
struct {
uint32_t reserved0 : 30;
uint32_t xpd_xtalx2: 1;
uint32_t xpd_xtal : 1;
};
uint32_t val;
} pmu_lp_xtal_reg_t;
typedef union {
struct {
uint32_t reserved0 : 23;
uint32_t vdd_io_mode : 4;
uint32_t bod_source_sel: 1;
uint32_t vddbat_mode : 2;
uint32_t mem_dslp : 1;
uint32_t peri_pd_en : 1;
};
uint32_t val;
} pmu_lp_dig_power_reg_t;
typedef union {
struct {
uint32_t reserved0 : 27;
uint32_t xpd_lppll : 1;
uint32_t xpd_xtal32k: 1;
uint32_t xpd_rc32k : 1;
uint32_t xpd_fosc : 1;
uint32_t pd_osc : 1;
};
uint32_t val;
} pmu_lp_clk_power_reg_t;
typedef union {
struct {
uint32_t reserved0 : 9;
uint32_t dcdc_ccm_enb : 1;
uint32_t dcdc_clear_rdy : 1;
uint32_t dig_reg_dpcur_bias: 2;
uint32_t dig_reg_dsfmos : 4;
uint32_t dcm_vset : 5;
uint32_t dcm_mode : 2;
uint32_t reserved1 : 1;
uint32_t xpd_bias : 1;
uint32_t reserved2 : 3;
uint32_t discnnt_dig_rtc : 1;
uint32_t pd_cur : 1;
uint32_t bias_sleep : 1;
};
uint32_t val;
} pmu_lp_bias_reg_t;
typedef struct pmu_lp_hw_regmap {
pmu_lp_regulator0_reg_t regulator0;
pmu_lp_regulator1_reg_t regulator1;
pmu_lp_xtal_reg_t xtal; /* Only LP_SLEEP mode under lp system, xtal is valid */
pmu_lp_dig_power_reg_t dig_power;
pmu_lp_clk_power_reg_t clk_power;
pmu_lp_bias_reg_t bias; /* Only LP_SLEEP mode under lp system, bias is valid */
} pmu_lp_hw_regmap_t;
typedef union {
struct {
uint32_t tie_low_global_bbpll_icg : 1;
uint32_t tie_low_global_xtal_icg : 1;
uint32_t tie_low_i2c_retention : 1;
uint32_t tie_low_xpd_bb_i2c : 1;
uint32_t tie_low_xpd_bbpll_i2c : 1;
uint32_t tie_low_xpd_bbpll : 1;
uint32_t tie_low_xpd_xtal : 1;
uint32_t tie_low_global_xtalx2_icg : 1;
uint32_t tie_low_xpd_xtalx2 : 1;
uint32_t reserved0 : 14;
uint32_t tie_high_xtalx2 : 1;
uint32_t tie_high_global_xtalx2_icg: 1;
uint32_t tie_high_global_bbpll_icg : 1;
uint32_t tie_high_global_xtal_icg : 1;
uint32_t tie_high_i2c_retention : 1;
uint32_t tie_high_xpd_bb_i2c : 1;
uint32_t tie_high_xpd_bbpll_i2c : 1;
uint32_t tie_high_xpd_bbpll : 1;
uint32_t tie_high_xpd_xtal : 1;
};
uint32_t val;
} pmu_imm_hp_clk_power_reg_t;
typedef union {
struct {
uint32_t reserved0 : 28;
uint32_t update_dig_icg_switch: 1;
uint32_t tie_low_icg_slp_sel : 1;
uint32_t tie_high_icg_slp_sel : 1;
uint32_t update_dig_sysclk_sel: 1;
};
uint32_t val;
} pmu_imm_sleep_sysclk_reg_t;
typedef union {
struct {
uint32_t reserved0 : 31;
uint32_t update_dig_icg_func_en: 1;
};
uint32_t val;
} pmu_imm_hp_func_icg_reg_t;
typedef union {
struct {
uint32_t reserved0 : 31;
uint32_t update_dig_icg_apb_en: 1;
};
uint32_t val;
} pmu_imm_hp_apb_icg_reg_t;
typedef union {
struct {
uint32_t reserved0 : 31;
uint32_t update_dig_icg_modem_en: 1;
};
uint32_t val;
} pmu_imm_modem_icg_reg_t;
typedef union {
struct {
uint32_t reserved0 : 30;
uint32_t tie_low_lp_rootclk_sel : 1;
uint32_t tie_high_lp_rootclk_sel: 1;
};
uint32_t val;
} pmu_imm_lp_icg_reg_t;
typedef union {
struct {
uint32_t reserved0 : 26;
uint32_t tie_high_dig_pad_slp_sel: 1;
uint32_t tie_low_dig_pad_slp_sel : 1;
uint32_t tie_high_lp_pad_hold_all: 1;
uint32_t tie_low_lp_pad_hold_all : 1;
uint32_t tie_high_hp_pad_hold_all: 1;
uint32_t tie_low_hp_pad_hold_all : 1;
};
uint32_t val;
} pmu_imm_pad_hold_all_reg_t;
typedef union {
struct {
uint32_t reserved0 : 30;
uint32_t tie_high_i2c_iso_en: 1;
uint32_t tie_low_i2c_iso_en : 1;
};
uint32_t val;
} pmu_imm_i2c_isolate_reg_t;
typedef struct pmu_imm_hw_regmap {
pmu_imm_hp_clk_power_reg_t clk_power;
pmu_imm_sleep_sysclk_reg_t sleep_sysclk;
pmu_imm_hp_func_icg_reg_t hp_func_icg;
pmu_imm_hp_apb_icg_reg_t hp_apb_icg;
pmu_imm_modem_icg_reg_t modem_icg;
pmu_imm_lp_icg_reg_t lp_icg;
pmu_imm_pad_hold_all_reg_t pad_hold_all;
pmu_imm_i2c_isolate_reg_t i2c_iso;
} pmu_imm_hw_regmap_t;
typedef union {
struct {
uint32_t reserved0 : 5;
uint32_t hp_powerdown_timer: 9;
uint32_t hp_powerup_timer : 9;
uint32_t hp_wait_timer : 9;
};
uint32_t val;
} pmu_power_wait_timer0_reg_t;
typedef union {
struct {
uint32_t reserved0 : 9;
uint32_t lp_powerdown_timer: 7;
uint32_t lp_powerup_timer : 7;
uint32_t lp_wait_timer : 9;
};
uint32_t val;
} pmu_power_wait_timer1_reg_t;
typedef union {
struct {
uint32_t lp_iso_wait_timer: 8;
uint32_t lp_rst_wait_timer: 8;
uint32_t hp_iso_wait_timer: 8;
uint32_t hp_rst_wait_timer: 8;
};
uint32_t val;
} pmu_power_wait_timer2_reg_t;
typedef union {
struct {
uint32_t force_reset : 1;
uint32_t force_iso : 1;
uint32_t force_pu : 1;
uint32_t force_no_reset: 1;
uint32_t force_no_iso : 1;
uint32_t force_pd : 1;
uint32_t mask : 5; /* Invalid of lp peripherals */
uint32_t reserved0 : 16; /* Invalid of lp peripherals */
uint32_t pd_mask : 5; /* Invalid of lp peripherals */
};
uint32_t val;
} pmu_power_domain_cntl_reg_t;
typedef union {
struct {
uint32_t force_hp_mem_iso : 4;
uint32_t force_hp_mem_pd : 4;
uint32_t reserved0 : 16;
uint32_t force_hp_mem_no_iso: 4;
uint32_t force_hp_mem_pu : 4;
};
uint32_t val;
} pmu_power_memory_cntl_reg_t;
typedef union {
struct {
uint32_t mem2_pd_mask : 5;
uint32_t mem1_pd_mask : 5;
uint32_t mem0_pd_mask : 5;
uint32_t reserved0 : 2;
uint32_t mem2_mask : 5;
uint32_t mem1_mask : 5;
uint32_t mem0_mask : 5;
};
uint32_t val;
} pmu_power_memory_mask_reg_t;
typedef union {
struct {
uint32_t force_hp_pad_no_iso_all: 1;
uint32_t force_hp_pad_iso_all : 1;
uint32_t reserved0 : 30;
};
uint32_t val;
} pmu_power_hp_pad_reg_t;
typedef union {
struct {
uint32_t ldo_rdy : 1;
uint32_t sw_en_xpd : 1;
uint32_t sw_en_thru : 1;
uint32_t sw_en_standby : 1;
uint32_t sw_en_power_adjust: 1;
uint32_t sw_en_endet : 1;
uint32_t reserved0 : 16;
uint32_t bypass_ldo_rdy : 1;
uint32_t xpd : 1;
uint32_t thru : 1;
uint32_t standby : 1;
uint32_t power_adjust : 4;
uint32_t reserved1 : 1;
uint32_t endet : 1;
};
uint32_t val;
} pmu_power_flash_ldo_reg_t;
typedef union {
struct {
uint32_t reserved0 : 22;
uint32_t ldo_sw_en_tiel : 1;
uint32_t ldo_power_sel : 1;
uint32_t ldo_sw_en_power_sel: 1;
uint32_t ldo_wait_target : 4;
uint32_t ldo_tiel_en : 1;
uint32_t ldo_tiel : 1;
uint32_t ldo_sw_update : 1;
};
uint32_t val;
} pmu_power_vdd_flash_reg_t;
typedef union {
struct {
uint32_t ldo_rdy : 1;
uint32_t sw_en_xpd : 1;
uint32_t reserved0 : 1;
uint32_t sw_en_thru : 1;
uint32_t sw_en_standby : 1;
uint32_t sw_en_power_adjust: 1;
uint32_t sw_en_endet : 1;
uint32_t reserved1 : 15;
uint32_t bypass_ldo_rdy : 1;
uint32_t xpd : 1;
uint32_t thru : 1;
uint32_t standby : 1;
uint32_t power_adjust : 4;
uint32_t reserved2 : 1;
uint32_t endet : 1;
};
uint32_t val;
} pmu_power_io_ldo_reg_t;
typedef union {
struct {
uint32_t reserved0 : 23;
uint32_t ldo_power_sel : 1;
uint32_t ldo_sw_en_power_sel: 1;
uint32_t reserved1 : 7;
};
uint32_t val;
} pmu_power_vdd_io_reg_t;
typedef union {
struct {
uint32_t wait_xtal_stable: 16;
uint32_t wait_pll_stable : 16;
};
uint32_t val;
} pmu_power_clk_wait_cntl_reg_t;
typedef struct pmu_power_hw_regmap {
pmu_power_wait_timer0_reg_t wait_timer0;
pmu_power_wait_timer1_reg_t wait_timer1;
pmu_power_wait_timer2_reg_t wait_timer2;
pmu_power_domain_cntl_reg_t hp_pd[5]; /* Include TOP, HPAON, HPCPU, HPPERI and MODEM power domain */
pmu_power_domain_cntl_reg_t lp_peri;
pmu_power_memory_cntl_reg_t mem_cntl;
pmu_power_memory_mask_reg_t mem_mask;
pmu_power_hp_pad_reg_t hp_pad;
pmu_power_flash_ldo_reg_t flash_ldo[2]; /* Include Flash 1p8 and 1p2 LDO */
pmu_power_vdd_flash_reg_t vdd_flash;
pmu_power_io_ldo_reg_t io_ldo;
pmu_power_vdd_io_reg_t vdd_io;
pmu_power_clk_wait_cntl_reg_t clk_wait;
} pmu_power_hw_regmap_t;
typedef union {
struct {
uint32_t reserved0: 31;
uint32_t sleep_req: 1;
};
uint32_t val;
} pmu_slp_wakeup_cntl0_reg_t;
typedef union {
struct {
uint32_t sleep_reject_ena: 31;
uint32_t slp_reject_en : 1;
};
uint32_t val;
} pmu_slp_wakeup_cntl1_reg_t;
typedef union {
struct {
uint32_t lp_min_slp_val: 8;
uint32_t hp_min_slp_val: 8;
uint32_t sleep_prt_sel : 2;
uint32_t reserved0 : 14;
};
uint32_t val;
} pmu_slp_wakeup_cntl3_reg_t;
typedef union {
struct {
uint32_t reserved0 : 31;
uint32_t slp_reject_cause_clr: 1;
};
uint32_t val;
} pmu_slp_wakeup_cntl4_reg_t;
typedef union {
struct {
uint32_t modem_wait_target : 20;
uint32_t reserved0 : 4;
uint32_t lp_ana_wait_target: 8;
};
uint32_t val;
} pmu_slp_wakeup_cntl5_reg_t;
typedef union {
struct {
uint32_t soc_wakeup_wait : 20;
uint32_t reserved0 : 10;
uint32_t soc_wakeup_wait_cfg: 2;
};
uint32_t val;
} pmu_slp_wakeup_cntl6_reg_t;
typedef union {
struct {
uint32_t reserved0 : 15;
uint32_t ana_wait_clk_sel: 1;
uint32_t ana_wait_target : 16;
};
uint32_t val;
} pmu_slp_wakeup_cntl7_reg_t;
typedef union {
struct {
uint32_t wakeup_cause: 32;
};
uint32_t val;
} pmu_slp_wakeup_status0_reg_t;
typedef union {
struct {
uint32_t reject_cause: 32;
};
uint32_t val;
} pmu_slp_wakeup_status1_reg_t;
typedef struct pmu_wakeup_hw_regmap {
pmu_slp_wakeup_cntl0_reg_t cntl0;
pmu_slp_wakeup_cntl1_reg_t cntl1;
uint32_t cntl2;
pmu_slp_wakeup_cntl3_reg_t cntl3;
pmu_slp_wakeup_cntl4_reg_t cntl4;
pmu_slp_wakeup_cntl5_reg_t cntl5;
pmu_slp_wakeup_cntl6_reg_t cntl6;
pmu_slp_wakeup_cntl7_reg_t cntl7;
pmu_slp_wakeup_status0_reg_t status0;
pmu_slp_wakeup_status1_reg_t status1;
} pmu_wakeup_hw_regmap_t;
typedef union {
struct {
uint32_t i2c_por_wait_target: 8;
uint32_t reserved0 : 24;
};
uint32_t val;
} pmu_hp_clk_poweron_reg_t;
typedef union {
struct {
uint32_t modify_icg_cntl_wait: 8;
uint32_t switch_icg_cntl_wait: 8;
uint32_t reserved0 : 16;
};
uint32_t val;
} pmu_hp_clk_cntl_reg_t;
typedef union {
struct {
uint32_t reserved0: 31;
uint32_t por_done : 1;
};
uint32_t val;
} pmu_por_status_reg_t;
typedef union {
struct {
uint32_t reserved0 : 26;
uint32_t xpd_force_rftx : 1;
uint32_t xpd_perif_i2c : 1;
uint32_t xpd_rftx_i2c : 1;
uint32_t xpd_rfrx_i2c : 1;
uint32_t xpd_rfpll : 1;
uint32_t xpd_force_rfpll: 1;
};
uint32_t val;
} pmu_rf_pwc_reg_t;
typedef union {
struct {
uint32_t vddbat_mode : 2;
uint32_t reserved0 : 29;
uint32_t vddbat_sw_update: 1;
};
uint32_t val;
} pmu_vddbat_cfg_reg_t;
typedef union {
struct {
uint32_t reserved0 : 31;
uint32_t backup_sysclk_nodiv: 1;
};
uint32_t val;
} pmu_backup_cfg_reg_t;
typedef union {
struct {
uint32_t reserved0 : 27;
uint32_t lp_cpu_exc : 1;
uint32_t sdio_idle : 1;
uint32_t sw : 1;
uint32_t soc_sleep_reject: 1;
uint32_t soc_wakeup : 1;
};
uint32_t val;
} pmu_hp_intr_reg_t;
typedef struct pmu_hp_ext_hw_regmap {
pmu_hp_clk_poweron_reg_t clk_poweron;
pmu_hp_clk_cntl_reg_t clk_cntl;
pmu_por_status_reg_t por_status;
pmu_rf_pwc_reg_t rf_pwc;
pmu_vddbat_cfg_reg_t vddbat_cfg;
pmu_backup_cfg_reg_t backup_cfg;
pmu_hp_intr_reg_t int_raw;
pmu_hp_intr_reg_t int_st;
pmu_hp_intr_reg_t int_ena;
pmu_hp_intr_reg_t int_clr;
} pmu_hp_ext_hw_regmap_t;
typedef union {
struct {
uint32_t reserved0 : 20;
uint32_t lp_cpu_wakeup : 1;
uint32_t modem_switch_active_end : 1;
uint32_t sleep_switch_active_end : 1;
uint32_t sleep_switch_modem_end : 1;
uint32_t modem_switch_sleep_end : 1;
uint32_t active_switch_sleep_end : 1;
uint32_t modem_switch_active_start: 1;
uint32_t sleep_switch_active_start: 1;
uint32_t sleep_switch_modem_start : 1;
uint32_t modem_switch_sleep_start : 1;
uint32_t active_switch_sleep_start: 1;
uint32_t hp_sw_trigger : 1;
};
uint32_t val;
} pmu_lp_intr_reg_t;
typedef union {
struct {
uint32_t waiti_rdy : 1;
uint32_t stall_rdy : 1;
uint32_t reserved0 : 16;
uint32_t force_stall : 1;
uint32_t slp_waiti_flag_en : 1;
uint32_t slp_stall_flag_en : 1;
uint32_t slp_stall_wait : 8;
uint32_t slp_stall_en : 1;
uint32_t slp_reset_en : 1;
uint32_t slp_bypass_intr_en: 1;
};
uint32_t val;
} pmu_lp_cpu_pwr0_reg_t;
typedef union {
struct {
uint32_t wakeup_en: 16;
uint32_t reserved0: 15;
uint32_t sleep_req: 1;
};
uint32_t val;
} pmu_lp_cpu_pwr1_reg_t;
typedef struct pmu_lp_ext_hw_regmap {
pmu_lp_intr_reg_t int_raw;
pmu_lp_intr_reg_t int_st;
pmu_lp_intr_reg_t int_ena;
pmu_lp_intr_reg_t int_clr;
pmu_lp_cpu_pwr0_reg_t pwr0;
pmu_lp_cpu_pwr1_reg_t pwr1;
} pmu_lp_ext_hw_regmap_t;
typedef union {
struct {
uint32_t reserved0 : 30;
uint32_t lp_trigger_hp: 1;
uint32_t hp_trigger_lp: 1;
};
uint32_t val;
} pmu_hp_lp_cpu_comm_reg_t;
typedef union {
struct {
uint32_t reserved0 : 31;
uint32_t dig_regulator_en_cal: 1;
};
uint32_t val;
} pmu_hp_regulator_cfg_reg_t;
typedef union {
struct {
uint32_t reserved0 : 11;
uint32_t main_last_st_state: 7;
uint32_t main_tar_st_state : 7;
uint32_t main_cur_st_state : 7;
};
uint32_t val;
} pmu_main_state_reg_t;
typedef union {
struct {
uint32_t reserved0 : 13;
uint32_t backup_st_state: 5;
uint32_t lp_pwr_st_state: 5;
uint32_t hp_pwr_st_state: 9;
};
uint32_t val;
} pmu_pwr_state_reg_t;
typedef union {
struct {
uint32_t stable_xpd_bbpll_state : 1;
uint32_t stable_xpd_xtal_state : 1;
uint32_t reserved0 : 13;
uint32_t sysclk_slp_sel_state : 1;
uint32_t sysclk_sel_state : 2;
uint32_t sysclk_nodiv_state : 1;
uint32_t icg_sysclk_en_state : 1;
uint32_t icg_modem_switch_state : 1;
uint32_t icg_modem_code_state : 2;
uint32_t icg_slp_sel_state : 1;
uint32_t icg_global_xtal_state : 1;
uint32_t icg_global_pll_state : 1;
uint32_t ana_i2c_iso_en_state : 1;
uint32_t ana_i2c_retention_state: 1;
uint32_t ana_xpd_bb_i2c_state : 1;
uint32_t ana_xpd_bbpll_i2c_state: 1;
uint32_t ana_xpd_bbpll_state : 1;
uint32_t ana_xpd_xtal_state : 1;
};
uint32_t val;
} pmu_clk_state0_reg_t;
typedef union {
struct {
uint32_t icg_func_en_state: 32;
};
uint32_t val;
} pmu_clk_state1_reg_t;
typedef union {
struct {
uint32_t icg_apb_en_state: 32;
};
uint32_t val;
} pmu_clk_state2_reg_t;
typedef union {
struct {
uint32_t dsfmos_use_por : 1;
uint32_t reserved0 : 21;
uint32_t dcdc_dcm_update : 1;
uint32_t dcdc_pcur_limit : 3;
uint32_t dcdc_bias_cal_done: 1;
uint32_t dcdc_ccm_sw_en : 1;
uint32_t dcdc_vcm_enb : 1;
uint32_t dcdc_ccm_rdy : 1;
uint32_t dcdc_vcm_rdy : 1;
uint32_t dcdc_rdy_clr : 1;
};
uint32_t val;
} pmu_dcm_ctrl_reg_t;
typedef union {
struct {
uint32_t reserved0 : 24;
uint32_t dcdc_boost_ccm_ctrlen: 1;
uint32_t dcdc_boost_ccm_enb : 1;
uint32_t dcdc_boost_en : 1;
uint32_t dcdc_boost_dreg : 5;
};
uint32_t val;
} pmu_dcm_boost_ctrl_reg_t;
typedef union {
struct {
uint32_t touch_sleep_cycles : 16;
uint32_t reserved0 : 5;
uint32_t touch_wait_cycles : 9;
uint32_t touch_sleep_timer_en: 1;
uint32_t touch_force_done : 1;
};
uint32_t val;
} pmu_touch_pwr_ctrl_reg_t;
typedef union {
struct {
uint32_t reserved_0:23;
/** ext_ocode : R/W; bitpos: [30:23]; default: 120;
* need_des
*/
uint32_t ext_ocode:8;
/** ext_force_ocode : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ext_force_ocode:1;
};
uint32_t val;
} pmu_ble_bandgap_ctrl_reg_t;
typedef struct pmu_dev {
volatile pmu_hp_hw_regmap_t hp_sys[3];
volatile pmu_lp_hw_regmap_t lp_sys[2];
volatile pmu_imm_hw_regmap_t imm;
volatile pmu_power_hw_regmap_t power;
volatile pmu_wakeup_hw_regmap_t wakeup;
volatile pmu_hp_ext_hw_regmap_t hp_ext;
volatile pmu_lp_ext_hw_regmap_t lp_ext;
volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_common;
volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg;
volatile pmu_main_state_reg_t main_state;
volatile pmu_pwr_state_reg_t pwr_state;
volatile pmu_clk_state0_reg_t clk_state0;
volatile pmu_clk_state1_reg_t clk_state1;
volatile pmu_clk_state2_reg_t clk_state2;
volatile pmu_dcm_ctrl_reg_t dcm_ctrl;
volatile pmu_dcm_boost_ctrl_reg_t dcm_boost_ctrl;
volatile pmu_touch_pwr_ctrl_reg_t touch_pwr_ctrl;
volatile pmu_ble_bandgap_ctrl_reg_t ble_bandgap_ctrl;
uint32_t reserved[141];
union {
struct {
uint32_t pmu_date: 31;
uint32_t clk_en : 1;
};
uint32_t val;
} date;
} pmu_dev_t;
extern pmu_dev_t PMU;
#ifndef __cplusplus
_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

3001
components/soc/esp32h4/register/soc/pmu_struct_mp.h
View File

File diff suppressed because it is too large Load Diff