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Merge branch 'change/change_msync_vaddr_not_cacheable_behaviour' into 'master'
cache: when vaddr is not cacheable, msync will return not supported See merge request espressif/esp-idf!41105
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@@ -101,7 +101,10 @@ esp_err_t esp_cache_msync(void *addr, size_t size, int flags)
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uint32_t cache_level = 0;
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uint32_t cache_level = 0;
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uint32_t cache_id = 0;
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uint32_t cache_id = 0;
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valid = cache_hal_vaddr_to_cache_level_id(vaddr, size, &cache_level, &cache_id);
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valid = cache_hal_vaddr_to_cache_level_id(vaddr, size, &cache_level, &cache_id);
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ESP_RETURN_ON_FALSE_ISR(valid, ESP_ERR_INVALID_ARG, TAG, "invalid addr or null pointer");
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if (!valid) {
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ESP_EARLY_LOGD(TAG, "vaddr is not in cacheable range, do nothing");
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return ESP_ERR_NOT_SUPPORTED;
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}
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cache_type_t cache_type = CACHE_TYPE_DATA;
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cache_type_t cache_type = CACHE_TYPE_DATA;
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if (flags & ESP_CACHE_MSYNC_FLAG_TYPE_INST) {
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if (flags & ESP_CACHE_MSYNC_FLAG_TYPE_INST) {
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@@ -76,6 +76,7 @@ extern "C" {
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* - Successful msync
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* - Successful msync
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* - For C2M direction, if this chip doesn't support cache writeback, if the input addr is a cache supported one, this API will return ESP_OK
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* - For C2M direction, if this chip doesn't support cache writeback, if the input addr is a cache supported one, this API will return ESP_OK
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* - ESP_ERR_INVALID_ARG: Invalid argument, not cache supported addr, see printed logs
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* - ESP_ERR_INVALID_ARG: Invalid argument, not cache supported addr, see printed logs
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* - ESP_ERR_NOT_SUPPORTED: Vaddr is not in cacheable range, API will do nothing
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*/
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*/
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esp_err_t esp_cache_msync(void *addr, size_t size, int flags);
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esp_err_t esp_cache_msync(void *addr, size_t size, int flags);
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