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Merge branch 'change/change_msync_vaddr_not_cacheable_behaviour' into 'master'

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cache: when vaddr is not cacheable, msync will return not supported

See merge request espressif/esp-idf!41105
This commit is contained in:
Armando (Dou Yiwen)
2025-08-14 01:21:33 +00:00
parent 5046f31c1b 71a09b82a4
commit 68cbef3175
2 changed files with 5 additions and 1 deletions
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5
components/esp_mm/esp_cache_msync.c
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@@ -101,7 +101,10 @@ esp_err_t esp_cache_msync(void *addr, size_t size, int flags)
uint32_t cache_level = 0;
uint32_t cache_id = 0;
valid = cache_hal_vaddr_to_cache_level_id(vaddr, size, &cache_level, &cache_id);
ESP_RETURN_ON_FALSE_ISR(valid, ESP_ERR_INVALID_ARG, TAG, "invalid addr or null pointer");
if (!valid) {
ESP_EARLY_LOGD(TAG, "vaddr is not in cacheable range, do nothing");
return ESP_ERR_NOT_SUPPORTED;
}
cache_type_t cache_type = CACHE_TYPE_DATA;
if (flags & ESP_CACHE_MSYNC_FLAG_TYPE_INST) {

1
components/esp_mm/include/esp_cache.h
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@@ -76,6 +76,7 @@ extern "C" {
* - Successful msync
* - For C2M direction, if this chip doesn't support cache writeback, if the input addr is a cache supported one, this API will return ESP_OK
* - ESP_ERR_INVALID_ARG: Invalid argument, not cache supported addr, see printed logs
* - ESP_ERR_NOT_SUPPORTED: Vaddr is not in cacheable range, API will do nothing
*/
esp_err_t esp_cache_msync(void *addr, size_t size, int flags);