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Fix the int_enable_flag may not compile without bt problem
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@@ -1450,7 +1450,7 @@ void IRAM_ATTR __attribute__((noinline)) r_assert(const char *condition, int par
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#define BT_INT_STA_REG (0x3FF7100C)
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#define BT_INT_STA_REG (0x3FF7100C)
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#define BLE_INT_STA_REG (0x3FF71210)
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#define BLE_INT_STA_REG (0x3FF71210)
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int _int_enable_flag=0;
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extern int _int_enable_flag;
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extern bool connection_is_alive();
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extern bool connection_is_alive();
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extern uint32_t real_bt_isr_count ;
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extern uint32_t real_bt_isr_count ;
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@@ -40,6 +40,7 @@
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static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
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static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
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static volatile uint32_t reason[ portNUM_PROCESSORS ];
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static volatile uint32_t reason[ portNUM_PROCESSORS ];
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int _int_enable_flag = 0;
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/*
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/*
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ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
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ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
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@@ -78,7 +79,6 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) {
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*/
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*/
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}
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}
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if(my_reason_val & REASON_GET_INT) {
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if(my_reason_val & REASON_GET_INT) {
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extern int _int_enable_flag;
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asm volatile ("rsr %0, INTENABLE\n" :"=r"(_int_enable_flag));
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asm volatile ("rsr %0, INTENABLE\n" :"=r"(_int_enable_flag));
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}
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}
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}
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}
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