espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-01 03:34:32 +02:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'change/esp_ldo_reserve_for_spi_flash_v5.4' into 'release/v5.4'

Browse Source 
LDO calibration on ESP32-P4 (v5.4)

See merge request espressif/esp-idf!34864
This commit is contained in:
morris
2024-11-13 17:11:39 +08:00
parent 09f1411389 e5a5cb8779
commit 6932df2ce8
10 changed files with 1963 additions and 197 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1018
components/efuse/esp32p4/esp_efuse_table.c
View File

File diff suppressed because it is too large Load Diff

116
components/efuse/esp32p4/esp_efuse_table.csv
View File

@@ -9,7 +9,7 @@
# this will generate new source files, next rebuild all the sources.
# !!!!!!!!!!! #
# This file was generated by regtools.py based on the efuses.yaml file with the version: d4a48929387e281bd05db8cfb3a85f60
# This file was generated by regtools.py based on the efuses.yaml file with the version: 73787d3f5ae45b80abca925a7562120b
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
@@ -79,7 +79,35 @@ WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis
WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR
WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
WR_DIS.LDO_VO1_DREF, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO1_DREF
WR_DIS.LDO_VO2_DREF, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO2_DREF
WR_DIS.LDO_VO1_MUL, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO1_MUL
WR_DIS.LDO_VO2_MUL, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO2_MUL
WR_DIS.LDO_VO3_K, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO3_K
WR_DIS.LDO_VO3_VOS, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO3_VOS
WR_DIS.LDO_VO3_C, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO3_C
WR_DIS.LDO_VO4_K, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO4_K
WR_DIS.LDO_VO4_VOS, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO4_VOS
WR_DIS.LDO_VO4_C, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO4_C
WR_DIS.ACTIVE_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_HP_DBIAS
WR_DIS.ACTIVE_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_LP_DBIAS
WR_DIS.LSLP_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBIAS
WR_DIS.DSLP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_DBG
WR_DIS.DSLP_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBIAS
WR_DIS.LP_DCDC_DBIAS_VOL_GAP, EFUSE_BLK0, 20, 1, [] wr_dis of LP_DCDC_DBIAS_VOL_GAP
WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
WR_DIS.ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
WR_DIS.ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
WR_DIS.ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
WR_DIS.ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
WR_DIS.ADC2_AVE_INITCODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN0
WR_DIS.ADC2_AVE_INITCODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN1
WR_DIS.ADC2_AVE_INITCODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN2
WR_DIS.ADC2_AVE_INITCODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN3
WR_DIS.ADC1_HI_DOUT_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN0
WR_DIS.ADC1_HI_DOUT_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN1
WR_DIS.ADC1_HI_DOUT_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN2
WR_DIS.ADC1_HI_DOUT_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN3
WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
@@ -89,6 +117,25 @@ WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.K
WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
WR_DIS.ADC2_HI_DOUT_ATTEN0, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN0
WR_DIS.ADC2_HI_DOUT_ATTEN1, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN1
WR_DIS.ADC2_HI_DOUT_ATTEN2, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN2
WR_DIS.ADC2_HI_DOUT_ATTEN3, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN3
WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH6_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH7_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF
WR_DIS.ADC2_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF
WR_DIS.ADC2_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF
WR_DIS.ADC2_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF
WR_DIS.ADC2_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF
WR_DIS.ADC2_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF
WR_DIS.ADC2_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF
WR_DIS.TEMPERATURE_SENSOR, EFUSE_BLK0, 29, 1, [] wr_dis of TEMPERATURE_SENSOR
WR_DIS.USB_DEVICE_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_DEVICE_EXCHG_PINS
WR_DIS.USB_OTG11_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_OTG11_EXCHG_PINS
WR_DIS.USB_PHY_SEL, EFUSE_BLK0, 30, 1, [] wr_dis of USB_PHY_SEL
@@ -101,6 +148,25 @@ RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.K
RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
RD_DIS.ADC2_HI_DOUT_ATTEN0, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN0
RD_DIS.ADC2_HI_DOUT_ATTEN1, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN1
RD_DIS.ADC2_HI_DOUT_ATTEN2, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN2
RD_DIS.ADC2_HI_DOUT_ATTEN3, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN3
RD_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH6_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH7_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF
RD_DIS.ADC2_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF
RD_DIS.ADC2_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF
RD_DIS.ADC2_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF
RD_DIS.ADC2_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF
RD_DIS.ADC2_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF
RD_DIS.ADC2_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF
RD_DIS.TEMPERATURE_SENSOR, EFUSE_BLK0, 38, 1, [] rd_dis of TEMPERATURE_SENSOR
USB_DEVICE_EXCHG_PINS, EFUSE_BLK0, 39, 1, [] Enable usb device exchange pins of D+ and D-
USB_OTG11_EXCHG_PINS, EFUSE_BLK0, 40, 1, [] Enable usb otg11 exchange pins of D+ and D-
DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled
@@ -177,7 +243,35 @@ PSRAM_CAP, EFUSE_BLK1, 77, 3, [] PSRAM
TEMP, EFUSE_BLK1, 80, 2, [] Operating temperature of the ESP chip
PSRAM_VENDOR, EFUSE_BLK1, 82, 2, [] PSRAM vendor
PKG_VERSION, EFUSE_BLK1, 84, 3, [] Package version
LDO_VO1_DREF, EFUSE_BLK1, 88, 4, [] Output VO1 parameter
LDO_VO2_DREF, EFUSE_BLK1, 92, 4, [] Output VO2 parameter
LDO_VO1_MUL, EFUSE_BLK1, 96, 3, [] Output VO1 parameter
LDO_VO2_MUL, EFUSE_BLK1, 99, 3, [] Output VO2 parameter
LDO_VO3_K, EFUSE_BLK1, 102, 8, [] Output VO3 calibration parameter
LDO_VO3_VOS, EFUSE_BLK1, 110, 6, [] Output VO3 calibration parameter
LDO_VO3_C, EFUSE_BLK1, 116, 6, [] Output VO3 calibration parameter
LDO_VO4_K, EFUSE_BLK1, 122, 8, [] Output VO4 calibration parameter
LDO_VO4_VOS, EFUSE_BLK1, 130, 6, [] Output VO4 calibration parameter
LDO_VO4_C, EFUSE_BLK1, 136, 6, [] Output VO4 calibration parameter
ACTIVE_HP_DBIAS, EFUSE_BLK1, 144, 4, [] Active HP DBIAS of fixed voltage
ACTIVE_LP_DBIAS, EFUSE_BLK1, 148, 4, [] Active LP DBIAS of fixed voltage
LSLP_HP_DBIAS, EFUSE_BLK1, 152, 4, [] LSLP HP DBIAS of fixed voltage
DSLP_DBG, EFUSE_BLK1, 156, 4, [] DSLP BDG of fixed voltage
DSLP_LP_DBIAS, EFUSE_BLK1, 160, 5, [] DSLP LP DBIAS of fixed voltage
LP_DCDC_DBIAS_VOL_GAP, EFUSE_BLK1, 165, 5, [] DBIAS gap between LP and DCDC
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK2, 128, 10, [] Average initcode of ADC1 atten0
ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK2, 138, 10, [] Average initcode of ADC1 atten1
ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK2, 148, 10, [] Average initcode of ADC1 atten2
ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK2, 158, 10, [] Average initcode of ADC1 atten3
ADC2_AVE_INITCODE_ATTEN0, EFUSE_BLK2, 168, 10, [] Average initcode of ADC2 atten0
ADC2_AVE_INITCODE_ATTEN1, EFUSE_BLK2, 178, 10, [] Average initcode of ADC2 atten1
ADC2_AVE_INITCODE_ATTEN2, EFUSE_BLK2, 188, 10, [] Average initcode of ADC2 atten2
ADC2_AVE_INITCODE_ATTEN3, EFUSE_BLK2, 198, 10, [] Average initcode of ADC2 atten3
ADC1_HI_DOUT_ATTEN0, EFUSE_BLK2, 208, 10, [] HI_DOUT of ADC1 atten0
ADC1_HI_DOUT_ATTEN1, EFUSE_BLK2, 218, 10, [] HI_DOUT of ADC1 atten1
ADC1_HI_DOUT_ATTEN2, EFUSE_BLK2, 228, 10, [] HI_DOUT of ADC1 atten2
ADC1_HI_DOUT_ATTEN3, EFUSE_BLK2, 238, 10, [] HI_DOUT of ADC1 atten3
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
@@ -186,4 +280,22 @@ KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KE
KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data
KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data
KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)
ADC2_HI_DOUT_ATTEN0, EFUSE_BLK10, 0, 10, [] HI_DOUT of ADC2 atten0
ADC2_HI_DOUT_ATTEN1, EFUSE_BLK10, 10, 10, [] HI_DOUT of ADC2 atten1
ADC2_HI_DOUT_ATTEN2, EFUSE_BLK10, 20, 10, [] HI_DOUT of ADC2 atten2
ADC2_HI_DOUT_ATTEN3, EFUSE_BLK10, 30, 10, [] HI_DOUT of ADC2 atten3
ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 40, 4, [] Gap between ADC1_ch0 and average initcode
ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 44, 4, [] Gap between ADC1_ch1 and average initcode
ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 48, 4, [] Gap between ADC1_ch2 and average initcode
ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 52, 4, [] Gap between ADC1_ch3 and average initcode
ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 56, 4, [] Gap between ADC1_ch4 and average initcode
ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 60, 4, [] Gap between ADC1_ch5 and average initcode
ADC1_CH6_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 64, 4, [] Gap between ADC1_ch6 and average initcode
ADC1_CH7_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 68, 4, [] Gap between ADC1_ch7 and average initcode
ADC2_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 72, 4, [] Gap between ADC2_ch0 and average initcode
ADC2_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 76, 4, [] Gap between ADC2_ch1 and average initcode
ADC2_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 80, 4, [] Gap between ADC2_ch2 and average initcode
ADC2_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 84, 4, [] Gap between ADC2_ch3 and average initcode
ADC2_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 88, 4, [] Gap between ADC2_ch4 and average initcode
ADC2_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 92, 4, [] Gap between ADC2_ch5 and average initcode
TEMPERATURE_SENSOR, EFUSE_BLK10, 96, 9, [] Temperature calibration data
Can't render this file because it contains an unexpected character in line 8 and column 53.

117
components/efuse/esp32p4/include/esp_efuse_table.h
View File

@@ -10,7 +10,7 @@ extern "C" {
#include "esp_efuse.h"
// md5_digest_table 0d4e1f49db99de4dd9d3eac8d8e6078b
// md5_digest_table c56ed98dde7a08c8f70d57a01faba96a
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -92,7 +92,35 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_DREF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_DREF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_MUL[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_MUL[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_K[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_VOS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_C[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_K[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_VOS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_C[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBG[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_DCDC_DBIAS_VOL_GAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
@@ -112,6 +140,25 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[];
@@ -131,6 +178,25 @@ extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_TEMPERATURE_SENSOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[];
extern const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_EXCHG_PINS[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
@@ -209,7 +275,35 @@ extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_DREF[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_DREF[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_MUL[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_MUL[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_K[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_VOS[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_C[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_K[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_VOS[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_C[];
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBG[];
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_LP_DCDC_DBIAS_VOL_GAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
@@ -227,8 +321,25 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[];
#ifdef __cplusplus
}

6
components/esp_hw_support/ldo/esp_ldo_regulator.c
View File

@@ -24,6 +24,7 @@ typedef struct ldo_regulator_channel_t {
int ref_cnt;
struct {
uint32_t adjustable : 1;
uint32_t bypass : 1;
} flags;
} ldo_regulator_channel_t;
@@ -83,7 +84,7 @@ esp_err_t esp_ldo_acquire_channel(const esp_ldo_channel_config_t *config, esp_ld
uint8_t mul = 0;
// calculate the dref and mul
ldo_ll_voltage_to_dref_mul(unit_id, config->voltage_mv, &dref, &mul);
ldo_ll_adjust_voltage(unit_id, dref, mul);
ldo_ll_adjust_voltage(unit_id, dref, mul, config->flags.bypass);
// set the ldo unit owner ship
ldo_ll_set_owner(unit_id, config->flags.owned_by_hw ? LDO_LL_UNIT_OWNER_HW : LDO_LL_UNIT_OWNER_SW);
// suppress voltage ripple
@@ -94,6 +95,7 @@ esp_err_t esp_ldo_acquire_channel(const esp_ldo_channel_config_t *config, esp_ld
channel->ref_cnt++;
channel->voltage_mv = config->voltage_mv;
channel->flags.adjustable = config->flags.adjustable;
channel->flags.bypass = config->flags.bypass;
channel->chan_id = config->chan_id;
}
portEXIT_CRITICAL(&s_spinlock);
@@ -155,7 +157,7 @@ esp_err_t esp_ldo_channel_adjust_voltage(esp_ldo_channel_handle_t chan, int volt
uint8_t mul = 0;
// calculate the dref and mul
ldo_ll_voltage_to_dref_mul(unit_id, voltage_mv, &dref, &mul);
ldo_ll_adjust_voltage(unit_id, dref, mul);
ldo_ll_adjust_voltage(unit_id, dref, mul, chan->flags.bypass);
return ESP_OK;
}

3
components/esp_hw_support/ldo/include/esp_ldo_regulator.h
View File

@@ -30,7 +30,8 @@ typedef struct {
/// Extra flags of a LDO channel
struct ldo_extra_flags {
uint32_t adjustable : 1; /*!< Whether the LDO channel is adjustable, and the voltage can be updated by `esp_ldo_channel_adjust_voltage` */
uint32_t owned_by_hw: 1; /*!< If the LDO channel is owned by hardware, then software configurations will be overridden by hardware */
uint32_t owned_by_hw: 1; /*!< If the LDO channel is owned by hardware, then software configurations can be overridden by hardware (e.g. eFuse) */
uint32_t bypass: 1; /*!< Whether to bypass the regulator, i.e., the input voltage is sourced directly to the output */
} flags; /*!< Flags for the LDO channel */
} esp_ldo_channel_config_t;

8
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_ldo.c
View File

@@ -25,7 +25,7 @@ TEST_CASE("LDO channel acquire and release (no adjustable)", "[LDO]")
TEST_ASSERT_EQUAL(success_ldo_chans[0], success_ldo_chans[1]);
TEST_ASSERT_EQUAL(success_ldo_chans[0], success_ldo_chans[2]);
// can't acquire with a different voltage
ldo_chan_config.voltage_mv = 3300;
ldo_chan_config.voltage_mv = 2500;
TEST_ESP_ERR(ESP_ERR_INVALID_ARG, esp_ldo_acquire_channel(&ldo_chan_config, &fail_ldo_chan));
// the channel has been acquired as "not adjustable" before, so we can't acquire it as "adjustable" again
ldo_chan_config = (esp_ldo_channel_config_t) {
@@ -36,7 +36,7 @@ TEST_CASE("LDO channel acquire and release (no adjustable)", "[LDO]")
TEST_ESP_ERR(ESP_ERR_INVALID_ARG, esp_ldo_acquire_channel(&ldo_chan_config, &fail_ldo_chan));
// can't change the voltage for a non-adjustable channel
TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_ldo_channel_adjust_voltage(success_ldo_chans[0], 3300));
TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_ldo_channel_adjust_voltage(success_ldo_chans[0], 1900));
for (int i = 0; i < 3; i++) {
TEST_ESP_OK(esp_ldo_release_channel(success_ldo_chans[i]));
@@ -62,7 +62,7 @@ TEST_CASE("LDO channel acquire and release (adjustable)", "[LDO]")
TEST_ESP_ERR(ESP_ERR_INVALID_ARG, esp_ldo_acquire_channel(&ldo_chan_config, &fail_ldo_chan));
// can change voltage for an adjustable channel
TEST_ESP_OK(esp_ldo_channel_adjust_voltage(success_ldo_chan, 3300));
TEST_ESP_OK(esp_ldo_channel_adjust_voltage(success_ldo_chan, 2500));
TEST_ESP_OK(esp_ldo_release_channel(success_ldo_chan));
}
@@ -71,7 +71,7 @@ TEST_CASE("LDO channel state dump", "[LDO][manual][ignore]")
esp_ldo_channel_handle_t success_ldo_chans[3] = {};
esp_ldo_channel_config_t ldo_chan_config = {
.chan_id = 2,
.voltage_mv = 1800,
.voltage_mv = 1900,
};
TEST_ESP_OK(esp_ldo_acquire_channel(&ldo_chan_config, &success_ldo_chans[0]));

4
components/hal/esp32p4/include/hal/efuse_ll.h
View File

@@ -73,7 +73,7 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_ver
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
{
return EFUSE.rd_mac_sys_2.disable_blk_version_major;
return EFUSE.rd_mac_sys_2.blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
@@ -83,7 +83,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_m
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
{
return EFUSE.rd_mac_sys_2.blk_version_major;
return EFUSE.rd_mac_sys_2.disable_blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)

170
components/hal/esp32p4/include/hal/ldo_ll.h
View File

@@ -14,31 +14,23 @@
#include "hal/efuse_hal.h"
#include "hal/pmu_types.h"
#include "soc/pmu_struct.h"
#include "soc/efuse_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define LDO_LL_NUM_UNITS 4 // NUmber of LDO units
#define LDO_LL_ADJUSTABLE_CHAN_MASK 0x0F // all the 4 channels can be adjustable
#define LDO_LL_NUM_UNITS 4 // Number of LDO units
#define LDO_LL_ADJUSTABLE_CHAN_MASK 0x0F // all the 4 channels are adjustable by setting "mul" and "dref" registers
#define LDO_LL_MAX_VOLTAGE_MV 3300
#define LDO_LL_MIN_VOLTAGE_MV 500
/**
* LDO LL macros, these macros are in the unit of mV
* @brief In the analog design, the LDO output "channel" is index from 1, i.e., VO1, VO2, VO3, VO4.
* But in software, we mapped them to "LDO unit", which is index from 0, i.e., 0, 1, 2, 3.
*/
#define LDO_LL_EXT_LDO_DREF_VOL_H_BASE 1000
#define LDO_LL_EXT_LDO_DREF_VOL_H_STEP 100
#define LDO_LL_EXT_LDO_DREF_VOL_L_BASE 500
#define LDO_LL_EXT_LDO_DREF_VOL_L_STEP 50
#define LDO_LL_EXT_LDO_MUL_VOL_BASE 1000
#define LDO_LL_EXT_LDO_MUL_VOL_STEP 250
/**
* LDO ID to real unit ID
*/
#define LDO_ID2UNIT(ldo_id) ((ldo_id) - 1)
#define LDO_ID2UNIT(ldo_id) ((ldo_id) - 1)
/**
* @brief LDO unit owner
@@ -51,6 +43,7 @@ typedef enum {
/**
* @brief Check if a LDO channel is valid
*
* @param ldo_chan LDO channel ID, note, this is indexed from 1
* @return True for valid, false for invalid
*/
__attribute__((always_inline))
@@ -73,26 +66,76 @@ static inline bool ldo_ll_is_valid_ldo_channel(int ldo_chan)
__attribute__((always_inline))
static inline void ldo_ll_voltage_to_dref_mul(int ldo_unit, int voltage_mv, uint8_t *dref, uint8_t *mul)
{
// TODO [IDF-10754]: also take the calibration parameters into account
if (voltage_mv <= 500) {
*dref = 0;
*mul = 0;
} else if (voltage_mv <= 900) {
*mul = 0;
*dref = (voltage_mv - LDO_LL_EXT_LDO_DREF_VOL_L_BASE) / LDO_LL_EXT_LDO_DREF_VOL_L_STEP;
} else if (voltage_mv <= 1600) {
*mul = 1;
*dref = 6 + (voltage_mv - LDO_LL_EXT_LDO_DREF_VOL_H_BASE) / LDO_LL_EXT_LDO_DREF_VOL_H_STEP;
} else if (voltage_mv <= 2000) {
*mul = 4;
*dref = (voltage_mv / 2 - LDO_LL_EXT_LDO_DREF_VOL_L_BASE) / LDO_LL_EXT_LDO_DREF_VOL_L_STEP;
} else if (voltage_mv <= 3200) {
*mul = 4;
*dref = 9 + (voltage_mv / 2 - LDO_LL_EXT_LDO_DREF_VOL_H_BASE) / LDO_LL_EXT_LDO_DREF_VOL_H_STEP;
} else {
*mul = 7;
*dref = 15;
uint8_t efuse_k = 0;
uint8_t efuse_vos = 0;
uint8_t efuse_c = 0;
// to avoid using FPU, enlarge the constants by 1000 as fixed point
int K_1000 = 1000;
int Vos_1000 = 0;
int C_1000 = 1000;
if (efuse_hal_blk_version() >= 1) {
// load the calibration values from the eFuse
if (ldo_unit == 2) {
efuse_k = EFUSE.rd_mac_sys_3.ldo_vo3_k;
efuse_vos = EFUSE.rd_mac_sys_3.ldo_vo3_vos;
efuse_c = EFUSE.rd_mac_sys_3.ldo_vo3_c;
}
if (ldo_unit == 3) {
efuse_k = (EFUSE.rd_mac_sys_4.ldo_vo4_k_1 << 6) + EFUSE.rd_mac_sys_3.ldo_vo4_k;
efuse_vos = EFUSE.rd_mac_sys_4.ldo_vo4_vos;
efuse_c = EFUSE.rd_mac_sys_4.ldo_vo4_c;
}
// convert the eFuse calibration values to fixed point, note these values are signed
if (efuse_k) {
K_1000 = efuse_k & 0x80 ? -1 * (efuse_k & 0x7F) + 975 : efuse_k + 975;
}
if (efuse_vos) {
Vos_1000 = efuse_vos & 0x20 ? -1 * (efuse_vos & 0x1F) - 3 : efuse_vos - 3;
}
if (efuse_c) {
C_1000 = efuse_c & 0x20 ? -1 * (efuse_c & 0x1F) + 990 : efuse_c + 990;
}
}
// iterate all the possible dref and mul values to find the best match
int min_voltage_diff = 400000000;
uint8_t matched_dref = 0;
uint8_t matched_mul = 0;
for (uint8_t dref_val = 0; dref_val < 16; dref_val++) {
int vref_20 = (dref_val < 9) ? (10 + dref_val) : (20 + (dref_val - 9) * 2);
for (uint8_t mul_val = 0; mul_val < 8; mul_val++) {
int vout_80000000 = (vref_20 * K_1000 + 20 * Vos_1000) * (4000 + mul_val * C_1000);
int diff = voltage_mv * 80000 - vout_80000000;
if (diff < 0) {
diff = -diff;
}
if (diff < min_voltage_diff) {
min_voltage_diff = diff;
matched_dref = dref_val;
matched_mul = mul_val;
}
}
}
if (efuse_hal_blk_version() >= 1) {
// For unit0 and unit1, the mul and dref value are calibrated and saved in the efuse, load them when available
if (ldo_unit == 0 && voltage_mv == 1800) {
if (EFUSE.rd_mac_sys_2.ldo_vo1_dref && EFUSE.rd_mac_sys_3.ldo_vo1_mul) {
matched_mul = EFUSE.rd_mac_sys_3.ldo_vo1_mul;
matched_dref = EFUSE.rd_mac_sys_2.ldo_vo1_dref;
}
}
if (ldo_unit == 1 && voltage_mv == 1900) {
if (EFUSE.rd_mac_sys_2.ldo_vo2_dref && EFUSE.rd_mac_sys_3.ldo_vo2_mul) {
matched_mul = EFUSE.rd_mac_sys_3.ldo_vo2_mul;
matched_dref = EFUSE.rd_mac_sys_2.ldo_vo2_dref;
}
}
}
*dref = matched_dref;
*mul = matched_mul;
}
/**
@@ -113,6 +156,39 @@ static inline void ldo_ll_set_owner(int ldo_unit, ldo_ll_unit_owner_t owner)
* - 1: tieh_sel, i.e. by software
*/
PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo.force_tieh_sel = owner;
/**
* tieh_sel:
* - 0: tieh;
* - 1: sdmmc0_tieh;
* - 2: 3.3V;
* - 3: sdmmc1_tieh;
*/
PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo.tieh_sel = 0;
}
/**
* @brief Adjust voltage of a LDO unit
*
* @note When bypass is enabled, the input voltage is sourced directly to the output.
* The dref and mul values will be ignored.
*
* @param ldo_unit LDO unit
* @param dref A parameter which controls the internal reference voltage
* @param mul Multiply factor
* @param bypass True: bypass; False: not bypass.
*/
__attribute__((always_inline))
static inline void ldo_ll_adjust_voltage(int ldo_unit, uint8_t dref, uint8_t mul, bool bypass)
{
uint8_t index_array[LDO_LL_NUM_UNITS] = {0, 3, 1, 4};
/**
* tieh:
* - 0: Vref * Mul
* - 1: 3.3V
*/
PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo.tieh = bypass;
PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo_ana.dref = dref;
PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo_ana.mul = mul;
}
/**
@@ -132,34 +208,6 @@ static inline void ldo_ll_enable(int ldo_unit, bool enable)
PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo.xpd = enable;
}
/**
* @brief Adjust voltage of a LDO unit
*
* @param ldo_unit LDO unit
* @param dref A parameter which controls the internal reference voltage
* @param mul Multiply factor
*/
__attribute__((always_inline))
static inline void ldo_ll_adjust_voltage(int ldo_unit, uint8_t dref, uint8_t mul)
{
uint8_t index_array[LDO_LL_NUM_UNITS] = {0, 3, 1, 4};
PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo_ana.dref = dref;
PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo_ana.mul = mul;
/**
* tieh:
* - 0: Vref * Mul
* - 1: 3.3V
*
* tieh_sel:
* - 0: tieh;
* - 1: sdmmc0_tieh;
* - 2: 3.3V;
* - 3: sdmmc1_tieh;
*/
PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo.tieh_sel = 0;
PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo.tieh = 0;
}
/**
* @brief Enable power on delay of a LDO unit
*

466
components/soc/esp32p4/register/soc/efuse_reg.h
View File

@@ -654,16 +654,16 @@ extern "C" {
#define EFUSE_KM_DISABLE_DEPLOY_MODE_V 0x0000000FU
#define EFUSE_KM_DISABLE_DEPLOY_MODE_S 8
/** EFUSE_USB_DEVICE_DREFL : RO; bitpos: [13:12]; default: 0;
* Represents the usb device single-end input low threshold, 0.8 V to 1.04 V with step
* of 80 mV.
* Represents the usb device single-end input low threshold; 0.8 V to 1.04 V with step
* of 80 mV
*/
#define EFUSE_USB_DEVICE_DREFL 0x00000003U
#define EFUSE_USB_DEVICE_DREFL_M (EFUSE_USB_DEVICE_DREFL_V << EFUSE_USB_DEVICE_DREFL_S)
#define EFUSE_USB_DEVICE_DREFL_V 0x00000003U
#define EFUSE_USB_DEVICE_DREFL_S 12
/** EFUSE_USB_OTG11_DREFL : RO; bitpos: [15:14]; default: 0;
* Represents the usb otg11 single-end input low threshold, 0.8 V to 1.04 V with step
* of 80 mV.
* Represents the usb otg11 single-end input low threshold; 0.8 V to 1.04 V with step
* of 80 mV
*/
#define EFUSE_USB_OTG11_DREFL 0x00000003U
#define EFUSE_USB_OTG11_DREFL_M (EFUSE_USB_OTG11_DREFL_V << EFUSE_USB_OTG11_DREFL_S)
@@ -817,56 +817,161 @@ extern "C" {
#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
#define EFUSE_PKG_VERSION_V 0x00000007U
#define EFUSE_PKG_VERSION_S 20
/** EFUSE_RESERVED_1_87 : R; bitpos: [31:23]; default: 0;
/** EFUSE_RESERVED_1_87 : R; bitpos: [23]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_1_87 0x000001FFU
#define EFUSE_RESERVED_1_87 (BIT(23))
#define EFUSE_RESERVED_1_87_M (EFUSE_RESERVED_1_87_V << EFUSE_RESERVED_1_87_S)
#define EFUSE_RESERVED_1_87_V 0x000001FFU
#define EFUSE_RESERVED_1_87_V 0x00000001U
#define EFUSE_RESERVED_1_87_S 23
/** EFUSE_LDO_VO1_DREF : R; bitpos: [27:24]; default: 0;
* Output VO1 parameter
*/
#define EFUSE_LDO_VO1_DREF 0x0000000FU
#define EFUSE_LDO_VO1_DREF_M (EFUSE_LDO_VO1_DREF_V << EFUSE_LDO_VO1_DREF_S)
#define EFUSE_LDO_VO1_DREF_V 0x0000000FU
#define EFUSE_LDO_VO1_DREF_S 24
/** EFUSE_LDO_VO2_DREF : R; bitpos: [31:28]; default: 0;
* Output VO2 parameter
*/
#define EFUSE_LDO_VO2_DREF 0x0000000FU
#define EFUSE_LDO_VO2_DREF_M (EFUSE_LDO_VO2_DREF_V << EFUSE_LDO_VO2_DREF_S)
#define EFUSE_LDO_VO2_DREF_V 0x0000000FU
#define EFUSE_LDO_VO2_DREF_S 28
/** EFUSE_RD_MAC_SYS_3_REG register
* BLOCK1 data register $n.
*/
#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0;
* Reserved.
/** EFUSE_LDO_VO1_MUL : R; bitpos: [2:0]; default: 0;
* Output VO1 parameter
*/
#define EFUSE_MAC_RESERVED_2 0x0003FFFFU
#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S)
#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU
#define EFUSE_MAC_RESERVED_2_S 0
/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
* Stores the first 14 bits of the zeroth part of system data.
#define EFUSE_LDO_VO1_MUL 0x00000007U
#define EFUSE_LDO_VO1_MUL_M (EFUSE_LDO_VO1_MUL_V << EFUSE_LDO_VO1_MUL_S)
#define EFUSE_LDO_VO1_MUL_V 0x00000007U
#define EFUSE_LDO_VO1_MUL_S 0
/** EFUSE_LDO_VO2_MUL : R; bitpos: [5:3]; default: 0;
* Output VO2 parameter
*/
#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU
#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU
#define EFUSE_SYS_DATA_PART0_0_S 18
#define EFUSE_LDO_VO2_MUL 0x00000007U
#define EFUSE_LDO_VO2_MUL_M (EFUSE_LDO_VO2_MUL_V << EFUSE_LDO_VO2_MUL_S)
#define EFUSE_LDO_VO2_MUL_V 0x00000007U
#define EFUSE_LDO_VO2_MUL_S 3
/** EFUSE_LDO_VO3_K : R; bitpos: [13:6]; default: 0;
* Output VO3 calibration parameter
*/
#define EFUSE_LDO_VO3_K 0x000000FFU
#define EFUSE_LDO_VO3_K_M (EFUSE_LDO_VO3_K_V << EFUSE_LDO_VO3_K_S)
#define EFUSE_LDO_VO3_K_V 0x000000FFU
#define EFUSE_LDO_VO3_K_S 6
/** EFUSE_LDO_VO3_VOS : R; bitpos: [19:14]; default: 0;
* Output VO3 calibration parameter
*/
#define EFUSE_LDO_VO3_VOS 0x0000003FU
#define EFUSE_LDO_VO3_VOS_M (EFUSE_LDO_VO3_VOS_V << EFUSE_LDO_VO3_VOS_S)
#define EFUSE_LDO_VO3_VOS_V 0x0000003FU
#define EFUSE_LDO_VO3_VOS_S 14
/** EFUSE_LDO_VO3_C : R; bitpos: [25:20]; default: 0;
* Output VO3 calibration parameter
*/
#define EFUSE_LDO_VO3_C 0x0000003FU
#define EFUSE_LDO_VO3_C_M (EFUSE_LDO_VO3_C_V << EFUSE_LDO_VO3_C_S)
#define EFUSE_LDO_VO3_C_V 0x0000003FU
#define EFUSE_LDO_VO3_C_S 20
/** EFUSE_LDO_VO4_K : R; bitpos: [31:26]; default: 0;
* Output VO4 calibration parameter
*/
#define EFUSE_LDO_VO4_K 0x0000003FU
#define EFUSE_LDO_VO4_K_M (EFUSE_LDO_VO4_K_V << EFUSE_LDO_VO4_K_S)
#define EFUSE_LDO_VO4_K_V 0x0000003FU
#define EFUSE_LDO_VO4_K_S 26
/** EFUSE_RD_MAC_SYS_4_REG register
* BLOCK1 data register $n.
*/
#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
* Stores the first 32 bits of the zeroth part of system data.
/** EFUSE_LDO_VO4_K_1 : R; bitpos: [1:0]; default: 0;
* Output VO4 calibration parameter
*/
#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART0_1_S 0
#define EFUSE_LDO_VO4_K_1 0x00000003U
#define EFUSE_LDO_VO4_K_1_M (EFUSE_LDO_VO4_K_1_V << EFUSE_LDO_VO4_K_1_S)
#define EFUSE_LDO_VO4_K_1_V 0x00000003U
#define EFUSE_LDO_VO4_K_1_S 0
/** EFUSE_LDO_VO4_VOS : R; bitpos: [7:2]; default: 0;
* Output VO4 calibration parameter
*/
#define EFUSE_LDO_VO4_VOS 0x0000003FU
#define EFUSE_LDO_VO4_VOS_M (EFUSE_LDO_VO4_VOS_V << EFUSE_LDO_VO4_VOS_S)
#define EFUSE_LDO_VO4_VOS_V 0x0000003FU
#define EFUSE_LDO_VO4_VOS_S 2
/** EFUSE_LDO_VO4_C : R; bitpos: [13:8]; default: 0;
* Output VO4 calibration parameter
*/
#define EFUSE_LDO_VO4_C 0x0000003FU
#define EFUSE_LDO_VO4_C_M (EFUSE_LDO_VO4_C_V << EFUSE_LDO_VO4_C_S)
#define EFUSE_LDO_VO4_C_V 0x0000003FU
#define EFUSE_LDO_VO4_C_S 8
/** EFUSE_RESERVED_1_142 : R; bitpos: [15:14]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_1_142 0x00000003U
#define EFUSE_RESERVED_1_142_M (EFUSE_RESERVED_1_142_V << EFUSE_RESERVED_1_142_S)
#define EFUSE_RESERVED_1_142_V 0x00000003U
#define EFUSE_RESERVED_1_142_S 14
/** EFUSE_ACTIVE_HP_DBIAS : R; bitpos: [19:16]; default: 0;
* Active HP DBIAS of fixed voltage
*/
#define EFUSE_ACTIVE_HP_DBIAS 0x0000000FU
#define EFUSE_ACTIVE_HP_DBIAS_M (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S)
#define EFUSE_ACTIVE_HP_DBIAS_V 0x0000000FU
#define EFUSE_ACTIVE_HP_DBIAS_S 16
/** EFUSE_ACTIVE_LP_DBIAS : R; bitpos: [23:20]; default: 0;
* Active LP DBIAS of fixed voltage
*/
#define EFUSE_ACTIVE_LP_DBIAS 0x0000000FU
#define EFUSE_ACTIVE_LP_DBIAS_M (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S)
#define EFUSE_ACTIVE_LP_DBIAS_V 0x0000000FU
#define EFUSE_ACTIVE_LP_DBIAS_S 20
/** EFUSE_LSLP_HP_DBIAS : R; bitpos: [27:24]; default: 0;
* LSLP HP DBIAS of fixed voltage
*/
#define EFUSE_LSLP_HP_DBIAS 0x0000000FU
#define EFUSE_LSLP_HP_DBIAS_M (EFUSE_LSLP_HP_DBIAS_V << EFUSE_LSLP_HP_DBIAS_S)
#define EFUSE_LSLP_HP_DBIAS_V 0x0000000FU
#define EFUSE_LSLP_HP_DBIAS_S 24
/** EFUSE_DSLP_DBG : R; bitpos: [31:28]; default: 0;
* DSLP BDG of fixed voltage
*/
#define EFUSE_DSLP_DBG 0x0000000FU
#define EFUSE_DSLP_DBG_M (EFUSE_DSLP_DBG_V << EFUSE_DSLP_DBG_S)
#define EFUSE_DSLP_DBG_V 0x0000000FU
#define EFUSE_DSLP_DBG_S 28
/** EFUSE_RD_MAC_SYS_5_REG register
* BLOCK1 data register $n.
*/
#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0;
* Stores the second 32 bits of the zeroth part of system data.
/** EFUSE_DSLP_LP_DBIAS : R; bitpos: [4:0]; default: 0;
* DSLP LP DBIAS of fixed voltage
*/
#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S)
#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART0_2_S 0
#define EFUSE_DSLP_LP_DBIAS 0x0000001FU
#define EFUSE_DSLP_LP_DBIAS_M (EFUSE_DSLP_LP_DBIAS_V << EFUSE_DSLP_LP_DBIAS_S)
#define EFUSE_DSLP_LP_DBIAS_V 0x0000001FU
#define EFUSE_DSLP_LP_DBIAS_S 0
/** EFUSE_LP_DCDC_DBIAS_VOL_GAP : R; bitpos: [9:5]; default: 0;
* DBIAS gap between LP and DCDC
*/
#define EFUSE_LP_DCDC_DBIAS_VOL_GAP 0x0000001FU
#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_M (EFUSE_LP_DCDC_DBIAS_VOL_GAP_V << EFUSE_LP_DCDC_DBIAS_VOL_GAP_S)
#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_V 0x0000001FU
#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_S 5
/** EFUSE_RESERVED_1_170 : R; bitpos: [31:10]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_1_170 0x003FFFFFU
#define EFUSE_RESERVED_1_170_M (EFUSE_RESERVED_1_170_V << EFUSE_RESERVED_1_170_S)
#define EFUSE_RESERVED_1_170_V 0x003FFFFFU
#define EFUSE_RESERVED_1_170_S 10
/** EFUSE_RD_SYS_PART1_DATA0_REG register
* Register $n of BLOCK2 (system).
@@ -920,49 +1025,133 @@ extern "C" {
* Register $n of BLOCK2 (system).
*/
#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
* Stores the fourth 32 bits of the first part of system data.
/** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [9:0]; default: 0;
* Average initcode of ADC1 atten0
*/
#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_4_S 0
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0 0x000003FFU
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S)
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V 0x000003FFU
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S 0
/** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [19:10]; default: 0;
* Average initcode of ADC1 atten1
*/
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1 0x000003FFU
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S)
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V 0x000003FFU
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S 10
/** EFUSE_ADC1_AVE_INITCODE_ATTEN2 : R; bitpos: [29:20]; default: 0;
* Average initcode of ADC1 atten2
*/
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2 0x000003FFU
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_M (EFUSE_ADC1_AVE_INITCODE_ATTEN2_V << EFUSE_ADC1_AVE_INITCODE_ATTEN2_S)
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_V 0x000003FFU
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_S 20
/** EFUSE_ADC1_AVE_INITCODE_ATTEN3 : R; bitpos: [31:30]; default: 0;
* Average initcode of ADC1 atten3
*/
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3 0x00000003U
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_M (EFUSE_ADC1_AVE_INITCODE_ATTEN3_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_S)
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_V 0x00000003U
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S 30
/** EFUSE_RD_SYS_PART1_DATA5_REG register
* Register $n of BLOCK2 (system).
*/
#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
* Stores the fifth 32 bits of the first part of system data.
/** EFUSE_ADC1_AVE_INITCODE_ATTEN3_1 : R; bitpos: [7:0]; default: 0;
* Average initcode of ADC1 atten3
*/
#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_5_S 0
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1 0x000000FFU
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_S)
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_V 0x000000FFU
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_S 0
/** EFUSE_ADC2_AVE_INITCODE_ATTEN0 : R; bitpos: [17:8]; default: 0;
* Average initcode of ADC2 atten0
*/
#define EFUSE_ADC2_AVE_INITCODE_ATTEN0 0x000003FFU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_M (EFUSE_ADC2_AVE_INITCODE_ATTEN0_V << EFUSE_ADC2_AVE_INITCODE_ATTEN0_S)
#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_V 0x000003FFU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_S 8
/** EFUSE_ADC2_AVE_INITCODE_ATTEN1 : R; bitpos: [27:18]; default: 0;
* Average initcode of ADC2 atten1
*/
#define EFUSE_ADC2_AVE_INITCODE_ATTEN1 0x000003FFU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_M (EFUSE_ADC2_AVE_INITCODE_ATTEN1_V << EFUSE_ADC2_AVE_INITCODE_ATTEN1_S)
#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_V 0x000003FFU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_S 18
/** EFUSE_ADC2_AVE_INITCODE_ATTEN2 : R; bitpos: [31:28]; default: 0;
* Average initcode of ADC2 atten2
*/
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2 0x0000000FU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_M (EFUSE_ADC2_AVE_INITCODE_ATTEN2_V << EFUSE_ADC2_AVE_INITCODE_ATTEN2_S)
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_V 0x0000000FU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_S 28
/** EFUSE_RD_SYS_PART1_DATA6_REG register
* Register $n of BLOCK2 (system).
*/
#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
* Stores the sixth 32 bits of the first part of system data.
/** EFUSE_ADC2_AVE_INITCODE_ATTEN2_1 : R; bitpos: [5:0]; default: 0;
* Average initcode of ADC2 atten2
*/
#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_6_S 0
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1 0x0000003FU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_M (EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_V << EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_S)
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_V 0x0000003FU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_S 0
/** EFUSE_ADC2_AVE_INITCODE_ATTEN3 : R; bitpos: [15:6]; default: 0;
* Average initcode of ADC2 atten3
*/
#define EFUSE_ADC2_AVE_INITCODE_ATTEN3 0x000003FFU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_M (EFUSE_ADC2_AVE_INITCODE_ATTEN3_V << EFUSE_ADC2_AVE_INITCODE_ATTEN3_S)
#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_V 0x000003FFU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_S 6
/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [25:16]; default: 0;
* HI_DOUT of ADC1 atten0
*/
#define EFUSE_ADC1_HI_DOUT_ATTEN0 0x000003FFU
#define EFUSE_ADC1_HI_DOUT_ATTEN0_M (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S)
#define EFUSE_ADC1_HI_DOUT_ATTEN0_V 0x000003FFU
#define EFUSE_ADC1_HI_DOUT_ATTEN0_S 16
/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [31:26]; default: 0;
* HI_DOUT of ADC1 atten1
*/
#define EFUSE_ADC1_HI_DOUT_ATTEN1 0x0000003FU
#define EFUSE_ADC1_HI_DOUT_ATTEN1_M (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S)
#define EFUSE_ADC1_HI_DOUT_ATTEN1_V 0x0000003FU
#define EFUSE_ADC1_HI_DOUT_ATTEN1_S 26
/** EFUSE_RD_SYS_PART1_DATA7_REG register
* Register $n of BLOCK2 (system).
*/
#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
* Stores the seventh 32 bits of the first part of system data.
/** EFUSE_ADC1_HI_DOUT_ATTEN1_1 : R; bitpos: [3:0]; default: 0;
* HI_DOUT of ADC1 atten1
*/
#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_7_S 0
#define EFUSE_ADC1_HI_DOUT_ATTEN1_1 0x0000000FU
#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_M (EFUSE_ADC1_HI_DOUT_ATTEN1_1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_1_S)
#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_V 0x0000000FU
#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_S 0
/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [13:4]; default: 0;
* HI_DOUT of ADC1 atten2
*/
#define EFUSE_ADC1_HI_DOUT_ATTEN2 0x000003FFU
#define EFUSE_ADC1_HI_DOUT_ATTEN2_M (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S)
#define EFUSE_ADC1_HI_DOUT_ATTEN2_V 0x000003FFU
#define EFUSE_ADC1_HI_DOUT_ATTEN2_S 4
/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [23:14]; default: 0;
* HI_DOUT of ADC1 atten3
*/
#define EFUSE_ADC1_HI_DOUT_ATTEN3 0x000003FFU
#define EFUSE_ADC1_HI_DOUT_ATTEN3_M (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S)
#define EFUSE_ADC1_HI_DOUT_ATTEN3_V 0x000003FFU
#define EFUSE_ADC1_HI_DOUT_ATTEN3_S 14
/** EFUSE_RESERVED_2_248 : R; bitpos: [31:24]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_2_248 0x000000FFU
#define EFUSE_RESERVED_2_248_M (EFUSE_RESERVED_2_248_V << EFUSE_RESERVED_2_248_S)
#define EFUSE_RESERVED_2_248_V 0x000000FFU
#define EFUSE_RESERVED_2_248_S 24
/** EFUSE_RD_USR_DATA0_REG register
* Register $n of BLOCK3 (user).
@@ -1654,49 +1843,168 @@ extern "C" {
* Register $n of BLOCK10 (system).
*/
#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
* Stores the $nth 32 bits of the 2nd part of system data.
/** EFUSE_ADC2_HI_DOUT_ATTEN0 : R; bitpos: [9:0]; default: 0;
* HI_DOUT of ADC2 atten0
*/
#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART2_0_S 0
#define EFUSE_ADC2_HI_DOUT_ATTEN0 0x000003FFU
#define EFUSE_ADC2_HI_DOUT_ATTEN0_M (EFUSE_ADC2_HI_DOUT_ATTEN0_V << EFUSE_ADC2_HI_DOUT_ATTEN0_S)
#define EFUSE_ADC2_HI_DOUT_ATTEN0_V 0x000003FFU
#define EFUSE_ADC2_HI_DOUT_ATTEN0_S 0
/** EFUSE_ADC2_HI_DOUT_ATTEN1 : R; bitpos: [19:10]; default: 0;
* HI_DOUT of ADC2 atten1
*/
#define EFUSE_ADC2_HI_DOUT_ATTEN1 0x000003FFU
#define EFUSE_ADC2_HI_DOUT_ATTEN1_M (EFUSE_ADC2_HI_DOUT_ATTEN1_V << EFUSE_ADC2_HI_DOUT_ATTEN1_S)
#define EFUSE_ADC2_HI_DOUT_ATTEN1_V 0x000003FFU
#define EFUSE_ADC2_HI_DOUT_ATTEN1_S 10
/** EFUSE_ADC2_HI_DOUT_ATTEN2 : R; bitpos: [29:20]; default: 0;
* HI_DOUT of ADC2 atten2
*/
#define EFUSE_ADC2_HI_DOUT_ATTEN2 0x000003FFU
#define EFUSE_ADC2_HI_DOUT_ATTEN2_M (EFUSE_ADC2_HI_DOUT_ATTEN2_V << EFUSE_ADC2_HI_DOUT_ATTEN2_S)
#define EFUSE_ADC2_HI_DOUT_ATTEN2_V 0x000003FFU
#define EFUSE_ADC2_HI_DOUT_ATTEN2_S 20
/** EFUSE_ADC2_HI_DOUT_ATTEN3 : R; bitpos: [31:30]; default: 0;
* HI_DOUT of ADC2 atten3
*/
#define EFUSE_ADC2_HI_DOUT_ATTEN3 0x00000003U
#define EFUSE_ADC2_HI_DOUT_ATTEN3_M (EFUSE_ADC2_HI_DOUT_ATTEN3_V << EFUSE_ADC2_HI_DOUT_ATTEN3_S)
#define EFUSE_ADC2_HI_DOUT_ATTEN3_V 0x00000003U
#define EFUSE_ADC2_HI_DOUT_ATTEN3_S 30
/** EFUSE_RD_SYS_PART2_DATA1_REG register
* Register $n of BLOCK9 (KEY5).
*/
#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
* Stores the $nth 32 bits of the 2nd part of system data.
/** EFUSE_ADC2_HI_DOUT_ATTEN3_1 : R; bitpos: [7:0]; default: 0;
* HI_DOUT of ADC2 atten3
*/
#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART2_1_S 0
#define EFUSE_ADC2_HI_DOUT_ATTEN3_1 0x000000FFU
#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_M (EFUSE_ADC2_HI_DOUT_ATTEN3_1_V << EFUSE_ADC2_HI_DOUT_ATTEN3_1_S)
#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_V 0x000000FFU
#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_S 0
/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [11:8]; default: 0;
* Gap between ADC1_ch0 and average initcode
*/
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S 8
/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [15:12]; default: 0;
* Gap between ADC1_ch1 and average initcode
*/
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S 12
/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [19:16]; default: 0;
* Gap between ADC1_ch2 and average initcode
*/
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S 16
/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [23:20]; default: 0;
* Gap between ADC1_ch3 and average initcode
*/
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S 20
/** EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [27:24]; default: 0;
* Gap between ADC1_ch4 and average initcode
*/
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S 24
/** EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF : R; bitpos: [31:28]; default: 0;
* Gap between ADC1_ch5 and average initcode
*/
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S 28
/** EFUSE_RD_SYS_PART2_DATA2_REG register
* Register $n of BLOCK10 (system).
*/
#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
* Stores the $nth 32 bits of the 2nd part of system data.
/** EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF : R; bitpos: [3:0]; default: 0;
* Gap between ADC1_ch6 and average initcode
*/
#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART2_2_S 0
#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_S 0
/** EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF : R; bitpos: [7:4]; default: 0;
* Gap between ADC1_ch7 and average initcode
*/
#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_S 4
/** EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [11:8]; default: 0;
* Gap between ADC2_ch0 and average initcode
*/
#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_S 8
/** EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [15:12]; default: 0;
* Gap between ADC2_ch1 and average initcode
*/
#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_S 12
/** EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [19:16]; default: 0;
* Gap between ADC2_ch2 and average initcode
*/
#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_S 16
/** EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [23:20]; default: 0;
* Gap between ADC2_ch3 and average initcode
*/
#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_S 20
/** EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [27:24]; default: 0;
* Gap between ADC2_ch4 and average initcode
*/
#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_S 24
/** EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF : R; bitpos: [31:28]; default: 0;
* Gap between ADC2_ch5 and average initcode
*/
#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_S 28
/** EFUSE_RD_SYS_PART2_DATA3_REG register
* Register $n of BLOCK10 (system).
*/
#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
* Stores the $nth 32 bits of the 2nd part of system data.
/** EFUSE_TEMPERATURE_SENSOR : R; bitpos: [8:0]; default: 0;
* Temperature calibration data
*/
#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART2_3_S 0
#define EFUSE_TEMPERATURE_SENSOR 0x000001FFU
#define EFUSE_TEMPERATURE_SENSOR_M (EFUSE_TEMPERATURE_SENSOR_V << EFUSE_TEMPERATURE_SENSOR_S)
#define EFUSE_TEMPERATURE_SENSOR_V 0x000001FFU
#define EFUSE_TEMPERATURE_SENSOR_S 0
/** EFUSE_RESERVED_10_105 : R; bitpos: [31:9]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_10_105 0x007FFFFFU
#define EFUSE_RESERVED_10_105_M (EFUSE_RESERVED_10_105_V << EFUSE_RESERVED_10_105_S)
#define EFUSE_RESERVED_10_105_V 0x007FFFFFU
#define EFUSE_RESERVED_10_105_S 9
/** EFUSE_RD_SYS_PART2_DATA4_REG register
* Register $n of BLOCK10 (system).

252
components/soc/esp32p4/register/soc/efuse_struct.h
View File

@@ -607,10 +607,18 @@ typedef union {
* Package version
*/
uint32_t pkg_version:3;
/** reserved_1_87 : R; bitpos: [31:23]; default: 0;
/** reserved_1_87 : R; bitpos: [23]; default: 0;
* reserved
*/
uint32_t reserved_1_87:9;
uint32_t reserved_1_87:1;
/** ldo_vo1_dref : R; bitpos: [27:24]; default: 0;
* Output VO1 parameter
*/
uint32_t ldo_vo1_dref:4;
/** ldo_vo2_dref : R; bitpos: [31:28]; default: 0;
* Output VO2 parameter
*/
uint32_t ldo_vo2_dref:4;
};
uint32_t val;
} efuse_rd_mac_sys_2_reg_t;
@@ -620,14 +628,30 @@ typedef union {
*/
typedef union {
struct {
/** mac_reserved_2 : RO; bitpos: [17:0]; default: 0;
* Reserved.
/** ldo_vo1_mul : R; bitpos: [2:0]; default: 0;
* Output VO1 parameter
*/
uint32_t mac_reserved_2:18;
/** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
* Stores the first 14 bits of the zeroth part of system data.
uint32_t ldo_vo1_mul:3;
/** ldo_vo2_mul : R; bitpos: [5:3]; default: 0;
* Output VO2 parameter
*/
uint32_t sys_data_part0_0:14;
uint32_t ldo_vo2_mul:3;
/** ldo_vo3_k : R; bitpos: [13:6]; default: 0;
* Output VO3 calibration parameter
*/
uint32_t ldo_vo3_k:8;
/** ldo_vo3_vos : R; bitpos: [19:14]; default: 0;
* Output VO3 calibration parameter
*/
uint32_t ldo_vo3_vos:6;
/** ldo_vo3_c : R; bitpos: [25:20]; default: 0;
* Output VO3 calibration parameter
*/
uint32_t ldo_vo3_c:6;
/** ldo_vo4_k : R; bitpos: [31:26]; default: 0;
* Output VO4 calibration parameter
*/
uint32_t ldo_vo4_k:6;
};
uint32_t val;
} efuse_rd_mac_sys_3_reg_t;
@@ -637,10 +661,38 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
* Stores the first 32 bits of the zeroth part of system data.
/** ldo_vo4_k_1 : R; bitpos: [1:0]; default: 0;
* Output VO4 calibration parameter
*/
uint32_t sys_data_part0_1:32;
uint32_t ldo_vo4_k_1:2;
/** ldo_vo4_vos : R; bitpos: [7:2]; default: 0;
* Output VO4 calibration parameter
*/
uint32_t ldo_vo4_vos:6;
/** ldo_vo4_c : R; bitpos: [13:8]; default: 0;
* Output VO4 calibration parameter
*/
uint32_t ldo_vo4_c:6;
/** reserved_1_142 : R; bitpos: [15:14]; default: 0;
* reserved
*/
uint32_t reserved_1_142:2;
/** active_hp_dbias : R; bitpos: [19:16]; default: 0;
* Active HP DBIAS of fixed voltage
*/
uint32_t active_hp_dbias:4;
/** active_lp_dbias : R; bitpos: [23:20]; default: 0;
* Active LP DBIAS of fixed voltage
*/
uint32_t active_lp_dbias:4;
/** lslp_hp_dbias : R; bitpos: [27:24]; default: 0;
* LSLP HP DBIAS of fixed voltage
*/
uint32_t lslp_hp_dbias:4;
/** dslp_dbg : R; bitpos: [31:28]; default: 0;
* DSLP BDG of fixed voltage
*/
uint32_t dslp_dbg:4;
};
uint32_t val;
} efuse_rd_mac_sys_4_reg_t;
@@ -650,10 +702,18 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
* Stores the second 32 bits of the zeroth part of system data.
/** dslp_lp_dbias : R; bitpos: [4:0]; default: 0;
* DSLP LP DBIAS of fixed voltage
*/
uint32_t sys_data_part0_2:32;
uint32_t dslp_lp_dbias:5;
/** lp_dcdc_dbias_vol_gap : R; bitpos: [9:5]; default: 0;
* DBIAS gap between LP and DCDC
*/
uint32_t lp_dcdc_dbias_vol_gap:5;
/** reserved_1_170 : R; bitpos: [31:10]; default: 0;
* reserved
*/
uint32_t reserved_1_170:22;
};
uint32_t val;
} efuse_rd_mac_sys_5_reg_t;
@@ -715,10 +775,22 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0;
* Stores the fourth 32 bits of the first part of system data.
/** adc1_ave_initcode_atten0 : R; bitpos: [9:0]; default: 0;
* Average initcode of ADC1 atten0
*/
uint32_t sys_data_part1_4:32;
uint32_t adc1_ave_initcode_atten0:10;
/** adc1_ave_initcode_atten1 : R; bitpos: [19:10]; default: 0;
* Average initcode of ADC1 atten1
*/
uint32_t adc1_ave_initcode_atten1:10;
/** adc1_ave_initcode_atten2 : R; bitpos: [29:20]; default: 0;
* Average initcode of ADC1 atten2
*/
uint32_t adc1_ave_initcode_atten2:10;
/** adc1_ave_initcode_atten3 : R; bitpos: [31:30]; default: 0;
* Average initcode of ADC1 atten3
*/
uint32_t adc1_ave_initcode_atten3:2;
};
uint32_t val;
} efuse_rd_sys_part1_data4_reg_t;
@@ -728,10 +800,22 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0;
* Stores the fifth 32 bits of the first part of system data.
/** adc1_ave_initcode_atten3_1 : R; bitpos: [7:0]; default: 0;
* Average initcode of ADC1 atten3
*/
uint32_t sys_data_part1_5:32;
uint32_t adc1_ave_initcode_atten3_1:8;
/** adc2_ave_initcode_atten0 : R; bitpos: [17:8]; default: 0;
* Average initcode of ADC2 atten0
*/
uint32_t adc2_ave_initcode_atten0:10;
/** adc2_ave_initcode_atten1 : R; bitpos: [27:18]; default: 0;
* Average initcode of ADC2 atten1
*/
uint32_t adc2_ave_initcode_atten1:10;
/** adc2_ave_initcode_atten2 : R; bitpos: [31:28]; default: 0;
* Average initcode of ADC2 atten2
*/
uint32_t adc2_ave_initcode_atten2:4;
};
uint32_t val;
} efuse_rd_sys_part1_data5_reg_t;
@@ -741,10 +825,22 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0;
* Stores the sixth 32 bits of the first part of system data.
/** adc2_ave_initcode_atten2_1 : R; bitpos: [5:0]; default: 0;
* Average initcode of ADC2 atten2
*/
uint32_t sys_data_part1_6:32;
uint32_t adc2_ave_initcode_atten2_1:6;
/** adc2_ave_initcode_atten3 : R; bitpos: [15:6]; default: 0;
* Average initcode of ADC2 atten3
*/
uint32_t adc2_ave_initcode_atten3:10;
/** adc1_hi_dout_atten0 : R; bitpos: [25:16]; default: 0;
* HI_DOUT of ADC1 atten0
*/
uint32_t adc1_hi_dout_atten0:10;
/** adc1_hi_dout_atten1 : R; bitpos: [31:26]; default: 0;
* HI_DOUT of ADC1 atten1
*/
uint32_t adc1_hi_dout_atten1:6;
};
uint32_t val;
} efuse_rd_sys_part1_data6_reg_t;
@@ -754,10 +850,22 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0;
* Stores the seventh 32 bits of the first part of system data.
/** adc1_hi_dout_atten1_1 : R; bitpos: [3:0]; default: 0;
* HI_DOUT of ADC1 atten1
*/
uint32_t sys_data_part1_7:32;
uint32_t adc1_hi_dout_atten1_1:4;
/** adc1_hi_dout_atten2 : R; bitpos: [13:4]; default: 0;
* HI_DOUT of ADC1 atten2
*/
uint32_t adc1_hi_dout_atten2:10;
/** adc1_hi_dout_atten3 : R; bitpos: [23:14]; default: 0;
* HI_DOUT of ADC1 atten3
*/
uint32_t adc1_hi_dout_atten3:10;
/** reserved_2_248 : R; bitpos: [31:24]; default: 0;
* reserved
*/
uint32_t reserved_2_248:8;
};
uint32_t val;
} efuse_rd_sys_part1_data7_reg_t;
@@ -1503,10 +1611,22 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
* Stores the $nth 32 bits of the 2nd part of system data.
/** adc2_hi_dout_atten0 : R; bitpos: [9:0]; default: 0;
* HI_DOUT of ADC2 atten0
*/
uint32_t sys_data_part2_0:32;
uint32_t adc2_hi_dout_atten0:10;
/** adc2_hi_dout_atten1 : R; bitpos: [19:10]; default: 0;
* HI_DOUT of ADC2 atten1
*/
uint32_t adc2_hi_dout_atten1:10;
/** adc2_hi_dout_atten2 : R; bitpos: [29:20]; default: 0;
* HI_DOUT of ADC2 atten2
*/
uint32_t adc2_hi_dout_atten2:10;
/** adc2_hi_dout_atten3 : R; bitpos: [31:30]; default: 0;
* HI_DOUT of ADC2 atten3
*/
uint32_t adc2_hi_dout_atten3:2;
};
uint32_t val;
} efuse_rd_sys_part2_data0_reg_t;
@@ -1516,10 +1636,34 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
* Stores the $nth 32 bits of the 2nd part of system data.
/** adc2_hi_dout_atten3_1 : R; bitpos: [7:0]; default: 0;
* HI_DOUT of ADC2 atten3
*/
uint32_t sys_data_part2_1:32;
uint32_t adc2_hi_dout_atten3_1:8;
/** adc1_ch0_atten0_initcode_diff : R; bitpos: [11:8]; default: 0;
* Gap between ADC1_ch0 and average initcode
*/
uint32_t adc1_ch0_atten0_initcode_diff:4;
/** adc1_ch1_atten0_initcode_diff : R; bitpos: [15:12]; default: 0;
* Gap between ADC1_ch1 and average initcode
*/
uint32_t adc1_ch1_atten0_initcode_diff:4;
/** adc1_ch2_atten0_initcode_diff : R; bitpos: [19:16]; default: 0;
* Gap between ADC1_ch2 and average initcode
*/
uint32_t adc1_ch2_atten0_initcode_diff:4;
/** adc1_ch3_atten0_initcode_diff : R; bitpos: [23:20]; default: 0;
* Gap between ADC1_ch3 and average initcode
*/
uint32_t adc1_ch3_atten0_initcode_diff:4;
/** adc1_ch4_atten0_initcode_diff : R; bitpos: [27:24]; default: 0;
* Gap between ADC1_ch4 and average initcode
*/
uint32_t adc1_ch4_atten0_initcode_diff:4;
/** adc1_ch5_atten0_initcode_diff : R; bitpos: [31:28]; default: 0;
* Gap between ADC1_ch5 and average initcode
*/
uint32_t adc1_ch5_atten0_initcode_diff:4;
};
uint32_t val;
} efuse_rd_sys_part2_data1_reg_t;
@@ -1529,10 +1673,38 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
* Stores the $nth 32 bits of the 2nd part of system data.
/** adc1_ch6_atten0_initcode_diff : R; bitpos: [3:0]; default: 0;
* Gap between ADC1_ch6 and average initcode
*/
uint32_t sys_data_part2_2:32;
uint32_t adc1_ch6_atten0_initcode_diff:4;
/** adc1_ch7_atten0_initcode_diff : R; bitpos: [7:4]; default: 0;
* Gap between ADC1_ch7 and average initcode
*/
uint32_t adc1_ch7_atten0_initcode_diff:4;
/** adc2_ch0_atten0_initcode_diff : R; bitpos: [11:8]; default: 0;
* Gap between ADC2_ch0 and average initcode
*/
uint32_t adc2_ch0_atten0_initcode_diff:4;
/** adc2_ch1_atten0_initcode_diff : R; bitpos: [15:12]; default: 0;
* Gap between ADC2_ch1 and average initcode
*/
uint32_t adc2_ch1_atten0_initcode_diff:4;
/** adc2_ch2_atten0_initcode_diff : R; bitpos: [19:16]; default: 0;
* Gap between ADC2_ch2 and average initcode
*/
uint32_t adc2_ch2_atten0_initcode_diff:4;
/** adc2_ch3_atten0_initcode_diff : R; bitpos: [23:20]; default: 0;
* Gap between ADC2_ch3 and average initcode
*/
uint32_t adc2_ch3_atten0_initcode_diff:4;
/** adc2_ch4_atten0_initcode_diff : R; bitpos: [27:24]; default: 0;
* Gap between ADC2_ch4 and average initcode
*/
uint32_t adc2_ch4_atten0_initcode_diff:4;
/** adc2_ch5_atten0_initcode_diff : R; bitpos: [31:28]; default: 0;
* Gap between ADC2_ch5 and average initcode
*/
uint32_t adc2_ch5_atten0_initcode_diff:4;
};
uint32_t val;
} efuse_rd_sys_part2_data2_reg_t;
@@ -1542,10 +1714,14 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
* Stores the $nth 32 bits of the 2nd part of system data.
/** temperature_sensor : R; bitpos: [8:0]; default: 0;
* Temperature calibration data
*/
uint32_t sys_data_part2_3:32;
uint32_t temperature_sensor:9;
/** reserved_10_105 : R; bitpos: [31:9]; default: 0;
* reserved
*/
uint32_t reserved_10_105:23;
};
uint32_t val;
} efuse_rd_sys_part2_data3_reg_t;