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Merge branch 'feature/support_esp32s3_wifi_lightsleep' into 'master'

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support esp32s3 wifi lightsleep

Closes IDF-1781

See merge request espressif/esp-idf!14569
This commit is contained in:
Jiang Jiang Jian
2021-08-06 12:51:46 +00:00
parent bf0431f026 df93733e56
commit 6e1f8a68b9
12 changed files with 72 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
components/esp_phy/Kconfig
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@@ -81,7 +81,7 @@ menu "PHY"
config ESP32_PHY_MAC_BB_PD
bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled"
depends on (IDF_TARGET_ESP32C3 && FREERTOS_USE_TICKLESS_IDLE)
depends on ((IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3) && FREERTOS_USE_TICKLESS_IDLE)
default n
help
If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered

2
components/esp_phy/include/phy.h
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@@ -69,7 +69,7 @@ void phy_wakeup_init(void);
*/
void phy_close_rf(void);
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2
#if !CONFIG_IDF_TARGET_ESP32
/**
* @brief Disable PHY temperature sensor.
*/

2
components/esp_phy/src/phy_init.c
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@@ -262,7 +262,7 @@ void esp_phy_disable(void)
phy_digital_regs_store();
// Disable PHY and RF.
phy_close_rf();
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2
#if !CONFIG_IDF_TARGET_ESP32
// Disable PHY temperature sensor
phy_xpd_tsens();
#endif

17
components/esp_rom/include/esp32s3/rom/apb_backup_dma.h Normal file
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@@ -0,0 +1,17 @@
/*
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
void ets_apb_backup_init_lock_func(void(* _apb_backup_lock)(void), void(* _apb_backup_unlock)(void));
#ifdef __cplusplus
}
#endif

1
components/esp_system/port/soc/esp32s3/CMakeLists.txt
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@@ -3,6 +3,7 @@ set(srcs "highint_hdl.S"
"reset_reason.c"
"system_internal.c"
"cache_err_int.c"
"apb_backup_dma.c"
"../../arch/xtensa/panic_arch.c"
"../../arch/xtensa/panic_handler_asm.S"
"../../arch/xtensa/expression_with_stack.c"

36
components/esp_system/port/soc/esp32s3/apb_backup_dma.c Normal file
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@@ -0,0 +1,36 @@
/*
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc_caps.h"
#include "esp_attr.h"
#include "freertos/FreeRTOS.h"
#include "freertos/portmacro.h"
#include "esp32s3/rom/apb_backup_dma.h"
static portMUX_TYPE s_apb_backup_dma_mutex = portMUX_INITIALIZER_UNLOCKED;
static void IRAM_ATTR apb_backup_dma_lock(void)
{
if (xPortInIsrContext()) {
portENTER_CRITICAL_ISR(&s_apb_backup_dma_mutex);
} else {
portENTER_CRITICAL(&s_apb_backup_dma_mutex);
}
}
static void IRAM_ATTR apb_backup_dma_unlock(void)
{
if (xPortInIsrContext()) {
portEXIT_CRITICAL_ISR(&s_apb_backup_dma_mutex);
} else {
portEXIT_CRITICAL(&s_apb_backup_dma_mutex);
}
}
void esp_apb_backup_dma_lock_init(void)
{
ets_apb_backup_init_lock_func(apb_backup_dma_lock, apb_backup_dma_unlock);
}

5
components/esp_system/port/soc/esp32s3/clk.c
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@@ -311,6 +311,11 @@ __attribute__((weak)) void esp_perip_clk_init(void)
CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
/* Set WiFi light sleep clock source to RTC slow clock */
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M);
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
/* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE);
}

2
components/esp_wifi/lib

Submodule components/esp_wifi/lib updated: 0a82aeac1f...cdba5629f4

2
components/soc/esp32s3/include/soc/soc_caps.h
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@@ -39,6 +39,8 @@
#define SOC_ADC_SUPPORT_RTC_CTRL (1)
#define SOC_ADC_ARBITER_SUPPORTED (1)
/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
#define SOC_APB_BACKUP_DMA (1)
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#include "brownout_caps.h"

4
components/soc/esp32s3/include/soc/syscon_reg.h
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@@ -169,9 +169,9 @@ extern "C" {
#define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG
/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
/*description: */
#define SYSTEM_WIFI_CLK_EN 0xFFFFFFFF
#define SYSTEM_WIFI_CLK_EN 0x00FB9FCF
#define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V) << (SYSTEM_WIFI_CLK_EN_S))
#define SYSTEM_WIFI_CLK_EN_V 0xFFFFFFFF
#define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF
#define SYSTEM_WIFI_CLK_EN_S 0
/* Mask for all Wifi clock bits, 6 */

6
examples/wifi/power_save/main/Kconfig.projbuild
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@@ -73,13 +73,13 @@ menu "Example Configuration"
config EXAMPLE_MIN_CPU_FREQ_40M
bool "40 MHz (use with 40MHz XTAL)"
depends on IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || ESP32_XTAL_FREQ_40 || ESP32_XTAL_FREQ_AUTO
depends on !IDF_TARGET_ESP32 || ESP32_XTAL_FREQ_40 || ESP32_XTAL_FREQ_AUTO
config EXAMPLE_MIN_CPU_FREQ_20M
bool "20 MHz (use with 40MHz XTAL)"
depends on IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || ESP32_XTAL_FREQ_40 || ESP32_XTAL_FREQ_AUTO
depends on !IDF_TARGET_ESP32 || ESP32_XTAL_FREQ_40 || ESP32_XTAL_FREQ_AUTO
config EXAMPLE_MIN_CPU_FREQ_10M
bool "10 MHz (use with 40MHz XTAL)"
depends on IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || ESP32_XTAL_FREQ_40 || ESP32_XTAL_FREQ_AUTO
depends on !IDF_TARGET_ESP32 || ESP32_XTAL_FREQ_40 || ESP32_XTAL_FREQ_AUTO
config EXAMPLE_MIN_CPU_FREQ_26M
bool "26 MHz (use with 26MHz XTAL)"
depends on ESP32_XTAL_FREQ_26 || ESP32_XTAL_FREQ_AUTO

2
examples/wifi/power_save/main/power_save.c
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@@ -101,6 +101,8 @@ void app_main(void)
esp_pm_config_esp32s2_t pm_config = {
#elif CONFIG_IDF_TARGET_ESP32C3
esp_pm_config_esp32c3_t pm_config = {
#elif CONFIG_IDF_TARGET_ESP32S3
esp_pm_config_esp32s3_t pm_config = {
#endif
.max_freq_mhz = CONFIG_EXAMPLE_MAX_CPU_FREQ_MHZ,
.min_freq_mhz = CONFIG_EXAMPLE_MIN_CPU_FREQ_MHZ,