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feat(soc/usb): Add USB related changes to soc_caps and usb_dwc_periph

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This commit changes the following:

- Add types and data structures indicating the available USB controllers
for each target.
This commit is contained in:
Tomas Rezucha
2024-04-03 00:48:24 +08:00
committed by BOT
parent 4143156926
commit 7019a9f61c
10 changed files with 295 additions and 87 deletions
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5
components/soc/CMakeLists.txt
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@ -138,10 +138,7 @@ if(CONFIG_SOC_IEEE802154_SUPPORTED)
endif()
if(CONFIG_SOC_USB_OTG_SUPPORTED)
if(NOT ${target} STREQUAL "esp32p4")
list(APPEND srcs "${target_folder}/usb_periph.c"
"${target_folder}/usb_dwc_periph.c")
endif()
list(APPEND srcs "${target_folder}/usb_dwc_periph.c")
endif()
if(CONFIG_SOC_DAC_SUPPORTED)

8
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@ -1087,6 +1087,14 @@ config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
bool
default y
config SOC_USB_OTG_PERIPH_NUM
int
default 2
config SOC_USB_UTMI_PHY_NUM
int
default 1
config SOC_PARLIO_GROUPS
int
default 1

9
components/soc/esp32p4/include/soc/soc_caps.h
View File

@ -411,9 +411,16 @@
#define SOC_MCPWM_SUPPORT_EVENT_COMPARATOR (1) ///< Support event comparator (based on ETM)
#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
/*-------------------------- USB CAPS ----------------------------------------*/
// USB Serial JTAG Caps
// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
// USB OTG Caps
#define SOC_USB_OTG_PERIPH_NUM (2U)
// USB PHY Caps
#define SOC_USB_UTMI_PHY_NUM (1U)
/*-------------------------- PARLIO CAPS --------------------------------------*/
#define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */
#define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */

50
components/soc/esp32p4/usb_dwc_periph.c Normal file
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@ -0,0 +1,50 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stddef.h>
#include "soc/interrupts.h"
#include "soc/gpio_sig_map.h"
#include "soc/usb_dwc_periph.h"
#include "soc/usb_dwc_struct.h"
/* -------------------------------- Private --------------------------------- */
static const usb_utmi_otg_signal_conn_t dwc_fs_otg_signals = {
// Inputs
.iddig = USB_OTG11_IDDIG_PAD_IN_IDX,
.avalid = USB_OTG11_AVALID_PAD_IN_IDX,
.bvalid = USB_SRP_BVALID_PAD_IN_IDX,
.vbusvalid = USB_OTG11_VBUSVALID_PAD_IN_IDX,
.sessend = USB_SRP_SESSEND_PAD_IN_IDX,
// Outputs
.idpullup = USB_OTG11_IDPULLUP_PAD_OUT_IDX,
.dppulldown = USB_OTG11_DPPULLDOWN_PAD_OUT_IDX,
.dmpulldown = USB_OTG11_DMPULLDOWN_PAD_OUT_IDX,
.drvvbus = USB_OTG11_DRVVBUS_PAD_OUT_IDX,
.chrgvbus = USB_SRP_CHRGVBUS_PAD_OUT_IDX,
.dischrgvbus = USB_SRP_DISCHRGVBUS_PAD_OUT_IDX,
};
/* --------------------------------- Public --------------------------------- */
const usb_dwc_info_t usb_dwc_info = {
.controllers = {
// High-Speed USB-DWC
[0] = {
.fsls_signals = NULL,
.otg_signals = NULL,
.irq = ETS_USB_OTG_INTR_SOURCE,
.irq_2nd_cpu = ETS_USB_OTG_ENDP_MULTI_PROC_INTR_SOURCE,
},
// Full-Speed USB-DWC
[1] = {
.fsls_signals = NULL,
.otg_signals = &dwc_fs_otg_signals,
.irq = ETS_USB_OTG11_CH0_INTR_SOURCE,
.irq_2nd_cpu = -1,
},
},
};

72
components/soc/esp32s2/usb_dwc_periph.c
View File

@ -4,8 +4,78 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/usb_dwc_periph.h"
#include "soc/gpio_sig_map.h"
#include "soc/usb_periph.h"
#include "soc/interrupts.h"
#include "soc/usb_dwc_periph.h"
/* -------------------------------- Private --------------------------------- */
static const usb_fsls_serial_signal_conn_t fsls_signals = {
// Inputs
.rx_dp = USB_EXTPHY_VP_IDX,
.rx_dm = USB_EXTPHY_VM_IDX,
.rx_rcv = USB_EXTPHY_RCV_IDX,
// Outputs
.suspend_n = USB_EXTPHY_SUSPND_IDX,
.tx_enable_n = USB_EXTPHY_OEN_IDX,
.tx_dp = USB_EXTPHY_VPO_IDX,
.tx_dm = USB_EXTPHY_VMO_IDX,
.fs_edge_sel = USB_EXTPHY_SPEED_IDX,
};
static const usb_utmi_otg_signal_conn_t otg_signals = {
// Inputs
.iddig = USB_OTG_IDDIG_IN_IDX,
.avalid = USB_OTG_AVALID_IN_IDX,
.bvalid = USB_SRP_BVALID_IN_IDX,
.vbusvalid = USB_OTG_VBUSVALID_IN_IDX,
.sessend = USB_SRP_SESSEND_IN_IDX,
// Outputs
.idpullup = USB_OTG_IDPULLUP_IDX,
.dppulldown = USB_OTG_DPPULLDOWN_IDX,
.dmpulldown = USB_OTG_DMPULLDOWN_IDX,
.drvvbus = USB_OTG_DRVVBUS_IDX,
.chrgvbus = USB_SRP_CHRGVBUS_IDX,
.dischrgvbus = USB_SRP_DISCHRGVBUS_IDX,
};
/* --------------------------------- Public --------------------------------- */
const usb_dwc_info_t usb_dwc_info = {
.controllers = {
[0] = {
.fsls_signals = &fsls_signals,
.otg_signals = &otg_signals,
.irq = ETS_USB_INTR_SOURCE,
.irq_2nd_cpu = -1,
},
},
};
/* ------------------------------- Deprecated ------------------------------- */
/*
Note: These IO pins are deprecated. When connecting USB OTG to an external FSLS
PHY, the FSLS Serial Interface signals can be routed to any GPIO via the GPIO
matrix. Thus, this mapping of signals to IO pins is meaningless.
Todo: Remove in IDF v6.0 (IDF-9029)
*/
const usb_iopin_dsc_t usb_periph_iopins[] = {
{USBPHY_VP_NUM, USB_EXTPHY_VP_IDX, 0, 1},
{USBPHY_VM_NUM, USB_EXTPHY_VM_IDX, 0, 1},
{USBPHY_RCV_NUM, USB_EXTPHY_RCV_IDX, 0, 1},
{USBPHY_OEN_NUM, USB_EXTPHY_OEN_IDX, 1, 1},
{USBPHY_VPO_NUM, USB_EXTPHY_VPO_IDX, 1, 1},
{USBPHY_VMO_NUM, USB_EXTPHY_VMO_IDX, 1, 1},
{GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_IDDIG_IN_IDX, 0, 0}, //connected connector is mini-B
//connected connector is mini-B
{GPIO_MATRIX_CONST_ONE_INPUT, USB_SRP_BVALID_IN_IDX, 0, 0}, //HIGH to force USB device mode
{GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_VBUSVALID_IN_IDX, 0, 0}, //receiving a valid Vbus from host
{GPIO_MATRIX_CONST_ZERO_INPUT, USB_OTG_AVALID_IN_IDX, 0, 0},
{-1, -1, 0, 0}
};
/*
Bunch of constants for USB peripheral: GPIO signals

30
components/soc/esp32s2/usb_periph.c
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@ -1,30 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc_caps.h"
#include "soc/usb_periph.h"
/*
Note: These IO pins are deprecated. When connecting USB OTG to an external FSLS
PHY, the FSLS Serial Interface signals can be routed to any GPIO via the GPIO
matrix. Thus, this mapping of signals to IO pins is meaningless.
Todo: Remove in IDF v6.0 (IDF-9029)
*/
const usb_iopin_dsc_t usb_periph_iopins[] = {
{USBPHY_VP_NUM, USB_EXTPHY_VP_IDX, 0, 1},
{USBPHY_VM_NUM, USB_EXTPHY_VM_IDX, 0, 1},
{USBPHY_RCV_NUM, USB_EXTPHY_RCV_IDX, 0, 1},
{USBPHY_OEN_NUM, USB_EXTPHY_OEN_IDX, 1, 1},
{USBPHY_VPO_NUM, USB_EXTPHY_VPO_IDX, 1, 1},
{USBPHY_VMO_NUM, USB_EXTPHY_VMO_IDX, 1, 1},
{GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_IDDIG_IN_IDX, 0, 0}, //connected connector is mini-B
//connected connector is mini-B
{GPIO_MATRIX_CONST_ONE_INPUT, USB_SRP_BVALID_IN_IDX, 0, 0}, //HIGH to force USB device mode
{GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_VBUSVALID_IN_IDX, 0, 0}, //receiving a valid Vbus from host
{GPIO_MATRIX_CONST_ZERO_INPUT, USB_OTG_AVALID_IN_IDX, 0, 0},
{-1, -1, 0, 0}
};

73
components/soc/esp32s3/usb_dwc_periph.c
View File

@ -4,8 +4,79 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/usb_dwc_periph.h"
#include <stddef.h>
#include "soc/gpio_sig_map.h"
#include "soc/usb_periph.h"
#include "soc/interrupts.h"
#include "soc/usb_dwc_periph.h"
/* -------------------------------- Private --------------------------------- */
static const usb_fsls_serial_signal_conn_t fsls_signals = {
// Inputs
.rx_dp = USB_EXTPHY_VP_IDX,
.rx_dm = USB_EXTPHY_VM_IDX,
.rx_rcv = USB_EXTPHY_RCV_IDX,
// Outputs
.suspend_n = USB_EXTPHY_SUSPND_IDX,
.tx_enable_n = USB_EXTPHY_OEN_IDX,
.tx_dp = USB_EXTPHY_VPO_IDX,
.tx_dm = USB_EXTPHY_VMO_IDX,
.fs_edge_sel = USB_EXTPHY_SPEED_IDX,
};
static const usb_utmi_otg_signal_conn_t otg_signals = {
// Inputs
.iddig = USB_OTG_IDDIG_IN_IDX,
.avalid = USB_OTG_AVALID_IN_IDX,
.bvalid = USB_SRP_BVALID_IN_IDX,
.vbusvalid = USB_OTG_VBUSVALID_IN_IDX,
.sessend = USB_SRP_SESSEND_IN_IDX,
// Outputs
.idpullup = USB_OTG_IDPULLUP_IDX,
.dppulldown = USB_OTG_DPPULLDOWN_IDX,
.dmpulldown = USB_OTG_DMPULLDOWN_IDX,
.drvvbus = USB_OTG_DRVVBUS_IDX,
.chrgvbus = USB_SRP_CHRGVBUS_IDX,
.dischrgvbus = USB_SRP_DISCHRGVBUS_IDX,
};
/* --------------------------------- Public --------------------------------- */
const usb_dwc_info_t usb_dwc_info = {
.controllers = {
[0] = {
.fsls_signals = &fsls_signals,
.otg_signals = &otg_signals,
.irq = ETS_USB_INTR_SOURCE,
.irq_2nd_cpu = -1,
},
},
};
/* ------------------------------- Deprecated ------------------------------- */
/*
Note: These IO pins are deprecated. When connecting USB OTG to an external FSLS
PHY, the FSLS Serial Interface signals can be routed to any GPIO via the GPIO
matrix. Thus, this mapping of signals to IO pins is meaningless.
Todo: Remove in IDF v6.0 (IDF-9029)
*/
const usb_iopin_dsc_t usb_periph_iopins[] = {
{USBPHY_VP_NUM, USB_EXTPHY_VP_IDX, 0, 1},
{USBPHY_VM_NUM, USB_EXTPHY_VM_IDX, 0, 1},
{USBPHY_RCV_NUM, USB_EXTPHY_RCV_IDX, 0, 1},
{USBPHY_OEN_NUM, USB_EXTPHY_OEN_IDX, 1, 1},
{USBPHY_VPO_NUM, USB_EXTPHY_VPO_IDX, 1, 1},
{USBPHY_VMO_NUM, USB_EXTPHY_VMO_IDX, 1, 1},
{GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_IDDIG_IN_IDX, 0, 0}, //connected connector is mini-B
//connected connector is mini-B
{GPIO_MATRIX_CONST_ONE_INPUT, USB_SRP_BVALID_IN_IDX, 0, 0}, //HIGH to force USB device mode
{GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_VBUSVALID_IN_IDX, 0, 0}, //receiving a valid Vbus from host
{GPIO_MATRIX_CONST_ZERO_INPUT, USB_OTG_AVALID_IN_IDX, 0, 0},
{-1, -1, 0, 0}
};
/*
Bunch of constants for USB peripheral: GPIO signals

30
components/soc/esp32s3/usb_periph.c
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@ -1,30 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc_caps.h"
#include "soc/usb_periph.h"
/*
Note: These IO pins are deprecated. When connecting USB OTG to an external FSLS
PHY, the FSLS Serial Interface signals can be routed to any GPIO via the GPIO
matrix. Thus, this mapping of signals to IO pins is meaningless.
Todo: Remove in IDF v6.0 (IDF-9029)
*/
const usb_iopin_dsc_t usb_periph_iopins[] = {
{USBPHY_VP_NUM, USB_EXTPHY_VP_IDX, 0, 1},
{USBPHY_VM_NUM, USB_EXTPHY_VM_IDX, 0, 1},
{USBPHY_RCV_NUM, USB_EXTPHY_RCV_IDX, 0, 1},
{USBPHY_OEN_NUM, USB_EXTPHY_OEN_IDX, 1, 1},
{USBPHY_VPO_NUM, USB_EXTPHY_VPO_IDX, 1, 1},
{USBPHY_VMO_NUM, USB_EXTPHY_VMO_IDX, 1, 1},
{GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_IDDIG_IN_IDX, 0, 0}, //connected connector is mini-B
//connected connector is mini-B
{GPIO_MATRIX_CONST_ONE_INPUT, USB_SRP_BVALID_IN_IDX, 0, 0}, //HIGH to force USB device mode
{GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_VBUSVALID_IN_IDX, 0, 0}, //receiving a valid Vbus from host
{GPIO_MATRIX_CONST_ZERO_INPUT, USB_OTG_AVALID_IN_IDX, 0, 0},
{-1, -1, 0, 0}
};

79
components/soc/include/soc/usb_dwc_periph.h
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@ -1,18 +1,93 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "soc/soc_pins.h"
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#include "soc/gpio_sig_map.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_USB_OTG_SUPPORTED
/* ---------------------------------- Types --------------------------------- */
/**
* @brief USB PHY FSLS Serial Interface Signals
*
* Structure to store the GPIO matrix signal indexes for a USB PHY FSLS Serial
* interface's signals.
*
* @note Refer to section "2.2.1.13 FsLsSerialMode" of the UTMI+ for more
* details regarding the FSLS Serial Interface.
*/
typedef struct {
// Inputs
int rx_dp;
int rx_dm;
int rx_rcv;
// Outputs
int suspend_n;
int tx_enable_n;
int tx_dp;
int tx_dm;
int fs_edge_sel;
} usb_fsls_serial_signal_conn_t;
/**
* @brief USB PHY UTMI OTG Interface Signal Index Type
*
* Structure to store the GPIO matrix signal indexes for a UTMI PHY interface's
* OTG signals.
*/
typedef struct {
// Inputs
int iddig;
int avalid;
int bvalid;
int vbusvalid;
int sessend;
// Outputs
int idpullup;
int dppulldown;
int dmpulldown;
int drvvbus;
int chrgvbus;
int dischrgvbus;
} usb_utmi_otg_signal_conn_t;
/**
* @brief USB Controller Information
*
* Structure to store information for all USB-DWC instances
*/
typedef struct {
struct {
const usb_fsls_serial_signal_conn_t * const fsls_signals; // Must be set if external PHY is supported by controller
const usb_utmi_otg_signal_conn_t * const otg_signals;
const int irq;
const int irq_2nd_cpu; // The USB-DWC can provide 2nd interrupt so each CPU can have its own interrupt line. Set to -1 if not supported
} controllers [SOC_USB_OTG_PERIPH_NUM];
} usb_dwc_info_t;
extern const usb_dwc_info_t usb_dwc_info;
#endif // SOC_USB_OTG_SUPPORTED
/* ------------------------------- Deprecated ------------------------------- */
/* Todo: Remove in ESP-IDF v6.0 (IDF-9052) */
#if SOC_USB_OTG_SUPPORTED
/*
Stores a bunch of USB-peripheral data.
*/
@ -41,6 +116,8 @@ typedef struct {
extern const usb_phy_signal_conn_t usb_otg_periph_signal;
#endif // SOC_USB_OTG_SUPPORTED
#ifdef __cplusplus
}
#endif

26
components/usb/hcd_dwc.c
View File

@ -12,11 +12,11 @@
#include "freertos/semphr.h"
#include "esp_heap_caps.h"
#include "esp_intr_alloc.h"
#include "soc/interrupts.h" // For interrupt index
#include "esp_err.h"
#include "esp_log.h"
#include "soc/usb_dwc_periph.h"
#include "hal/usb_dwc_hal.h"
#include "hal/usb_dwc_types.h"
#include "hcd.h"
#include "usb_private.h"
#include "usb/usb_types_ch9.h"
@ -28,15 +28,6 @@
// ----------------------------------------------------- Macros --------------------------------------------------------
// ------------------ Target specific ----------------------
// TODO: Remove target specific section after support for multiple USB peripherals is implemented
#include "sdkconfig.h"
#if (CONFIG_IDF_TARGET_ESP32P4)
#define USB_INTR ETS_USB_OTG_INTR_SOURCE
#else
#define USB_INTR ETS_USB_INTR_SOURCE
#endif
// --------------------- Constants -------------------------
#define INIT_DELAY_MS 30 // A delay of at least 25ms to enter Host mode. Make it 30ms to be safe
@ -64,22 +55,19 @@
#define XFER_LIST_LEN_ISOC 64 // Implement longer ISOC transfer list to give us enough space for additional timing margin
#define XFER_LIST_ISOC_MARGIN 3 // The 1st ISOC transfer is scheduled 3 (micro)frames later so we have enough timing margin
// ------------------------ Flags --------------------------
// ------------------------ Internal --------------------------
/**
* @brief Bit masks for the HCD to use in the URBs reserved_flags field
* @brief Values for the HCD to use in the URBs hcd_var field
*
* The URB object has a reserved_flags member for host stack's internal use. The following flags will be set in
* reserved_flags in order to keep track of state of an URB within the HCD.
* The URB object has a hcd_var member for host stack's internal use. The following values will be set in
* hcd_var in order to keep track of state of an URB within the HCD.
*/
#define URB_HCD_STATE_IDLE 0 // The URB is not enqueued in an HCD pipe
#define URB_HCD_STATE_PENDING 1 // The URB is enqueued and pending execution
#define URB_HCD_STATE_INFLIGHT 2 // The URB is currently in flight
#define URB_HCD_STATE_DONE 3 // The URB has completed execution or is retired, and is waiting to be dequeued
#define URB_HCD_STATE_SET(reserved_flags, state) (reserved_flags = (reserved_flags & ~URB_HCD_STATE_MASK) | state)
#define URB_HCD_STATE_GET(reserved_flags) (reserved_flags & URB_HCD_STATE_MASK)
// -------------------- Convenience ------------------------
const char *HCD_DWC_TAG = "HCD DWC";
@ -1005,7 +993,7 @@ esp_err_t hcd_install(const hcd_config_t *config)
goto port_alloc_err;
}
// Allocate interrupt
err_ret = esp_intr_alloc(USB_INTR,
err_ret = esp_intr_alloc(usb_dwc_info.controllers[0].irq,
config->intr_flags | ESP_INTR_FLAG_INTRDISABLED, // The interrupt must be disabled until the port is initialized
intr_hdlr_main,
(void *)p_hcd_obj_dmy->port_obj,