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Merge branch 'feat/cache_panic_h4' into 'master'

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cache: panic support on h4

Closes IDF-12288

See merge request espressif/esp-idf!41023
This commit is contained in:
Armando (Dou Yiwen)
2025-08-05 03:23:56 +00:00
parent 4173af5620 e179056b7c
commit 72cb973022
5 changed files with 31 additions and 10 deletions
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3
components/esp_hw_support/linker.lf
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@@ -13,6 +13,9 @@ entries:
cpu: esp_cpu_compare_and_set (noflash)
esp_memory_utils (noflash)
clk_utils (noflash)
if IDF_TARGET_ESP32H4 = y || IDF_TARGET_ESP32H21 = y:
# IDF-13780
rtc_clk (noflash)
if PM_SLP_IRAM_OPT = y:
rtc_clk (noflash)
rtc_time (noflash_text)

3
components/esp_rom/esp32h4/include/esp32h4/rom/rtc.h
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@@ -100,7 +100,8 @@ typedef enum {
USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core (hp system)*/
USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core (hp system)*/
JTAG_RESET = 24, /**<24, jtag reset CPU*/
CPU_LOCKUP_RESET = 25, /**<25, cpu lockup reset*/
RTC_PWR_GLITCH_RESET = 25, /**<25, RTC power glitch reset system*/
CPU_LOCKUP_RESET = 26, /**<26, cpu lockup reset*/
} RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h

9
components/esp_system/port/soc/esp32h4/cache_err_int.c
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@@ -19,8 +19,6 @@
#include "hal/cache_ll.h"
#include "esp_private/cache_err_int.h"
// TODO: [ESP32H4] IDF-12288 inherited from verification branch, need check
static const char *TAG = "CACHE_ERR";
const char cache_error_msg[] = "Cache access error";
@@ -64,6 +62,13 @@ void esp_cache_err_int_init(void)
esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
/**
* Here we
* 1. enable the cache fail tracer to take cache error interrupt into effect.
* 2. clear potential cache error interrupt raw bits
* 3. enable cache error interrupt en bits
*/
cache_ll_l1_enable_fail_tracer(0, true);
/* On the hardware side, start by clearing all the bits responsible for cache access error */
cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
/* Then enable cache access error interrupts. */

24
components/hal/esp32h4/include/hal/cache_ll.h
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@@ -10,6 +10,7 @@
#include <stdbool.h>
#include "soc/cache_reg.h"
#include "soc/cache_struct.h"
#include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
@@ -813,42 +814,53 @@ static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32
return valid;
}
/**
* Enable the Cache fail tracer
*
* @param cache_id cache ID
* @param en enable / disable
*/
static inline void cache_ll_l1_enable_fail_tracer(uint32_t cache_id, bool en)
{
CACHE.trace_ena.l1_cache_trace_ena = en;
}
/*------------------------------------------------------------------------------
* Interrupt
*----------------------------------------------------------------------------*/
/**
* @brief Enable Cache access error interrupt
*
* @param cache_id Cache ID, not used on C3. For compabitlity
* @param cache_id Cache ID
* @param mask Interrupt mask
*/
static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
{
SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask);
CACHE.l1_cache_acs_fail_int_ena.val |= mask;
}
/**
* @brief Clear Cache access error interrupt status
*
* @param cache_id Cache ID, not used on C3. For compabitlity
* @param cache_id Cache ID
* @param mask Interrupt mask
*/
static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
{
SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask);
CACHE.l1_cache_acs_fail_int_clr.val = mask;
}
/**
* @brief Get Cache access error interrupt status
*
* @param cache_id Cache ID, not used on C3. For compabitlity
* @param cache_id Cache ID
* @param mask Interrupt mask
*
* @return Status mask
*/
static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
{
return GET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG, mask);
return CACHE.l1_cache_acs_fail_int_st.val & mask;
}
#ifdef __cplusplus

2
components/soc/esp32h4/include/soc/reset_reasons.h
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@@ -46,7 +46,7 @@ typedef enum {
RESET_REASON_CORE_USB_UART = 0x15, // USB UART resets the digital core (hp system)
RESET_REASON_CORE_USB_JTAG = 0x16, // USB JTAG resets the digital core (hp system)
RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0
RESET_REASON_CPU_LOCKUP = 0x19, // Triggered when the CPU enters lockup (exception inside the exception handler would cause this)
RESET_REASON_CPU_LOCKUP = 0x1A, // Triggered when the CPU enters lockup (exception inside the exception handler would cause this)
} soc_reset_reason_t;
#ifdef __cplusplus