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spi_slave: Fix MOSI/MISO enable on transaction preparation

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MOSI and MISO enablement were conditioned to the existence of TX
and RX buffers, respectively. This is valid for the SPI Master,
but for the SPI Slave the opposite is expected.
This commit is contained in:
Gustavo Henrique Nihei
2021-05-21 11:15:55 -03:00
committed by bot
parent 920e7796b4
commit 74f010ddfd
1 changed files with 2 additions and 2 deletions
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4
components/hal/spi_slave_hal_iram.c
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@@ -71,8 +71,8 @@ void spi_slave_hal_prepare_data(const spi_slave_hal_context_t *hal)
spi_ll_slave_set_rx_bitlen(hal->hw, hal->bitlen);
spi_ll_slave_set_tx_bitlen(hal->hw, hal->bitlen);
spi_ll_enable_mosi(hal->hw, (hal->tx_buffer == NULL) ? 0 : 1);
spi_ll_enable_miso(hal->hw, (hal->rx_buffer == NULL) ? 0 : 1);
spi_ll_enable_mosi(hal->hw, (hal->rx_buffer == NULL) ? 0 : 1);
spi_ll_enable_miso(hal->hw, (hal->tx_buffer == NULL) ? 0 : 1);
}
void spi_slave_hal_store_result(spi_slave_hal_context_t *hal)