mirror of
https://github.com/espressif/esp-idf.git
synced 2025-07-30 10:47:19 +02:00
feat(hw_support): move call_start_cpu0 into flash to save IRAM
This commit is contained in:
Michael (XIAO Xufeng)
@ -22,6 +22,7 @@
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#include "esp_rom_sys.h"
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#include "esp_rom_caps.h"
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#include "sdkconfig.h"
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#include "soc/soc_caps.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "soc/dport_reg.h"
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@ -258,6 +259,13 @@ void IRAM_ATTR call_start_cpu1(void)
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esp_rom_delay_us(100);
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}
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/* SPI Flash driver initialization runs in the CORE stage of ESP SYSTEM INIT FN of core 0, which runs in parallel
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* with this function. During that, the scheduler (hence the ipc service) is not ready, while the flash driver needs
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* to disable the cache. s_resume_cores indicates the end of CORE stage.
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*
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* Other CPUs are not allowed to access the flash through the cache, i.e. run code which is not placed in IRAM or
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* print string which locates on flash, until the SECONDARY stage of ESP SYSTEM INIT FN.
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*/
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SYS_STARTUP_FN();
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}
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@ -350,18 +358,8 @@ void IRAM_ATTR do_multicore_settings(void)
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#endif // !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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#endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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/*
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* We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
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* and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
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*/
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void IRAM_ATTR call_start_cpu0(void)
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FORCE_INLINE_ATTR IRAM_ATTR void init_cpu(void)
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{
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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soc_reset_reason_t __attribute__((unused)) rst_reas[SOC_CPU_CORES_NUM];
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#else
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soc_reset_reason_t __attribute__((unused)) rst_reas[1];
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#endif
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#ifdef __riscv
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if (esp_cpu_dbgr_is_attached()) {
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/* Let debugger some time to detect that target started, halt it, enable ebreaks and resume.
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@ -404,13 +402,19 @@ void IRAM_ATTR call_start_cpu0(void)
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extern uint32_t esp_tee_service_call(int argc, ...);
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esprv_int_setup_mgmt_cb((void *)esp_tee_service_call);
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#endif
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}
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//Keep this static, the compiler will check if rst_reas is initialized.
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FORCE_INLINE_ATTR IRAM_ATTR void get_reset_reason(soc_reset_reason_t *rst_reas)
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{
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rst_reas[0] = esp_rom_get_reset_reason(0);
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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rst_reas[1] = esp_rom_get_reset_reason(1);
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#endif
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}
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//Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this.
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FORCE_INLINE_ATTR IRAM_ATTR void init_bss(const soc_reset_reason_t *rst_reas)
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{
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#if SOC_MEM_NON_CONTIGUOUS_SRAM
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memset(&_bss_start_low, 0, (&_bss_end_low - &_bss_start_low) * sizeof(_bss_start_low));
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memset(&_bss_start_high, 0, (&_bss_end_high - &_bss_start_high) * sizeof(_bss_start_high));
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@ -434,49 +438,30 @@ void IRAM_ATTR call_start_cpu0(void)
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memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
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}
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#endif
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}
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#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP && !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE && !CONFIG_IDF_TARGET_ESP32H4 // TODO IDF-12289
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// It helps to fix missed cache settings for other cores. It happens when bootloader is unicore.
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do_multicore_settings();
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#endif
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#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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//cache hal ctx needs to be initialised
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cache_hal_init();
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#endif
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// When the APP is loaded into ram for execution, some hardware initialization behaviors
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// in the bootloader are still necessary
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#if CONFIG_APP_BUILD_TYPE_RAM
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FORCE_INLINE_ATTR IRAM_ATTR void ram_app_init(void)
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{
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bootloader_init();
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#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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bootloader_flash_hardware_init();
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#endif //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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}
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#endif //#if CONFIG_APP_BUILD_TYPE_RAM
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#if CONFIG_IDF_TARGET_ESP32P4
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#define RWDT_RESET RESET_REASON_CORE_RWDT
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#define MWDT_RESET RESET_REASON_CORE_MWDT
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#else
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#define RWDT_RESET RESET_REASON_CORE_RTC_WDT
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#define MWDT_RESET RESET_REASON_CORE_MWDT0
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#endif
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#ifndef CONFIG_BOOTLOADER_WDT_ENABLE
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// from panic handler we can be reset by RWDT or TG0WDT
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if (rst_reas[0] == RWDT_RESET || rst_reas[0] == MWDT_RESET
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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|| rst_reas[1] == RWDT_RESET || rst_reas[1] == MWDT_RESET
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#endif
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) {
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wdt_hal_context_t rtc_wdt_ctx = RWDT_HAL_CONTEXT_DEFAULT();
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_disable(&rtc_wdt_ctx);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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}
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#endif
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#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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//Keep this static, the compiler will check output parameters are initialized.
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FORCE_INLINE_ATTR IRAM_ATTR void cache_init(void)
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{
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE && !CONFIG_IDF_TARGET_ESP32H4 // TODO IDF-12289
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// It helps to fix missed cache settings for other cores. It happens when bootloader is unicore.
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do_multicore_settings();
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#endif
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//cache hal ctx needs to be initialised
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cache_hal_init();
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#if CONFIG_IDF_TARGET_ESP32S2
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/* Configure the mode of instruction cache : cache size, cache associated ways, cache line size. */
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extern void esp_config_instruction_cache_mode(void);
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@ -509,41 +494,59 @@ void IRAM_ATTR call_start_cpu0(void)
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esp_config_l2_cache_mode();
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#endif
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#if ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
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#if CONFIG_APP_BUILD_TYPE_ELF_RAM
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// For RAM loadable ELF case, we don't need to reserve IROM/DROM as instructions and data
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// are all in internal RAM. If the RAM loadable ELF has any requirement to memory map the
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// external flash then it should use flash or partition mmap APIs.
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#if ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
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uint32_t cache_mmu_irom_size = 0;
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__attribute__((unused)) uint32_t cache_mmu_drom_size = 0;
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#else // CONFIG_APP_BUILD_TYPE_ELF_RAM
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#if !CONFIG_APP_BUILD_TYPE_ELF_RAM
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uint32_t _instruction_size = (uint32_t)&_instruction_reserved_end - (uint32_t)&_instruction_reserved_start;
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uint32_t cache_mmu_irom_size = ((_instruction_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t);
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uint32_t _rodata_size = (uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start;
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__attribute__((unused)) uint32_t cache_mmu_drom_size = ((_rodata_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t);
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cache_mmu_irom_size = ((_instruction_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t);
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#endif // !CONFIG_APP_BUILD_TYPE_ELF_RAM
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/* Configure the Cache MMU size for instruction and rodata in flash. */
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Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
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#endif // ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
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}
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#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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#if CONFIG_ESPTOOLPY_OCT_FLASH && !CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT
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bool efuse_opflash_en = efuse_ll_get_flash_type();
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if (!efuse_opflash_en) {
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ESP_DRAM_LOGE(TAG, "Octal Flash option selected, but EFUSE not configured!");
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abort();
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// On chips with different virtual address space for flash and PSRAM, code in flash is not available before XIP is
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// initialized. Hence, these functions have to be in the IRAM.
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#if SOC_MMU_PER_EXT_MEM_TARGET
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#define MSPI_INIT_ATTR FORCE_INLINE_ATTR IRAM_ATTR
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#else
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#define MSPI_INIT_ATTR NOINLINE_ATTR static
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#endif
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MSPI_INIT_ATTR void sys_rtc_init(const soc_reset_reason_t *rst_reas)
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{
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#if CONFIG_IDF_TARGET_ESP32P4
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#define RWDT_RESET RESET_REASON_CORE_RWDT
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#define MWDT_RESET RESET_REASON_CORE_MWDT
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#else
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#define RWDT_RESET RESET_REASON_CORE_RTC_WDT
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#define MWDT_RESET RESET_REASON_CORE_MWDT0
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#endif
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#ifndef CONFIG_BOOTLOADER_WDT_ENABLE
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// from panic handler we can be reset by RWDT or TG0WDT
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if (rst_reas[0] == RWDT_RESET || rst_reas[0] == MWDT_RESET
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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|| rst_reas[1] == RWDT_RESET || rst_reas[1] == MWDT_RESET
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#endif
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) {
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wdt_hal_context_t rtc_wdt_ctx = RWDT_HAL_CONTEXT_DEFAULT();
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_disable(&rtc_wdt_ctx);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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}
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#endif
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esp_mspi_pin_init();
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// For Octal flash, it's hard to implement a read_id function in OPI mode for all vendors.
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// So we have to read it here in SPI mode, before entering the OPI mode.
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bootloader_flash_update_id();
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// Configure the power related stuff. After this the MSPI timing tuning can be done.
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esp_rtc_init();
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}
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NOINLINE_ATTR IRAM_ATTR void flash_init_state(void)
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{
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/**
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* This function initialise the Flash chip to the user-defined settings.
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*
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@ -557,8 +560,27 @@ void IRAM_ATTR call_start_cpu0(void)
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// some state of flash is modified.
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mspi_timing_flash_tuning();
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#endif
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}
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esp_mmu_map_init();
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#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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MSPI_INIT_ATTR void mspi_init(void)
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{
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#if CONFIG_ESPTOOLPY_OCT_FLASH && !CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT
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bool efuse_opflash_en = efuse_ll_get_flash_type();
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if (!efuse_opflash_en) {
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ESP_DRAM_LOGE(TAG, "Octal Flash option selected, but EFUSE not configured!");
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abort();
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}
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#endif
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esp_mspi_pin_init();
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// For Octal flash, it's hard to implement a read_id function in OPI mode for all vendors.
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// So we have to read it here in SPI mode, before entering the OPI mode.
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bootloader_flash_update_id();
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flash_init_state();
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esp_mmu_map_init(); //required by image_process() and flash_mmap APIs
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#if !CONFIG_APP_BUILD_TYPE_ELF_RAM
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#if CONFIG_SPIRAM_FLASH_LOAD_TO_PSRAM
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@ -585,15 +607,18 @@ void IRAM_ATTR call_start_cpu0(void)
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#endif
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}
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#endif
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}
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#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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//----------------------------------Separator-----------------------------//
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/**
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* @note
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* After this stage, you can access the flash through the cache, i.e. run code which is not placed in IRAM
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* or print string which locates on flash
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*/
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/*
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* Initialize other parts of the system, including other CPUs.
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* As CPU0 needs to disable the cache in system_early_init function, the other cores are not allowed to run with the
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* cache until the SYS_STARTUP_FN.
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*/
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NOINLINE_ATTR static void system_early_init(const soc_reset_reason_t *rst_reas)
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{
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#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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esp_mspi_pin_reserve();
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#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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@ -647,8 +672,19 @@ void IRAM_ATTR call_start_cpu0(void)
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#endif //CONFIG_SPIRAM_MEMTEST
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#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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//TODO: IDF-5023, replace with MMU driver
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#if CONFIG_IDF_TARGET_ESP32S3
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uint32_t cache_mmu_irom_size = 0;
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uint32_t cache_mmu_drom_size = 0;
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#if !CONFIG_APP_BUILD_TYPE_ELF_RAM
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uint32_t _instruction_size = (uint32_t)&_instruction_reserved_end - (uint32_t)&_instruction_reserved_start;
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cache_mmu_irom_size = ((_instruction_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t);
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uint32_t _rodata_size = (uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start;
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cache_mmu_drom_size = ((_rodata_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t);
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#endif // !CONFIG_APP_BUILD_TYPE_ELF_RAM
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int s_instr_flash2spiram_off = 0;
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int s_rodata_flash2spiram_off = 0;
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#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
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@ -827,7 +863,6 @@ void IRAM_ATTR call_start_cpu0(void)
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s_cpu_inited[0] = true;
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volatile bool cpus_inited = false;
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while (!cpus_inited) {
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cpus_inited = true;
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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@ -836,6 +871,67 @@ void IRAM_ATTR call_start_cpu0(void)
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esp_rom_delay_us(100);
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}
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#endif
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}
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/*
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* We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
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* and the other CPU is in reset. We do have a stack, so we can do the initialization in C.
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*
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* CORE 0 CORE 1
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*
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* call_start_cpu0
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* │
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* ▼
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* cache & other core init
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* │
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* ▼
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* system_early_init────────────────►call_start_cpu1
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* │ │
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* ▼ ▼
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* ESP SYSTEM INIT FN:CORE core init...
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* (accesses to ext mem here) │
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* │ │
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* ▼ ▼
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* ESP SYSTEM INIT FN:SECONDARY ESP SYSTEM INIT FN
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*/
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void IRAM_ATTR call_start_cpu0(void)
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{
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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soc_reset_reason_t rst_reas[SOC_CPU_CORES_NUM] = { [0 ... SOC_CPU_CORES_NUM - 1] = RESET_REASON_CHIP_POWER_ON };
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#else
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soc_reset_reason_t rst_reas[1] = { RESET_REASON_CHIP_POWER_ON };
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#endif
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init_cpu();
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get_reset_reason(rst_reas);
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// Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this.
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init_bss(rst_reas);
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// When the APP is loaded into ram for execution, some hardware initialization steps used to be executed in the
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// bootloader are done here.
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#if CONFIG_APP_BUILD_TYPE_RAM
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ram_app_init();
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#endif //CONFIG_APP_BUILD_TYPE_RAM
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// Initialize the cache.
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#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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cache_init();
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#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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sys_rtc_init(rst_reas);
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// Frequency adjustment and other MSPI initialization stuff like PSRAM initialization.
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#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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mspi_init();
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#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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/* ----------------------------------Separator-----------------------------
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* CPU0 can access external memory (cache) now. Please do not access external memory before this.
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*/
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// Initialize other parts of the system, including other CPUs.
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// As CPU0 needs to disable the cache in system_early_init function and in the CORE stage of ESP SYSTEM INIT FN, the
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// other cores are not allowed to run with the cache until the SECONDARY stage of ESP SYSTEM INIT FN.
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system_early_init(rst_reas);
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SYS_STARTUP_FN();
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}
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@ -200,11 +200,17 @@ static void do_secondary_init(void)
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static void start_cpu0_default(void)
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{
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// Initialize core components and services.
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// Operations that needs the cache to be disabled have to be done here.
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do_core_init();
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// Execute constructors.
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do_global_ctors();
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/* ----------------------------------Separator-----------------------------
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* After this stage, other CPU start running with the cache, however the scheduler (and ipc service) is not available.
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* Don't touch the cache/MMU until the OS is up.
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*/
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// Execute init functions of other components; blocks
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// until all cores finish (when !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE).
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do_secondary_init();
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