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Merge branch 'fix/cache_32m_map' into 'master'

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fix(spi_flash): Fix the cache map 32M flash failed on esp32c5

See merge request espressif/esp-idf!42506
This commit is contained in:
C.S.M
2025-10-14 14:28:02 +08:00
parent 7c1700b0ee 942f2dd0f9
commit 79cc42a940
1 changed files with 10 additions and 2 deletions
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components/esp_rom/patches/esp_rom_spiflash.c
+10 -2
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@@ -774,11 +774,19 @@ void esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, const
// Patch for ROM function `esp_rom_opiflash_cache_mode_config`, because when dummy is 0,
// `SPI_MEM_USR_DUMMY` should be 0. `esp_rom_opiflash_cache_mode_config` doesn't handle this
// properly.
if (cache->dummy_bit_len == 0) {
uint16_t dummy_cyclelen = cache->dummy_bit_len;
if (mode == ESP_ROM_SPIFLASH_DIO_MODE) {
dummy_cyclelen -= 4; // wb_mode(8) / line_width(2)
dummy_cyclelen += rom_spiflash_legacy_data->dummy_len_plus[0];
} else if (mode == ESP_ROM_SPIFLASH_QIO_MODE) {
dummy_cyclelen -= 2; // wb_mode(8) / line_width(4)
dummy_cyclelen += rom_spiflash_legacy_data->dummy_len_plus[0];
}
if (dummy_cyclelen == 0) {
REG_CLR_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_DUMMY);
} else {
REG_SET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_DUMMY);
REG_SET_FIELD(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN, cache->dummy_bit_len - 1 + rom_spiflash_legacy_data->dummy_len_plus[0]);
REG_SET_FIELD(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN, dummy_cyclelen - 1);
}
REG_SET_FIELD(SPI_MEM_USER2_REG(0), SPI_MEM_USR_COMMAND_VALUE, cache->cmd);
REG_SET_FIELD(SPI_MEM_USER2_REG(0), SPI_MEM_USR_COMMAND_BITLEN, cache->cmd_bit_len - 1);