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https://github.com/espressif/esp-idf.git
synced 2025-10-03 10:30:58 +02:00
test(i3c_master): Add multi test for i3c master
This commit is contained in:
@@ -332,14 +332,14 @@ static esp_err_t i3c_pins_config(const i3c_master_bus_config_t *bus_config)
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{
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esp_err_t ret = ESP_OK;
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// SDA pin configurations
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ESP_RETURN_ON_ERROR(gpio_set_level(bus_config->sda_io_num, 1), TAG, "i2c sda pin set level failed");
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ESP_RETURN_ON_ERROR(gpio_set_level(bus_config->sda_io_num, 1), TAG, "i3c sda pin set level failed");
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gpio_input_enable(bus_config->sda_io_num);
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gpio_func_sel(bus_config->sda_io_num, PIN_FUNC_GPIO);
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gpio_matrix_output(bus_config->sda_io_num, i3c_master_periph_signal->sda_out_sig, 0, 0);
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gpio_matrix_input(bus_config->sda_io_num, i3c_master_periph_signal->sda_in_sig, 0);
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// SCL pin configurations
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ESP_RETURN_ON_ERROR(gpio_set_level(bus_config->scl_io_num, 1), TAG, "i2c scl pin set level failed");
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ESP_RETURN_ON_ERROR(gpio_set_level(bus_config->scl_io_num, 1), TAG, "i3c scl pin set level failed");
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gpio_input_enable(bus_config->scl_io_num);
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gpio_func_sel(bus_config->scl_io_num, PIN_FUNC_GPIO);
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gpio_matrix_output(bus_config->scl_io_num, i3c_master_periph_signal->scl_out_sig, 0, 0);
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@@ -445,7 +445,6 @@ static esp_err_t do_dma_transaction_handler(i3c_master_bus_handle_t bus_handle,
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{
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esp_err_t err = ESP_OK;
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bus_handle->cur_trans = trans;
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printf("here, do dma\n");
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portENTER_CRITICAL_SAFE(&bus_handle->spinlock);
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if (trans->scl_freq_hz > 400 * 1000) {
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@@ -509,7 +508,6 @@ static esp_err_t do_dma_transaction_handler(i3c_master_bus_handle_t bus_handle,
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portENTER_CRITICAL_SAFE(&bus_handle->spinlock);
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i3c_master_ll_start_transaction(bus_handle->hal.dev);
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portEXIT_CRITICAL_SAFE(&bus_handle->spinlock);
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printf("here, start transaction\n");
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return ESP_OK;
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}
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@@ -27,5 +27,5 @@ endif()
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message(STATUS "Checking i3c registers are not read-write by half-word")
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include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake)
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check_register_rw_half_word(SOC_MODULES "i3c_mst" "i3c_mst_mem" "hp_sys_clkrst" "lpperi" "lp_clkrst"
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HAL_MODULES "i3c_master")
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check_register_rw_half_word(SOC_MODULES "i3c_mst" "i3c_mst_mem" "hp_sys_clkrst" "i3c_slv"
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HAL_MODULES "i3c_master" "i3c_slave")
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@@ -1,7 +1,8 @@
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set(srcs "test_app_main.c"
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"test_i3c_master_common.c"
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"test_i3c_master_common.cpp"
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"test_i3c_multi.cpp"
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)
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idf_component_register(SRCS ${srcs}
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PRIV_REQUIRES unity test_utils esp_driver_i3c
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PRIV_REQUIRES unity test_utils esp_driver_i3c esp_driver_uart esp_driver_gpio
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WHOLE_ARCHIVE)
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@@ -10,7 +10,7 @@
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#include "esp_heap_caps.h"
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#include "sdkconfig.h"
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#define LEAKS (100)
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#define LEAKS (150)
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void setUp(void)
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{
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@@ -0,0 +1,27 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "sdkconfig.h"
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#include "soc/gpio_num.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define I3C_SLAVE_SCL_IO GPIO_NUM_32 /*!<gpio number for I3C slave clock */
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#define I3C_SLAVE_SDA_IO GPIO_NUM_33 /*!<gpio number for I3C slave data */
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#define I3C_MASTER_SCL_IO GPIO_NUM_32 /*!< gpio number for I3C master clock */
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#define I3C_MASTER_SDA_IO GPIO_NUM_33 /*!< gpio number for I3C master data */
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#define TEST_STATIC_ADDRESS 0x6a
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#define TEST_DYNAMIC_ADDRESS 0x06
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#define DATA_LENGTH 16
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#ifdef __cplusplus
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}
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#endif
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@@ -14,16 +14,21 @@
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#include "freertos/FreeRTOS.h"
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#include "esp_log.h"
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#include "test_utils.h"
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#include "test_i3c_board.h"
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#include "driver/uart.h"
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#include "driver/gpio.h"
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static const char TAG[] = "test-i3c";
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TEST_CASE("I3C bus install-uninstall test", "[i3c]")
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{
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i3c_master_bus_config_t i3c_bus_config = {
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.sda_io_num = I3C_MASTER_SDA_IO,
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.scl_io_num = I3C_MASTER_SCL_IO,
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.clock_source = I3C_MASTER_CLK_SRC_DEFAULT,
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.scl_io_num = 5,
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.sda_io_num = 6,
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.trans_queue_depth = 30,
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.intr_priority = 0,
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.flags = {0}
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};
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i3c_master_bus_handle_t bus_handle;
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@@ -42,10 +47,12 @@ TEST_CASE("I3C bus install-uninstall test", "[i3c]")
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TEST_CASE("I3C driver memory leaking check", "[i3c]")
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{
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i3c_master_bus_config_t i3c_bus_config = {
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.sda_io_num = I3C_MASTER_SDA_IO,
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.scl_io_num = I3C_MASTER_SCL_IO,
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.clock_source = I3C_MASTER_CLK_SRC_DEFAULT,
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.scl_io_num = 5,
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.sda_io_num = 6,
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.trans_queue_depth = 30,
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.intr_priority = 0,
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.flags = {0}
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};
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i3c_master_bus_handle_t bus_handle;
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@@ -62,33 +69,34 @@ TEST_CASE("I3C driver memory leaking check", "[i3c]")
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TEST_CASE("I3C device add & remove check", "[i3c]")
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{
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i3c_master_bus_config_t i2c_mst_config_1 = {
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.sda_io_num = I3C_MASTER_SDA_IO,
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.scl_io_num = I3C_MASTER_SCL_IO,
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.clock_source = I3C_MASTER_CLK_SRC_DEFAULT,
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.scl_io_num = 5,
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.sda_io_num = 6,
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.flags.enable_async_trans = true,
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.trans_queue_depth = 30,
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.intr_priority = 0,
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.flags = {.enable_async_trans = 1}
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};
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i3c_master_bus_handle_t bus_handle;
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TEST_ESP_OK(i3c_new_master_bus(&i2c_mst_config_1, &bus_handle));
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i3c_device_i2c_config_t dev_cfg_1 = {
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.scl_freq_hz = 100 * 1000,
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.device_address = 0x10,
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.scl_freq_hz = 100 * 1000
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};
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i3c_master_i2c_device_handle_t dev_1;
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TEST_ESP_OK(i3c_master_bus_add_i2c_device(bus_handle, &dev_cfg_1, &dev_1));
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i3c_device_i2c_config_t dev_cfg_2 = {
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.scl_freq_hz = 100 * 1000,
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.device_address = 0x20,
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.scl_freq_hz = 100 * 1000
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};
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i3c_master_i2c_device_handle_t dev_2;
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TEST_ESP_OK(i3c_master_bus_add_i2c_device(bus_handle, &dev_cfg_2, &dev_2));
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i3c_device_i2c_config_t dev_cfg_3 = {
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.scl_freq_hz = 100 * 1000,
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.device_address = 0x30,
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.scl_freq_hz = 100 * 1000
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};
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i3c_master_i2c_device_handle_t dev_3;
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TEST_ESP_OK(i3c_master_bus_add_i2c_device(bus_handle, &dev_cfg_3, &dev_3));
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@@ -100,3 +108,49 @@ TEST_CASE("I3C device add & remove check", "[i3c]")
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TEST_ESP_OK(i3c_master_bus_rm_i2c_device(dev_3));
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TEST_ESP_OK(i3c_del_master_bus(bus_handle));
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}
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TEST_CASE("I3C master clock frequency test", "[i3c]")
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{
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uint8_t data_wr[500] = { 0 };
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i3c_master_bus_config_t i3c_mst_config = {
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.sda_io_num = I3C_MASTER_SDA_IO,
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.scl_io_num = I3C_MASTER_SCL_IO,
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.clock_source = I3C_MASTER_CLK_SRC_DEFAULT,
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.trans_queue_depth = 1,
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.intr_priority = 0,
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.flags = {0}
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};
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i3c_master_bus_handle_t bus_handle;
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gpio_pullup_en(I3C_MASTER_SCL_IO);
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gpio_pullup_en(I3C_MASTER_SDA_IO);
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TEST_ESP_OK(i3c_new_master_bus(&i3c_mst_config, &bus_handle));
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i3c_device_i2c_config_t dev_cfg_1 = {
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.device_address = TEST_STATIC_ADDRESS,
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.scl_freq_hz = 400 * 1000
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};
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i3c_master_i2c_device_handle_t dev_1;
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TEST_ESP_OK(i3c_master_bus_add_i2c_device(bus_handle, &dev_cfg_1, &dev_1));
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uart_bitrate_detect_config_t conf = {
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.rx_io_num = I3C_MASTER_SCL_IO,
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.source_clk = UART_SCLK_DEFAULT,
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};
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uart_bitrate_res_t res = {};
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uart_detect_bitrate_start(UART_NUM_1, &conf);
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i3c_master_i2c_device_transmit(dev_1, data_wr, 50, -1);
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vTaskDelay(pdMS_TO_TICKS(50));
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uart_detect_bitrate_stop(UART_NUM_1, true, &res);
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int freq_hz = res.clk_freq_hz / res.pos_period;
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printf("The tested I3C SCL frequency(fm) is %d\n", freq_hz);
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TEST_ASSERT_INT_WITHIN(500, 400000, freq_hz);
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TEST_ESP_OK(i3c_master_bus_rm_i2c_device(dev_1));
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TEST_ESP_OK(i3c_del_master_bus(bus_handle));
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}
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@@ -0,0 +1,247 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Unlicense OR CC0-1.0
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*/
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#include <stdio.h>
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#include <string.h>
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#include "sdkconfig.h"
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#include "unity.h"
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#include "esp_err.h"
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#include "soc/clk_tree_defs.h"
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#include "esp_private/periph_ctrl.h"
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#include "driver/i3c_master.h"
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#include "driver/i3c_master_i2c.h"
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#include "hal/i3c_slave_ll.h"
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#include "esp_log.h"
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#include "test_utils.h"
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#include "test_i3c_board.h"
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#include "esp_private/gpio.h"
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#include "driver/gpio.h"
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#include "esp_heap_caps.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/io_mux_reg.h"
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#include "soc/i3c_slv_struct.h"
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#include "soc/i3c_slv_reg.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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static const char TAG[] = "test-i3c";
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static esp_err_t i3c_slave_pins_config(void)
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{
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esp_err_t ret = ESP_OK;
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// SDA pin configurations
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gpio_input_enable(I3C_SLAVE_SDA_IO);
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gpio_func_sel(I3C_SLAVE_SDA_IO, PIN_FUNC_GPIO);
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gpio_matrix_output(I3C_SLAVE_SDA_IO, I3C_SLV_SDA_PAD_OUT_IDX, 0, 0);
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gpio_matrix_input(I3C_SLAVE_SDA_IO, I3C_SLV_SDA_PAD_IN_IDX, 0);
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// SCL pin configurations
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gpio_input_enable(I3C_SLAVE_SCL_IO);
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gpio_func_sel(I3C_SLAVE_SCL_IO, PIN_FUNC_GPIO);
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gpio_matrix_output(I3C_SLAVE_SCL_IO, I3C_SLV_SCL_PAD_OUT_IDX, 0, 0);
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gpio_matrix_input(I3C_SLAVE_SCL_IO, I3C_SLV_SCL_PAD_IN_IDX, 0);
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return ret;
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}
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static void i3c_slave_init(void)
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{
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PERIPH_RCC_ATOMIC() {
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i3c_slave_ll_enable_bus_clock(&I3C_SLV, true);
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i3c_slave_ll_reset_register(&I3C_SLV);
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}
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i3c_slave_pins_config();
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i3c_slave_ll_config_static_address(&I3C_SLV, TEST_STATIC_ADDRESS);
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i3c_slave_ll_enable_intr_mask(&I3C_SLV, I3C_SLAVE_LL_EVENT_INTR);
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i3c_slave_ll_unlock_register(&I3C_SLV, true);
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i3c_slave_ll_set_transmit_fifo_threshold(&I3C_SLV, 1);
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i3c_slave_ll_set_receive_fifo_threshold(&I3C_SLV, 1);
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}
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static void i3c_i2c_slave_read_test(void)
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{
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unity_wait_for_signal("i2c master init first");
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uint8_t *temp_data = (uint8_t*)heap_caps_malloc(DATA_LENGTH, MALLOC_CAP_DEFAULT);
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assert(temp_data);
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i3c_slave_init();
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unity_send_signal("i2c slave init finish");
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unity_wait_for_signal("master write");
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i3c_slave_ll_read_data(&I3C_SLV, temp_data, DATA_LENGTH);
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ESP_LOG_BUFFER_HEX(TAG, temp_data, DATA_LENGTH);
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for (int i = 0; i < DATA_LENGTH; i++) {
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TEST_ASSERT(temp_data[i] == i);
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}
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unity_send_signal("ready to delete");
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free(temp_data);
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}
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static void i3c_i2c_master_write_test(void)
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{
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uint8_t data_wr[DATA_LENGTH] = { 0 };
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int i;
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i3c_master_bus_config_t i3c_mst_config = {
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.sda_io_num = I3C_MASTER_SDA_IO,
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.scl_io_num = I3C_MASTER_SCL_IO,
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.clock_source = I3C_MASTER_CLK_SRC_DEFAULT,
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.trans_queue_depth = 1,
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.intr_priority = 0,
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.flags = {0}
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};
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i3c_master_bus_handle_t bus_handle;
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gpio_pullup_en(I3C_MASTER_SCL_IO);
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gpio_pullup_en(I3C_MASTER_SDA_IO);
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TEST_ESP_OK(i3c_new_master_bus(&i3c_mst_config, &bus_handle));
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i3c_device_i2c_config_t dev_cfg = {
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.device_address = TEST_STATIC_ADDRESS,
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.scl_freq_hz = 100 * 1000
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};
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i3c_master_i2c_device_handle_t dev;
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TEST_ESP_OK(i3c_master_bus_add_i2c_device(bus_handle, &dev_cfg, &dev));
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unity_send_signal("i2c master init first");
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unity_wait_for_signal("i2c slave init finish");
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unity_send_signal("master write");
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for (i = 0; i < DATA_LENGTH; i++) {
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data_wr[i] = i;
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}
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ESP_LOG_BUFFER_HEX(TAG, data_wr, i);
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i3c_master_i2c_device_transmit(dev, data_wr, DATA_LENGTH, -1);
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unity_wait_for_signal("ready to delete");
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TEST_ESP_OK(i3c_master_bus_rm_i2c_device(dev));
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TEST_ESP_OK(i3c_del_master_bus(bus_handle));
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}
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TEST_CASE_MULTIPLE_DEVICES("I3C-I2C master write slave test in fifo mode", "[i3c][test_env=generic_multi_device][timeout=150]", i3c_i2c_master_write_test, i3c_i2c_slave_read_test);
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static void i3c_i2c_master_read_slave_test(void)
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{
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uint8_t data_rd[DATA_LENGTH] = {0};
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i3c_master_bus_config_t i3c_mst_config = {
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.sda_io_num = I3C_MASTER_SDA_IO,
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.scl_io_num = I3C_MASTER_SCL_IO,
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.clock_source = I3C_MASTER_CLK_SRC_DEFAULT,
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.trans_queue_depth = 1,
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.intr_priority = 0,
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.flags = {0}
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};
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i3c_master_bus_handle_t bus_handle;
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gpio_pullup_en(I3C_MASTER_SCL_IO);
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gpio_pullup_en(I3C_MASTER_SDA_IO);
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TEST_ESP_OK(i3c_new_master_bus(&i3c_mst_config, &bus_handle));
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i3c_device_i2c_config_t dev_cfg = {
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.device_address = TEST_STATIC_ADDRESS,
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.scl_freq_hz = 100 * 1000
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};
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i3c_master_i2c_device_handle_t dev;
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TEST_ESP_OK(i3c_master_bus_add_i2c_device(bus_handle, &dev_cfg, &dev));
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unity_wait_for_signal("i2c slave init finish");
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i3c_master_i2c_device_receive(dev, data_rd, DATA_LENGTH, -1);
|
||||
vTaskDelay(100 / portTICK_PERIOD_MS);
|
||||
for (int i = 0; i < DATA_LENGTH; i++) {
|
||||
printf("%x\n", data_rd[i]);
|
||||
TEST_ASSERT(data_rd[i] == i);
|
||||
}
|
||||
unity_send_signal("ready to delete master read test");
|
||||
|
||||
TEST_ESP_OK(i3c_master_bus_rm_i2c_device(dev));
|
||||
TEST_ESP_OK(i3c_del_master_bus(bus_handle));
|
||||
}
|
||||
|
||||
static void i3c_i2c_slave_write_buffer_test(void)
|
||||
{
|
||||
|
||||
uint8_t data_wr[DATA_LENGTH];
|
||||
|
||||
i3c_slave_init();
|
||||
|
||||
for (int i = 0; i < DATA_LENGTH; i++) {
|
||||
data_wr[i] = i;
|
||||
}
|
||||
|
||||
i3c_slave_ll_write_data(&I3C_SLV, data_wr, DATA_LENGTH);
|
||||
|
||||
unity_send_signal("i2c slave init finish");
|
||||
|
||||
unity_wait_for_signal("ready to delete master read test");
|
||||
}
|
||||
|
||||
TEST_CASE_MULTIPLE_DEVICES("I3C-I2C master read slave test in fifo mode", "[i3c][test_env=generic_multi_device][timeout=150]", i3c_i2c_master_read_slave_test, i3c_i2c_slave_write_buffer_test);
|
||||
|
||||
static void i3c_i2c_master_write_via_dma_test(void)
|
||||
{
|
||||
__attribute__((aligned(4))) uint8_t data_wr[DATA_LENGTH] = { 0 };
|
||||
int i;
|
||||
|
||||
i3c_master_bus_config_t i3c_mst_config = {
|
||||
.sda_io_num = I3C_MASTER_SDA_IO,
|
||||
.scl_io_num = I3C_MASTER_SCL_IO,
|
||||
.clock_source = I3C_MASTER_CLK_SRC_DEFAULT,
|
||||
.trans_queue_depth = 1,
|
||||
.intr_priority = 0,
|
||||
.flags = {0}
|
||||
};
|
||||
i3c_master_bus_handle_t bus_handle;
|
||||
gpio_pullup_en(I3C_MASTER_SCL_IO);
|
||||
gpio_pullup_en(I3C_MASTER_SDA_IO);
|
||||
|
||||
TEST_ESP_OK(i3c_new_master_bus(&i3c_mst_config, &bus_handle));
|
||||
|
||||
i3c_device_i2c_config_t dev_cfg = {
|
||||
.device_address = TEST_STATIC_ADDRESS,
|
||||
.scl_freq_hz = 100 * 1000
|
||||
};
|
||||
i3c_master_i2c_device_handle_t dev;
|
||||
TEST_ESP_OK(i3c_master_bus_add_i2c_device(bus_handle, &dev_cfg, &dev));
|
||||
|
||||
i3c_master_dma_config_t dma_config = {
|
||||
.max_transfer_size = 50,
|
||||
.dma_burst_size = 16,
|
||||
};
|
||||
|
||||
i3c_master_bus_decorate_dma(bus_handle, &dma_config);
|
||||
|
||||
unity_send_signal("i2c master init first");
|
||||
|
||||
unity_wait_for_signal("i2c slave init finish");
|
||||
|
||||
unity_send_signal("master write");
|
||||
for (i = 0; i < DATA_LENGTH; i++) {
|
||||
data_wr[i] = i;
|
||||
}
|
||||
|
||||
ESP_LOG_BUFFER_HEX(TAG, data_wr, i);
|
||||
i3c_master_i2c_device_transmit(dev, data_wr, DATA_LENGTH, -1);
|
||||
|
||||
unity_wait_for_signal("ready to delete");
|
||||
|
||||
TEST_ESP_OK(i3c_master_bus_rm_i2c_device(dev));
|
||||
TEST_ESP_OK(i3c_master_bus_decorate_dma(bus_handle, NULL));
|
||||
TEST_ESP_OK(i3c_del_master_bus(bus_handle));
|
||||
}
|
||||
|
||||
TEST_CASE_MULTIPLE_DEVICES("I3C-I2C master write slave test in dma mode", "[i3c][test_env=generic_multi_device][timeout=150]", i3c_i2c_master_write_via_dma_test, i3c_i2c_slave_read_test);
|
@@ -18,3 +18,17 @@ from pytest_embedded_idf.utils import soc_filtered_targets
|
||||
@idf_parametrize('target', soc_filtered_targets('SOC_I3C_MASTER_SUPPORTED == 1'), indirect=['target'])
|
||||
def test_i3c(dut: Dut) -> None:
|
||||
dut.run_all_single_board_cases()
|
||||
|
||||
|
||||
@pytest.mark.generic_multi_device
|
||||
@pytest.mark.parametrize(
|
||||
'count, config',
|
||||
[
|
||||
(2, 'release'),
|
||||
(2, 'cache_safe'),
|
||||
],
|
||||
indirect=True,
|
||||
)
|
||||
@idf_parametrize('target', soc_filtered_targets('SOC_I3C_MASTER_SUPPORTED == 1'), indirect=['target'])
|
||||
def test_i3c_multi_device(case_tester) -> None: # type: ignore
|
||||
case_tester.run_all_multi_dev_cases(reset=True)
|
||||
|
@@ -84,7 +84,7 @@ void periph_rcc_exit(void);
|
||||
#ifdef __PERIPH_CTRL_ALLOW_LEGACY_API
|
||||
#define __PERIPH_CTRL_DEPRECATE_ATTR
|
||||
#else
|
||||
#define __PERIPH_CTRL_DEPRECATE_ATTR __attribute__((deprecated("This function is not functional on "CONFIG_IDF_TARGET)))
|
||||
#define __PERIPH_CTRL_DEPRECATE_ATTR __attribute__((deprecated("This function is not functional on " CONFIG_IDF_TARGET)))
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
Reference in New Issue
Block a user