espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-03 12:44:33 +02:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'bugfix/esp32c6_src_clk_label' into 'master'

Browse Source 
clk: esp32c6: rename modem clock source selection

See merge request espressif/esp-idf!39756
This commit is contained in:
Wu Zheng Hui
2025-06-17 22:01:33 +08:00
parent 5f1ad2c18d 044de64f5b
commit 8ab969db1c
2 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
components/esp_system/port/soc/esp32c6/clk.c
View File

@@ -231,7 +231,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K \
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? MODEM_CLOCK_LPCLK_SRC_RC32K \
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K \
: SOC_RTC_SLOW_CLK_SRC_RC_SLOW);
: MODEM_CLOCK_LPCLK_SRC_RC_SLOW);
modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);

2
components/esp_system/port/soc/esp32c61/clk.c
View File

@@ -194,7 +194,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
(rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_RC_SLOW
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K
: SOC_RTC_SLOW_CLK_SRC_RC_SLOW);
: MODEM_CLOCK_LPCLK_SRC_RC_SLOW);
modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
#endif