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fix chip broken bug in monitor mode c3 s2 to v4.4

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This commit is contained in:
hongshuqing
2023-05-15 19:36:25 +08:00
committed by Xiao Xufeng
parent f326b7e7a6
commit 8e911f67b8
6 changed files with 227 additions and 86 deletions
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2
components/esp_hw_support/port/esp32c3/rtc_pm.c
View File

@@ -53,9 +53,7 @@ pm_sw_reject_t pm_set_sleep_mode(pm_sleep_mode_t sleep_mode, void(*pmac_save_par
switch (sleep_mode) {
case PM_LIGHT_SLEEP:
cfg.wifi_pd_en = 1;
cfg.dig_dbias_wak = 4;
cfg.dig_dbias_slp = 0;
cfg.rtc_dbias_wak = 0;
cfg.rtc_dbias_slp = 0;
rtc_sleep_init(cfg);
break;

119
components/esp_hw_support/port/esp32c3/rtc_sleep.c
View File

@@ -84,36 +84,90 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_
};
if (sleep_flags & RTC_SLEEP_PD_DIG) {
unsigned atten_deep_sleep = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
#if CONFIG_ESP32C3_REV_MIN_FULL < 3
assert(sleep_flags & RTC_SLEEP_PD_XTAL);
bool eco2_workaround = false;
#if CONFIG_ESP32C3_REV_MIN_FULL < 3
if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 3)) {
atten_deep_sleep = 0; /* workaround for deep sleep issue in high temp on ECO2 and below */
eco2_workaround = true; /* workaround for deep sleep issue in high temp on ECO2 and below */
}
#endif
if (!(sleep_flags & RTC_SLEEP_PD_INT_8M)) {
/*
* dbg_att_slp need to set to 0: rtc voltage is about 0.83v
* support all features:
* - 8MD256 as RTC slow clock src
* - RTC memory under high temperature
* - RTC IO as input
*/
out_config->rtc_regulator_fpu = 1;
out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP;
out_config->rtc_dbias_slp = 0;
} else if (sleep_flags & RTC_SLEEP_NO_ULTRA_LOW) {
/*
* Default mode
* rtc voltage in sleep need stable and not less than 0.7v
* support features:
* - RTC memory under high temperature
* - RTC IO as input
*/
out_config->rtc_regulator_fpu = 1;
out_config->dbg_atten_slp = eco2_workaround ? RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP: RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_DEEPSLEEP_0V7;
} else {
/*
* rtc regulator not opened and rtc voltage is about 0.66v (ultra low power):
* not support features:
* - RTC IO as input
* - RTC memory under high temperature
*/
out_config->rtc_regulator_fpu = 0;
out_config->dbg_atten_slp = eco2_workaround ? RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP: RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
out_config->rtc_dbias_slp = 0; /* not used */
}
#endif
out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10;
out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP;
out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10;
out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP;
out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT;
out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT;
out_config->dbg_atten_slp = atten_deep_sleep;
out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT;
out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT;
out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT;
} else {
out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10;
out_config->dig_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP;
out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10;
out_config->rtc_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP;
out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT;
out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT;
out_config->dbg_atten_slp = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP;
out_config->bias_sleep_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_BIASSLP_SLEEP_ON : RTC_CNTL_BIASSLP_SLEEP_DEFAULT;
out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT;
out_config->pd_cur_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_PD_CUR_SLEEP_ON : RTC_CNTL_PD_CUR_SLEEP_DEFAULT;
out_config->rtc_regulator_fpu = 1;
// rtc & digital voltage from high to low
if ((sleep_flags & RTC_SLEEP_DIG_USE_8M) || !(sleep_flags & RTC_SLEEP_PD_XTAL)) {
/*
* digital voltage need to be >= 1.1v
* if 8MD256 select as RTC slow clock src, only need dbg_atten_slp set to 0
* Support all features:
* - XTAL
* - RC 8M used by digital system
* - 8MD256 as RTC slow clock src
*/
out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP;
out_config->dig_dbias_slp = RTC_CNTL_DBIAS_1V10;
out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_1V10;
} else if (!(sleep_flags & RTC_SLEEP_PD_INT_8M)){
/*
* dbg_att_slp need to set to 0: digital voltage is about 0.67v & rtc vol is about 0.83v
* Support features:
* - 8MD256 as RTC slow clock src
*/
out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP;
out_config->dig_dbias_slp = 0;
out_config->rtc_dbias_slp = 0;
} else {
/*
* digital voltage not less than 0.6v.
* not support features:
* - XTAL
* - RC 8M used by digital system
* - 8MD256 as RTC slow clock src
*/
out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT;
out_config->dig_dbias_slp = RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V6;
out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V6;
}
}
if (!(sleep_flags & RTC_SLEEP_PD_XTAL)) {
out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_ON;
out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_ON;
} else {
out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT;
out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT;
}
}
@@ -145,20 +199,19 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN);
}
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT);
assert(!cfg.pd_cur_slp || cfg.bias_sleep_slp);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, cfg.dbg_atten_monitor);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, cfg.dbg_atten_slp);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, cfg.bias_sleep_slp);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, cfg.pd_cur_monitor);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp);
if (cfg.deep_slp) {
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU |
@@ -166,10 +219,10 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
} else {
SET_PERI_REG_MASK(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DG_VDD_DRV_B_SLP_EN);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT);
SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
}
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, cfg.rtc_regulator_fpu);
if (!cfg.int_8m_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);

2
components/esp_hw_support/port/esp32s2/rtc_pm.c
View File

@@ -53,9 +53,7 @@ pm_sw_reject_t pm_set_sleep_mode(pm_sleep_mode_t sleep_mode, void(*pmac_save_par
switch (sleep_mode) {
case PM_LIGHT_SLEEP:
cfg.wifi_pd_en = 1;
cfg.dig_dbias_wak = 4;
cfg.dig_dbias_slp = 0;
cfg.rtc_dbias_wak = 0;
cfg.rtc_dbias_slp = 0;
rtc_sleep_init(cfg);
break;

129
components/esp_hw_support/port/esp32s2/rtc_sleep.c
View File

@@ -71,33 +71,102 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_
};
if (sleep_flags & RTC_SLEEP_PD_DIG) {
out_config->dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10;
out_config->dig_dbias_slp = RTC_CNTL_DIG_DBIAS_0V90;
out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10;
out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_1V00;
out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT;
out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT;
out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT;
out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT;
out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT;
assert(sleep_flags & RTC_SLEEP_PD_XTAL);
out_config->dig_dbias_slp = 0; //not used
//rtc voltage from high to low
if ((sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) || !(sleep_flags & RTC_SLEEP_PD_INT_8M)) {
/*
* rtc voltage in sleep mode >= 0.9v
* if 8MD256 select as RTC slow clock src, only need dbg_atten_slp set to 0
* Support all features:
* - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monitor = 0)
* - 8MD256 as RTC slow clock src
* - RTC IO as input
* - RTC Memory at high temperature
* - ULP
* - Touch sensor
*/
out_config->rtc_regulator_fpu = 1;
out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP;
out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_0V90;
} else if (sleep_flags & RTC_SLEEP_NO_ULTRA_LOW) {
/*
* rtc voltage in sleep mode >= 0.7v (default mode)
* Support features:
* - RTC IO as input
* - RTC Memory at high temperature
* - ULP
* - Touch sensor
*/
out_config->rtc_regulator_fpu = 1;
out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_DEEPSLEEP_0V7;
} else {
/*
* rtc regulator not opened and rtc voltage is about 0.66v (ultra low power)
* Support features:
* - ULP
* - Touch sensor
*/
out_config->rtc_regulator_fpu = 0;
out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
out_config->rtc_dbias_slp = 0;
}
} else {
out_config->rtc_regulator_fpu = 1;
// rtc & digital voltage from high to low
if ((sleep_flags & RTC_SLEEP_DIG_USE_8M) || !(sleep_flags & RTC_SLEEP_PD_XTAL) || !(sleep_flags & RTC_SLEEP_PD_INT_8M)) {
/*
* digital voltage need to be >= 1.1v
* if 8MD256 select as RTC slow clock src, only need dbg_atten_slp set to 0
* rtc voltage need to near digital voltage to keep system stable
* Support all features:
* - XTAL
* - RC 8M used by digital system
* - 8MD256 as RTC slow clock src (only need dbg_atten_slp set to 0)
* - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monitor = 0)
* - ULP
* - Touch sensor
*/
out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP;
out_config->dig_dbias_slp = RTC_CNTL_DBIAS_1V10;
out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_1V10;
} else if (sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) {
/*
* rtc voltage need to be >= 0.9v
* digital voltage need to near rtc voltage to make system stable and low current
* Support features:
* - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monitor = 0)
* - ULP
* - Touch sensor
*/
out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT;
out_config->dig_dbias_slp = RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V9;
out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V9;
} else {
/*
* digital voltage not less than 0.75v.
* rtc voltage need to near digital voltage to keep system stable
* Support features:
* - ULP
* - Touch sensor
*/
out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT;
out_config->dig_dbias_slp = RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V75;
out_config->rtc_dbias_slp = RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V75;
}
}
if (!(sleep_flags & RTC_SLEEP_PD_XTAL)) {
out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_ON;
out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_ON;
out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_ON;
out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_ON;
} else {
out_config->dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10;
out_config->dig_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DIG_DBIAS_1V10
: !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_DIG_DBIAS_1V10
: RTC_CNTL_DIG_DBIAS_0V90;
out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10;
out_config->rtc_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10
: !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_DBIAS_1V10
: RTC_CNTL_DBIAS_1V00;
out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT;
out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT;
out_config->dbg_atten_slp = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP;
out_config->bias_sleep_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_BIASSLP_SLEEP_ON : RTC_CNTL_BIASSLP_SLEEP_DEFAULT;
out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT;
out_config->pd_cur_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_PD_CUR_SLEEP_ON : RTC_CNTL_PD_CUR_SLEEP_DEFAULT;
out_config->pd_cur_monitor = (sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR)?
RTC_CNTL_PD_CUR_MONITOR_ON : RTC_CNTL_PD_CUR_MONITOR_DEFAULT;
out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT;
out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT;
}
}
@@ -146,12 +215,13 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
}
assert(!cfg.pd_cur_monitor || cfg.bias_sleep_monitor);
assert(!cfg.pd_cur_slp || cfg.bias_sleep_slp);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, cfg.rtc_dbias_slp);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, cfg.rtc_dbias_wak);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, cfg.dig_dbias_wak);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, cfg.dbg_atten_monitor);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, cfg.bias_sleep_slp);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, cfg.pd_cur_monitor);
@@ -159,16 +229,15 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, cfg.dbg_atten_slp);
if (cfg.deep_slp) {
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU |
RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU);
} else {
SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
}
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, cfg.rtc_regulator_fpu);
if (!cfg.int_8m_pd_en) {
REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
} else {

30
components/soc/esp32c3/include/soc/rtc.h
View File

@@ -62,7 +62,6 @@ extern "C" {
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
*/
#define RTC_CNTL_DBIAS_SLP 5 //sleep dig_dbias & rtc_dbias
#define RTC_CNTL_DBIAS_0V90 13 //digital voltage
#define RTC_CNTL_DBIAS_0V95 16
#define RTC_CNTL_DBIAS_1V00 18
@@ -111,14 +110,27 @@ set sleep_init default param
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP 0
#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1
#define RTC_CNTL_BIASSLP_SLEEP_ON 0
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
#define RTC_CNTL_PD_CUR_SLEEP_ON 0
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0
#define RTC_CNTL_BIASSLP_SLEEP_ON 0
#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1
#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0
#define RTC_CNTL_PD_CUR_SLEEP_ON 0
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
/*
use together with RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT
*/
#define RTC_CNTL_RTC_DBIAS_DEEPSLEEP_0V7 25
/*
use together with RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT
*/
#define RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V6 5
#define RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V6 5
/*
The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
@@ -651,18 +663,14 @@ typedef struct {
uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals
uint32_t deep_slp : 1; //!< power down digital domain
uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode
uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode
uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode
uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode
uint32_t dbg_atten_monitor : 4; //!< voltage parameter, in monitor mode
uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode
uint32_t dbg_atten_slp : 4; //!< voltage parameter, in sleep mode
uint32_t bias_sleep_slp : 1; //!< circuit control parameter, in sleep mode
uint32_t pd_cur_monitor : 1; //!< circuit control parameter, in monitor mode
uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode
uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep
uint32_t rtc_regulator_fpu : 1; //!< keep rtc regulator powered up in sleep
uint32_t deep_slp_reject : 1;
uint32_t light_slp_reject : 1;
} rtc_sleep_config_t;

31
components/soc/esp32s2/include/soc/rtc.h
View File

@@ -123,13 +123,30 @@ set sleep_init default param
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 6
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0
#define RTC_CNTL_BIASSLP_SLEEP_ON 0
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP 0
#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1
#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 1
#define RTC_CNTL_PD_CUR_SLEEP_ON 0
#define RTC_CNTL_BIASSLP_SLEEP_ON 0
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
#define RTC_CNTL_PD_CUR_SLEEP_ON 0
#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 1
#define RTC_CNTL_BIASSLP_MONITOR_ON 0
#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 1
#define RTC_CNTL_PD_CUR_MONITOR_ON 0
/*
use together with RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT
*/
#define RTC_CNTL_RTC_DBIAS_DEEPSLEEP_0V7 RTC_CNTL_DBIAS_1V25
/*
use together with RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT
*/
#define RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V9 5
#define RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V9 4
#define RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V75 0
#define RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V75 1
#define APLL_SDM_STOP_VAL_1 0x09
#define APLL_SDM_STOP_VAL_2_REV0 0x69
@@ -674,11 +691,8 @@ typedef struct {
uint32_t int_8m_pd_en : 1; //!< Power down Internal 8M oscillator
uint32_t deep_slp : 1; //!< power down digital domain
uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
uint32_t dig_dbias_wak : 3; //!< set bias for digital domain, in active mode
uint32_t dig_dbias_slp : 3; //!< set bias for digital domain, in sleep mode
uint32_t rtc_dbias_wak : 3; //!< set bias for RTC domain, in active mode
uint32_t rtc_dbias_slp : 3; //!< set bias for RTC domain, in sleep mode
uint32_t dbg_atten_monitor : 4; //!< voltage parameter, in monitor mode
uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode
uint32_t dbg_atten_slp : 4; //!< voltage parameter, in sleep mode
uint32_t bias_sleep_slp : 1; //!< circuit control parameter, in sleep mode
@@ -686,6 +700,7 @@ typedef struct {
uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode
uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep
uint32_t rtc_regulator_fpu : 1; //!< keep rtc regulator powered up in sleep
uint32_t deep_slp_reject : 1;
uint32_t light_slp_reject : 1;
} rtc_sleep_config_t;