mirror of
https://github.com/espressif/esp-idf.git
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Feature: high level interrupt(5)
This commit is contained in:
baohongde
223
components/bt/hli_api.c
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223
components/bt/hli_api.c
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@ -0,0 +1,223 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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// All rights reserved.
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#include <string.h>
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#include "esp_log.h"
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#include "esp_heap_caps.h"
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#include "xtensa/core-macros.h"
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#include "soc/dport_reg.h"
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#include "hli_api.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/queue.h"
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#define HLI_MAX_HANDLERS 4
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typedef struct {
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intr_handler_t handler;
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void* arg;
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uint32_t intr_reg;
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uint32_t intr_mask;
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} hli_handler_info_t;
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static hli_handler_info_t s_hli_handlers[HLI_MAX_HANDLERS];
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static const char* TAG = "hli_queue";
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esp_err_t hli_intr_register(intr_handler_t handler, void* arg, uint32_t intr_reg, uint32_t intr_mask)
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{
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for (hli_handler_info_t* hip = s_hli_handlers;
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hip < s_hli_handlers + HLI_MAX_HANDLERS;
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++hip) {
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if (hip->handler == NULL) {
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hip->arg = arg;
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hip->intr_reg = intr_reg;
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hip->intr_mask = intr_mask;
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hip->handler = handler; /* set last, indicates the entry as valid */
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return ESP_OK;
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}
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}
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return ESP_ERR_NO_MEM;
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}
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void IRAM_ATTR hli_c_handler(void)
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{
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bool handled = false;
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/* Iterate over registered interrupt handlers,
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* and check if the expected mask is present in the interrupt status register.
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*/
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for (hli_handler_info_t* hip = s_hli_handlers;
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hip < s_hli_handlers + HLI_MAX_HANDLERS;
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++hip) {
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if (hip->handler == NULL) {
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continue;
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}
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uint32_t reg = hip->intr_reg;
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uint32_t val;
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if (reg == 0) { /* special case for CPU internal interrupts */
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val = XTHAL_GET_INTERRUPT();
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} else {
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/* "reg" might not be in DPORT, but this will work in any case */
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val = DPORT_REG_READ(reg);
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}
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if ((val & hip->intr_mask) != 0) {
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handled = true;
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(*hip->handler)(hip->arg);
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}
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}
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if (!handled) {
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ets_printf(DRAM_STR("hli_c_handler: no handler found!\n"));
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abort();
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}
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}
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uint32_t hli_intr_disable(void)
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{
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// disable level 4 and below
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return XTOS_SET_INTLEVEL(XCHAL_DEBUGLEVEL - 2);
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}
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void hli_intr_restore(uint32_t state)
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{
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XTOS_RESTORE_JUST_INTLEVEL(state);
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}
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#define HLI_META_QUEUE_SIZE 16
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#define HLI_QUEUE_MAX_ELEM_SIZE 32
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#define HLI_QUEUE_SW_INT_NUM 29
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#define HLI_QUEUE_FLAG_SEMAPHORE BIT(0)
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struct hli_queue_t s_meta_queue;
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static inline char* IRAM_ATTR wrap_ptr(hli_queue_handle_t queue, char *ptr)
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{
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return (ptr == queue->bufend) ? queue->buf : ptr;
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}
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static inline bool IRAM_ATTR queue_empty(hli_queue_handle_t queue)
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{
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return queue->begin == queue->end;
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}
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static inline bool IRAM_ATTR queue_full(hli_queue_handle_t queue)
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{
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return wrap_ptr(queue, queue->end + queue->elem_size) == queue->begin;
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}
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static void IRAM_ATTR queue_isr_handler(void* arg)
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{
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int do_yield = pdFALSE;
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XTHAL_SET_INTCLEAR(BIT(HLI_QUEUE_SW_INT_NUM));
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hli_queue_handle_t queue;
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while (hli_queue_get(&s_meta_queue, &queue)) {
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static char scratch[HLI_QUEUE_MAX_ELEM_SIZE];
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while (hli_queue_get(queue, scratch)) {
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int res = pdPASS;
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if ((queue->flags & HLI_QUEUE_FLAG_SEMAPHORE) != 0) {
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res = xSemaphoreGiveFromISR((SemaphoreHandle_t) queue->downstream, &do_yield);
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} else {
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res = xQueueSendFromISR(queue->downstream, scratch, &do_yield);
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}
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if (res == pdFAIL) {
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ESP_EARLY_LOGE(TAG, "Failed to send to queue %p", queue->downstream);
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}
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}
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}
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if (do_yield) {
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portYIELD_FROM_ISR();
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}
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}
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static void IRAM_ATTR queue_signal(hli_queue_handle_t queue)
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{
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bool res = hli_queue_put(&s_meta_queue, &queue);
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if (!res) {
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abort();
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}
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XTHAL_SET_INTSET(BIT(HLI_QUEUE_SW_INT_NUM));
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}
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static void queue_init(hli_queue_handle_t queue, size_t buf_size, size_t elem_size, QueueHandle_t downstream)
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{
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queue->elem_size = elem_size;
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queue->begin = queue->buf;
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queue->end = queue->buf;
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queue->bufend = queue->buf + buf_size;
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queue->downstream = downstream;
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queue->flags = 0;
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}
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void hli_queue_setup(void)
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{
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queue_init(&s_meta_queue, HLI_META_QUEUE_SIZE * sizeof(void*), sizeof(void*), NULL);
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ESP_ERROR_CHECK(esp_intr_alloc(ETS_INTERNAL_SW1_INTR_SOURCE, ESP_INTR_FLAG_IRAM, queue_isr_handler, NULL, NULL));
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xt_ints_on(BIT(HLI_QUEUE_SW_INT_NUM));
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}
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hli_queue_handle_t hli_queue_create(size_t nelem, size_t elem_size, QueueHandle_t downstream)
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{
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const size_t buf_elem = nelem + 1;
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if (elem_size > HLI_QUEUE_MAX_ELEM_SIZE) {
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return NULL;
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}
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size_t buf_size = buf_elem * elem_size;
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hli_queue_handle_t res = (hli_queue_handle_t) heap_caps_malloc(sizeof(*res) + buf_size,
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MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
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if (res == NULL) {
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return NULL;
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}
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queue_init(res, buf_size, elem_size, downstream);
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return res;
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}
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hli_queue_handle_t hli_semaphore_create(size_t max_count, SemaphoreHandle_t downstream)
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{
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const size_t elem_size = 1;
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hli_queue_handle_t res = hli_queue_create(max_count, elem_size, (QueueHandle_t) downstream);
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if (res == NULL) {
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return NULL;
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}
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res->flags |= HLI_QUEUE_FLAG_SEMAPHORE;
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return res;
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}
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void hli_queue_delete(hli_queue_handle_t queue)
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{
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free(queue);
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}
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bool IRAM_ATTR hli_queue_get(hli_queue_handle_t queue, void* out)
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{
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uint32_t int_state = hli_intr_disable();
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bool res = false;
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if (!queue_empty(queue)) {
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memcpy(out, queue->begin, queue->elem_size);
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queue->begin = wrap_ptr(queue, queue->begin + queue->elem_size);
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res = true;
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}
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hli_intr_restore(int_state);
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return res;
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}
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bool IRAM_ATTR hli_queue_put(hli_queue_handle_t queue, const void* data)
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{
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uint32_t int_state = hli_intr_disable();
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bool res = false;
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bool was_empty = queue_empty(queue);
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if (!queue_full(queue)) {
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memcpy(queue->end, data, queue->elem_size);
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queue->end = wrap_ptr(queue, queue->end + queue->elem_size);
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if (was_empty && queue != &s_meta_queue) {
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queue_signal(queue);
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}
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res = true;
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}
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hli_intr_restore(int_state);
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return res;
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}
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bool IRAM_ATTR hli_semaphore_give(hli_queue_handle_t queue)
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{
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uint8_t data = 0;
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return hli_queue_put(queue, &data);
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}
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141
components/bt/hli_api.h
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141
components/bt/hli_api.h
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@ -0,0 +1,141 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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// All rights reserved.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include "esp_err.h"
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#include "esp_intr_alloc.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/queue.h"
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#include "freertos/semphr.h"
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/*** Queues ***/
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struct hli_queue_t
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{
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size_t elem_size;
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char* begin;
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char* end;
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const char* bufend;
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QueueHandle_t downstream;
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int flags;
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char buf[0];
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};
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/**
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* @brief Register a high level interrupt function
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*
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* @param handler interrupt handler function
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* @param arg argument to pass to the interrupt handler
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* @param intr_reg address of the peripheral register containing the interrupt status,
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* or value 0 to get the status from CPU INTERRUPT register
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* @param intr_mask mask of the interrupt, in the interrupt status register
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* @return
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* - ESP_OK on success
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* - ESP_ERR_NO_MEM if too many handlers are registered
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*/
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esp_err_t hli_intr_register(intr_handler_t handler, void* arg, uint32_t intr_reg, uint32_t intr_mask);
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/**
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* @brief Mask all interrupts (including high level ones) on the current CPU
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*
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* @return uint32_t interrupt status, pass it to hli_intr_restore
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*/
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uint32_t hli_intr_disable(void);
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/**
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* @brief Re-enable interrupts
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*
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* @param state value returned by hli_intr_disable
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*/
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void hli_intr_restore(uint32_t state);
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/**
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* @brief Type of a hli queue
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*/
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typedef struct hli_queue_t* hli_queue_handle_t;
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/**
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* @brief Initialize hli_queue module. Must be called once before using hli queue APIs.
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*/
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void hli_queue_setup(void);
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/**
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* @brief Create a hli queue, wrapping a FreeRTOS queue
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*
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* This queue can be used from high level interrupts,
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* but **ONLY ON THE CPU WHERE hli_queue_setup WAS CALLED**. Values sent to this
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* queue are automatically forwarded to "downstream" FreeRTOS queue using a level 3
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* software interrupt.
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*
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* @param nelem number of elements in the queue
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* @param elem_size size of one element; must match element size of a downstream queue
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* @param downstream FreeRTOS queue to send the values to
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* @return hli_queue_handle_t handle of the created queue, or NULL on failure
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*/
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hli_queue_handle_t hli_queue_create(size_t nelem, size_t elem_size, QueueHandle_t downstream);
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/**
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* @brief Create a hli queue, wrapping a FreeRTOS semaphore
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*
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* See notes on hli_queue_create.
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*
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* @param max_count maximum semaphore count
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* @param downstream FreeRTOS semaphore to forward the calls to
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* @return hli_queue_handle_t handle of the created queue, or NULL on failure
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*/
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hli_queue_handle_t hli_semaphore_create(size_t max_count, SemaphoreHandle_t downstream);
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/**
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* @brief Delete a hli queue
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*
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* Make sure noone is using the queue before deleting it.
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*
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* @param queue handle returned by hli_queue_create or hli_semaphore_create
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*/
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void hli_queue_delete(hli_queue_handle_t queue);
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/**
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* @brief Get one element from a hli queue
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*
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* Usually not used, values get sent to a downstream FreeRTOS queue automatically.
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* However if downstream queue is NULL, this API can be used to get values from a hli queue.
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*
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* @param queue handle of a queue
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* @param out pointer where to store the element
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* @return true if the element was successfully read from the queue
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*/
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bool hli_queue_get(hli_queue_handle_t queue, void* out);
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/**
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* @brief Put one element into a hli queue
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*
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* This puts copies an element into the queue and raises a software interrupt (level 3).
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* In the interrupt, the value is copied to a FreeRTOS "downstream" queue.
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*
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* Note that if the value does not fit into a downstream queue, no error is returned,
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* and the value is lost.
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*
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* @param queue handle of a queue
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* @param data pointer to the element to be sent
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* @return true if data was placed into the hli queue successfully
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*/
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bool hli_queue_put(hli_queue_handle_t queue, const void* data);
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/**
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* @brief "Give" a semaphore wrapped by a hli queue
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*
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* @param queue handle returned by hli_semaphore_create
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* @return true if the event was sent to a hli queue successfully
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*/
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bool hli_semaphore_give(hli_queue_handle_t queue);
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#ifdef __cplusplus
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}
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#endif
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76
components/bt/hli_vectors.S
Normal file
76
components/bt/hli_vectors.S
Normal file
@ -0,0 +1,76 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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// All rights reserved.
|
||||
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#include <xtensa/coreasm.h>
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#include <xtensa/corebits.h>
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#include <xtensa/config/system.h>
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#include "freertos/xtensa_context.h"
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#define L5_INTR_STACK_SIZE 4096
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.data
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_l5_intr_stack:
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.space L5_INTR_STACK_SIZE
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.section .iram1,"ax"
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.global xt_highint5
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.type xt_highint5,@function
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.align 4
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xt_highint5:
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/* Allocate exception frame and save minimal context. */
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mov a0, sp
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addi sp, sp, -XT_STK_FRMSZ
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s32i a0, sp, XT_STK_A1
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#if XCHAL_HAVE_WINDOWED
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s32e a0, sp, -12 /* for debug backtrace */
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#endif
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rsr a0, EPS_5 /* save interruptee's PS */
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s32i a0, sp, XT_STK_PS
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rsr a0, EPC_5 /* save interruptee's PC */
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s32i a0, sp, XT_STK_PC
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#if XCHAL_HAVE_WINDOWED
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s32e a0, sp, -16 /* for debug backtrace */
|
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#endif
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s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */
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s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */
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call0 _xt_context_save
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_highint5_stack_switch:
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mov a7, sp
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movi sp, _l5_intr_stack + L5_INTR_STACK_SIZE - 16
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s32e a7, sp, -12
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movi a0, _Level5Vector+6 /* For GDB: pretend we came from the interrupt vector */
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s32e a0, sp, -16
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movi a0, _highint5_stack_switch /* For GDB: cosmetics, for the frame where stack switch happened */
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/* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
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movi a6, PS_INTLEVEL(5) | PS_UM | PS_WOE
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wsr a6, PS
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rsync
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/* Call C handler */
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mov a6, sp
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call4 hli_c_handler
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l32e sp, sp, -12 /* switch back to the original stack */
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call0 _xt_context_restore
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l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
|
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wsr a0, EPS_5
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l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
|
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wsr a0, EPC_5
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l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
|
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l32i sp, sp, XT_STK_A1 /* remove exception frame */
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rsync /* ensure PS and EPC written */
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rsr a0, EXCSAVE_5 /* restore a0 */
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rfi 5
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||||
|
||||
/* The linker has no reason to link in this file; all symbols it exports are already defined
|
||||
(weakly!) in the default int handler. Define a symbol here so we can use it to have the
|
||||
linker inspect this anyway. */
|
||||
|
||||
.global ld_include_hli_vectors_bt
|
||||
ld_include_hli_vectors_bt:
|
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@ -410,7 +410,7 @@ _xt_panic:
|
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s32i a0, sp, XT_STK_A0
|
||||
|
||||
/* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
|
||||
movi a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
|
||||
movi a0, PS_INTLEVEL(XCHAL_DEBUGLEVEL - 1) | PS_UM | PS_WOE
|
||||
wsr a0, PS
|
||||
|
||||
//Call panic handler
|
||||
@ -693,11 +693,11 @@ _xt_user_exc:
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rsr a0, EXCSAVE_1 /* save interruptee's a0 */
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s32i a0, sp, XT_STK_A0
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/* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */
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/* Set up PS for C, reenable debug and NMI interrupts, and clear EXCM. */
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#ifdef __XTENSA_CALL0_ABI__
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movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
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movi a0, PS_INTLEVEL(XCHAL_DEBUGLEVEL - 1) | PS_UM
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#else
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movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
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movi a0, PS_INTLEVEL(XCHAL_DEBUGLEVEL - 1) | PS_UM | PS_WOE
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#endif
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wsr a0, PS
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||||
|
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Block a user