feat(soc): p4 hw ver2 registers

components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h

@@ -120,7 +120,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
     int i;
     for (i = 0; i < (int)rd_len; i++) {
         if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
-        buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
+        buf[i] = HAL_FORCE_READ_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte);
     }
     return i;
 }
@@ -139,7 +139,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w
     int i;
     for (i = 0; i < (int)wr_len; i++) {
         if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
-        USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
+        HAL_FORCE_MODIFY_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte, buf[i]);
     }
     return i;
 }

components/soc/esp32p4/register/hw_ver2/soc/i2s_reg.h

@@ -11,6 +11,8 @@
 extern "C" {
 #endif
 
+#define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE + (i) * 0x1000)
+
 /** I2S_INT_RAW_REG register
  *  I2S interrupt raw register, valid in level.
  */

components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_eco5_struct.h

@@ -0,0 +1,868 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of clk_en register
+ *  dsi bridge clk control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  this bit configures force_on of dsi_bridge register clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_clk_en_reg_t;
+
+/** Type of en register
+ *  dsi bridge en register
+ */
+typedef union {
+    struct {
+        /** dsi_en : R/W; bitpos: [0]; default: 0;
+         *  this bit configures module enable of dsi_bridge. 0: disable, 1: enable
+         */
+        uint32_t dsi_en:1;
+        /** dsi_brig_rst : R/W; bitpos: [1]; default: 0;
+         *  Configures software reset of dsi_bridge. 0: release reset, 1: reset
+         */
+        uint32_t dsi_brig_rst:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_en_reg_t;
+
+/** Type of dma_req_cfg register
+ *  dsi bridge dma burst len register
+ */
+typedef union {
+    struct {
+        /** dma_burst_len : R/W; bitpos: [11:0]; default: 128;
+         *  this field configures the num of 64-bit in one dma burst transfer, valid only when
+         *  dsi_bridge as flow controller
+         */
+        uint32_t dma_burst_len:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} dsi_brg_dma_req_cfg_reg_t;
+
+/** Type of raw_num_cfg register
+ *  dsi bridge raw number control register
+ */
+typedef union {
+    struct {
+        /** raw_num_total : R/W; bitpos: [21:0]; default: 230400;
+         *  this field configures number of total pix bits/64
+         */
+        uint32_t raw_num_total:22;
+        /** unalign_64bit_en : R/W; bitpos: [22]; default: 0;
+         *  this field configures whether the total pix bits is a multiple of 64bits. 0: align
+         *  to 64-bit, 1: unalign to 64-bit
+         */
+        uint32_t unalign_64bit_en:1;
+        uint32_t reserved_23:8;
+        /** raw_num_total_set : WT; bitpos: [31]; default: 0;
+         *  this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable,
+         *  1: enable. valid only when dsi_bridge as flow controller
+         */
+        uint32_t raw_num_total_set:1;
+    };
+    uint32_t val;
+} dsi_brg_raw_num_cfg_reg_t;
+
+/** Type of raw_buf_credit_ctl register
+ *  dsi bridge credit register
+ */
+typedef union {
+    struct {
+        /** credit_thrd : R/W; bitpos: [14:0]; default: 1024;
+         *  this field configures the threshold whether dsi_bridge fifo can receive one more
+         *  64-bit, valid only when dsi_bridge as flow controller
+         */
+        uint32_t credit_thrd:15;
+        uint32_t reserved_15:1;
+        /** credit_burst_thrd : R/W; bitpos: [30:16]; default: 800;
+         *  this field configures the threshold whether dsi_bridge fifo can receive one more
+         *  dma burst, valid only when dsi_bridge as flow controller
+         */
+        uint32_t credit_burst_thrd:15;
+        /** credit_reset : R/W; bitpos: [31]; default: 0;
+         *  this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when
+         *  dsi_bridge as flow controller
+         */
+        uint32_t credit_reset:1;
+    };
+    uint32_t val;
+} dsi_brg_raw_buf_credit_ctl_reg_t;
+
+/** Type of pixel_type register
+ *  dsi bridge dpi type control register
+ */
+typedef union {
+    struct {
+        /** raw_type : R/W; bitpos: [3:0]; default: 0;
+         *  this field configures the raw pixel type. 0: rgb888, 1:rgb666, 2:rgb565, 8:yuv444,
+         *  9:yuv422, 10:yuv420, 12:gray
+         */
+        uint32_t raw_type:4;
+        /** dpi_config : R/W; bitpos: [5:4]; default: 0;
+         *  this field configures the pixel arrange type of dpi interface
+         */
+        uint32_t dpi_config:2;
+        /** data_in_type : R/W; bitpos: [6]; default: 0;
+         *  input data type, 0: not yuv, 1: yuv
+         */
+        uint32_t data_in_type:1;
+        /** dpi_type : R/W; bitpos: [10:7]; default: 0;
+         *  this field configures the dpi pixel type. 0: rgb888, 1:rgb666, 2:rgb565
+         */
+        uint32_t dpi_type:4;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} dsi_brg_pixel_type_reg_t;
+
+/** Type of dma_block_interval register
+ *  dsi bridge dma block interval control register
+ */
+typedef union {
+    struct {
+        /** dma_block_slot : R/W; bitpos: [9:0]; default: 9;
+         *  this field configures the max block_slot_cnt
+         */
+        uint32_t dma_block_slot:10;
+        /** dma_block_interval : R/W; bitpos: [27:10]; default: 9;
+         *  this field configures the max block_interval_cnt, block_interval_cnt increased by 1
+         *  when block_slot_cnt if full
+         */
+        uint32_t dma_block_interval:18;
+        /** raw_num_total_auto_reload : R/W; bitpos: [28]; default: 1;
+         *  this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable
+         */
+        uint32_t raw_num_total_auto_reload:1;
+        /** dma_block_interval_en : R/W; bitpos: [29]; default: 1;
+         *  this bit configures enable of interval between dma block transfer, 0: disable, 1:
+         *  enable
+         */
+        uint32_t dma_block_interval_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} dsi_brg_dma_block_interval_reg_t;
+
+/** Type of dma_req_interval register
+ *  dsi bridge dma req interval control register
+ */
+typedef union {
+    struct {
+        /** dma_req_interval : R/W; bitpos: [15:0]; default: 1;
+         *  this field configures the interval between dma req events
+         */
+        uint32_t dma_req_interval:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_brg_dma_req_interval_reg_t;
+
+/** Type of dpi_lcd_ctl register
+ *  dsi bridge dpi signal control register
+ */
+typedef union {
+    struct {
+        /** dpishutdn : R/W; bitpos: [0]; default: 0;
+         *  this bit configures dpishutdn signal in dpi interface
+         */
+        uint32_t dpishutdn:1;
+        /** dpicolorm : R/W; bitpos: [1]; default: 0;
+         *  this bit configures dpicolorm signal in dpi interface
+         */
+        uint32_t dpicolorm:1;
+        /** dpiupdatecfg : R/W; bitpos: [2]; default: 0;
+         *  this bit configures dpiupdatecfg signal in dpi interface
+         */
+        uint32_t dpiupdatecfg:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dsi_brg_dpi_lcd_ctl_reg_t;
+
+/** Type of dpi_rsv_dpi_data register
+ *  dsi bridge dpi reserved data register
+ */
+typedef union {
+    struct {
+        /** dpi_rsv_data : R/W; bitpos: [29:0]; default: 16383;
+         *  this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow
+         */
+        uint32_t dpi_rsv_data:30;
+        /** dpi_dbg_en : R/W; bitpos: [30]; default: 0;
+         *  Configures data debug feature enable. 0: disable, 1: enable
+         */
+        uint32_t dpi_dbg_en:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} dsi_brg_dpi_rsv_dpi_data_reg_t;
+
+/** Type of dpi_v_cfg0 register
+ *  dsi bridge dpi v config register 0
+ */
+typedef union {
+    struct {
+        /** vtotal : R/W; bitpos: [11:0]; default: 525;
+         *  this field configures the total length of one frame (by line) for dpi output, must
+         *  meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank
+         */
+        uint32_t vtotal:12;
+        uint32_t reserved_12:4;
+        /** vdisp : R/W; bitpos: [27:16]; default: 480;
+         *  this field configures the length of valid line (by line) for dpi output
+         */
+        uint32_t vdisp:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dsi_brg_dpi_v_cfg0_reg_t;
+
+/** Type of dpi_v_cfg1 register
+ *  dsi bridge dpi v config register 1
+ */
+typedef union {
+    struct {
+        /** vbank : R/W; bitpos: [11:0]; default: 33;
+         *  this field configures the length between vsync and valid line (by line) for dpi
+         *  output
+         */
+        uint32_t vbank:12;
+        uint32_t reserved_12:4;
+        /** vsync : R/W; bitpos: [27:16]; default: 2;
+         *  this field configures the length of vsync (by line) for dpi output
+         */
+        uint32_t vsync:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dsi_brg_dpi_v_cfg1_reg_t;
+
+/** Type of dpi_h_cfg0 register
+ *  dsi bridge dpi h config register 0
+ */
+typedef union {
+    struct {
+        /** htotal : R/W; bitpos: [11:0]; default: 800;
+         *  this field configures the total length of one line (by pixel num) for dpi output,
+         *  must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank
+         */
+        uint32_t htotal:12;
+        uint32_t reserved_12:4;
+        /** hdisp : R/W; bitpos: [27:16]; default: 640;
+         *  this field configures the length of valid pixel data (by pixel num) for dpi output
+         */
+        uint32_t hdisp:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dsi_brg_dpi_h_cfg0_reg_t;
+
+/** Type of dpi_h_cfg1 register
+ *  dsi bridge dpi h config register 1
+ */
+typedef union {
+    struct {
+        /** hbank : R/W; bitpos: [11:0]; default: 48;
+         *  this field configures the length between hsync and pixel data valid (by pixel num)
+         *  for dpi output
+         */
+        uint32_t hbank:12;
+        uint32_t reserved_12:4;
+        /** hsync : R/W; bitpos: [27:16]; default: 96;
+         *  this field configures the length of hsync (by pixel num) for dpi output
+         */
+        uint32_t hsync:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dsi_brg_dpi_h_cfg1_reg_t;
+
+/** Type of dpi_misc_config register
+ *  dsi_bridge dpi misc config register
+ */
+typedef union {
+    struct {
+        /** dpi_en : R/W; bitpos: [0]; default: 0;
+         *  this bit configures enable of dpi output, 0: disable, 1: enable
+         */
+        uint32_t dpi_en:1;
+        uint32_t reserved_1:3;
+        /** fifo_underrun_discard_vcnt : R/W; bitpos: [15:4]; default: 413;
+         *  this field configures the underrun interrupt musk, when underrun occurs and line
+         *  cnt is less then this field
+         */
+        uint32_t fifo_underrun_discard_vcnt:12;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_brg_dpi_misc_config_reg_t;
+
+/** Type of dpi_config_update register
+ *  dsi_bridge dpi config update register
+ */
+typedef union {
+    struct {
+        /** dpi_config_update : WT; bitpos: [0]; default: 0;
+         *  write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_*
+         */
+        uint32_t dpi_config_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_dpi_config_update_reg_t;
+
+/** Type of host_trigger_rev register
+ *  dsi_bridge host trigger reverse control register
+ */
+typedef union {
+    struct {
+        /** tx_trigger_rev_en : R/W; bitpos: [0]; default: 0;
+         *  tx_trigger reverse. 0: disable, 1: enable
+         */
+        uint32_t tx_trigger_rev_en:1;
+        /** rx_trigger_rev_en : R/W; bitpos: [1]; default: 0;
+         *  rx_trigger reverse. 0: disable, 1: enable
+         */
+        uint32_t rx_trigger_rev_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_host_trigger_rev_reg_t;
+
+/** Type of blk_raw_num_cfg register
+ *  dsi_bridge block raw number control register
+ */
+typedef union {
+    struct {
+        /** blk_raw_num_total : R/W; bitpos: [21:0]; default: 230400;
+         *  this field configures number of total block pix bits/64
+         */
+        uint32_t blk_raw_num_total:22;
+        uint32_t reserved_22:9;
+        /** blk_raw_num_total_set : WT; bitpos: [31]; default: 0;
+         *  write 1 to reload reg_blk_raw_num_total to internal cnt
+         */
+        uint32_t blk_raw_num_total_set:1;
+    };
+    uint32_t val;
+} dsi_brg_blk_raw_num_cfg_reg_t;
+
+/** Type of dma_frame_interval register
+ *  dsi_bridge dam frame interval control register
+ */
+typedef union {
+    struct {
+        /** dma_frame_slot : R/W; bitpos: [9:0]; default: 9;
+         *  this field configures the max frame_slot_cnt
+         */
+        uint32_t dma_frame_slot:10;
+        /** dma_frame_interval : R/W; bitpos: [27:10]; default: 9;
+         *  this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1
+         *  when frame_slot_cnt if full
+         */
+        uint32_t dma_frame_interval:18;
+        /** dma_multiblk_en : R/W; bitpos: [28]; default: 0;
+         *  this bit configures enable multi-blk transfer, 0: disable, 1: enable
+         */
+        uint32_t dma_multiblk_en:1;
+        /** dma_frame_interval_en : R/W; bitpos: [29]; default: 1;
+         *  this bit configures enable interval between frame transfer, 0: disable, 1: enable
+         */
+        uint32_t dma_frame_interval_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} dsi_brg_dma_frame_interval_reg_t;
+
+/** Type of mem_aux_ctrl register
+ *  dsi_bridge mem aux control register
+ */
+typedef union {
+    struct {
+        /** dsi_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  this field configures dsi_bridge fifo memory aux ctrl
+         */
+        uint32_t dsi_mem_aux_ctrl:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dsi_brg_mem_aux_ctrl_reg_t;
+
+/** Type of rdn_eco_low register
+ *  dsi_bridge rdn eco all low register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  rdn_eco_low
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} dsi_brg_rdn_eco_low_reg_t;
+
+/** Type of rdn_eco_high register
+ *  dsi_bridge rdn eco all high register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  rdn_eco_high
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} dsi_brg_rdn_eco_high_reg_t;
+
+/** Type of host_ctrl register
+ *  dsi_bridge host control register
+ */
+typedef union {
+    struct {
+        /** dsi_cfg_ref_clk_en : R/W; bitpos: [0]; default: 1;
+         *  this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1:
+         *  enable
+         */
+        uint32_t dsi_cfg_ref_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_host_ctrl_reg_t;
+
+/** Type of mem_clk_ctrl register
+ *  dsi_bridge mem force on control register
+ */
+typedef union {
+    struct {
+        /** dsi_bridge_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1:
+         *  force on
+         */
+        uint32_t dsi_bridge_mem_clk_force_on:1;
+        /** dsi_mem_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on
+         */
+        uint32_t dsi_mem_clk_force_on:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_mem_clk_ctrl_reg_t;
+
+/** Type of dma_flow_ctrl register
+ *  dsi_bridge dma flow controller register
+ */
+typedef union {
+    struct {
+        /** dsi_dma_flow_controller : R/W; bitpos: [0]; default: 1;
+         *  this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge
+         *  as flow controller
+         */
+        uint32_t dsi_dma_flow_controller:1;
+        uint32_t reserved_1:3;
+        /** dma_flow_multiblk_num : R/W; bitpos: [7:4]; default: 1;
+         *  this field configures the num of blocks when multi-blk is enable and dmac as flow
+         *  controller
+         */
+        uint32_t dma_flow_multiblk_num:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} dsi_brg_dma_flow_ctrl_reg_t;
+
+/** Type of raw_buf_almost_empty_thrd register
+ *  dsi_bridge buffer empty threshold register
+ */
+typedef union {
+    struct {
+        /** dsi_raw_buf_almost_empty_thrd : R/W; bitpos: [10:0]; default: 512;
+         *  this field configures the fifo almost empty threshold, is valid only when dmac as
+         *  flow controller
+         */
+        uint32_t dsi_raw_buf_almost_empty_thrd:11;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} dsi_brg_raw_buf_almost_empty_thrd_reg_t;
+
+/** Type of yuv_cfg register
+ *  dsi_bridge yuv format config register
+ */
+typedef union {
+    struct {
+        /** protocol : R/W; bitpos: [0]; default: 0;
+         *  this bit configures yuv protoocl, 0: bt.601, 1: bt.709
+         */
+        uint32_t protocol:1;
+        /** yuv_pix_endian : R/W; bitpos: [1]; default: 0;
+         *  this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0
+         */
+        uint32_t yuv_pix_endian:1;
+        /** yuv422_format : R/W; bitpos: [3:2]; default: 0;
+         *  this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy
+         */
+        uint32_t yuv422_format:2;
+        /** yuv_range : R/W; bitpos: [4]; default: 0;
+         *  Configures yuv pixel range, 0: limit range, 1: full range
+         */
+        uint32_t yuv_range:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} dsi_brg_yuv_cfg_reg_t;
+
+/** Type of phy_lp_loopback_ctrl register
+ *  dsi phy lp_loopback test ctrl
+ */
+typedef union {
+    struct {
+        /** phy_lp_txdataesc_1 : R/W; bitpos: [7:0]; default: 0;
+         *  txdataesc_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txdataesc_1:8;
+        /** phy_lp_txrequestesc_1 : R/W; bitpos: [8]; default: 0;
+         *  txrequestesc_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txrequestesc_1:1;
+        /** phy_lp_txvalidesc_1 : R/W; bitpos: [9]; default: 0;
+         *  txvalidesc_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txvalidesc_1:1;
+        /** phy_lp_txlpdtesc_1 : R/W; bitpos: [10]; default: 0;
+         *  txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txlpdtesc_1:1;
+        /** phy_lp_basedir_1 : R/W; bitpos: [11]; default: 0;
+         *  basedir_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_basedir_1:1;
+        uint32_t reserved_12:4;
+        /** phy_lp_txdataesc_0 : R/W; bitpos: [23:16]; default: 0;
+         *  txdataesc_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txdataesc_0:8;
+        /** phy_lp_txrequestesc_0 : R/W; bitpos: [24]; default: 0;
+         *  txrequestesc_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txrequestesc_0:1;
+        /** phy_lp_txvalidesc_0 : R/W; bitpos: [25]; default: 0;
+         *  txvalidesc_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txvalidesc_0:1;
+        /** phy_lp_txlpdtesc_0 : R/W; bitpos: [26]; default: 0;
+         *  txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txlpdtesc_0:1;
+        /** phy_lp_basedir_0 : R/W; bitpos: [27]; default: 0;
+         *  basedir_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_basedir_0:1;
+        /** phy_lp_loopback_check : WT; bitpos: [28]; default: 0;
+         *  dsi phy lp_loopback test start check
+         */
+        uint32_t phy_lp_loopback_check:1;
+        /** phy_lp_loopback_check_done : RO; bitpos: [29]; default: 0;
+         *  dsi phy lp_loopback test check done
+         */
+        uint32_t phy_lp_loopback_check_done:1;
+        /** phy_lp_loopback_en : R/W; bitpos: [30]; default: 0;
+         *  dsi phy lp_loopback ctrl en
+         */
+        uint32_t phy_lp_loopback_en:1;
+        /** phy_lp_loopback_ok : RO; bitpos: [31]; default: 0;
+         *  result of dsi phy lp_loopback test
+         */
+        uint32_t phy_lp_loopback_ok:1;
+    };
+    uint32_t val;
+} dsi_brg_phy_lp_loopback_ctrl_reg_t;
+
+/** Type of phy_hs_loopback_ctrl register
+ *  dsi phy hp_loopback test ctrl
+ */
+typedef union {
+    struct {
+        /** phy_hs_txdatahs_1 : R/W; bitpos: [7:0]; default: 0;
+         *  txdatahs_1 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txdatahs_1:8;
+        /** phy_hs_txrequestdatahs_1 : R/W; bitpos: [8]; default: 0;
+         *  txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txrequestdatahs_1:1;
+        /** phy_hs_basedir_1 : R/W; bitpos: [9]; default: 1;
+         *  basedir_1 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_basedir_1:1;
+        uint32_t reserved_10:6;
+        /** phy_hs_txdatahs_0 : R/W; bitpos: [23:16]; default: 0;
+         *  txdatahs_0 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txdatahs_0:8;
+        /** phy_hs_txrequestdatahs_0 : R/W; bitpos: [24]; default: 0;
+         *  txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txrequestdatahs_0:1;
+        /** phy_hs_basedir_0 : R/W; bitpos: [25]; default: 0;
+         *  basedir_0 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_basedir_0:1;
+        uint32_t reserved_26:1;
+        /** phy_hs_txrequesthsclk : R/W; bitpos: [27]; default: 0;
+         *  txrequesthsclk when  enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txrequesthsclk:1;
+        /** phy_hs_loopback_check : WT; bitpos: [28]; default: 0;
+         *  dsi phy hs_loopback test start check
+         */
+        uint32_t phy_hs_loopback_check:1;
+        /** phy_hs_loopback_check_done : RO; bitpos: [29]; default: 0;
+         *  dsi phy hs_loopback test check done
+         */
+        uint32_t phy_hs_loopback_check_done:1;
+        /** phy_hs_loopback_en : R/W; bitpos: [30]; default: 0;
+         *  dsi phy hs_loopback ctrl en
+         */
+        uint32_t phy_hs_loopback_en:1;
+        /** phy_hs_loopback_ok : RO; bitpos: [31]; default: 0;
+         *  result of dsi phy hs_loopback test
+         */
+        uint32_t phy_hs_loopback_ok:1;
+    };
+    uint32_t val;
+} dsi_brg_phy_hs_loopback_ctrl_reg_t;
+
+/** Type of phy_loopback_cnt register
+ *  loopback test cnt
+ */
+typedef union {
+    struct {
+        /** phy_hs_check_cnt_th : R/W; bitpos: [7:0]; default: 64;
+         *  hs_loopback test check cnt
+         */
+        uint32_t phy_hs_check_cnt_th:8;
+        uint32_t reserved_8:8;
+        /** phy_lp_check_cnt_th : R/W; bitpos: [23:16]; default: 64;
+         *  lp_loopback test check cnt
+         */
+        uint32_t phy_lp_check_cnt_th:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dsi_brg_phy_loopback_cnt_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of fifo_flow_status register
+ *  dsi bridge raw buffer depth register
+ */
+typedef union {
+    struct {
+        /** raw_buf_depth : RO; bitpos: [13:0]; default: 0;
+         *  this field configures the depth of dsi_bridge fifo depth
+         */
+        uint32_t raw_buf_depth:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dsi_brg_fifo_flow_status_reg_t;
+
+/** Type of host_bist_ctl register
+ *  dsi_bridge host bist control register
+ */
+typedef union {
+    struct {
+        /** bistok : RO; bitpos: [0]; default: 0;
+         *  bistok
+         */
+        uint32_t bistok:1;
+        /** biston : R/W; bitpos: [1]; default: 0;
+         *  biston
+         */
+        uint32_t biston:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_host_bist_ctl_reg_t;
+
+/** Type of rdn_eco_cs register
+ *  dsi_bridge rdn eco cs register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  rdn_eco_en
+         */
+        uint32_t rdn_eco_en:1;
+        /** rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  rdn_eco_result
+         */
+        uint32_t rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_rdn_eco_cs_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_ena register
+ *  dsi_bridge interrupt enable register
+ */
+typedef union {
+    struct {
+        /** underrun_int_ena : R/W; bitpos: [0]; default: 0;
+         *  write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled
+         *  by dpi_underrun  interrupt signal
+         */
+        uint32_t underrun_int_ena:1;
+        /** vsync_int_ena : R/W; bitpos: [1]; default: 0;
+         *  write 1 to enables dpi_vsync_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by
+         *  dpi_vsync  interrupt signal
+         */
+        uint32_t vsync_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  dsi_bridge interrupt clear register
+ */
+typedef union {
+    struct {
+        /** underrun_int_clr : WT; bitpos: [0]; default: 0;
+         *  write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
+         */
+        uint32_t underrun_int_clr:1;
+        /** vsync_int_clr : WT; bitpos: [1]; default: 0;
+         *  write 1 to this bit to clear dpi_vsync_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
+         */
+        uint32_t vsync_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_int_clr_reg_t;
+
+/** Type of int_raw register
+ *  dsi_bridge raw interrupt register
+ */
+typedef union {
+    struct {
+        /** underrun_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  the raw interrupt status of dpi_underrun
+         */
+        uint32_t underrun_int_raw:1;
+        /** vsync_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  the raw interrupt status of dpi_vsync
+         */
+        uint32_t vsync_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_int_raw_reg_t;
+
+/** Type of int_st register
+ *  dsi_bridge masked interrupt register
+ */
+typedef union {
+    struct {
+        /** underrun_int_st : RO; bitpos: [0]; default: 0;
+         *  the masked interrupt status of dpi_underrun
+         */
+        uint32_t underrun_int_st:1;
+        /** vsync_int_st : RO; bitpos: [1]; default: 0;
+         *  the masked interrupt status of dpi_vsync
+         */
+        uint32_t vsync_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_int_st_reg_t;
+
+
+/** Group: Version Register */
+/** Type of ver_date register
+ *  version control register
+ */
+typedef union {
+    struct {
+        /** ver_data : R/W; bitpos: [31:0]; default: 539296009;
+         *  Represents csv version
+         */
+        uint32_t ver_data:32;
+    };
+    uint32_t val;
+} dsi_brg_ver_date_reg_t;
+
+
+typedef struct {
+    volatile dsi_brg_clk_en_reg_t clk_en;
+    volatile dsi_brg_en_reg_t en;
+    volatile dsi_brg_dma_req_cfg_reg_t dma_req_cfg;
+    volatile dsi_brg_raw_num_cfg_reg_t raw_num_cfg;
+    volatile dsi_brg_raw_buf_credit_ctl_reg_t raw_buf_credit_ctl;
+    volatile dsi_brg_fifo_flow_status_reg_t fifo_flow_status;
+    volatile dsi_brg_pixel_type_reg_t pixel_type;
+    volatile dsi_brg_dma_block_interval_reg_t dma_block_interval;
+    volatile dsi_brg_dma_req_interval_reg_t dma_req_interval;
+    volatile dsi_brg_dpi_lcd_ctl_reg_t dpi_lcd_ctl;
+    volatile dsi_brg_dpi_rsv_dpi_data_reg_t dpi_rsv_dpi_data;
+    uint32_t reserved_02c;
+    volatile dsi_brg_dpi_v_cfg0_reg_t dpi_v_cfg0;
+    volatile dsi_brg_dpi_v_cfg1_reg_t dpi_v_cfg1;
+    volatile dsi_brg_dpi_h_cfg0_reg_t dpi_h_cfg0;
+    volatile dsi_brg_dpi_h_cfg1_reg_t dpi_h_cfg1;
+    volatile dsi_brg_dpi_misc_config_reg_t dpi_misc_config;
+    volatile dsi_brg_dpi_config_update_reg_t dpi_config_update;
+    uint32_t reserved_048[2];
+    volatile dsi_brg_int_ena_reg_t int_ena;
+    volatile dsi_brg_int_clr_reg_t int_clr;
+    volatile dsi_brg_int_raw_reg_t int_raw;
+    volatile dsi_brg_int_st_reg_t int_st;
+    volatile dsi_brg_host_bist_ctl_reg_t host_bist_ctl;
+    volatile dsi_brg_host_trigger_rev_reg_t host_trigger_rev;
+    volatile dsi_brg_blk_raw_num_cfg_reg_t blk_raw_num_cfg;
+    volatile dsi_brg_dma_frame_interval_reg_t dma_frame_interval;
+    volatile dsi_brg_mem_aux_ctrl_reg_t mem_aux_ctrl;
+    volatile dsi_brg_rdn_eco_cs_reg_t rdn_eco_cs;
+    volatile dsi_brg_rdn_eco_low_reg_t rdn_eco_low;
+    volatile dsi_brg_rdn_eco_high_reg_t rdn_eco_high;
+    volatile dsi_brg_host_ctrl_reg_t host_ctrl;
+    volatile dsi_brg_mem_clk_ctrl_reg_t mem_clk_ctrl;
+    volatile dsi_brg_dma_flow_ctrl_reg_t dma_flow_ctrl;
+    volatile dsi_brg_raw_buf_almost_empty_thrd_reg_t raw_buf_almost_empty_thrd;
+    volatile dsi_brg_yuv_cfg_reg_t yuv_cfg;
+    volatile dsi_brg_phy_lp_loopback_ctrl_reg_t phy_lp_loopback_ctrl;
+    volatile dsi_brg_phy_hs_loopback_ctrl_reg_t phy_hs_loopback_ctrl;
+    volatile dsi_brg_phy_loopback_cnt_reg_t phy_loopback_cnt;
+    uint32_t reserved_0a0[24];
+    volatile dsi_brg_ver_date_reg_t ver_date;
+} dsi_brg_dev_t;
+
+extern dsi_brg_dev_t MIPI_DSI_BRIDGE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(dsi_brg_dev_t) == 0x104, "Invalid size of dsi_brg_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_reg.h

@@ -0,0 +1,907 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DSI_BRG_CLK_EN_REG register
+ *  dsi bridge clk control register
+ */
+#define DSI_BRG_CLK_EN_REG (DR_REG_DSI_BRG_BASE + 0x0)
+/** DSI_BRG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  this bit configures force_on of dsi_bridge register clock gate
+ */
+#define DSI_BRG_CLK_EN    (BIT(0))
+#define DSI_BRG_CLK_EN_M  (DSI_BRG_CLK_EN_V << DSI_BRG_CLK_EN_S)
+#define DSI_BRG_CLK_EN_V  0x00000001U
+#define DSI_BRG_CLK_EN_S  0
+
+/** DSI_BRG_EN_REG register
+ *  dsi bridge en register
+ */
+#define DSI_BRG_EN_REG (DR_REG_DSI_BRG_BASE + 0x4)
+/** DSI_BRG_DSI_EN : R/W; bitpos: [0]; default: 0;
+ *  this bit configures module enable of dsi_bridge. 0: disable, 1: enable
+ */
+#define DSI_BRG_DSI_EN    (BIT(0))
+#define DSI_BRG_DSI_EN_M  (DSI_BRG_DSI_EN_V << DSI_BRG_DSI_EN_S)
+#define DSI_BRG_DSI_EN_V  0x00000001U
+#define DSI_BRG_DSI_EN_S  0
+/** DSI_BRG_DSI_BRIG_RST : R/W; bitpos: [1]; default: 0;
+ *  Configures software reset of dsi_bridge. 0: release reset, 1: reset
+ */
+#define DSI_BRG_DSI_BRIG_RST    (BIT(1))
+#define DSI_BRG_DSI_BRIG_RST_M  (DSI_BRG_DSI_BRIG_RST_V << DSI_BRG_DSI_BRIG_RST_S)
+#define DSI_BRG_DSI_BRIG_RST_V  0x00000001U
+#define DSI_BRG_DSI_BRIG_RST_S  1
+
+/** DSI_BRG_DMA_REQ_CFG_REG register
+ *  dsi bridge dma burst len register
+ */
+#define DSI_BRG_DMA_REQ_CFG_REG (DR_REG_DSI_BRG_BASE + 0x8)
+/** DSI_BRG_DMA_BURST_LEN : R/W; bitpos: [11:0]; default: 128;
+ *  this field configures the num of 64-bit in one dma burst transfer, valid only when
+ *  dsi_bridge as flow controller
+ */
+#define DSI_BRG_DMA_BURST_LEN    0x00000FFFU
+#define DSI_BRG_DMA_BURST_LEN_M  (DSI_BRG_DMA_BURST_LEN_V << DSI_BRG_DMA_BURST_LEN_S)
+#define DSI_BRG_DMA_BURST_LEN_V  0x00000FFFU
+#define DSI_BRG_DMA_BURST_LEN_S  0
+
+/** DSI_BRG_RAW_NUM_CFG_REG register
+ *  dsi bridge raw number control register
+ */
+#define DSI_BRG_RAW_NUM_CFG_REG (DR_REG_DSI_BRG_BASE + 0xc)
+/** DSI_BRG_RAW_NUM_TOTAL : R/W; bitpos: [21:0]; default: 230400;
+ *  this field configures number of total pix bits/64
+ */
+#define DSI_BRG_RAW_NUM_TOTAL    0x003FFFFFU
+#define DSI_BRG_RAW_NUM_TOTAL_M  (DSI_BRG_RAW_NUM_TOTAL_V << DSI_BRG_RAW_NUM_TOTAL_S)
+#define DSI_BRG_RAW_NUM_TOTAL_V  0x003FFFFFU
+#define DSI_BRG_RAW_NUM_TOTAL_S  0
+/** DSI_BRG_UNALIGN_64BIT_EN : R/W; bitpos: [22]; default: 0;
+ *  this field configures whether the total pix bits is a multiple of 64bits. 0: align
+ *  to 64-bit, 1: unalign to 64-bit
+ */
+#define DSI_BRG_UNALIGN_64BIT_EN    (BIT(22))
+#define DSI_BRG_UNALIGN_64BIT_EN_M  (DSI_BRG_UNALIGN_64BIT_EN_V << DSI_BRG_UNALIGN_64BIT_EN_S)
+#define DSI_BRG_UNALIGN_64BIT_EN_V  0x00000001U
+#define DSI_BRG_UNALIGN_64BIT_EN_S  22
+/** DSI_BRG_RAW_NUM_TOTAL_SET : WT; bitpos: [31]; default: 0;
+ *  this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable,
+ *  1: enable. valid only when dsi_bridge as flow controller
+ */
+#define DSI_BRG_RAW_NUM_TOTAL_SET    (BIT(31))
+#define DSI_BRG_RAW_NUM_TOTAL_SET_M  (DSI_BRG_RAW_NUM_TOTAL_SET_V << DSI_BRG_RAW_NUM_TOTAL_SET_S)
+#define DSI_BRG_RAW_NUM_TOTAL_SET_V  0x00000001U
+#define DSI_BRG_RAW_NUM_TOTAL_SET_S  31
+
+/** DSI_BRG_RAW_BUF_CREDIT_CTL_REG register
+ *  dsi bridge credit register
+ */
+#define DSI_BRG_RAW_BUF_CREDIT_CTL_REG (DR_REG_DSI_BRG_BASE + 0x10)
+/** DSI_BRG_CREDIT_THRD : R/W; bitpos: [14:0]; default: 1024;
+ *  this field configures the threshold whether dsi_bridge fifo can receive one more
+ *  64-bit, valid only when dsi_bridge as flow controller
+ */
+#define DSI_BRG_CREDIT_THRD    0x00007FFFU
+#define DSI_BRG_CREDIT_THRD_M  (DSI_BRG_CREDIT_THRD_V << DSI_BRG_CREDIT_THRD_S)
+#define DSI_BRG_CREDIT_THRD_V  0x00007FFFU
+#define DSI_BRG_CREDIT_THRD_S  0
+/** DSI_BRG_CREDIT_BURST_THRD : R/W; bitpos: [30:16]; default: 800;
+ *  this field configures the threshold whether dsi_bridge fifo can receive one more
+ *  dma burst, valid only when dsi_bridge as flow controller
+ */
+#define DSI_BRG_CREDIT_BURST_THRD    0x00007FFFU
+#define DSI_BRG_CREDIT_BURST_THRD_M  (DSI_BRG_CREDIT_BURST_THRD_V << DSI_BRG_CREDIT_BURST_THRD_S)
+#define DSI_BRG_CREDIT_BURST_THRD_V  0x00007FFFU
+#define DSI_BRG_CREDIT_BURST_THRD_S  16
+/** DSI_BRG_CREDIT_RESET : R/W; bitpos: [31]; default: 0;
+ *  this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when
+ *  dsi_bridge as flow controller
+ */
+#define DSI_BRG_CREDIT_RESET    (BIT(31))
+#define DSI_BRG_CREDIT_RESET_M  (DSI_BRG_CREDIT_RESET_V << DSI_BRG_CREDIT_RESET_S)
+#define DSI_BRG_CREDIT_RESET_V  0x00000001U
+#define DSI_BRG_CREDIT_RESET_S  31
+
+/** DSI_BRG_FIFO_FLOW_STATUS_REG register
+ *  dsi bridge raw buffer depth register
+ */
+#define DSI_BRG_FIFO_FLOW_STATUS_REG (DR_REG_DSI_BRG_BASE + 0x14)
+/** DSI_BRG_RAW_BUF_DEPTH : RO; bitpos: [13:0]; default: 0;
+ *  this field configures the depth of dsi_bridge fifo depth
+ */
+#define DSI_BRG_RAW_BUF_DEPTH    0x00003FFFU
+#define DSI_BRG_RAW_BUF_DEPTH_M  (DSI_BRG_RAW_BUF_DEPTH_V << DSI_BRG_RAW_BUF_DEPTH_S)
+#define DSI_BRG_RAW_BUF_DEPTH_V  0x00003FFFU
+#define DSI_BRG_RAW_BUF_DEPTH_S  0
+
+/** DSI_BRG_PIXEL_TYPE_REG register
+ *  dsi bridge dpi type control register
+ */
+#define DSI_BRG_PIXEL_TYPE_REG (DR_REG_DSI_BRG_BASE + 0x18)
+/** DSI_BRG_RAW_TYPE : R/W; bitpos: [3:0]; default: 0;
+ *  this field configures the raw pixel type. 0: rgb888, 1:rgb666, 2:rgb565, 8:yuv444,
+ *  9:yuv422, 10:yuv420, 12:gray
+ */
+#define DSI_BRG_RAW_TYPE    0x0000000FU
+#define DSI_BRG_RAW_TYPE_M  (DSI_BRG_RAW_TYPE_V << DSI_BRG_RAW_TYPE_S)
+#define DSI_BRG_RAW_TYPE_V  0x0000000FU
+#define DSI_BRG_RAW_TYPE_S  0
+/** DSI_BRG_DPI_CONFIG : R/W; bitpos: [5:4]; default: 0;
+ *  this field configures the pixel arrange type of dpi interface
+ */
+#define DSI_BRG_DPI_CONFIG    0x00000003U
+#define DSI_BRG_DPI_CONFIG_M  (DSI_BRG_DPI_CONFIG_V << DSI_BRG_DPI_CONFIG_S)
+#define DSI_BRG_DPI_CONFIG_V  0x00000003U
+#define DSI_BRG_DPI_CONFIG_S  4
+/** DSI_BRG_DATA_IN_TYPE : R/W; bitpos: [6]; default: 0;
+ *  input data type, 0: not yuv, 1: yuv
+ */
+#define DSI_BRG_DATA_IN_TYPE    (BIT(6))
+#define DSI_BRG_DATA_IN_TYPE_M  (DSI_BRG_DATA_IN_TYPE_V << DSI_BRG_DATA_IN_TYPE_S)
+#define DSI_BRG_DATA_IN_TYPE_V  0x00000001U
+#define DSI_BRG_DATA_IN_TYPE_S  6
+/** DSI_BRG_DPI_TYPE : R/W; bitpos: [10:7]; default: 0;
+ *  this field configures the dpi pixel type. 0: rgb888, 1:rgb666, 2:rgb565
+ */
+#define DSI_BRG_DPI_TYPE    0x0000000FU
+#define DSI_BRG_DPI_TYPE_M  (DSI_BRG_DPI_TYPE_V << DSI_BRG_DPI_TYPE_S)
+#define DSI_BRG_DPI_TYPE_V  0x0000000FU
+#define DSI_BRG_DPI_TYPE_S  7
+
+/** DSI_BRG_DMA_BLOCK_INTERVAL_REG register
+ *  dsi bridge dma block interval control register
+ */
+#define DSI_BRG_DMA_BLOCK_INTERVAL_REG (DR_REG_DSI_BRG_BASE + 0x1c)
+/** DSI_BRG_DMA_BLOCK_SLOT : R/W; bitpos: [9:0]; default: 9;
+ *  this field configures the max block_slot_cnt
+ */
+#define DSI_BRG_DMA_BLOCK_SLOT    0x000003FFU
+#define DSI_BRG_DMA_BLOCK_SLOT_M  (DSI_BRG_DMA_BLOCK_SLOT_V << DSI_BRG_DMA_BLOCK_SLOT_S)
+#define DSI_BRG_DMA_BLOCK_SLOT_V  0x000003FFU
+#define DSI_BRG_DMA_BLOCK_SLOT_S  0
+/** DSI_BRG_DMA_BLOCK_INTERVAL : R/W; bitpos: [27:10]; default: 9;
+ *  this field configures the max block_interval_cnt, block_interval_cnt increased by 1
+ *  when block_slot_cnt if full
+ */
+#define DSI_BRG_DMA_BLOCK_INTERVAL    0x0003FFFFU
+#define DSI_BRG_DMA_BLOCK_INTERVAL_M  (DSI_BRG_DMA_BLOCK_INTERVAL_V << DSI_BRG_DMA_BLOCK_INTERVAL_S)
+#define DSI_BRG_DMA_BLOCK_INTERVAL_V  0x0003FFFFU
+#define DSI_BRG_DMA_BLOCK_INTERVAL_S  10
+/** DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD : R/W; bitpos: [28]; default: 1;
+ *  this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable
+ */
+#define DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD    (BIT(28))
+#define DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_M  (DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_V << DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_S)
+#define DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_V  0x00000001U
+#define DSI_BRG_RAW_NUM_TOTAL_AUTO_RELOAD_S  28
+/** DSI_BRG_DMA_BLOCK_INTERVAL_EN : R/W; bitpos: [29]; default: 1;
+ *  this bit configures enable of interval between dma block transfer, 0: disable, 1:
+ *  enable
+ */
+#define DSI_BRG_DMA_BLOCK_INTERVAL_EN    (BIT(29))
+#define DSI_BRG_DMA_BLOCK_INTERVAL_EN_M  (DSI_BRG_DMA_BLOCK_INTERVAL_EN_V << DSI_BRG_DMA_BLOCK_INTERVAL_EN_S)
+#define DSI_BRG_DMA_BLOCK_INTERVAL_EN_V  0x00000001U
+#define DSI_BRG_DMA_BLOCK_INTERVAL_EN_S  29
+
+/** DSI_BRG_DMA_REQ_INTERVAL_REG register
+ *  dsi bridge dma req interval control register
+ */
+#define DSI_BRG_DMA_REQ_INTERVAL_REG (DR_REG_DSI_BRG_BASE + 0x20)
+/** DSI_BRG_DMA_REQ_INTERVAL : R/W; bitpos: [15:0]; default: 1;
+ *  this field configures the interval between dma req events
+ */
+#define DSI_BRG_DMA_REQ_INTERVAL    0x0000FFFFU
+#define DSI_BRG_DMA_REQ_INTERVAL_M  (DSI_BRG_DMA_REQ_INTERVAL_V << DSI_BRG_DMA_REQ_INTERVAL_S)
+#define DSI_BRG_DMA_REQ_INTERVAL_V  0x0000FFFFU
+#define DSI_BRG_DMA_REQ_INTERVAL_S  0
+
+/** DSI_BRG_DPI_LCD_CTL_REG register
+ *  dsi bridge dpi signal control register
+ */
+#define DSI_BRG_DPI_LCD_CTL_REG (DR_REG_DSI_BRG_BASE + 0x24)
+/** DSI_BRG_DPISHUTDN : R/W; bitpos: [0]; default: 0;
+ *  this bit configures dpishutdn signal in dpi interface
+ */
+#define DSI_BRG_DPISHUTDN    (BIT(0))
+#define DSI_BRG_DPISHUTDN_M  (DSI_BRG_DPISHUTDN_V << DSI_BRG_DPISHUTDN_S)
+#define DSI_BRG_DPISHUTDN_V  0x00000001U
+#define DSI_BRG_DPISHUTDN_S  0
+/** DSI_BRG_DPICOLORM : R/W; bitpos: [1]; default: 0;
+ *  this bit configures dpicolorm signal in dpi interface
+ */
+#define DSI_BRG_DPICOLORM    (BIT(1))
+#define DSI_BRG_DPICOLORM_M  (DSI_BRG_DPICOLORM_V << DSI_BRG_DPICOLORM_S)
+#define DSI_BRG_DPICOLORM_V  0x00000001U
+#define DSI_BRG_DPICOLORM_S  1
+/** DSI_BRG_DPIUPDATECFG : R/W; bitpos: [2]; default: 0;
+ *  this bit configures dpiupdatecfg signal in dpi interface
+ */
+#define DSI_BRG_DPIUPDATECFG    (BIT(2))
+#define DSI_BRG_DPIUPDATECFG_M  (DSI_BRG_DPIUPDATECFG_V << DSI_BRG_DPIUPDATECFG_S)
+#define DSI_BRG_DPIUPDATECFG_V  0x00000001U
+#define DSI_BRG_DPIUPDATECFG_S  2
+
+/** DSI_BRG_DPI_RSV_DPI_DATA_REG register
+ *  dsi bridge dpi reserved data register
+ */
+#define DSI_BRG_DPI_RSV_DPI_DATA_REG (DR_REG_DSI_BRG_BASE + 0x28)
+/** DSI_BRG_DPI_RSV_DATA : R/W; bitpos: [29:0]; default: 16383;
+ *  this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow
+ */
+#define DSI_BRG_DPI_RSV_DATA    0x3FFFFFFFU
+#define DSI_BRG_DPI_RSV_DATA_M  (DSI_BRG_DPI_RSV_DATA_V << DSI_BRG_DPI_RSV_DATA_S)
+#define DSI_BRG_DPI_RSV_DATA_V  0x3FFFFFFFU
+#define DSI_BRG_DPI_RSV_DATA_S  0
+/** DSI_BRG_DPI_DBG_EN : R/W; bitpos: [30]; default: 0;
+ *  Configures data debug feature enable. 0: disable, 1: enable
+ */
+#define DSI_BRG_DPI_DBG_EN    (BIT(30))
+#define DSI_BRG_DPI_DBG_EN_M  (DSI_BRG_DPI_DBG_EN_V << DSI_BRG_DPI_DBG_EN_S)
+#define DSI_BRG_DPI_DBG_EN_V  0x00000001U
+#define DSI_BRG_DPI_DBG_EN_S  30
+
+/** DSI_BRG_DPI_V_CFG0_REG register
+ *  dsi bridge dpi v config register 0
+ */
+#define DSI_BRG_DPI_V_CFG0_REG (DR_REG_DSI_BRG_BASE + 0x30)
+/** DSI_BRG_VTOTAL : R/W; bitpos: [11:0]; default: 525;
+ *  this field configures the total length of one frame (by line) for dpi output, must
+ *  meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank
+ */
+#define DSI_BRG_VTOTAL    0x00000FFFU
+#define DSI_BRG_VTOTAL_M  (DSI_BRG_VTOTAL_V << DSI_BRG_VTOTAL_S)
+#define DSI_BRG_VTOTAL_V  0x00000FFFU
+#define DSI_BRG_VTOTAL_S  0
+/** DSI_BRG_VDISP : R/W; bitpos: [27:16]; default: 480;
+ *  this field configures the length of valid line (by line) for dpi output
+ */
+#define DSI_BRG_VDISP    0x00000FFFU
+#define DSI_BRG_VDISP_M  (DSI_BRG_VDISP_V << DSI_BRG_VDISP_S)
+#define DSI_BRG_VDISP_V  0x00000FFFU
+#define DSI_BRG_VDISP_S  16
+
+/** DSI_BRG_DPI_V_CFG1_REG register
+ *  dsi bridge dpi v config register 1
+ */
+#define DSI_BRG_DPI_V_CFG1_REG (DR_REG_DSI_BRG_BASE + 0x34)
+/** DSI_BRG_VBANK : R/W; bitpos: [11:0]; default: 33;
+ *  this field configures the length between vsync and valid line (by line) for dpi
+ *  output
+ */
+#define DSI_BRG_VBANK    0x00000FFFU
+#define DSI_BRG_VBANK_M  (DSI_BRG_VBANK_V << DSI_BRG_VBANK_S)
+#define DSI_BRG_VBANK_V  0x00000FFFU
+#define DSI_BRG_VBANK_S  0
+/** DSI_BRG_VSYNC : R/W; bitpos: [27:16]; default: 2;
+ *  this field configures the length of vsync (by line) for dpi output
+ */
+#define DSI_BRG_VSYNC    0x00000FFFU
+#define DSI_BRG_VSYNC_M  (DSI_BRG_VSYNC_V << DSI_BRG_VSYNC_S)
+#define DSI_BRG_VSYNC_V  0x00000FFFU
+#define DSI_BRG_VSYNC_S  16
+
+/** DSI_BRG_DPI_H_CFG0_REG register
+ *  dsi bridge dpi h config register 0
+ */
+#define DSI_BRG_DPI_H_CFG0_REG (DR_REG_DSI_BRG_BASE + 0x38)
+/** DSI_BRG_HTOTAL : R/W; bitpos: [11:0]; default: 800;
+ *  this field configures the total length of one line (by pixel num) for dpi output,
+ *  must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank
+ */
+#define DSI_BRG_HTOTAL    0x00000FFFU
+#define DSI_BRG_HTOTAL_M  (DSI_BRG_HTOTAL_V << DSI_BRG_HTOTAL_S)
+#define DSI_BRG_HTOTAL_V  0x00000FFFU
+#define DSI_BRG_HTOTAL_S  0
+/** DSI_BRG_HDISP : R/W; bitpos: [27:16]; default: 640;
+ *  this field configures the length of valid pixel data (by pixel num) for dpi output
+ */
+#define DSI_BRG_HDISP    0x00000FFFU
+#define DSI_BRG_HDISP_M  (DSI_BRG_HDISP_V << DSI_BRG_HDISP_S)
+#define DSI_BRG_HDISP_V  0x00000FFFU
+#define DSI_BRG_HDISP_S  16
+
+/** DSI_BRG_DPI_H_CFG1_REG register
+ *  dsi bridge dpi h config register 1
+ */
+#define DSI_BRG_DPI_H_CFG1_REG (DR_REG_DSI_BRG_BASE + 0x3c)
+/** DSI_BRG_HBANK : R/W; bitpos: [11:0]; default: 48;
+ *  this field configures the length between hsync and pixel data valid (by pixel num)
+ *  for dpi output
+ */
+#define DSI_BRG_HBANK    0x00000FFFU
+#define DSI_BRG_HBANK_M  (DSI_BRG_HBANK_V << DSI_BRG_HBANK_S)
+#define DSI_BRG_HBANK_V  0x00000FFFU
+#define DSI_BRG_HBANK_S  0
+/** DSI_BRG_HSYNC : R/W; bitpos: [27:16]; default: 96;
+ *  this field configures the length of hsync (by pixel num) for dpi output
+ */
+#define DSI_BRG_HSYNC    0x00000FFFU
+#define DSI_BRG_HSYNC_M  (DSI_BRG_HSYNC_V << DSI_BRG_HSYNC_S)
+#define DSI_BRG_HSYNC_V  0x00000FFFU
+#define DSI_BRG_HSYNC_S  16
+
+/** DSI_BRG_DPI_MISC_CONFIG_REG register
+ *  dsi_bridge dpi misc config register
+ */
+#define DSI_BRG_DPI_MISC_CONFIG_REG (DR_REG_DSI_BRG_BASE + 0x40)
+/** DSI_BRG_DPI_EN : R/W; bitpos: [0]; default: 0;
+ *  this bit configures enable of dpi output, 0: disable, 1: enable
+ */
+#define DSI_BRG_DPI_EN    (BIT(0))
+#define DSI_BRG_DPI_EN_M  (DSI_BRG_DPI_EN_V << DSI_BRG_DPI_EN_S)
+#define DSI_BRG_DPI_EN_V  0x00000001U
+#define DSI_BRG_DPI_EN_S  0
+/** DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT : R/W; bitpos: [15:4]; default: 413;
+ *  this field configures the underrun interrupt musk, when underrun occurs and line
+ *  cnt is less then this field
+ */
+#define DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT    0x00000FFFU
+#define DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_M  (DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_V << DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_S)
+#define DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_V  0x00000FFFU
+#define DSI_BRG_FIFO_UNDERRUN_DISCARD_VCNT_S  4
+
+/** DSI_BRG_DPI_CONFIG_UPDATE_REG register
+ *  dsi_bridge dpi config update register
+ */
+#define DSI_BRG_DPI_CONFIG_UPDATE_REG (DR_REG_DSI_BRG_BASE + 0x44)
+/** DSI_BRG_DPI_CONFIG_UPDATE : WT; bitpos: [0]; default: 0;
+ *  write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_*
+ */
+#define DSI_BRG_DPI_CONFIG_UPDATE    (BIT(0))
+#define DSI_BRG_DPI_CONFIG_UPDATE_M  (DSI_BRG_DPI_CONFIG_UPDATE_V << DSI_BRG_DPI_CONFIG_UPDATE_S)
+#define DSI_BRG_DPI_CONFIG_UPDATE_V  0x00000001U
+#define DSI_BRG_DPI_CONFIG_UPDATE_S  0
+
+/** DSI_BRG_INT_ENA_REG register
+ *  dsi_bridge interrupt enable register
+ */
+#define DSI_BRG_INT_ENA_REG (DR_REG_DSI_BRG_BASE + 0x50)
+/** DSI_BRG_UNDERRUN_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled
+ *  by dpi_underrun  interrupt signal
+ */
+#define DSI_BRG_UNDERRUN_INT_ENA    (BIT(0))
+#define DSI_BRG_UNDERRUN_INT_ENA_M  (DSI_BRG_UNDERRUN_INT_ENA_V << DSI_BRG_UNDERRUN_INT_ENA_S)
+#define DSI_BRG_UNDERRUN_INT_ENA_V  0x00000001U
+#define DSI_BRG_UNDERRUN_INT_ENA_S  0
+/** DSI_BRG_VSYNC_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  write 1 to enables dpi_vsync_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by
+ *  dpi_vsync  interrupt signal
+ */
+#define DSI_BRG_VSYNC_INT_ENA    (BIT(1))
+#define DSI_BRG_VSYNC_INT_ENA_M  (DSI_BRG_VSYNC_INT_ENA_V << DSI_BRG_VSYNC_INT_ENA_S)
+#define DSI_BRG_VSYNC_INT_ENA_V  0x00000001U
+#define DSI_BRG_VSYNC_INT_ENA_S  1
+
+/** DSI_BRG_INT_CLR_REG register
+ *  dsi_bridge interrupt clear register
+ */
+#define DSI_BRG_INT_CLR_REG (DR_REG_DSI_BRG_BASE + 0x54)
+/** DSI_BRG_UNDERRUN_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
+ */
+#define DSI_BRG_UNDERRUN_INT_CLR    (BIT(0))
+#define DSI_BRG_UNDERRUN_INT_CLR_M  (DSI_BRG_UNDERRUN_INT_CLR_V << DSI_BRG_UNDERRUN_INT_CLR_S)
+#define DSI_BRG_UNDERRUN_INT_CLR_V  0x00000001U
+#define DSI_BRG_UNDERRUN_INT_CLR_S  0
+/** DSI_BRG_VSYNC_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  write 1 to this bit to clear dpi_vsync_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
+ */
+#define DSI_BRG_VSYNC_INT_CLR    (BIT(1))
+#define DSI_BRG_VSYNC_INT_CLR_M  (DSI_BRG_VSYNC_INT_CLR_V << DSI_BRG_VSYNC_INT_CLR_S)
+#define DSI_BRG_VSYNC_INT_CLR_V  0x00000001U
+#define DSI_BRG_VSYNC_INT_CLR_S  1
+
+/** DSI_BRG_INT_RAW_REG register
+ *  dsi_bridge raw interrupt register
+ */
+#define DSI_BRG_INT_RAW_REG (DR_REG_DSI_BRG_BASE + 0x58)
+/** DSI_BRG_UNDERRUN_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  the raw interrupt status of dpi_underrun
+ */
+#define DSI_BRG_UNDERRUN_INT_RAW    (BIT(0))
+#define DSI_BRG_UNDERRUN_INT_RAW_M  (DSI_BRG_UNDERRUN_INT_RAW_V << DSI_BRG_UNDERRUN_INT_RAW_S)
+#define DSI_BRG_UNDERRUN_INT_RAW_V  0x00000001U
+#define DSI_BRG_UNDERRUN_INT_RAW_S  0
+/** DSI_BRG_VSYNC_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  the raw interrupt status of dpi_vsync
+ */
+#define DSI_BRG_VSYNC_INT_RAW    (BIT(1))
+#define DSI_BRG_VSYNC_INT_RAW_M  (DSI_BRG_VSYNC_INT_RAW_V << DSI_BRG_VSYNC_INT_RAW_S)
+#define DSI_BRG_VSYNC_INT_RAW_V  0x00000001U
+#define DSI_BRG_VSYNC_INT_RAW_S  1
+
+/** DSI_BRG_INT_ST_REG register
+ *  dsi_bridge masked interrupt register
+ */
+#define DSI_BRG_INT_ST_REG (DR_REG_DSI_BRG_BASE + 0x5c)
+/** DSI_BRG_UNDERRUN_INT_ST : RO; bitpos: [0]; default: 0;
+ *  the masked interrupt status of dpi_underrun
+ */
+#define DSI_BRG_UNDERRUN_INT_ST    (BIT(0))
+#define DSI_BRG_UNDERRUN_INT_ST_M  (DSI_BRG_UNDERRUN_INT_ST_V << DSI_BRG_UNDERRUN_INT_ST_S)
+#define DSI_BRG_UNDERRUN_INT_ST_V  0x00000001U
+#define DSI_BRG_UNDERRUN_INT_ST_S  0
+/** DSI_BRG_VSYNC_INT_ST : RO; bitpos: [1]; default: 0;
+ *  the masked interrupt status of dpi_vsync
+ */
+#define DSI_BRG_VSYNC_INT_ST    (BIT(1))
+#define DSI_BRG_VSYNC_INT_ST_M  (DSI_BRG_VSYNC_INT_ST_V << DSI_BRG_VSYNC_INT_ST_S)
+#define DSI_BRG_VSYNC_INT_ST_V  0x00000001U
+#define DSI_BRG_VSYNC_INT_ST_S  1
+
+/** DSI_BRG_HOST_BIST_CTL_REG register
+ *  dsi_bridge host bist control register
+ */
+#define DSI_BRG_HOST_BIST_CTL_REG (DR_REG_DSI_BRG_BASE + 0x60)
+/** DSI_BRG_BISTOK : RO; bitpos: [0]; default: 0;
+ *  bistok
+ */
+#define DSI_BRG_BISTOK    (BIT(0))
+#define DSI_BRG_BISTOK_M  (DSI_BRG_BISTOK_V << DSI_BRG_BISTOK_S)
+#define DSI_BRG_BISTOK_V  0x00000001U
+#define DSI_BRG_BISTOK_S  0
+/** DSI_BRG_BISTON : R/W; bitpos: [1]; default: 0;
+ *  biston
+ */
+#define DSI_BRG_BISTON    (BIT(1))
+#define DSI_BRG_BISTON_M  (DSI_BRG_BISTON_V << DSI_BRG_BISTON_S)
+#define DSI_BRG_BISTON_V  0x00000001U
+#define DSI_BRG_BISTON_S  1
+
+/** DSI_BRG_HOST_TRIGGER_REV_REG register
+ *  dsi_bridge host trigger reverse control register
+ */
+#define DSI_BRG_HOST_TRIGGER_REV_REG (DR_REG_DSI_BRG_BASE + 0x64)
+/** DSI_BRG_TX_TRIGGER_REV_EN : R/W; bitpos: [0]; default: 0;
+ *  tx_trigger reverse. 0: disable, 1: enable
+ */
+#define DSI_BRG_TX_TRIGGER_REV_EN    (BIT(0))
+#define DSI_BRG_TX_TRIGGER_REV_EN_M  (DSI_BRG_TX_TRIGGER_REV_EN_V << DSI_BRG_TX_TRIGGER_REV_EN_S)
+#define DSI_BRG_TX_TRIGGER_REV_EN_V  0x00000001U
+#define DSI_BRG_TX_TRIGGER_REV_EN_S  0
+/** DSI_BRG_RX_TRIGGER_REV_EN : R/W; bitpos: [1]; default: 0;
+ *  rx_trigger reverse. 0: disable, 1: enable
+ */
+#define DSI_BRG_RX_TRIGGER_REV_EN    (BIT(1))
+#define DSI_BRG_RX_TRIGGER_REV_EN_M  (DSI_BRG_RX_TRIGGER_REV_EN_V << DSI_BRG_RX_TRIGGER_REV_EN_S)
+#define DSI_BRG_RX_TRIGGER_REV_EN_V  0x00000001U
+#define DSI_BRG_RX_TRIGGER_REV_EN_S  1
+
+/** DSI_BRG_BLK_RAW_NUM_CFG_REG register
+ *  dsi_bridge block raw number control register
+ */
+#define DSI_BRG_BLK_RAW_NUM_CFG_REG (DR_REG_DSI_BRG_BASE + 0x68)
+/** DSI_BRG_BLK_RAW_NUM_TOTAL : R/W; bitpos: [21:0]; default: 230400;
+ *  this field configures number of total block pix bits/64
+ */
+#define DSI_BRG_BLK_RAW_NUM_TOTAL    0x003FFFFFU
+#define DSI_BRG_BLK_RAW_NUM_TOTAL_M  (DSI_BRG_BLK_RAW_NUM_TOTAL_V << DSI_BRG_BLK_RAW_NUM_TOTAL_S)
+#define DSI_BRG_BLK_RAW_NUM_TOTAL_V  0x003FFFFFU
+#define DSI_BRG_BLK_RAW_NUM_TOTAL_S  0
+/** DSI_BRG_BLK_RAW_NUM_TOTAL_SET : WT; bitpos: [31]; default: 0;
+ *  write 1 to reload reg_blk_raw_num_total to internal cnt
+ */
+#define DSI_BRG_BLK_RAW_NUM_TOTAL_SET    (BIT(31))
+#define DSI_BRG_BLK_RAW_NUM_TOTAL_SET_M  (DSI_BRG_BLK_RAW_NUM_TOTAL_SET_V << DSI_BRG_BLK_RAW_NUM_TOTAL_SET_S)
+#define DSI_BRG_BLK_RAW_NUM_TOTAL_SET_V  0x00000001U
+#define DSI_BRG_BLK_RAW_NUM_TOTAL_SET_S  31
+
+/** DSI_BRG_DMA_FRAME_INTERVAL_REG register
+ *  dsi_bridge dam frame interval control register
+ */
+#define DSI_BRG_DMA_FRAME_INTERVAL_REG (DR_REG_DSI_BRG_BASE + 0x6c)
+/** DSI_BRG_DMA_FRAME_SLOT : R/W; bitpos: [9:0]; default: 9;
+ *  this field configures the max frame_slot_cnt
+ */
+#define DSI_BRG_DMA_FRAME_SLOT    0x000003FFU
+#define DSI_BRG_DMA_FRAME_SLOT_M  (DSI_BRG_DMA_FRAME_SLOT_V << DSI_BRG_DMA_FRAME_SLOT_S)
+#define DSI_BRG_DMA_FRAME_SLOT_V  0x000003FFU
+#define DSI_BRG_DMA_FRAME_SLOT_S  0
+/** DSI_BRG_DMA_FRAME_INTERVAL : R/W; bitpos: [27:10]; default: 9;
+ *  this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1
+ *  when frame_slot_cnt if full
+ */
+#define DSI_BRG_DMA_FRAME_INTERVAL    0x0003FFFFU
+#define DSI_BRG_DMA_FRAME_INTERVAL_M  (DSI_BRG_DMA_FRAME_INTERVAL_V << DSI_BRG_DMA_FRAME_INTERVAL_S)
+#define DSI_BRG_DMA_FRAME_INTERVAL_V  0x0003FFFFU
+#define DSI_BRG_DMA_FRAME_INTERVAL_S  10
+/** DSI_BRG_DMA_MULTIBLK_EN : R/W; bitpos: [28]; default: 0;
+ *  this bit configures enable multi-blk transfer, 0: disable, 1: enable
+ */
+#define DSI_BRG_DMA_MULTIBLK_EN    (BIT(28))
+#define DSI_BRG_DMA_MULTIBLK_EN_M  (DSI_BRG_DMA_MULTIBLK_EN_V << DSI_BRG_DMA_MULTIBLK_EN_S)
+#define DSI_BRG_DMA_MULTIBLK_EN_V  0x00000001U
+#define DSI_BRG_DMA_MULTIBLK_EN_S  28
+/** DSI_BRG_DMA_FRAME_INTERVAL_EN : R/W; bitpos: [29]; default: 1;
+ *  this bit configures enable interval between frame transfer, 0: disable, 1: enable
+ */
+#define DSI_BRG_DMA_FRAME_INTERVAL_EN    (BIT(29))
+#define DSI_BRG_DMA_FRAME_INTERVAL_EN_M  (DSI_BRG_DMA_FRAME_INTERVAL_EN_V << DSI_BRG_DMA_FRAME_INTERVAL_EN_S)
+#define DSI_BRG_DMA_FRAME_INTERVAL_EN_V  0x00000001U
+#define DSI_BRG_DMA_FRAME_INTERVAL_EN_S  29
+
+/** DSI_BRG_MEM_AUX_CTRL_REG register
+ *  dsi_bridge mem aux control register
+ */
+#define DSI_BRG_MEM_AUX_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x70)
+/** DSI_BRG_DSI_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896;
+ *  this field configures dsi_bridge fifo memory aux ctrl
+ */
+#define DSI_BRG_DSI_MEM_AUX_CTRL    0x00003FFFU
+#define DSI_BRG_DSI_MEM_AUX_CTRL_M  (DSI_BRG_DSI_MEM_AUX_CTRL_V << DSI_BRG_DSI_MEM_AUX_CTRL_S)
+#define DSI_BRG_DSI_MEM_AUX_CTRL_V  0x00003FFFU
+#define DSI_BRG_DSI_MEM_AUX_CTRL_S  0
+
+/** DSI_BRG_RDN_ECO_CS_REG register
+ *  dsi_bridge rdn eco cs register
+ */
+#define DSI_BRG_RDN_ECO_CS_REG (DR_REG_DSI_BRG_BASE + 0x74)
+/** DSI_BRG_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  rdn_eco_en
+ */
+#define DSI_BRG_RDN_ECO_EN    (BIT(0))
+#define DSI_BRG_RDN_ECO_EN_M  (DSI_BRG_RDN_ECO_EN_V << DSI_BRG_RDN_ECO_EN_S)
+#define DSI_BRG_RDN_ECO_EN_V  0x00000001U
+#define DSI_BRG_RDN_ECO_EN_S  0
+/** DSI_BRG_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  rdn_eco_result
+ */
+#define DSI_BRG_RDN_ECO_RESULT    (BIT(1))
+#define DSI_BRG_RDN_ECO_RESULT_M  (DSI_BRG_RDN_ECO_RESULT_V << DSI_BRG_RDN_ECO_RESULT_S)
+#define DSI_BRG_RDN_ECO_RESULT_V  0x00000001U
+#define DSI_BRG_RDN_ECO_RESULT_S  1
+
+/** DSI_BRG_RDN_ECO_LOW_REG register
+ *  dsi_bridge rdn eco all low register
+ */
+#define DSI_BRG_RDN_ECO_LOW_REG (DR_REG_DSI_BRG_BASE + 0x78)
+/** DSI_BRG_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  rdn_eco_low
+ */
+#define DSI_BRG_RDN_ECO_LOW    0xFFFFFFFFU
+#define DSI_BRG_RDN_ECO_LOW_M  (DSI_BRG_RDN_ECO_LOW_V << DSI_BRG_RDN_ECO_LOW_S)
+#define DSI_BRG_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define DSI_BRG_RDN_ECO_LOW_S  0
+
+/** DSI_BRG_RDN_ECO_HIGH_REG register
+ *  dsi_bridge rdn eco all high register
+ */
+#define DSI_BRG_RDN_ECO_HIGH_REG (DR_REG_DSI_BRG_BASE + 0x7c)
+/** DSI_BRG_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  rdn_eco_high
+ */
+#define DSI_BRG_RDN_ECO_HIGH    0xFFFFFFFFU
+#define DSI_BRG_RDN_ECO_HIGH_M  (DSI_BRG_RDN_ECO_HIGH_V << DSI_BRG_RDN_ECO_HIGH_S)
+#define DSI_BRG_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define DSI_BRG_RDN_ECO_HIGH_S  0
+
+/** DSI_BRG_HOST_CTRL_REG register
+ *  dsi_bridge host control register
+ */
+#define DSI_BRG_HOST_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x80)
+/** DSI_BRG_DSI_CFG_REF_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1:
+ *  enable
+ */
+#define DSI_BRG_DSI_CFG_REF_CLK_EN    (BIT(0))
+#define DSI_BRG_DSI_CFG_REF_CLK_EN_M  (DSI_BRG_DSI_CFG_REF_CLK_EN_V << DSI_BRG_DSI_CFG_REF_CLK_EN_S)
+#define DSI_BRG_DSI_CFG_REF_CLK_EN_V  0x00000001U
+#define DSI_BRG_DSI_CFG_REF_CLK_EN_S  0
+
+/** DSI_BRG_MEM_CLK_CTRL_REG register
+ *  dsi_bridge mem force on control register
+ */
+#define DSI_BRG_MEM_CLK_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x84)
+/** DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1:
+ *  force on
+ */
+#define DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON    (BIT(0))
+#define DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_M  (DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_V << DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_S)
+#define DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define DSI_BRG_DSI_BRIDGE_MEM_CLK_FORCE_ON_S  0
+/** DSI_BRG_DSI_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on
+ */
+#define DSI_BRG_DSI_MEM_CLK_FORCE_ON    (BIT(1))
+#define DSI_BRG_DSI_MEM_CLK_FORCE_ON_M  (DSI_BRG_DSI_MEM_CLK_FORCE_ON_V << DSI_BRG_DSI_MEM_CLK_FORCE_ON_S)
+#define DSI_BRG_DSI_MEM_CLK_FORCE_ON_V  0x00000001U
+#define DSI_BRG_DSI_MEM_CLK_FORCE_ON_S  1
+
+/** DSI_BRG_DMA_FLOW_CTRL_REG register
+ *  dsi_bridge dma flow controller register
+ */
+#define DSI_BRG_DMA_FLOW_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x88)
+/** DSI_BRG_DSI_DMA_FLOW_CONTROLLER : R/W; bitpos: [0]; default: 1;
+ *  this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge
+ *  as flow controller
+ */
+#define DSI_BRG_DSI_DMA_FLOW_CONTROLLER    (BIT(0))
+#define DSI_BRG_DSI_DMA_FLOW_CONTROLLER_M  (DSI_BRG_DSI_DMA_FLOW_CONTROLLER_V << DSI_BRG_DSI_DMA_FLOW_CONTROLLER_S)
+#define DSI_BRG_DSI_DMA_FLOW_CONTROLLER_V  0x00000001U
+#define DSI_BRG_DSI_DMA_FLOW_CONTROLLER_S  0
+/** DSI_BRG_DMA_FLOW_MULTIBLK_NUM : R/W; bitpos: [7:4]; default: 1;
+ *  this field configures the num of blocks when multi-blk is enable and dmac as flow
+ *  controller
+ */
+#define DSI_BRG_DMA_FLOW_MULTIBLK_NUM    0x0000000FU
+#define DSI_BRG_DMA_FLOW_MULTIBLK_NUM_M  (DSI_BRG_DMA_FLOW_MULTIBLK_NUM_V << DSI_BRG_DMA_FLOW_MULTIBLK_NUM_S)
+#define DSI_BRG_DMA_FLOW_MULTIBLK_NUM_V  0x0000000FU
+#define DSI_BRG_DMA_FLOW_MULTIBLK_NUM_S  4
+
+/** DSI_BRG_RAW_BUF_ALMOST_EMPTY_THRD_REG register
+ *  dsi_bridge buffer empty threshold register
+ */
+#define DSI_BRG_RAW_BUF_ALMOST_EMPTY_THRD_REG (DR_REG_DSI_BRG_BASE + 0x8c)
+/** DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD : R/W; bitpos: [10:0]; default: 512;
+ *  this field configures the fifo almost empty threshold, is valid only when dmac as
+ *  flow controller
+ */
+#define DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD    0x000007FFU
+#define DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_M  (DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_V << DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_S)
+#define DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_V  0x000007FFU
+#define DSI_BRG_DSI_RAW_BUF_ALMOST_EMPTY_THRD_S  0
+
+/** DSI_BRG_YUV_CFG_REG register
+ *  dsi_bridge yuv format config register
+ */
+#define DSI_BRG_YUV_CFG_REG (DR_REG_DSI_BRG_BASE + 0x90)
+/** DSI_BRG_PROTOCAL : R/W; bitpos: [0]; default: 0;
+ *  this bit configures yuv protoocl, 0: bt.601, 1: bt.709
+ */
+#define DSI_BRG_PROTOCAL    (BIT(0))
+#define DSI_BRG_PROTOCAL_M  (DSI_BRG_PROTOCAL_V << DSI_BRG_PROTOCAL_S)
+#define DSI_BRG_PROTOCAL_V  0x00000001U
+#define DSI_BRG_PROTOCAL_S  0
+/** DSI_BRG_YUV_PIX_ENDIAN : R/W; bitpos: [1]; default: 0;
+ *  this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0
+ */
+#define DSI_BRG_YUV_PIX_ENDIAN    (BIT(1))
+#define DSI_BRG_YUV_PIX_ENDIAN_M  (DSI_BRG_YUV_PIX_ENDIAN_V << DSI_BRG_YUV_PIX_ENDIAN_S)
+#define DSI_BRG_YUV_PIX_ENDIAN_V  0x00000001U
+#define DSI_BRG_YUV_PIX_ENDIAN_S  1
+/** DSI_BRG_YUV422_FORMAT : R/W; bitpos: [3:2]; default: 0;
+ *  this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy
+ */
+#define DSI_BRG_YUV422_FORMAT    0x00000003U
+#define DSI_BRG_YUV422_FORMAT_M  (DSI_BRG_YUV422_FORMAT_V << DSI_BRG_YUV422_FORMAT_S)
+#define DSI_BRG_YUV422_FORMAT_V  0x00000003U
+#define DSI_BRG_YUV422_FORMAT_S  2
+/** DSI_BRG_YUV_RANGE : R/W; bitpos: [4]; default: 0;
+ *  Configures yuv pixel range, 0: limit range, 1: full range
+ */
+#define DSI_BRG_YUV_RANGE    (BIT(4))
+#define DSI_BRG_YUV_RANGE_M  (DSI_BRG_YUV_RANGE_V << DSI_BRG_YUV_RANGE_S)
+#define DSI_BRG_YUV_RANGE_V  0x00000001U
+#define DSI_BRG_YUV_RANGE_S  4
+
+/** DSI_BRG_PHY_LP_LOOPBACK_CTRL_REG register
+ *  dsi phy lp_loopback test ctrl
+ */
+#define DSI_BRG_PHY_LP_LOOPBACK_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x94)
+/** DSI_BRG_PHY_LP_TXDATAESC_1 : R/W; bitpos: [7:0]; default: 0;
+ *  txdataesc_1 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_TXDATAESC_1    0x000000FFU
+#define DSI_BRG_PHY_LP_TXDATAESC_1_M  (DSI_BRG_PHY_LP_TXDATAESC_1_V << DSI_BRG_PHY_LP_TXDATAESC_1_S)
+#define DSI_BRG_PHY_LP_TXDATAESC_1_V  0x000000FFU
+#define DSI_BRG_PHY_LP_TXDATAESC_1_S  0
+/** DSI_BRG_PHY_LP_TXREQUESTESC_1 : R/W; bitpos: [8]; default: 0;
+ *  txrequestesc_1 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_TXREQUESTESC_1    (BIT(8))
+#define DSI_BRG_PHY_LP_TXREQUESTESC_1_M  (DSI_BRG_PHY_LP_TXREQUESTESC_1_V << DSI_BRG_PHY_LP_TXREQUESTESC_1_S)
+#define DSI_BRG_PHY_LP_TXREQUESTESC_1_V  0x00000001U
+#define DSI_BRG_PHY_LP_TXREQUESTESC_1_S  8
+/** DSI_BRG_PHY_LP_TXVALIDESC_1 : R/W; bitpos: [9]; default: 0;
+ *  txvalidesc_1 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_TXVALIDESC_1    (BIT(9))
+#define DSI_BRG_PHY_LP_TXVALIDESC_1_M  (DSI_BRG_PHY_LP_TXVALIDESC_1_V << DSI_BRG_PHY_LP_TXVALIDESC_1_S)
+#define DSI_BRG_PHY_LP_TXVALIDESC_1_V  0x00000001U
+#define DSI_BRG_PHY_LP_TXVALIDESC_1_S  9
+/** DSI_BRG_PHY_LP_TXLPDTESC_1 : R/W; bitpos: [10]; default: 0;
+ *  txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_TXLPDTESC_1    (BIT(10))
+#define DSI_BRG_PHY_LP_TXLPDTESC_1_M  (DSI_BRG_PHY_LP_TXLPDTESC_1_V << DSI_BRG_PHY_LP_TXLPDTESC_1_S)
+#define DSI_BRG_PHY_LP_TXLPDTESC_1_V  0x00000001U
+#define DSI_BRG_PHY_LP_TXLPDTESC_1_S  10
+/** DSI_BRG_PHY_LP_BASEDIR_1 : R/W; bitpos: [11]; default: 0;
+ *  basedir_1 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_BASEDIR_1    (BIT(11))
+#define DSI_BRG_PHY_LP_BASEDIR_1_M  (DSI_BRG_PHY_LP_BASEDIR_1_V << DSI_BRG_PHY_LP_BASEDIR_1_S)
+#define DSI_BRG_PHY_LP_BASEDIR_1_V  0x00000001U
+#define DSI_BRG_PHY_LP_BASEDIR_1_S  11
+/** DSI_BRG_PHY_LP_TXDATAESC_0 : R/W; bitpos: [23:16]; default: 0;
+ *  txdataesc_0 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_TXDATAESC_0    0x000000FFU
+#define DSI_BRG_PHY_LP_TXDATAESC_0_M  (DSI_BRG_PHY_LP_TXDATAESC_0_V << DSI_BRG_PHY_LP_TXDATAESC_0_S)
+#define DSI_BRG_PHY_LP_TXDATAESC_0_V  0x000000FFU
+#define DSI_BRG_PHY_LP_TXDATAESC_0_S  16
+/** DSI_BRG_PHY_LP_TXREQUESTESC_0 : R/W; bitpos: [24]; default: 0;
+ *  txrequestesc_0 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_TXREQUESTESC_0    (BIT(24))
+#define DSI_BRG_PHY_LP_TXREQUESTESC_0_M  (DSI_BRG_PHY_LP_TXREQUESTESC_0_V << DSI_BRG_PHY_LP_TXREQUESTESC_0_S)
+#define DSI_BRG_PHY_LP_TXREQUESTESC_0_V  0x00000001U
+#define DSI_BRG_PHY_LP_TXREQUESTESC_0_S  24
+/** DSI_BRG_PHY_LP_TXVALIDESC_0 : R/W; bitpos: [25]; default: 0;
+ *  txvalidesc_0 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_TXVALIDESC_0    (BIT(25))
+#define DSI_BRG_PHY_LP_TXVALIDESC_0_M  (DSI_BRG_PHY_LP_TXVALIDESC_0_V << DSI_BRG_PHY_LP_TXVALIDESC_0_S)
+#define DSI_BRG_PHY_LP_TXVALIDESC_0_V  0x00000001U
+#define DSI_BRG_PHY_LP_TXVALIDESC_0_S  25
+/** DSI_BRG_PHY_LP_TXLPDTESC_0 : R/W; bitpos: [26]; default: 0;
+ *  txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_TXLPDTESC_0    (BIT(26))
+#define DSI_BRG_PHY_LP_TXLPDTESC_0_M  (DSI_BRG_PHY_LP_TXLPDTESC_0_V << DSI_BRG_PHY_LP_TXLPDTESC_0_S)
+#define DSI_BRG_PHY_LP_TXLPDTESC_0_V  0x00000001U
+#define DSI_BRG_PHY_LP_TXLPDTESC_0_S  26
+/** DSI_BRG_PHY_LP_BASEDIR_0 : R/W; bitpos: [27]; default: 0;
+ *  basedir_0 ctrl when enable dsi phy lp_loopback_test
+ */
+#define DSI_BRG_PHY_LP_BASEDIR_0    (BIT(27))
+#define DSI_BRG_PHY_LP_BASEDIR_0_M  (DSI_BRG_PHY_LP_BASEDIR_0_V << DSI_BRG_PHY_LP_BASEDIR_0_S)
+#define DSI_BRG_PHY_LP_BASEDIR_0_V  0x00000001U
+#define DSI_BRG_PHY_LP_BASEDIR_0_S  27
+/** DSI_BRG_PHY_LP_LOOPBACK_CHECK : WT; bitpos: [28]; default: 0;
+ *  dsi phy lp_loopback test start check
+ */
+#define DSI_BRG_PHY_LP_LOOPBACK_CHECK    (BIT(28))
+#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_M  (DSI_BRG_PHY_LP_LOOPBACK_CHECK_V << DSI_BRG_PHY_LP_LOOPBACK_CHECK_S)
+#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_V  0x00000001U
+#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_S  28
+/** DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE : RO; bitpos: [29]; default: 0;
+ *  dsi phy lp_loopback test check done
+ */
+#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE    (BIT(29))
+#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_M  (DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_V << DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_S)
+#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_V  0x00000001U
+#define DSI_BRG_PHY_LP_LOOPBACK_CHECK_DONE_S  29
+/** DSI_BRG_PHY_LP_LOOPBACK_EN : R/W; bitpos: [30]; default: 0;
+ *  dsi phy lp_loopback ctrl en
+ */
+#define DSI_BRG_PHY_LP_LOOPBACK_EN    (BIT(30))
+#define DSI_BRG_PHY_LP_LOOPBACK_EN_M  (DSI_BRG_PHY_LP_LOOPBACK_EN_V << DSI_BRG_PHY_LP_LOOPBACK_EN_S)
+#define DSI_BRG_PHY_LP_LOOPBACK_EN_V  0x00000001U
+#define DSI_BRG_PHY_LP_LOOPBACK_EN_S  30
+/** DSI_BRG_PHY_LP_LOOPBACK_OK : RO; bitpos: [31]; default: 0;
+ *  result of dsi phy lp_loopback test
+ */
+#define DSI_BRG_PHY_LP_LOOPBACK_OK    (BIT(31))
+#define DSI_BRG_PHY_LP_LOOPBACK_OK_M  (DSI_BRG_PHY_LP_LOOPBACK_OK_V << DSI_BRG_PHY_LP_LOOPBACK_OK_S)
+#define DSI_BRG_PHY_LP_LOOPBACK_OK_V  0x00000001U
+#define DSI_BRG_PHY_LP_LOOPBACK_OK_S  31
+
+/** DSI_BRG_PHY_HS_LOOPBACK_CTRL_REG register
+ *  dsi phy hp_loopback test ctrl
+ */
+#define DSI_BRG_PHY_HS_LOOPBACK_CTRL_REG (DR_REG_DSI_BRG_BASE + 0x98)
+/** DSI_BRG_PHY_HS_TXDATAHS_1 : R/W; bitpos: [7:0]; default: 0;
+ *  txdatahs_1 ctrl when enable dsi phy hs_loopback_test
+ */
+#define DSI_BRG_PHY_HS_TXDATAHS_1    0x000000FFU
+#define DSI_BRG_PHY_HS_TXDATAHS_1_M  (DSI_BRG_PHY_HS_TXDATAHS_1_V << DSI_BRG_PHY_HS_TXDATAHS_1_S)
+#define DSI_BRG_PHY_HS_TXDATAHS_1_V  0x000000FFU
+#define DSI_BRG_PHY_HS_TXDATAHS_1_S  0
+/** DSI_BRG_PHY_HS_TXREQUESTDATAHS_1 : R/W; bitpos: [8]; default: 0;
+ *  txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test
+ */
+#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_1    (BIT(8))
+#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_M  (DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_V << DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_S)
+#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_V  0x00000001U
+#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_1_S  8
+/** DSI_BRG_PHY_HS_BASEDIR_1 : R/W; bitpos: [9]; default: 1;
+ *  basedir_1 ctrl when enable dsi phy hs_loopback_test
+ */
+#define DSI_BRG_PHY_HS_BASEDIR_1    (BIT(9))
+#define DSI_BRG_PHY_HS_BASEDIR_1_M  (DSI_BRG_PHY_HS_BASEDIR_1_V << DSI_BRG_PHY_HS_BASEDIR_1_S)
+#define DSI_BRG_PHY_HS_BASEDIR_1_V  0x00000001U
+#define DSI_BRG_PHY_HS_BASEDIR_1_S  9
+/** DSI_BRG_PHY_HS_TXDATAHS_0 : R/W; bitpos: [23:16]; default: 0;
+ *  txdatahs_0 ctrl when enable dsi phy hs_loopback_test
+ */
+#define DSI_BRG_PHY_HS_TXDATAHS_0    0x000000FFU
+#define DSI_BRG_PHY_HS_TXDATAHS_0_M  (DSI_BRG_PHY_HS_TXDATAHS_0_V << DSI_BRG_PHY_HS_TXDATAHS_0_S)
+#define DSI_BRG_PHY_HS_TXDATAHS_0_V  0x000000FFU
+#define DSI_BRG_PHY_HS_TXDATAHS_0_S  16
+/** DSI_BRG_PHY_HS_TXREQUESTDATAHS_0 : R/W; bitpos: [24]; default: 0;
+ *  txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test
+ */
+#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_0    (BIT(24))
+#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_M  (DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_V << DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_S)
+#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_V  0x00000001U
+#define DSI_BRG_PHY_HS_TXREQUESTDATAHS_0_S  24
+/** DSI_BRG_PHY_HS_BASEDIR_0 : R/W; bitpos: [25]; default: 0;
+ *  basedir_0 ctrl when enable dsi phy hs_loopback_test
+ */
+#define DSI_BRG_PHY_HS_BASEDIR_0    (BIT(25))
+#define DSI_BRG_PHY_HS_BASEDIR_0_M  (DSI_BRG_PHY_HS_BASEDIR_0_V << DSI_BRG_PHY_HS_BASEDIR_0_S)
+#define DSI_BRG_PHY_HS_BASEDIR_0_V  0x00000001U
+#define DSI_BRG_PHY_HS_BASEDIR_0_S  25
+/** DSI_BRG_PHY_HS_TXREQUESTHSCLK : R/W; bitpos: [27]; default: 0;
+ *  txrequesthsclk when  enable dsi phy hs_loopback_test
+ */
+#define DSI_BRG_PHY_HS_TXREQUESTHSCLK    (BIT(27))
+#define DSI_BRG_PHY_HS_TXREQUESTHSCLK_M  (DSI_BRG_PHY_HS_TXREQUESTHSCLK_V << DSI_BRG_PHY_HS_TXREQUESTHSCLK_S)
+#define DSI_BRG_PHY_HS_TXREQUESTHSCLK_V  0x00000001U
+#define DSI_BRG_PHY_HS_TXREQUESTHSCLK_S  27
+/** DSI_BRG_PHY_HS_LOOPBACK_CHECK : WT; bitpos: [28]; default: 0;
+ *  dsi phy hs_loopback test start check
+ */
+#define DSI_BRG_PHY_HS_LOOPBACK_CHECK    (BIT(28))
+#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_M  (DSI_BRG_PHY_HS_LOOPBACK_CHECK_V << DSI_BRG_PHY_HS_LOOPBACK_CHECK_S)
+#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_V  0x00000001U
+#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_S  28
+/** DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE : RO; bitpos: [29]; default: 0;
+ *  dsi phy hs_loopback test check done
+ */
+#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE    (BIT(29))
+#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_M  (DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_V << DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_S)
+#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_V  0x00000001U
+#define DSI_BRG_PHY_HS_LOOPBACK_CHECK_DONE_S  29
+/** DSI_BRG_PHY_HS_LOOPBACK_EN : R/W; bitpos: [30]; default: 0;
+ *  dsi phy hs_loopback ctrl en
+ */
+#define DSI_BRG_PHY_HS_LOOPBACK_EN    (BIT(30))
+#define DSI_BRG_PHY_HS_LOOPBACK_EN_M  (DSI_BRG_PHY_HS_LOOPBACK_EN_V << DSI_BRG_PHY_HS_LOOPBACK_EN_S)
+#define DSI_BRG_PHY_HS_LOOPBACK_EN_V  0x00000001U
+#define DSI_BRG_PHY_HS_LOOPBACK_EN_S  30
+/** DSI_BRG_PHY_HS_LOOPBACK_OK : RO; bitpos: [31]; default: 0;
+ *  result of dsi phy hs_loopback test
+ */
+#define DSI_BRG_PHY_HS_LOOPBACK_OK    (BIT(31))
+#define DSI_BRG_PHY_HS_LOOPBACK_OK_M  (DSI_BRG_PHY_HS_LOOPBACK_OK_V << DSI_BRG_PHY_HS_LOOPBACK_OK_S)
+#define DSI_BRG_PHY_HS_LOOPBACK_OK_V  0x00000001U
+#define DSI_BRG_PHY_HS_LOOPBACK_OK_S  31
+
+/** DSI_BRG_PHY_LOOPBACK_CNT_REG register
+ *  loopback test cnt
+ */
+#define DSI_BRG_PHY_LOOPBACK_CNT_REG (DR_REG_DSI_BRG_BASE + 0x9c)
+/** DSI_BRG_PHY_HS_CHECK_CNT_TH : R/W; bitpos: [7:0]; default: 64;
+ *  hs_loopback test check cnt
+ */
+#define DSI_BRG_PHY_HS_CHECK_CNT_TH    0x000000FFU
+#define DSI_BRG_PHY_HS_CHECK_CNT_TH_M  (DSI_BRG_PHY_HS_CHECK_CNT_TH_V << DSI_BRG_PHY_HS_CHECK_CNT_TH_S)
+#define DSI_BRG_PHY_HS_CHECK_CNT_TH_V  0x000000FFU
+#define DSI_BRG_PHY_HS_CHECK_CNT_TH_S  0
+/** DSI_BRG_PHY_LP_CHECK_CNT_TH : R/W; bitpos: [23:16]; default: 64;
+ *  lp_loopback test check cnt
+ */
+#define DSI_BRG_PHY_LP_CHECK_CNT_TH    0x000000FFU
+#define DSI_BRG_PHY_LP_CHECK_CNT_TH_M  (DSI_BRG_PHY_LP_CHECK_CNT_TH_V << DSI_BRG_PHY_LP_CHECK_CNT_TH_S)
+#define DSI_BRG_PHY_LP_CHECK_CNT_TH_V  0x000000FFU
+#define DSI_BRG_PHY_LP_CHECK_CNT_TH_S  16
+
+/** DSI_BRG_VER_DATE_REG register
+ *  version control register
+ */
+#define DSI_BRG_VER_DATE_REG (DR_REG_DSI_BRG_BASE + 0x100)
+/** DSI_BRG_VER_DATA : R/W; bitpos: [31:0]; default: 539296009;
+ *  Represents csv version
+ */
+#define DSI_BRG_VER_DATA    0xFFFFFFFFU
+#define DSI_BRG_VER_DATA_M  (DSI_BRG_VER_DATA_V << DSI_BRG_VER_DATA_S)
+#define DSI_BRG_VER_DATA_V  0xFFFFFFFFU
+#define DSI_BRG_VER_DATA_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/mipi_dsi_bridge_struct.h

@@ -0,0 +1,818 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of clk_en register
+ *  dsi bridge clk control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  this bit configures force_on of dsi_bridge register clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_clk_en_reg_t;
+
+/** Type of en register
+ *  dsi bridge en register
+ */
+typedef union {
+    struct {
+        /** dsi_en : R/W; bitpos: [0]; default: 0;
+         *  this bit configures module enable of dsi_bridge. 0: disable, 1: enable
+         */
+        uint32_t dsi_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_en_reg_t;
+
+/** Type of dma_req_cfg register
+ *  dsi bridge dma burst len register
+ */
+typedef union {
+    struct {
+        /** dma_burst_len : R/W; bitpos: [11:0]; default: 128;
+         *  this field configures the num of 64-bit in one dma burst transfer, valid only when
+         *  dsi_bridge as flow controller
+         */
+        uint32_t dma_burst_len:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} dsi_brg_dma_req_cfg_reg_t;
+
+/** Type of raw_num_cfg register
+ *  dsi bridge raw number control register
+ */
+typedef union {
+    struct {
+        /** raw_num_total : R/W; bitpos: [21:0]; default: 230400;
+         *  this field configures number of total pix bits/64
+         */
+        uint32_t raw_num_total:22;
+        /** unalign_64bit_en : R/W; bitpos: [22]; default: 0;
+         *  this field configures whether the total pix bits is a multiple of 64bits. 0: align
+         *  to 64-bit, 1: unalign to 64-bit
+         */
+        uint32_t unalign_64bit_en:1;
+        uint32_t reserved_23:8;
+        /** raw_num_total_set : WT; bitpos: [31]; default: 0;
+         *  this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable,
+         *  1: enable. valid only when dsi_bridge as flow controller
+         */
+        uint32_t raw_num_total_set:1;
+    };
+    uint32_t val;
+} dsi_brg_raw_num_cfg_reg_t;
+
+/** Type of raw_buf_credit_ctl register
+ *  dsi bridge credit register
+ */
+typedef union {
+    struct {
+        /** credit_thrd : R/W; bitpos: [14:0]; default: 1024;
+         *  this field configures the threshold whether dsi_bridge fifo can receive one more
+         *  64-bit, valid only when dsi_bridge as flow controller
+         */
+        uint32_t credit_thrd:15;
+        uint32_t reserved_15:1;
+        /** credit_burst_thrd : R/W; bitpos: [30:16]; default: 800;
+         *  this field configures the threshold whether dsi_bridge fifo can receive one more
+         *  dma burst, valid only when dsi_bridge as flow controller
+         */
+        uint32_t credit_burst_thrd:15;
+        /** credit_reset : R/W; bitpos: [31]; default: 0;
+         *  this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when
+         *  dsi_bridge as flow controller
+         */
+        uint32_t credit_reset:1;
+    };
+    uint32_t val;
+} dsi_brg_raw_buf_credit_ctl_reg_t;
+
+/** Type of pixel_type register
+ *  dsi bridge dpi type control register
+ */
+typedef union {
+    struct {
+        /** raw_type : R/W; bitpos: [3:0]; default: 0;
+         *  this field configures the pixel type. 0: rgb888, 1:rgb666, 2:rgb565
+         */
+        uint32_t raw_type:4;
+        /** dpi_config : R/W; bitpos: [5:4]; default: 0;
+         *  this field configures the pixel arrange type of dpi interface
+         */
+        uint32_t dpi_config:2;
+        /** data_in_type : R/W; bitpos: [6]; default: 0;
+         *  input data type, 0: rgb, 1: yuv
+         */
+        uint32_t data_in_type:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} dsi_brg_pixel_type_reg_t;
+
+/** Type of dma_block_interval register
+ *  dsi bridge dma block interval control register
+ */
+typedef union {
+    struct {
+        /** dma_block_slot : R/W; bitpos: [9:0]; default: 9;
+         *  this field configures the max block_slot_cnt
+         */
+        uint32_t dma_block_slot:10;
+        /** dma_block_interval : R/W; bitpos: [27:10]; default: 9;
+         *  this field configures the max block_interval_cnt, block_interval_cnt increased by 1
+         *  when block_slot_cnt if full
+         */
+        uint32_t dma_block_interval:18;
+        /** raw_num_total_auto_reload : R/W; bitpos: [28]; default: 1;
+         *  this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable
+         */
+        uint32_t raw_num_total_auto_reload:1;
+        /** dma_block_interval_en : R/W; bitpos: [29]; default: 1;
+         *  this bit configures enable of interval between dma block transfer, 0: disable, 1:
+         *  enable
+         */
+        uint32_t dma_block_interval_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} dsi_brg_dma_block_interval_reg_t;
+
+/** Type of dma_req_interval register
+ *  dsi bridge dma req interval control register
+ */
+typedef union {
+    struct {
+        /** dma_req_interval : R/W; bitpos: [15:0]; default: 1;
+         *  this field configures the interval between dma req events
+         */
+        uint32_t dma_req_interval:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_brg_dma_req_interval_reg_t;
+
+/** Type of dpi_lcd_ctl register
+ *  dsi bridge dpi signal control register
+ */
+typedef union {
+    struct {
+        /** dpishutdn : R/W; bitpos: [0]; default: 0;
+         *  this bit configures dpishutdn signal in dpi interface
+         */
+        uint32_t dpishutdn:1;
+        /** dpicolorm : R/W; bitpos: [1]; default: 0;
+         *  this bit configures dpicolorm signal in dpi interface
+         */
+        uint32_t dpicolorm:1;
+        /** dpiupdatecfg : R/W; bitpos: [2]; default: 0;
+         *  this bit configures dpiupdatecfg signal in dpi interface
+         */
+        uint32_t dpiupdatecfg:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dsi_brg_dpi_lcd_ctl_reg_t;
+
+/** Type of dpi_rsv_dpi_data register
+ *  dsi bridge dpi reserved data register
+ */
+typedef union {
+    struct {
+        /** dpi_rsv_data : R/W; bitpos: [29:0]; default: 16383;
+         *  this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow
+         */
+        uint32_t dpi_rsv_data:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} dsi_brg_dpi_rsv_dpi_data_reg_t;
+
+/** Type of dpi_v_cfg0 register
+ *  dsi bridge dpi v config register 0
+ */
+typedef union {
+    struct {
+        /** vtotal : R/W; bitpos: [11:0]; default: 525;
+         *  this field configures the total length of one frame (by line) for dpi output, must
+         *  meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank
+         */
+        uint32_t vtotal:12;
+        uint32_t reserved_12:4;
+        /** vdisp : R/W; bitpos: [27:16]; default: 480;
+         *  this field configures the length of valid line (by line) for dpi output
+         */
+        uint32_t vdisp:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dsi_brg_dpi_v_cfg0_reg_t;
+
+/** Type of dpi_v_cfg1 register
+ *  dsi bridge dpi v config register 1
+ */
+typedef union {
+    struct {
+        /** vbank : R/W; bitpos: [11:0]; default: 33;
+         *  this field configures the length between vsync and valid line (by line) for dpi
+         *  output
+         */
+        uint32_t vbank:12;
+        uint32_t reserved_12:4;
+        /** vsync : R/W; bitpos: [27:16]; default: 2;
+         *  this field configures the length of vsync (by line) for dpi output
+         */
+        uint32_t vsync:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dsi_brg_dpi_v_cfg1_reg_t;
+
+/** Type of dpi_h_cfg0 register
+ *  dsi bridge dpi h config register 0
+ */
+typedef union {
+    struct {
+        /** htotal : R/W; bitpos: [11:0]; default: 800;
+         *  this field configures the total length of one line (by pixel num) for dpi output,
+         *  must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank
+         */
+        uint32_t htotal:12;
+        uint32_t reserved_12:4;
+        /** hdisp : R/W; bitpos: [27:16]; default: 640;
+         *  this field configures the length of valid pixel data (by pixel num) for dpi output
+         */
+        uint32_t hdisp:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dsi_brg_dpi_h_cfg0_reg_t;
+
+/** Type of dpi_h_cfg1 register
+ *  dsi bridge dpi h config register 1
+ */
+typedef union {
+    struct {
+        /** hbank : R/W; bitpos: [11:0]; default: 48;
+         *  this field configures the length between hsync and pixel data valid (by pixel num)
+         *  for dpi output
+         */
+        uint32_t hbank:12;
+        uint32_t reserved_12:4;
+        /** hsync : R/W; bitpos: [27:16]; default: 96;
+         *  this field configures the length of hsync (by pixel num) for dpi output
+         */
+        uint32_t hsync:12;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dsi_brg_dpi_h_cfg1_reg_t;
+
+/** Type of dpi_misc_config register
+ *  dsi_bridge dpi misc config register
+ */
+typedef union {
+    struct {
+        /** dpi_en : R/W; bitpos: [0]; default: 0;
+         *  this bit configures enable of dpi output, 0: disable, 1: enable
+         */
+        uint32_t dpi_en:1;
+        uint32_t reserved_1:3;
+        /** fifo_underrun_discard_vcnt : R/W; bitpos: [15:4]; default: 413;
+         *  this field configures the underrun interrupt musk, when underrun occurs and line
+         *  cnt is less then this field
+         */
+        uint32_t fifo_underrun_discard_vcnt:12;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} dsi_brg_dpi_misc_config_reg_t;
+
+/** Type of dpi_config_update register
+ *  dsi_bridge dpi config update register
+ */
+typedef union {
+    struct {
+        /** dpi_config_update : WT; bitpos: [0]; default: 0;
+         *  write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_*
+         */
+        uint32_t dpi_config_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_dpi_config_update_reg_t;
+
+/** Type of host_trigger_rev register
+ *  dsi_bridge host trigger reverse control register
+ */
+typedef union {
+    struct {
+        /** tx_trigger_rev_en : R/W; bitpos: [0]; default: 0;
+         *  tx_trigger reverse. 0: disable, 1: enable
+         */
+        uint32_t tx_trigger_rev_en:1;
+        /** rx_trigger_rev_en : R/W; bitpos: [1]; default: 0;
+         *  rx_trigger reverse. 0: disable, 1: enable
+         */
+        uint32_t rx_trigger_rev_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_host_trigger_rev_reg_t;
+
+/** Type of blk_raw_num_cfg register
+ *  dsi_bridge block raw number control register
+ */
+typedef union {
+    struct {
+        /** blk_raw_num_total : R/W; bitpos: [21:0]; default: 230400;
+         *  this field configures number of total block pix bits/64
+         */
+        uint32_t blk_raw_num_total:22;
+        uint32_t reserved_22:9;
+        /** blk_raw_num_total_set : WT; bitpos: [31]; default: 0;
+         *  write 1 to reload reg_blk_raw_num_total to internal cnt
+         */
+        uint32_t blk_raw_num_total_set:1;
+    };
+    uint32_t val;
+} dsi_brg_blk_raw_num_cfg_reg_t;
+
+/** Type of dma_frame_interval register
+ *  dsi_bridge dam frame interval control register
+ */
+typedef union {
+    struct {
+        /** dma_frame_slot : R/W; bitpos: [9:0]; default: 9;
+         *  this field configures the max frame_slot_cnt
+         */
+        uint32_t dma_frame_slot:10;
+        /** dma_frame_interval : R/W; bitpos: [27:10]; default: 9;
+         *  this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1
+         *  when frame_slot_cnt if full
+         */
+        uint32_t dma_frame_interval:18;
+        /** dma_multiblk_en : R/W; bitpos: [28]; default: 0;
+         *  this bit configures enable multi-blk transfer, 0: disable, 1: enable
+         */
+        uint32_t dma_multiblk_en:1;
+        /** dma_frame_interval_en : R/W; bitpos: [29]; default: 1;
+         *  this bit configures enable interval between frame transfer, 0: disable, 1: enable
+         */
+        uint32_t dma_frame_interval_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} dsi_brg_dma_frame_interval_reg_t;
+
+/** Type of mem_aux_ctrl register
+ *  dsi_bridge mem aux control register
+ */
+typedef union {
+    struct {
+        /** dsi_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  this field configures dsi_bridge fifo memory aux ctrl
+         */
+        uint32_t dsi_mem_aux_ctrl:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dsi_brg_mem_aux_ctrl_reg_t;
+
+/** Type of rdn_eco_low register
+ *  dsi_bridge rdn eco all low register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  rdn_eco_low
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} dsi_brg_rdn_eco_low_reg_t;
+
+/** Type of rdn_eco_high register
+ *  dsi_bridge rdn eco all high register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  rdn_eco_high
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} dsi_brg_rdn_eco_high_reg_t;
+
+/** Type of host_ctrl register
+ *  dsi_bridge host control register
+ */
+typedef union {
+    struct {
+        /** dsi_cfg_ref_clk_en : R/W; bitpos: [0]; default: 1;
+         *  this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1:
+         *  enable
+         */
+        uint32_t dsi_cfg_ref_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_host_ctrl_reg_t;
+
+/** Type of mem_clk_ctrl register
+ *  dsi_bridge mem force on control register
+ */
+typedef union {
+    struct {
+        /** dsi_bridge_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1:
+         *  force on
+         */
+        uint32_t dsi_bridge_mem_clk_force_on:1;
+        /** dsi_mem_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on
+         */
+        uint32_t dsi_mem_clk_force_on:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_mem_clk_ctrl_reg_t;
+
+/** Type of dma_flow_ctrl register
+ *  dsi_bridge dma flow controller register
+ */
+typedef union {
+    struct {
+        /** dsi_dma_flow_controller : R/W; bitpos: [0]; default: 1;
+         *  this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge
+         *  as flow controller
+         */
+        uint32_t dsi_dma_flow_controller:1;
+        uint32_t reserved_1:3;
+        /** dma_flow_multiblk_num : R/W; bitpos: [7:4]; default: 1;
+         *  this field configures the num of blocks when multi-blk is enable and dmac as flow
+         *  controller
+         */
+        uint32_t dma_flow_multiblk_num:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} dsi_brg_dma_flow_ctrl_reg_t;
+
+/** Type of raw_buf_almost_empty_thrd register
+ *  dsi_bridge buffer empty threshold register
+ */
+typedef union {
+    struct {
+        /** dsi_raw_buf_almost_empty_thrd : R/W; bitpos: [10:0]; default: 512;
+         *  this field configures the fifo almost empty threshold, is valid only when dmac as
+         *  flow controller
+         */
+        uint32_t dsi_raw_buf_almost_empty_thrd:11;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} dsi_brg_raw_buf_almost_empty_thrd_reg_t;
+
+/** Type of yuv_cfg register
+ *  dsi_bridge yuv format config register
+ */
+typedef union {
+    struct {
+        /** protocol : R/W; bitpos: [0]; default: 0;
+         *  this bit configures yuv protocol, 0: bt.601, 1: bt.709
+         */
+        uint32_t protocol:1;
+        /** yuv_pix_endian : R/W; bitpos: [1]; default: 0;
+         *  this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0
+         */
+        uint32_t yuv_pix_endian:1;
+        /** yuv422_format : R/W; bitpos: [3:2]; default: 0;
+         *  this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy
+         */
+        uint32_t yuv422_format:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dsi_brg_yuv_cfg_reg_t;
+
+/** Type of phy_lp_loopback_ctrl register
+ *  dsi phy lp_loopback test ctrl
+ */
+typedef union {
+    struct {
+        /** phy_lp_txdataesc_1 : R/W; bitpos: [7:0]; default: 0;
+         *  txdataesc_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txdataesc_1:8;
+        /** phy_lp_txrequestesc_1 : R/W; bitpos: [8]; default: 0;
+         *  txrequestesc_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txrequestesc_1:1;
+        /** phy_lp_txvalidesc_1 : R/W; bitpos: [9]; default: 0;
+         *  txvalidesc_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txvalidesc_1:1;
+        /** phy_lp_txlpdtesc_1 : R/W; bitpos: [10]; default: 0;
+         *  txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txlpdtesc_1:1;
+        /** phy_lp_basedir_1 : R/W; bitpos: [11]; default: 0;
+         *  basedir_1 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_basedir_1:1;
+        uint32_t reserved_12:4;
+        /** phy_lp_txdataesc_0 : R/W; bitpos: [23:16]; default: 0;
+         *  txdataesc_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txdataesc_0:8;
+        /** phy_lp_txrequestesc_0 : R/W; bitpos: [24]; default: 0;
+         *  txrequestesc_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txrequestesc_0:1;
+        /** phy_lp_txvalidesc_0 : R/W; bitpos: [25]; default: 0;
+         *  txvalidesc_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txvalidesc_0:1;
+        /** phy_lp_txlpdtesc_0 : R/W; bitpos: [26]; default: 0;
+         *  txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_txlpdtesc_0:1;
+        /** phy_lp_basedir_0 : R/W; bitpos: [27]; default: 0;
+         *  basedir_0 ctrl when enable dsi phy lp_loopback_test
+         */
+        uint32_t phy_lp_basedir_0:1;
+        /** phy_lp_loopback_check : WT; bitpos: [28]; default: 0;
+         *  dsi phy lp_loopback test start check
+         */
+        uint32_t phy_lp_loopback_check:1;
+        /** phy_lp_loopback_check_done : RO; bitpos: [29]; default: 0;
+         *  dsi phy lp_loopback test check done
+         */
+        uint32_t phy_lp_loopback_check_done:1;
+        /** phy_lp_loopback_en : R/W; bitpos: [30]; default: 0;
+         *  dsi phy lp_loopback ctrl en
+         */
+        uint32_t phy_lp_loopback_en:1;
+        /** phy_lp_loopback_ok : RO; bitpos: [31]; default: 0;
+         *  result of dsi phy lp_loopback test
+         */
+        uint32_t phy_lp_loopback_ok:1;
+    };
+    uint32_t val;
+} dsi_brg_phy_lp_loopback_ctrl_reg_t;
+
+/** Type of phy_hs_loopback_ctrl register
+ *  dsi phy hp_loopback test ctrl
+ */
+typedef union {
+    struct {
+        /** phy_hs_txdatahs_1 : R/W; bitpos: [7:0]; default: 0;
+         *  txdatahs_1 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txdatahs_1:8;
+        /** phy_hs_txrequestdatahs_1 : R/W; bitpos: [8]; default: 0;
+         *  txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txrequestdatahs_1:1;
+        /** phy_hs_basedir_1 : R/W; bitpos: [9]; default: 1;
+         *  basedir_1 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_basedir_1:1;
+        uint32_t reserved_10:6;
+        /** phy_hs_txdatahs_0 : R/W; bitpos: [23:16]; default: 0;
+         *  txdatahs_0 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txdatahs_0:8;
+        /** phy_hs_txrequestdatahs_0 : R/W; bitpos: [24]; default: 0;
+         *  txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txrequestdatahs_0:1;
+        /** phy_hs_basedir_0 : R/W; bitpos: [25]; default: 0;
+         *  basedir_0 ctrl when enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_basedir_0:1;
+        uint32_t reserved_26:1;
+        /** phy_hs_txrequesthsclk : R/W; bitpos: [27]; default: 0;
+         *  txrequesthsclk when  enable dsi phy hs_loopback_test
+         */
+        uint32_t phy_hs_txrequesthsclk:1;
+        /** phy_hs_loopback_check : WT; bitpos: [28]; default: 0;
+         *  dsi phy hs_loopback test start check
+         */
+        uint32_t phy_hs_loopback_check:1;
+        /** phy_hs_loopback_check_done : RO; bitpos: [29]; default: 0;
+         *  dsi phy hs_loopback test check done
+         */
+        uint32_t phy_hs_loopback_check_done:1;
+        /** phy_hs_loopback_en : R/W; bitpos: [30]; default: 0;
+         *  dsi phy hs_loopback ctrl en
+         */
+        uint32_t phy_hs_loopback_en:1;
+        /** phy_hs_loopback_ok : RO; bitpos: [31]; default: 0;
+         *  result of dsi phy hs_loopback test
+         */
+        uint32_t phy_hs_loopback_ok:1;
+    };
+    uint32_t val;
+} dsi_brg_phy_hs_loopback_ctrl_reg_t;
+
+/** Type of phy_loopback_cnt register
+ *  loopback test cnt
+ */
+typedef union {
+    struct {
+        /** phy_hs_check_cnt_th : R/W; bitpos: [7:0]; default: 64;
+         *  hs_loopback test check cnt
+         */
+        uint32_t phy_hs_check_cnt_th:8;
+        uint32_t reserved_8:8;
+        /** phy_lp_check_cnt_th : R/W; bitpos: [23:16]; default: 64;
+         *  lp_loopback test check cnt
+         */
+        uint32_t phy_lp_check_cnt_th:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dsi_brg_phy_loopback_cnt_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of fifo_flow_status register
+ *  dsi bridge raw buffer depth register
+ */
+typedef union {
+    struct {
+        /** raw_buf_depth : RO; bitpos: [13:0]; default: 0;
+         *  this field configures the depth of dsi_bridge fifo depth
+         */
+        uint32_t raw_buf_depth:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dsi_brg_fifo_flow_status_reg_t;
+
+/** Type of host_bist_ctl register
+ *  dsi_bridge host bist control register
+ */
+typedef union {
+    struct {
+        /** bistok : RO; bitpos: [0]; default: 0;
+         *  bistok
+         */
+        uint32_t bistok:1;
+        /** biston : R/W; bitpos: [1]; default: 0;
+         *  biston
+         */
+        uint32_t biston:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_host_bist_ctl_reg_t;
+
+/** Type of rdn_eco_cs register
+ *  dsi_bridge rdn eco cs register
+ */
+typedef union {
+    struct {
+        /** rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  rdn_eco_en
+         */
+        uint32_t rdn_eco_en:1;
+        /** rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  rdn_eco_result
+         */
+        uint32_t rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dsi_brg_rdn_eco_cs_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_ena register
+ *  dsi_bridge interrupt enable register
+ */
+typedef union {
+    struct {
+        /** underrun_int_ena : R/W; bitpos: [0]; default: 0;
+         *  write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled
+         *  by dpi_underrun  interrupt signal
+         */
+        uint32_t underrun_int_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  dsi_bridge interrupt clear register
+ */
+typedef union {
+    struct {
+        /** underrun_int_clr : WT; bitpos: [0]; default: 0;
+         *  write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG
+         */
+        uint32_t underrun_int_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_int_clr_reg_t;
+
+/** Type of int_raw register
+ *  dsi_bridge raw interrupt register
+ */
+typedef union {
+    struct {
+        /** underrun_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  the raw interrupt status of dpi_underrun
+         */
+        uint32_t underrun_int_raw:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_int_raw_reg_t;
+
+/** Type of int_st register
+ *  dsi_bridge masked interrupt register
+ */
+typedef union {
+    struct {
+        /** underrun_int_st : RO; bitpos: [0]; default: 0;
+         *  the masked interrupt status of dpi_underrun
+         */
+        uint32_t underrun_int_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dsi_brg_int_st_reg_t;
+
+
+typedef struct dsi_brg_dev_t {
+    volatile dsi_brg_clk_en_reg_t clk_en;
+    volatile dsi_brg_en_reg_t en;
+    volatile dsi_brg_dma_req_cfg_reg_t dma_req_cfg;
+    volatile dsi_brg_raw_num_cfg_reg_t raw_num_cfg;
+    volatile dsi_brg_raw_buf_credit_ctl_reg_t raw_buf_credit_ctl;
+    volatile dsi_brg_fifo_flow_status_reg_t fifo_flow_status;
+    volatile dsi_brg_pixel_type_reg_t pixel_type;
+    volatile dsi_brg_dma_block_interval_reg_t dma_block_interval;
+    volatile dsi_brg_dma_req_interval_reg_t dma_req_interval;
+    volatile dsi_brg_dpi_lcd_ctl_reg_t dpi_lcd_ctl;
+    volatile dsi_brg_dpi_rsv_dpi_data_reg_t dpi_rsv_dpi_data;
+    uint32_t reserved_02c;
+    volatile dsi_brg_dpi_v_cfg0_reg_t dpi_v_cfg0;
+    volatile dsi_brg_dpi_v_cfg1_reg_t dpi_v_cfg1;
+    volatile dsi_brg_dpi_h_cfg0_reg_t dpi_h_cfg0;
+    volatile dsi_brg_dpi_h_cfg1_reg_t dpi_h_cfg1;
+    volatile dsi_brg_dpi_misc_config_reg_t dpi_misc_config;
+    volatile dsi_brg_dpi_config_update_reg_t dpi_config_update;
+    uint32_t reserved_048[2];
+    volatile dsi_brg_int_ena_reg_t int_ena;
+    volatile dsi_brg_int_clr_reg_t int_clr;
+    volatile dsi_brg_int_raw_reg_t int_raw;
+    volatile dsi_brg_int_st_reg_t int_st;
+    volatile dsi_brg_host_bist_ctl_reg_t host_bist_ctl;
+    volatile dsi_brg_host_trigger_rev_reg_t host_trigger_rev;
+    volatile dsi_brg_blk_raw_num_cfg_reg_t blk_raw_num_cfg;
+    volatile dsi_brg_dma_frame_interval_reg_t dma_frame_interval;
+    volatile dsi_brg_mem_aux_ctrl_reg_t mem_aux_ctrl;
+    volatile dsi_brg_rdn_eco_cs_reg_t rdn_eco_cs;
+    volatile dsi_brg_rdn_eco_low_reg_t rdn_eco_low;
+    volatile dsi_brg_rdn_eco_high_reg_t rdn_eco_high;
+    volatile dsi_brg_host_ctrl_reg_t host_ctrl;
+    volatile dsi_brg_mem_clk_ctrl_reg_t mem_clk_ctrl;
+    volatile dsi_brg_dma_flow_ctrl_reg_t dma_flow_ctrl;
+    volatile dsi_brg_raw_buf_almost_empty_thrd_reg_t raw_buf_almost_empty_thrd;
+    volatile dsi_brg_yuv_cfg_reg_t yuv_cfg;
+    volatile dsi_brg_phy_lp_loopback_ctrl_reg_t phy_lp_loopback_ctrl;
+    volatile dsi_brg_phy_hs_loopback_ctrl_reg_t phy_hs_loopback_ctrl;
+    volatile dsi_brg_phy_loopback_cnt_reg_t phy_loopback_cnt;
+} dsi_brg_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(dsi_brg_dev_t) == 0xa0, "Invalid size of dsi_brg_dev_t structure");
+#endif
+
+extern dsi_brg_dev_t MIPI_DSI_BRIDGE;
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/parl_io_reg.h

@@ -0,0 +1,495 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PARL_IO_RX_MODE_CFG_REG register
+ *  Parallel RX Sampling mode configuration register.
+ */
+#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_IO_BASE + 0x0)
+/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [24:21]; default: 7;
+ *  Configures rx external enable signal selection from IO PAD.
+ */
+#define PARL_IO_RX_EXT_EN_SEL    0x0000000FU
+#define PARL_IO_RX_EXT_EN_SEL_M  (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S)
+#define PARL_IO_RX_EXT_EN_SEL_V  0x0000000FU
+#define PARL_IO_RX_EXT_EN_SEL_S  21
+/** PARL_IO_RX_SW_EN : R/W; bitpos: [25]; default: 0;
+ *  Write 1 to enable data sampling by software.
+ */
+#define PARL_IO_RX_SW_EN    (BIT(25))
+#define PARL_IO_RX_SW_EN_M  (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S)
+#define PARL_IO_RX_SW_EN_V  0x00000001U
+#define PARL_IO_RX_SW_EN_S  25
+/** PARL_IO_RX_EXT_EN_INV : R/W; bitpos: [26]; default: 0;
+ *  Write 1 to invert the external enable signal.
+ */
+#define PARL_IO_RX_EXT_EN_INV    (BIT(26))
+#define PARL_IO_RX_EXT_EN_INV_M  (PARL_IO_RX_EXT_EN_INV_V << PARL_IO_RX_EXT_EN_INV_S)
+#define PARL_IO_RX_EXT_EN_INV_V  0x00000001U
+#define PARL_IO_RX_EXT_EN_INV_S  26
+/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [29:27]; default: 0;
+ *  Configures the rxd pulse sampling submode.
+ *  0: positive pulse start(data bit included) &&  positive pulse end(data bit included)
+ *  1: positive pulse start(data bit included) && positive pulse end (data bit excluded)
+ *  2: positive pulse start(data bit excluded) && positive pulse end (data bit included)
+ *  3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded)
+ *  4: positive pulse start(data bit included) && length end
+ *  5: positive pulse start(data bit excluded) && length end
+ */
+#define PARL_IO_RX_PULSE_SUBMODE_SEL    0x00000007U
+#define PARL_IO_RX_PULSE_SUBMODE_SEL_M  (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S)
+#define PARL_IO_RX_PULSE_SUBMODE_SEL_V  0x00000007U
+#define PARL_IO_RX_PULSE_SUBMODE_SEL_S  27
+/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [31:30]; default: 0;
+ *  Configures the rxd sampling mode.
+ *  0: external level enable mode
+ *  1: external pulse enable mode
+ *  2: internal software enable mode
+ */
+#define PARL_IO_RX_SMP_MODE_SEL    0x00000003U
+#define PARL_IO_RX_SMP_MODE_SEL_M  (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S)
+#define PARL_IO_RX_SMP_MODE_SEL_V  0x00000003U
+#define PARL_IO_RX_SMP_MODE_SEL_S  30
+
+/** PARL_IO_RX_DATA_CFG_REG register
+ *  Parallel RX data configuration register.
+ */
+#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x4)
+/** PARL_IO_RX_BITLEN : R/W; bitpos: [27:9]; default: 0;
+ *  Configures expected byte number of received data.
+ */
+#define PARL_IO_RX_BITLEN    0x0007FFFFU
+#define PARL_IO_RX_BITLEN_M  (PARL_IO_RX_BITLEN_V << PARL_IO_RX_BITLEN_S)
+#define PARL_IO_RX_BITLEN_V  0x0007FFFFU
+#define PARL_IO_RX_BITLEN_S  9
+/** PARL_IO_RX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
+ *  Write 1 to invert bit order of one byte sent from RX_FIFO to DMA.
+ */
+#define PARL_IO_RX_DATA_ORDER_INV    (BIT(28))
+#define PARL_IO_RX_DATA_ORDER_INV_M  (PARL_IO_RX_DATA_ORDER_INV_V << PARL_IO_RX_DATA_ORDER_INV_S)
+#define PARL_IO_RX_DATA_ORDER_INV_V  0x00000001U
+#define PARL_IO_RX_DATA_ORDER_INV_S  28
+/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
+ *  Configures the rxd bus width.
+ *  0: bus width is 1.
+ *  1: bus width is 2.
+ *  2: bus width is 4.
+ *  3: bus width is 8.
+ */
+#define PARL_IO_RX_BUS_WID_SEL    0x00000007U
+#define PARL_IO_RX_BUS_WID_SEL_M  (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S)
+#define PARL_IO_RX_BUS_WID_SEL_V  0x00000007U
+#define PARL_IO_RX_BUS_WID_SEL_S  29
+
+/** PARL_IO_RX_GENRL_CFG_REG register
+ *  Parallel RX general configuration register.
+ */
+#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x8)
+/** PARL_IO_RX_GATING_EN : R/W; bitpos: [12]; default: 0;
+ *  Write 1 to enable the clock gating of output rx clock.
+ */
+#define PARL_IO_RX_GATING_EN    (BIT(12))
+#define PARL_IO_RX_GATING_EN_M  (PARL_IO_RX_GATING_EN_V << PARL_IO_RX_GATING_EN_S)
+#define PARL_IO_RX_GATING_EN_V  0x00000001U
+#define PARL_IO_RX_GATING_EN_S  12
+/** PARL_IO_RX_TIMEOUT_THRES : R/W; bitpos: [28:13]; default: 4095;
+ *  Configures threshold of timeout counter.
+ */
+#define PARL_IO_RX_TIMEOUT_THRES    0x0000FFFFU
+#define PARL_IO_RX_TIMEOUT_THRES_M  (PARL_IO_RX_TIMEOUT_THRES_V << PARL_IO_RX_TIMEOUT_THRES_S)
+#define PARL_IO_RX_TIMEOUT_THRES_V  0x0000FFFFU
+#define PARL_IO_RX_TIMEOUT_THRES_S  13
+/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [29]; default: 1;
+ *  Write 1 to enable timeout function to generate error eof.
+ */
+#define PARL_IO_RX_TIMEOUT_EN    (BIT(29))
+#define PARL_IO_RX_TIMEOUT_EN_M  (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S)
+#define PARL_IO_RX_TIMEOUT_EN_V  0x00000001U
+#define PARL_IO_RX_TIMEOUT_EN_S  29
+/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [30]; default: 0;
+ *  Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
+ *  1'b1: eof generated by external enable signal.
+ */
+#define PARL_IO_RX_EOF_GEN_SEL    (BIT(30))
+#define PARL_IO_RX_EOF_GEN_SEL_M  (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S)
+#define PARL_IO_RX_EOF_GEN_SEL_V  0x00000001U
+#define PARL_IO_RX_EOF_GEN_SEL_S  30
+
+/** PARL_IO_RX_START_CFG_REG register
+ *  Parallel RX Start configuration register.
+ */
+#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0xc)
+/** PARL_IO_RX_START : R/W; bitpos: [31]; default: 0;
+ *  Write 1 to start rx data sampling.
+ */
+#define PARL_IO_RX_START    (BIT(31))
+#define PARL_IO_RX_START_M  (PARL_IO_RX_START_V << PARL_IO_RX_START_S)
+#define PARL_IO_RX_START_V  0x00000001U
+#define PARL_IO_RX_START_S  31
+
+/** PARL_IO_TX_DATA_CFG_REG register
+ *  Parallel TX data configuration register.
+ */
+#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x10)
+/** PARL_IO_TX_BITLEN : R/W; bitpos: [27:9]; default: 0;
+ *  Configures expected byte number of sent data.
+ */
+#define PARL_IO_TX_BITLEN    0x0007FFFFU
+#define PARL_IO_TX_BITLEN_M  (PARL_IO_TX_BITLEN_V << PARL_IO_TX_BITLEN_S)
+#define PARL_IO_TX_BITLEN_V  0x0007FFFFU
+#define PARL_IO_TX_BITLEN_S  9
+/** PARL_IO_TX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
+ *  Write 1 to invert bit order of one byte sent from TX_FIFO to IO data.
+ */
+#define PARL_IO_TX_DATA_ORDER_INV    (BIT(28))
+#define PARL_IO_TX_DATA_ORDER_INV_M  (PARL_IO_TX_DATA_ORDER_INV_V << PARL_IO_TX_DATA_ORDER_INV_S)
+#define PARL_IO_TX_DATA_ORDER_INV_V  0x00000001U
+#define PARL_IO_TX_DATA_ORDER_INV_S  28
+/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
+ *  Configures the txd bus width.
+ *  0: bus width is 1.
+ *  1: bus width is 2.
+ *  2: bus width is 4.
+ *  3: bus width is 8.
+ */
+#define PARL_IO_TX_BUS_WID_SEL    0x00000007U
+#define PARL_IO_TX_BUS_WID_SEL_M  (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S)
+#define PARL_IO_TX_BUS_WID_SEL_V  0x00000007U
+#define PARL_IO_TX_BUS_WID_SEL_S  29
+
+/** PARL_IO_TX_START_CFG_REG register
+ *  Parallel TX Start configuration register.
+ */
+#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0x14)
+/** PARL_IO_TX_START : R/W; bitpos: [31]; default: 0;
+ *  Write 1 to start tx data transmit.
+ */
+#define PARL_IO_TX_START    (BIT(31))
+#define PARL_IO_TX_START_M  (PARL_IO_TX_START_V << PARL_IO_TX_START_S)
+#define PARL_IO_TX_START_V  0x00000001U
+#define PARL_IO_TX_START_S  31
+
+/** PARL_IO_TX_GENRL_CFG_REG register
+ *  Parallel TX general configuration register.
+ */
+#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x18)
+/** PARL_IO_TX_EOF_GEN_SEL : R/W; bitpos: [13]; default: 0;
+ *  Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
+ *  1'b1: eof generated by DMA eof.
+ */
+#define PARL_IO_TX_EOF_GEN_SEL    (BIT(13))
+#define PARL_IO_TX_EOF_GEN_SEL_M  (PARL_IO_TX_EOF_GEN_SEL_V << PARL_IO_TX_EOF_GEN_SEL_S)
+#define PARL_IO_TX_EOF_GEN_SEL_V  0x00000001U
+#define PARL_IO_TX_EOF_GEN_SEL_S  13
+/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [29:14]; default: 0;
+ *  Configures bus value of transmitter in IDLE state.
+ */
+#define PARL_IO_TX_IDLE_VALUE    0x0000FFFFU
+#define PARL_IO_TX_IDLE_VALUE_M  (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S)
+#define PARL_IO_TX_IDLE_VALUE_V  0x0000FFFFU
+#define PARL_IO_TX_IDLE_VALUE_S  14
+/** PARL_IO_TX_GATING_EN : R/W; bitpos: [30]; default: 0;
+ *  Write 1 to enable the clock gating of output tx clock.
+ */
+#define PARL_IO_TX_GATING_EN    (BIT(30))
+#define PARL_IO_TX_GATING_EN_M  (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S)
+#define PARL_IO_TX_GATING_EN_V  0x00000001U
+#define PARL_IO_TX_GATING_EN_S  30
+/** PARL_IO_TX_VALID_OUTPUT_EN : R/W; bitpos: [31]; default: 0;
+ *  Write 1 to enable the output of tx data valid signal.
+ */
+#define PARL_IO_TX_VALID_OUTPUT_EN    (BIT(31))
+#define PARL_IO_TX_VALID_OUTPUT_EN_M  (PARL_IO_TX_VALID_OUTPUT_EN_V << PARL_IO_TX_VALID_OUTPUT_EN_S)
+#define PARL_IO_TX_VALID_OUTPUT_EN_V  0x00000001U
+#define PARL_IO_TX_VALID_OUTPUT_EN_S  31
+
+/** PARL_IO_FIFO_CFG_REG register
+ *  Parallel IO FIFO configuration register.
+ */
+#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_IO_BASE + 0x1c)
+/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0;
+ *  Write 1 to reset async fifo in tx module.
+ */
+#define PARL_IO_TX_FIFO_SRST    (BIT(30))
+#define PARL_IO_TX_FIFO_SRST_M  (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S)
+#define PARL_IO_TX_FIFO_SRST_V  0x00000001U
+#define PARL_IO_TX_FIFO_SRST_S  30
+/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0;
+ *  Write 1 to reset async fifo in rx module.
+ */
+#define PARL_IO_RX_FIFO_SRST    (BIT(31))
+#define PARL_IO_RX_FIFO_SRST_M  (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S)
+#define PARL_IO_RX_FIFO_SRST_V  0x00000001U
+#define PARL_IO_RX_FIFO_SRST_S  31
+
+/** PARL_IO_REG_UPDATE_REG register
+ *  Parallel IO FIFO configuration register.
+ */
+#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_IO_BASE + 0x20)
+/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [31]; default: 0;
+ *  Write 1 to update rx register configuration.
+ */
+#define PARL_IO_RX_REG_UPDATE    (BIT(31))
+#define PARL_IO_RX_REG_UPDATE_M  (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S)
+#define PARL_IO_RX_REG_UPDATE_V  0x00000001U
+#define PARL_IO_RX_REG_UPDATE_S  31
+
+/** PARL_IO_ST_REG register
+ *  Parallel IO module status register0.
+ */
+#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x24)
+/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0;
+ *  Represents the status that tx is ready to transmit.
+ */
+#define PARL_IO_TX_READY    (BIT(31))
+#define PARL_IO_TX_READY_M  (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S)
+#define PARL_IO_TX_READY_V  0x00000001U
+#define PARL_IO_TX_READY_S  31
+
+/** PARL_IO_INT_ENA_REG register
+ *  Parallel IO interrupt enable signal configuration register.
+ */
+#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28)
+/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable TX_FIFO_REMPTY_INT.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M  (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S  0
+/** PARL_IO_RX_FIFO_WOVF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable RX_FIFO_WOVF_INT.
+ */
+#define PARL_IO_RX_FIFO_WOVF_INT_ENA    (BIT(1))
+#define PARL_IO_RX_FIFO_WOVF_INT_ENA_M  (PARL_IO_RX_FIFO_WOVF_INT_ENA_V << PARL_IO_RX_FIFO_WOVF_INT_ENA_S)
+#define PARL_IO_RX_FIFO_WOVF_INT_ENA_V  0x00000001U
+#define PARL_IO_RX_FIFO_WOVF_INT_ENA_S  1
+/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable TX_EOF_INT.
+ */
+#define PARL_IO_TX_EOF_INT_ENA    (BIT(2))
+#define PARL_IO_TX_EOF_INT_ENA_M  (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S)
+#define PARL_IO_TX_EOF_INT_ENA_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_ENA_S  2
+
+/** PARL_IO_INT_RAW_REG register
+ *  Parallel IO interrupt raw signal status register.
+ */
+#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c)
+/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw interrupt status of TX_FIFO_REMPTY_INT.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M  (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S  0
+/** PARL_IO_RX_FIFO_WOVF_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  The raw interrupt status of RX_FIFO_WOVF_INT.
+ */
+#define PARL_IO_RX_FIFO_WOVF_INT_RAW    (BIT(1))
+#define PARL_IO_RX_FIFO_WOVF_INT_RAW_M  (PARL_IO_RX_FIFO_WOVF_INT_RAW_V << PARL_IO_RX_FIFO_WOVF_INT_RAW_S)
+#define PARL_IO_RX_FIFO_WOVF_INT_RAW_V  0x00000001U
+#define PARL_IO_RX_FIFO_WOVF_INT_RAW_S  1
+/** PARL_IO_TX_EOF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
+ *  The raw interrupt status of TX_EOF_INT.
+ */
+#define PARL_IO_TX_EOF_INT_RAW    (BIT(2))
+#define PARL_IO_TX_EOF_INT_RAW_M  (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S)
+#define PARL_IO_TX_EOF_INT_RAW_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_RAW_S  2
+
+/** PARL_IO_INT_ST_REG register
+ *  Parallel IO interrupt signal status register.
+ */
+#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30)
+/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of TX_FIFO_REMPTY_INT.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M  (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S  0
+/** PARL_IO_RX_FIFO_WOVF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of RX_FIFO_WOVF_INT.
+ */
+#define PARL_IO_RX_FIFO_WOVF_INT_ST    (BIT(1))
+#define PARL_IO_RX_FIFO_WOVF_INT_ST_M  (PARL_IO_RX_FIFO_WOVF_INT_ST_V << PARL_IO_RX_FIFO_WOVF_INT_ST_S)
+#define PARL_IO_RX_FIFO_WOVF_INT_ST_V  0x00000001U
+#define PARL_IO_RX_FIFO_WOVF_INT_ST_S  1
+/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of TX_EOF_INT.
+ */
+#define PARL_IO_TX_EOF_INT_ST    (BIT(2))
+#define PARL_IO_TX_EOF_INT_ST_M  (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S)
+#define PARL_IO_TX_EOF_INT_ST_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_ST_S  2
+
+/** PARL_IO_INT_CLR_REG register
+ *  Parallel IO interrupt  clear signal configuration register.
+ */
+#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34)
+/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear TX_FIFO_REMPTY_INT.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M  (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S  0
+/** PARL_IO_RX_FIFO_WOVF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear RX_FIFO_WOVF_INT.
+ */
+#define PARL_IO_RX_FIFO_WOVF_INT_CLR    (BIT(1))
+#define PARL_IO_RX_FIFO_WOVF_INT_CLR_M  (PARL_IO_RX_FIFO_WOVF_INT_CLR_V << PARL_IO_RX_FIFO_WOVF_INT_CLR_S)
+#define PARL_IO_RX_FIFO_WOVF_INT_CLR_V  0x00000001U
+#define PARL_IO_RX_FIFO_WOVF_INT_CLR_S  1
+/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear TX_EOF_INT.
+ */
+#define PARL_IO_TX_EOF_INT_CLR    (BIT(2))
+#define PARL_IO_TX_EOF_INT_CLR_M  (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S)
+#define PARL_IO_TX_EOF_INT_CLR_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_CLR_S  2
+
+/** PARL_IO_RX_ST0_REG register
+ *  Parallel IO RX status register0
+ */
+#define PARL_IO_RX_ST0_REG (DR_REG_PARL_IO_BASE + 0x38)
+/** PARL_IO_RX_CNT : RO; bitpos: [12:8]; default: 0;
+ *  Indicates the cycle number of reading Rx FIFO.
+ */
+#define PARL_IO_RX_CNT    0x0000001FU
+#define PARL_IO_RX_CNT_M  (PARL_IO_RX_CNT_V << PARL_IO_RX_CNT_S)
+#define PARL_IO_RX_CNT_V  0x0000001FU
+#define PARL_IO_RX_CNT_S  8
+/** PARL_IO_RX_FIFO_WR_BIT_CNT : RO; bitpos: [31:13]; default: 0;
+ *  Indicates the current written bit number into Rx FIFO.
+ */
+#define PARL_IO_RX_FIFO_WR_BIT_CNT    0x0007FFFFU
+#define PARL_IO_RX_FIFO_WR_BIT_CNT_M  (PARL_IO_RX_FIFO_WR_BIT_CNT_V << PARL_IO_RX_FIFO_WR_BIT_CNT_S)
+#define PARL_IO_RX_FIFO_WR_BIT_CNT_V  0x0007FFFFU
+#define PARL_IO_RX_FIFO_WR_BIT_CNT_S  13
+
+/** PARL_IO_RX_ST1_REG register
+ *  Parallel IO RX status register1
+ */
+#define PARL_IO_RX_ST1_REG (DR_REG_PARL_IO_BASE + 0x3c)
+/** PARL_IO_RX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
+ *  Indicates the current read bit number from Rx FIFO.
+ */
+#define PARL_IO_RX_FIFO_RD_BIT_CNT    0x0007FFFFU
+#define PARL_IO_RX_FIFO_RD_BIT_CNT_M  (PARL_IO_RX_FIFO_RD_BIT_CNT_V << PARL_IO_RX_FIFO_RD_BIT_CNT_S)
+#define PARL_IO_RX_FIFO_RD_BIT_CNT_V  0x0007FFFFU
+#define PARL_IO_RX_FIFO_RD_BIT_CNT_S  13
+
+/** PARL_IO_TX_ST0_REG register
+ *  Parallel IO TX status register0
+ */
+#define PARL_IO_TX_ST0_REG (DR_REG_PARL_IO_BASE + 0x40)
+/** PARL_IO_TX_CNT : RO; bitpos: [12:6]; default: 0;
+ *  Indicates the cycle number of reading Tx FIFO.
+ */
+#define PARL_IO_TX_CNT    0x0000007FU
+#define PARL_IO_TX_CNT_M  (PARL_IO_TX_CNT_V << PARL_IO_TX_CNT_S)
+#define PARL_IO_TX_CNT_V  0x0000007FU
+#define PARL_IO_TX_CNT_S  6
+/** PARL_IO_TX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
+ *  Indicates the current read bit number from Tx FIFO.
+ */
+#define PARL_IO_TX_FIFO_RD_BIT_CNT    0x0007FFFFU
+#define PARL_IO_TX_FIFO_RD_BIT_CNT_M  (PARL_IO_TX_FIFO_RD_BIT_CNT_V << PARL_IO_TX_FIFO_RD_BIT_CNT_S)
+#define PARL_IO_TX_FIFO_RD_BIT_CNT_V  0x0007FFFFU
+#define PARL_IO_TX_FIFO_RD_BIT_CNT_S  13
+
+/** PARL_IO_RX_CLK_CFG_REG register
+ *  Parallel IO RX clk configuration register
+ */
+#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x44)
+/** PARL_IO_RX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
+ *  Write 1 to invert the input Rx core clock.
+ */
+#define PARL_IO_RX_CLK_I_INV    (BIT(30))
+#define PARL_IO_RX_CLK_I_INV_M  (PARL_IO_RX_CLK_I_INV_V << PARL_IO_RX_CLK_I_INV_S)
+#define PARL_IO_RX_CLK_I_INV_V  0x00000001U
+#define PARL_IO_RX_CLK_I_INV_S  30
+/** PARL_IO_RX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
+ *  Write 1 to invert the output Rx core clock.
+ */
+#define PARL_IO_RX_CLK_O_INV    (BIT(31))
+#define PARL_IO_RX_CLK_O_INV_M  (PARL_IO_RX_CLK_O_INV_V << PARL_IO_RX_CLK_O_INV_S)
+#define PARL_IO_RX_CLK_O_INV_V  0x00000001U
+#define PARL_IO_RX_CLK_O_INV_S  31
+
+/** PARL_IO_TX_CLK_CFG_REG register
+ *  Parallel IO TX clk configuration register
+ */
+#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x48)
+/** PARL_IO_TX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
+ *  Write 1 to invert the input Tx core clock.
+ */
+#define PARL_IO_TX_CLK_I_INV    (BIT(30))
+#define PARL_IO_TX_CLK_I_INV_M  (PARL_IO_TX_CLK_I_INV_V << PARL_IO_TX_CLK_I_INV_S)
+#define PARL_IO_TX_CLK_I_INV_V  0x00000001U
+#define PARL_IO_TX_CLK_I_INV_S  30
+/** PARL_IO_TX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
+ *  Write 1 to invert the output Tx core clock.
+ */
+#define PARL_IO_TX_CLK_O_INV    (BIT(31))
+#define PARL_IO_TX_CLK_O_INV_M  (PARL_IO_TX_CLK_O_INV_V << PARL_IO_TX_CLK_O_INV_S)
+#define PARL_IO_TX_CLK_O_INV_V  0x00000001U
+#define PARL_IO_TX_CLK_O_INV_S  31
+
+/** PARL_IO_TX_CS_CFG_REG register
+ *  Parallel IO tx_cs_o generate configuration
+ */
+#define PARL_IO_TX_CS_CFG_REG (DR_REG_PARL_IO_BASE + 0x4c)
+/** PARL_IO_TX_CS_STOP_DELAY : R/W; bitpos: [15:0]; default: 0;
+ *  configure the delay between data tx end and tx_cs_o posedge
+ */
+#define PARL_IO_TX_CS_STOP_DELAY    0x0000FFFFU
+#define PARL_IO_TX_CS_STOP_DELAY_M  (PARL_IO_TX_CS_STOP_DELAY_V << PARL_IO_TX_CS_STOP_DELAY_S)
+#define PARL_IO_TX_CS_STOP_DELAY_V  0x0000FFFFU
+#define PARL_IO_TX_CS_STOP_DELAY_S  0
+/** PARL_IO_TX_CS_START_DELAY : R/W; bitpos: [31:16]; default: 0;
+ *  configure the delay between tx_cs_o negedge and data tx start
+ */
+#define PARL_IO_TX_CS_START_DELAY    0x0000FFFFU
+#define PARL_IO_TX_CS_START_DELAY_M  (PARL_IO_TX_CS_START_DELAY_V << PARL_IO_TX_CS_START_DELAY_S)
+#define PARL_IO_TX_CS_START_DELAY_V  0x0000FFFFU
+#define PARL_IO_TX_CS_START_DELAY_S  16
+
+/** PARL_IO_CLK_REG register
+ *  Parallel IO clk configuration register
+ */
+#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120)
+/** PARL_IO_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Force clock on for this register file
+ */
+#define PARL_IO_CLK_EN    (BIT(31))
+#define PARL_IO_CLK_EN_M  (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S)
+#define PARL_IO_CLK_EN_V  0x00000001U
+#define PARL_IO_CLK_EN_S  31
+
+/** PARL_IO_VERSION_REG register
+ *  Version register.
+ */
+#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc)
+/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 37786160;
+ *  Version of this register file
+ */
+#define PARL_IO_DATE    0x0FFFFFFFU
+#define PARL_IO_DATE_M  (PARL_IO_DATE_V << PARL_IO_DATE_S)
+#define PARL_IO_DATE_V  0x0FFFFFFFU
+#define PARL_IO_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/parl_io_struct.h

@@ -0,0 +1,525 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: PARL_IO RX  Mode Configuration */
+/** Type of rx_mode_cfg register
+ *  Parallel RX Sampling mode configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** rx_ext_en_sel : R/W; bitpos: [24:21]; default: 7;
+         *  Configures rx external enable signal selection from IO PAD.
+         */
+        uint32_t rx_ext_en_sel:4;
+        /** rx_sw_en : R/W; bitpos: [25]; default: 0;
+         *  Write 1 to enable data sampling by software.
+         */
+        uint32_t rx_sw_en:1;
+        /** rx_ext_en_inv : R/W; bitpos: [26]; default: 0;
+         *  Write 1 to invert the external enable signal.
+         */
+        uint32_t rx_ext_en_inv:1;
+        /** rx_pulse_submode_sel : R/W; bitpos: [29:27]; default: 0;
+         *  Configures the rxd pulse sampling submode.
+         *  0: positive pulse start(data bit included) &&  positive pulse end(data bit included)
+         *  1: positive pulse start(data bit included) && positive pulse end (data bit excluded)
+         *  2: positive pulse start(data bit excluded) && positive pulse end (data bit included)
+         *  3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded)
+         *  4: positive pulse start(data bit included) && length end
+         *  5: positive pulse start(data bit excluded) && length end
+         */
+        uint32_t rx_pulse_submode_sel:3;
+        /** rx_smp_mode_sel : R/W; bitpos: [31:30]; default: 0;
+         *  Configures the rxd sampling mode.
+         *  0: external level enable mode
+         *  1: external pulse enable mode
+         *  2: internal software enable mode
+         */
+        uint32_t rx_smp_mode_sel:2;
+    };
+    uint32_t val;
+} parl_io_rx_mode_cfg_reg_t;
+
+
+/** Group: PARL_IO RX Data Configuration */
+/** Type of rx_data_cfg register
+ *  Parallel RX data configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:9;
+        /** rx_bitlen : R/W; bitpos: [27:9]; default: 0;
+         *  Configures expected byte number of received data.
+         */
+        uint32_t rx_bitlen:19;
+        /** rx_data_order_inv : R/W; bitpos: [28]; default: 0;
+         *  Write 1 to invert bit order of one byte sent from RX_FIFO to DMA.
+         */
+        uint32_t rx_data_order_inv:1;
+        /** rx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
+         *  Configures the rxd bus width.
+         *  0: bus width is 1.
+         *  1: bus width is 2.
+         *  2: bus width is 4.
+         *  3: bus width is 8.
+         */
+        uint32_t rx_bus_wid_sel:3;
+    };
+    uint32_t val;
+} parl_io_rx_data_cfg_reg_t;
+
+
+/** Group: PARL_IO RX General Configuration */
+/** Type of rx_genrl_cfg register
+ *  Parallel RX general configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** rx_gating_en : R/W; bitpos: [12]; default: 0;
+         *  Write 1 to enable the clock gating of output rx clock.
+         */
+        uint32_t rx_gating_en:1;
+        /** rx_timeout_thres : R/W; bitpos: [28:13]; default: 4095;
+         *  Configures threshold of timeout counter.
+         */
+        uint32_t rx_timeout_thres:16;
+        /** rx_timeout_en : R/W; bitpos: [29]; default: 1;
+         *  Write 1 to enable timeout function to generate error eof.
+         */
+        uint32_t rx_timeout_en:1;
+        /** rx_eof_gen_sel : R/W; bitpos: [30]; default: 0;
+         *  Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
+         *  1'b1: eof generated by external enable signal.
+         */
+        uint32_t rx_eof_gen_sel:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} parl_io_rx_genrl_cfg_reg_t;
+
+
+/** Group: PARL_IO RX Start Configuration */
+/** Type of rx_start_cfg register
+ *  Parallel RX Start configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** rx_start : R/W; bitpos: [31]; default: 0;
+         *  Write 1 to start rx data sampling.
+         */
+        uint32_t rx_start:1;
+    };
+    uint32_t val;
+} parl_io_rx_start_cfg_reg_t;
+
+
+/** Group: PARL_IO TX Data Configuration */
+/** Type of tx_data_cfg register
+ *  Parallel TX data configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:9;
+        /** tx_bitlen : R/W; bitpos: [27:9]; default: 0;
+         *  Configures expected byte number of sent data.
+         */
+        uint32_t tx_bitlen:19;
+        /** tx_data_order_inv : R/W; bitpos: [28]; default: 0;
+         *  Write 1 to invert bit order of one byte sent from TX_FIFO to IO data.
+         */
+        uint32_t tx_data_order_inv:1;
+        /** tx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
+         *  Configures the txd bus width.
+         *  0: bus width is 1.
+         *  1: bus width is 2.
+         *  2: bus width is 4.
+         *  3: bus width is 8.
+         */
+        uint32_t tx_bus_wid_sel:3;
+    };
+    uint32_t val;
+} parl_io_tx_data_cfg_reg_t;
+
+
+/** Group: PARL_IO TX Start Configuration */
+/** Type of tx_start_cfg register
+ *  Parallel TX Start configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tx_start : R/W; bitpos: [31]; default: 0;
+         *  Write 1 to start tx data transmit.
+         */
+        uint32_t tx_start:1;
+    };
+    uint32_t val;
+} parl_io_tx_start_cfg_reg_t;
+
+
+/** Group: PARL_IO TX General Configuration */
+/** Type of tx_genrl_cfg register
+ *  Parallel TX general configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:13;
+        /** tx_eof_gen_sel : R/W; bitpos: [13]; default: 0;
+         *  Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
+         *  1'b1: eof generated by DMA eof.
+         */
+        uint32_t tx_eof_gen_sel:1;
+        /** tx_idle_value : R/W; bitpos: [29:14]; default: 0;
+         *  Configures bus value of transmitter in IDLE state.
+         */
+        uint32_t tx_idle_value:16;
+        /** tx_gating_en : R/W; bitpos: [30]; default: 0;
+         *  Write 1 to enable the clock gating of output tx clock.
+         */
+        uint32_t tx_gating_en:1;
+        /** tx_valid_output_en : R/W; bitpos: [31]; default: 0;
+         *  Write 1 to enable the output of tx data valid signal.
+         */
+        uint32_t tx_valid_output_en:1;
+    };
+    uint32_t val;
+} parl_io_tx_genrl_cfg_reg_t;
+
+
+/** Group: PARL_IO FIFO Configuration */
+/** Type of fifo_cfg register
+ *  Parallel IO FIFO configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** tx_fifo_srst : R/W; bitpos: [30]; default: 0;
+         *  Write 1 to reset async fifo in tx module.
+         */
+        uint32_t tx_fifo_srst:1;
+        /** rx_fifo_srst : R/W; bitpos: [31]; default: 0;
+         *  Write 1 to reset async fifo in rx module.
+         */
+        uint32_t rx_fifo_srst:1;
+    };
+    uint32_t val;
+} parl_io_fifo_cfg_reg_t;
+
+
+/** Group: PARL_IO Register Update Configuration */
+/** Type of reg_update register
+ *  Parallel IO FIFO configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** rx_reg_update : WT; bitpos: [31]; default: 0;
+         *  Write 1 to update rx register configuration.
+         */
+        uint32_t rx_reg_update:1;
+    };
+    uint32_t val;
+} parl_io_reg_update_reg_t;
+
+
+/** Group: PARL_IO Status */
+/** Type of st register
+ *  Parallel IO module status register0.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tx_ready : RO; bitpos: [31]; default: 0;
+         *  Represents the status that tx is ready to transmit.
+         */
+        uint32_t tx_ready:1;
+    };
+    uint32_t val;
+} parl_io_st_reg_t;
+
+
+/** Group: PARL_IO Interrupt Configuration and Status */
+/** Type of int_ena register
+ *  Parallel IO interrupt enable signal configuration register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable TX_FIFO_REMPTY_INT.
+         */
+        uint32_t tx_fifo_rempty_int_ena:1;
+        /** rx_fifo_wovf_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable RX_FIFO_WOVF_INT.
+         */
+        uint32_t rx_fifo_wovf_int_ena:1;
+        /** tx_eof_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable TX_EOF_INT.
+         */
+        uint32_t tx_eof_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  Parallel IO interrupt raw signal status register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw interrupt status of TX_FIFO_REMPTY_INT.
+         */
+        uint32_t tx_fifo_rempty_int_raw:1;
+        /** rx_fifo_wovf_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw interrupt status of RX_FIFO_WOVF_INT.
+         */
+        uint32_t rx_fifo_wovf_int_raw:1;
+        /** tx_eof_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  The raw interrupt status of TX_EOF_INT.
+         */
+        uint32_t tx_eof_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Parallel IO interrupt signal status register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of TX_FIFO_REMPTY_INT.
+         */
+        uint32_t tx_fifo_rempty_int_st:1;
+        /** rx_fifo_wovf_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of RX_FIFO_WOVF_INT.
+         */
+        uint32_t rx_fifo_wovf_int_st:1;
+        /** tx_eof_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of TX_EOF_INT.
+         */
+        uint32_t tx_eof_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_st_reg_t;
+
+/** Type of int_clr register
+ *  Parallel IO interrupt  clear signal configuration register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear TX_FIFO_REMPTY_INT.
+         */
+        uint32_t tx_fifo_rempty_int_clr:1;
+        /** rx_fifo_wovf_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear RX_FIFO_WOVF_INT.
+         */
+        uint32_t rx_fifo_wovf_int_clr:1;
+        /** tx_eof_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear TX_EOF_INT.
+         */
+        uint32_t tx_eof_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_clr_reg_t;
+
+
+/** Group: PARL_IO Rx Status0 */
+/** Type of rx_st0 register
+ *  Parallel IO RX status register0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** rx_cnt : RO; bitpos: [12:8]; default: 0;
+         *  Indicates the cycle number of reading Rx FIFO.
+         */
+        uint32_t rx_cnt:5;
+        /** rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0;
+         *  Indicates the current written bit number into Rx FIFO.
+         */
+        uint32_t rx_fifo_wr_bit_cnt:19;
+    };
+    uint32_t val;
+} parl_io_rx_st0_reg_t;
+
+
+/** Group: PARL_IO Rx Status1 */
+/** Type of rx_st1 register
+ *  Parallel IO RX status register1
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:13;
+        /** rx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
+         *  Indicates the current read bit number from Rx FIFO.
+         */
+        uint32_t rx_fifo_rd_bit_cnt:19;
+    };
+    uint32_t val;
+} parl_io_rx_st1_reg_t;
+
+
+/** Group: PARL_IO Tx Status0 */
+/** Type of tx_st0 register
+ *  Parallel IO TX status register0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** tx_cnt : RO; bitpos: [12:6]; default: 0;
+         *  Indicates the cycle number of reading Tx FIFO.
+         */
+        uint32_t tx_cnt:7;
+        /** tx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
+         *  Indicates the current read bit number from Tx FIFO.
+         */
+        uint32_t tx_fifo_rd_bit_cnt:19;
+    };
+    uint32_t val;
+} parl_io_tx_st0_reg_t;
+
+
+/** Group: PARL_IO Rx Clock Configuration */
+/** Type of rx_clk_cfg register
+ *  Parallel IO RX clk configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** rx_clk_i_inv : R/W; bitpos: [30]; default: 0;
+         *  Write 1 to invert the input Rx core clock.
+         */
+        uint32_t rx_clk_i_inv:1;
+        /** rx_clk_o_inv : R/W; bitpos: [31]; default: 0;
+         *  Write 1 to invert the output Rx core clock.
+         */
+        uint32_t rx_clk_o_inv:1;
+    };
+    uint32_t val;
+} parl_io_rx_clk_cfg_reg_t;
+
+
+/** Group: PARL_IO Tx Clock Configuration */
+/** Type of tx_clk_cfg register
+ *  Parallel IO TX clk configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** tx_clk_i_inv : R/W; bitpos: [30]; default: 0;
+         *  Write 1 to invert the input Tx core clock.
+         */
+        uint32_t tx_clk_i_inv:1;
+        /** tx_clk_o_inv : R/W; bitpos: [31]; default: 0;
+         *  Write 1 to invert the output Tx core clock.
+         */
+        uint32_t tx_clk_o_inv:1;
+    };
+    uint32_t val;
+} parl_io_tx_clk_cfg_reg_t;
+
+
+/** Group: PARL_TX_CS Configuration */
+/** Type of tx_cs_cfg register
+ *  Parallel IO tx_cs_o generate configuration
+ */
+typedef union {
+    struct {
+        /** tx_cs_stop_delay : R/W; bitpos: [15:0]; default: 0;
+         *  configure the delay between data tx end and tx_cs_o posedge
+         */
+        uint32_t tx_cs_stop_delay:16;
+        /** tx_cs_start_delay : R/W; bitpos: [31:16]; default: 0;
+         *  configure the delay between tx_cs_o negedge and data tx start
+         */
+        uint32_t tx_cs_start_delay:16;
+    };
+    uint32_t val;
+} parl_io_tx_cs_cfg_reg_t;
+
+
+/** Group: PARL_IO Clock Configuration */
+/** Type of clk register
+ *  Parallel IO clk configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Force clock on for this register file
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} parl_io_clk_reg_t;
+
+
+/** Group: PARL_IO Version Register */
+/** Type of version register
+ *  Version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 37786160;
+         *  Version of this register file
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} parl_io_version_reg_t;
+
+
+typedef struct parl_io_dev_t {
+    volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg;
+    volatile parl_io_rx_data_cfg_reg_t rx_data_cfg;
+    volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg;
+    volatile parl_io_rx_start_cfg_reg_t rx_start_cfg;
+    volatile parl_io_tx_data_cfg_reg_t tx_data_cfg;
+    volatile parl_io_tx_start_cfg_reg_t tx_start_cfg;
+    volatile parl_io_tx_genrl_cfg_reg_t tx_genrl_cfg;
+    volatile parl_io_fifo_cfg_reg_t fifo_cfg;
+    volatile parl_io_reg_update_reg_t reg_update;
+    volatile parl_io_st_reg_t st;
+    volatile parl_io_int_ena_reg_t int_ena;
+    volatile parl_io_int_raw_reg_t int_raw;
+    volatile parl_io_int_st_reg_t int_st;
+    volatile parl_io_int_clr_reg_t int_clr;
+    volatile parl_io_rx_st0_reg_t rx_st0;
+    volatile parl_io_rx_st1_reg_t rx_st1;
+    volatile parl_io_tx_st0_reg_t tx_st0;
+    volatile parl_io_rx_clk_cfg_reg_t rx_clk_cfg;
+    volatile parl_io_tx_clk_cfg_reg_t tx_clk_cfg;
+    volatile parl_io_tx_cs_cfg_reg_t tx_cs_cfg;
+    uint32_t reserved_050[52];
+    volatile parl_io_clk_reg_t clk;
+    uint32_t reserved_124[182];
+    volatile parl_io_version_reg_t version;
+} parl_io_dev_t;
+
+extern parl_io_dev_t PARL_IO;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/pau_reg.h

@@ -0,0 +1,332 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PAU_REGDMA_CONF_REG register
+ *  Peri backup control register
+ */
+#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0)
+/** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0;
+ *  backup error type
+ */
+#define PAU_FLOW_ERR    0x00000007U
+#define PAU_FLOW_ERR_M  (PAU_FLOW_ERR_V << PAU_FLOW_ERR_S)
+#define PAU_FLOW_ERR_V  0x00000007U
+#define PAU_FLOW_ERR_S  0
+/** PAU_START : WT; bitpos: [3]; default: 0;
+ *  backup start signal
+ */
+#define PAU_START    (BIT(3))
+#define PAU_START_M  (PAU_START_V << PAU_START_S)
+#define PAU_START_V  0x00000001U
+#define PAU_START_S  3
+/** PAU_TO_MEM : R/W; bitpos: [4]; default: 0;
+ *  backup direction(reg to mem / mem to reg)
+ */
+#define PAU_TO_MEM    (BIT(4))
+#define PAU_TO_MEM_M  (PAU_TO_MEM_V << PAU_TO_MEM_S)
+#define PAU_TO_MEM_V  0x00000001U
+#define PAU_TO_MEM_S  4
+/** PAU_LINK_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  Link select
+ */
+#define PAU_LINK_SEL    0x00000003U
+#define PAU_LINK_SEL_M  (PAU_LINK_SEL_V << PAU_LINK_SEL_S)
+#define PAU_LINK_SEL_V  0x00000003U
+#define PAU_LINK_SEL_S  5
+/** PAU_START_MAC : WT; bitpos: [7]; default: 0;
+ *  mac sw backup start signal
+ */
+#define PAU_START_MAC    (BIT(7))
+#define PAU_START_MAC_M  (PAU_START_MAC_V << PAU_START_MAC_S)
+#define PAU_START_MAC_V  0x00000001U
+#define PAU_START_MAC_S  7
+/** PAU_TO_MEM_MAC : R/W; bitpos: [8]; default: 0;
+ *  mac sw backup direction(reg to mem / mem to reg)
+ */
+#define PAU_TO_MEM_MAC    (BIT(8))
+#define PAU_TO_MEM_MAC_M  (PAU_TO_MEM_MAC_V << PAU_TO_MEM_MAC_S)
+#define PAU_TO_MEM_MAC_V  0x00000001U
+#define PAU_TO_MEM_MAC_S  8
+/** PAU_SEL_MAC : R/W; bitpos: [9]; default: 0;
+ *  mac hw/sw select
+ */
+#define PAU_SEL_MAC    (BIT(9))
+#define PAU_SEL_MAC_M  (PAU_SEL_MAC_V << PAU_SEL_MAC_S)
+#define PAU_SEL_MAC_V  0x00000001U
+#define PAU_SEL_MAC_S  9
+
+/** PAU_REGDMA_CLK_CONF_REG register
+ *  Clock control register
+ */
+#define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4)
+/** PAU_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  clock enable
+ */
+#define PAU_CLK_EN    (BIT(0))
+#define PAU_CLK_EN_M  (PAU_CLK_EN_V << PAU_CLK_EN_S)
+#define PAU_CLK_EN_V  0x00000001U
+#define PAU_CLK_EN_S  0
+
+/** PAU_REGDMA_ETM_CTRL_REG register
+ *  ETM start ctrl reg
+ */
+#define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8)
+/** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0;
+ *  etm_start_0 reg
+ */
+#define PAU_ETM_START_0    (BIT(0))
+#define PAU_ETM_START_0_M  (PAU_ETM_START_0_V << PAU_ETM_START_0_S)
+#define PAU_ETM_START_0_V  0x00000001U
+#define PAU_ETM_START_0_S  0
+/** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0;
+ *  etm_start_1 reg
+ */
+#define PAU_ETM_START_1    (BIT(1))
+#define PAU_ETM_START_1_M  (PAU_ETM_START_1_V << PAU_ETM_START_1_S)
+#define PAU_ETM_START_1_V  0x00000001U
+#define PAU_ETM_START_1_S  1
+/** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0;
+ *  etm_start_2 reg
+ */
+#define PAU_ETM_START_2    (BIT(2))
+#define PAU_ETM_START_2_M  (PAU_ETM_START_2_V << PAU_ETM_START_2_S)
+#define PAU_ETM_START_2_V  0x00000001U
+#define PAU_ETM_START_2_S  2
+/** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0;
+ *  etm_start_3 reg
+ */
+#define PAU_ETM_START_3    (BIT(3))
+#define PAU_ETM_START_3_M  (PAU_ETM_START_3_V << PAU_ETM_START_3_S)
+#define PAU_ETM_START_3_V  0x00000001U
+#define PAU_ETM_START_3_S  3
+
+/** PAU_REGDMA_LINK_0_ADDR_REG register
+ *  link_0_addr
+ */
+#define PAU_REGDMA_LINK_0_ADDR_REG (DR_REG_PAU_BASE + 0xc)
+/** PAU_LINK_ADDR_0 : R/W; bitpos: [31:0]; default: 0;
+ *  link_0_addr reg
+ */
+#define PAU_LINK_ADDR_0    0xFFFFFFFFU
+#define PAU_LINK_ADDR_0_M  (PAU_LINK_ADDR_0_V << PAU_LINK_ADDR_0_S)
+#define PAU_LINK_ADDR_0_V  0xFFFFFFFFU
+#define PAU_LINK_ADDR_0_S  0
+
+/** PAU_REGDMA_LINK_1_ADDR_REG register
+ *  Link_1_addr
+ */
+#define PAU_REGDMA_LINK_1_ADDR_REG (DR_REG_PAU_BASE + 0x10)
+/** PAU_LINK_ADDR_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Link_1_addr reg
+ */
+#define PAU_LINK_ADDR_1    0xFFFFFFFFU
+#define PAU_LINK_ADDR_1_M  (PAU_LINK_ADDR_1_V << PAU_LINK_ADDR_1_S)
+#define PAU_LINK_ADDR_1_V  0xFFFFFFFFU
+#define PAU_LINK_ADDR_1_S  0
+
+/** PAU_REGDMA_LINK_2_ADDR_REG register
+ *  Link_2_addr
+ */
+#define PAU_REGDMA_LINK_2_ADDR_REG (DR_REG_PAU_BASE + 0x14)
+/** PAU_LINK_ADDR_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Link_2_addr reg
+ */
+#define PAU_LINK_ADDR_2    0xFFFFFFFFU
+#define PAU_LINK_ADDR_2_M  (PAU_LINK_ADDR_2_V << PAU_LINK_ADDR_2_S)
+#define PAU_LINK_ADDR_2_V  0xFFFFFFFFU
+#define PAU_LINK_ADDR_2_S  0
+
+/** PAU_REGDMA_LINK_3_ADDR_REG register
+ *  Link_3_addr
+ */
+#define PAU_REGDMA_LINK_3_ADDR_REG (DR_REG_PAU_BASE + 0x18)
+/** PAU_LINK_ADDR_3 : R/W; bitpos: [31:0]; default: 0;
+ *  Link_3_addr reg
+ */
+#define PAU_LINK_ADDR_3    0xFFFFFFFFU
+#define PAU_LINK_ADDR_3_M  (PAU_LINK_ADDR_3_V << PAU_LINK_ADDR_3_S)
+#define PAU_LINK_ADDR_3_V  0xFFFFFFFFU
+#define PAU_LINK_ADDR_3_S  0
+
+/** PAU_REGDMA_LINK_MAC_ADDR_REG register
+ *  Link_mac_addr
+ */
+#define PAU_REGDMA_LINK_MAC_ADDR_REG (DR_REG_PAU_BASE + 0x1c)
+/** PAU_LINK_ADDR_MAC : R/W; bitpos: [31:0]; default: 0;
+ *  Link_mac_addr reg
+ */
+#define PAU_LINK_ADDR_MAC    0xFFFFFFFFU
+#define PAU_LINK_ADDR_MAC_M  (PAU_LINK_ADDR_MAC_V << PAU_LINK_ADDR_MAC_S)
+#define PAU_LINK_ADDR_MAC_V  0xFFFFFFFFU
+#define PAU_LINK_ADDR_MAC_S  0
+
+/** PAU_REGDMA_CURRENT_LINK_ADDR_REG register
+ *  current link addr
+ */
+#define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0x20)
+/** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  current link addr reg
+ */
+#define PAU_CURRENT_LINK_ADDR    0xFFFFFFFFU
+#define PAU_CURRENT_LINK_ADDR_M  (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S)
+#define PAU_CURRENT_LINK_ADDR_V  0xFFFFFFFFU
+#define PAU_CURRENT_LINK_ADDR_S  0
+
+/** PAU_REGDMA_BACKUP_ADDR_REG register
+ *  Backup addr
+ */
+#define PAU_REGDMA_BACKUP_ADDR_REG (DR_REG_PAU_BASE + 0x24)
+/** PAU_BACKUP_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  backup addr reg
+ */
+#define PAU_BACKUP_ADDR    0xFFFFFFFFU
+#define PAU_BACKUP_ADDR_M  (PAU_BACKUP_ADDR_V << PAU_BACKUP_ADDR_S)
+#define PAU_BACKUP_ADDR_V  0xFFFFFFFFU
+#define PAU_BACKUP_ADDR_S  0
+
+/** PAU_REGDMA_MEM_ADDR_REG register
+ *  mem addr
+ */
+#define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x28)
+/** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  mem addr reg
+ */
+#define PAU_MEM_ADDR    0xFFFFFFFFU
+#define PAU_MEM_ADDR_M  (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S)
+#define PAU_MEM_ADDR_V  0xFFFFFFFFU
+#define PAU_MEM_ADDR_S  0
+
+/** PAU_REGDMA_BKP_CONF_REG register
+ *  backup config
+ */
+#define PAU_REGDMA_BKP_CONF_REG (DR_REG_PAU_BASE + 0x2c)
+/** PAU_READ_INTERVAL : R/W; bitpos: [6:0]; default: 32;
+ *  Link read_interval
+ */
+#define PAU_READ_INTERVAL    0x0000007FU
+#define PAU_READ_INTERVAL_M  (PAU_READ_INTERVAL_V << PAU_READ_INTERVAL_S)
+#define PAU_READ_INTERVAL_V  0x0000007FU
+#define PAU_READ_INTERVAL_S  0
+/** PAU_LINK_TOUT_THRES : R/W; bitpos: [16:7]; default: 50;
+ *  link wait timeout threshold
+ */
+#define PAU_LINK_TOUT_THRES    0x000003FFU
+#define PAU_LINK_TOUT_THRES_M  (PAU_LINK_TOUT_THRES_V << PAU_LINK_TOUT_THRES_S)
+#define PAU_LINK_TOUT_THRES_V  0x000003FFU
+#define PAU_LINK_TOUT_THRES_S  7
+/** PAU_BURST_LIMIT : R/W; bitpos: [21:17]; default: 8;
+ *  burst limit
+ */
+#define PAU_BURST_LIMIT    0x0000001FU
+#define PAU_BURST_LIMIT_M  (PAU_BURST_LIMIT_V << PAU_BURST_LIMIT_S)
+#define PAU_BURST_LIMIT_V  0x0000001FU
+#define PAU_BURST_LIMIT_S  17
+/** PAU_BACKUP_TOUT_THRES : R/W; bitpos: [31:22]; default: 500;
+ *  Backup timeout threshold
+ */
+#define PAU_BACKUP_TOUT_THRES    0x000003FFU
+#define PAU_BACKUP_TOUT_THRES_M  (PAU_BACKUP_TOUT_THRES_V << PAU_BACKUP_TOUT_THRES_S)
+#define PAU_BACKUP_TOUT_THRES_V  0x000003FFU
+#define PAU_BACKUP_TOUT_THRES_S  22
+
+/** PAU_INT_ENA_REG register
+ *  Read only register for error and done
+ */
+#define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x30)
+/** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  backup done flag
+ */
+#define PAU_DONE_INT_ENA    (BIT(0))
+#define PAU_DONE_INT_ENA_M  (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S)
+#define PAU_DONE_INT_ENA_V  0x00000001U
+#define PAU_DONE_INT_ENA_S  0
+/** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  error flag
+ */
+#define PAU_ERROR_INT_ENA    (BIT(1))
+#define PAU_ERROR_INT_ENA_M  (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S)
+#define PAU_ERROR_INT_ENA_V  0x00000001U
+#define PAU_ERROR_INT_ENA_S  1
+
+/** PAU_INT_RAW_REG register
+ *  Read only register for error and done
+ */
+#define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x34)
+/** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  backup done flag
+ */
+#define PAU_DONE_INT_RAW    (BIT(0))
+#define PAU_DONE_INT_RAW_M  (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S)
+#define PAU_DONE_INT_RAW_V  0x00000001U
+#define PAU_DONE_INT_RAW_S  0
+/** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  error flag
+ */
+#define PAU_ERROR_INT_RAW    (BIT(1))
+#define PAU_ERROR_INT_RAW_M  (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S)
+#define PAU_ERROR_INT_RAW_V  0x00000001U
+#define PAU_ERROR_INT_RAW_S  1
+
+/** PAU_INT_CLR_REG register
+ *  Read only register for error and done
+ */
+#define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x38)
+/** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  backup done flag
+ */
+#define PAU_DONE_INT_CLR    (BIT(0))
+#define PAU_DONE_INT_CLR_M  (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S)
+#define PAU_DONE_INT_CLR_V  0x00000001U
+#define PAU_DONE_INT_CLR_S  0
+/** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  error flag
+ */
+#define PAU_ERROR_INT_CLR    (BIT(1))
+#define PAU_ERROR_INT_CLR_M  (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S)
+#define PAU_ERROR_INT_CLR_V  0x00000001U
+#define PAU_ERROR_INT_CLR_S  1
+
+/** PAU_INT_ST_REG register
+ *  Read only register for error and done
+ */
+#define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x3c)
+/** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  backup done flag
+ */
+#define PAU_DONE_INT_ST    (BIT(0))
+#define PAU_DONE_INT_ST_M  (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S)
+#define PAU_DONE_INT_ST_V  0x00000001U
+#define PAU_DONE_INT_ST_S  0
+/** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0;
+ *  error flag
+ */
+#define PAU_ERROR_INT_ST    (BIT(1))
+#define PAU_ERROR_INT_ST_M  (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S)
+#define PAU_ERROR_INT_ST_V  0x00000001U
+#define PAU_ERROR_INT_ST_S  1
+
+/** PAU_DATE_REG register
+ *  Date register.
+ */
+#define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc)
+/** PAU_DATE : R/W; bitpos: [27:0]; default: 36705040;
+ *  REGDMA date information/ REGDMA version information.
+ */
+#define PAU_DATE    0x0FFFFFFFU
+#define PAU_DATE_M  (PAU_DATE_V << PAU_DATE_S)
+#define PAU_DATE_V  0x0FFFFFFFU
+#define PAU_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/pau_struct.h

@@ -0,0 +1,339 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Register */
+/** Type of regdma_conf register
+ *  Peri backup control register
+ */
+typedef union {
+    struct {
+        /** flow_err : RO; bitpos: [2:0]; default: 0;
+         *  backup error type
+         */
+        uint32_t flow_err:3;
+        /** start : WT; bitpos: [3]; default: 0;
+         *  backup start signal
+         */
+        uint32_t start:1;
+        /** to_mem : R/W; bitpos: [4]; default: 0;
+         *  backup direction(reg to mem / mem to reg)
+         */
+        uint32_t to_mem:1;
+        /** link_sel : R/W; bitpos: [6:5]; default: 0;
+         *  Link select
+         */
+        uint32_t link_sel:2;
+        /** start_mac : WT; bitpos: [7]; default: 0;
+         *  mac sw backup start signal
+         */
+        uint32_t start_mac:1;
+        /** to_mem_mac : R/W; bitpos: [8]; default: 0;
+         *  mac sw backup direction(reg to mem / mem to reg)
+         */
+        uint32_t to_mem_mac:1;
+        /** sel_mac : R/W; bitpos: [9]; default: 0;
+         *  mac hw/sw select
+         */
+        uint32_t sel_mac:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} pau_regdma_conf_reg_t;
+
+/** Type of regdma_clk_conf register
+ *  Clock control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  clock enable
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} pau_regdma_clk_conf_reg_t;
+
+/** Type of regdma_etm_ctrl register
+ *  ETM start ctrl reg
+ */
+typedef union {
+    struct {
+        /** etm_start_0 : WT; bitpos: [0]; default: 0;
+         *  etm_start_0 reg
+         */
+        uint32_t etm_start_0:1;
+        /** etm_start_1 : WT; bitpos: [1]; default: 0;
+         *  etm_start_1 reg
+         */
+        uint32_t etm_start_1:1;
+        /** etm_start_2 : WT; bitpos: [2]; default: 0;
+         *  etm_start_2 reg
+         */
+        uint32_t etm_start_2:1;
+        /** etm_start_3 : WT; bitpos: [3]; default: 0;
+         *  etm_start_3 reg
+         */
+        uint32_t etm_start_3:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pau_regdma_etm_ctrl_reg_t;
+
+/** Type of regdma_link_0_addr register
+ *  link_0_addr
+ */
+typedef union {
+    struct {
+        /** link_addr_0 : R/W; bitpos: [31:0]; default: 0;
+         *  link_0_addr reg
+         */
+        uint32_t link_addr_0:32;
+    };
+    uint32_t val;
+} pau_regdma_link_0_addr_reg_t;
+
+/** Type of regdma_link_1_addr register
+ *  Link_1_addr
+ */
+typedef union {
+    struct {
+        /** link_addr_1 : R/W; bitpos: [31:0]; default: 0;
+         *  Link_1_addr reg
+         */
+        uint32_t link_addr_1:32;
+    };
+    uint32_t val;
+} pau_regdma_link_1_addr_reg_t;
+
+/** Type of regdma_link_2_addr register
+ *  Link_2_addr
+ */
+typedef union {
+    struct {
+        /** link_addr_2 : R/W; bitpos: [31:0]; default: 0;
+         *  Link_2_addr reg
+         */
+        uint32_t link_addr_2:32;
+    };
+    uint32_t val;
+} pau_regdma_link_2_addr_reg_t;
+
+/** Type of regdma_link_3_addr register
+ *  Link_3_addr
+ */
+typedef union {
+    struct {
+        /** link_addr_3 : R/W; bitpos: [31:0]; default: 0;
+         *  Link_3_addr reg
+         */
+        uint32_t link_addr_3:32;
+    };
+    uint32_t val;
+} pau_regdma_link_3_addr_reg_t;
+
+/** Type of regdma_link_mac_addr register
+ *  Link_mac_addr
+ */
+typedef union {
+    struct {
+        /** link_addr_mac : R/W; bitpos: [31:0]; default: 0;
+         *  Link_mac_addr reg
+         */
+        uint32_t link_addr_mac:32;
+    };
+    uint32_t val;
+} pau_regdma_link_mac_addr_reg_t;
+
+/** Type of regdma_current_link_addr register
+ *  current link addr
+ */
+typedef union {
+    struct {
+        /** current_link_addr : RO; bitpos: [31:0]; default: 0;
+         *  current link addr reg
+         */
+        uint32_t current_link_addr:32;
+    };
+    uint32_t val;
+} pau_regdma_current_link_addr_reg_t;
+
+/** Type of regdma_backup_addr register
+ *  Backup addr
+ */
+typedef union {
+    struct {
+        /** backup_addr : RO; bitpos: [31:0]; default: 0;
+         *  backup addr reg
+         */
+        uint32_t backup_addr:32;
+    };
+    uint32_t val;
+} pau_regdma_backup_addr_reg_t;
+
+/** Type of regdma_mem_addr register
+ *  mem addr
+ */
+typedef union {
+    struct {
+        /** mem_addr : RO; bitpos: [31:0]; default: 0;
+         *  mem addr reg
+         */
+        uint32_t mem_addr:32;
+    };
+    uint32_t val;
+} pau_regdma_mem_addr_reg_t;
+
+/** Type of regdma_bkp_conf register
+ *  backup config
+ */
+typedef union {
+    struct {
+        /** read_interval : R/W; bitpos: [6:0]; default: 32;
+         *  Link read_interval
+         */
+        uint32_t read_interval:7;
+        /** link_tout_thres : R/W; bitpos: [16:7]; default: 50;
+         *  link wait timeout threshold
+         */
+        uint32_t link_tout_thres:10;
+        /** burst_limit : R/W; bitpos: [21:17]; default: 8;
+         *  burst limit
+         */
+        uint32_t burst_limit:5;
+        /** backup_tout_thres : R/W; bitpos: [31:22]; default: 500;
+         *  Backup timeout threshold
+         */
+        uint32_t backup_tout_thres:10;
+    };
+    uint32_t val;
+} pau_regdma_bkp_conf_reg_t;
+
+/** Type of int_ena register
+ *  Read only register for error and done
+ */
+typedef union {
+    struct {
+        /** done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  backup done flag
+         */
+        uint32_t done_int_ena:1;
+        /** error_int_ena : R/W; bitpos: [1]; default: 0;
+         *  error flag
+         */
+        uint32_t error_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pau_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  Read only register for error and done
+ */
+typedef union {
+    struct {
+        /** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  backup done flag
+         */
+        uint32_t done_int_raw:1;
+        /** error_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  error flag
+         */
+        uint32_t error_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pau_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  Read only register for error and done
+ */
+typedef union {
+    struct {
+        /** done_int_clr : WT; bitpos: [0]; default: 0;
+         *  backup done flag
+         */
+        uint32_t done_int_clr:1;
+        /** error_int_clr : WT; bitpos: [1]; default: 0;
+         *  error flag
+         */
+        uint32_t error_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pau_int_clr_reg_t;
+
+/** Type of int_st register
+ *  Read only register for error and done
+ */
+typedef union {
+    struct {
+        /** done_int_st : RO; bitpos: [0]; default: 0;
+         *  backup done flag
+         */
+        uint32_t done_int_st:1;
+        /** error_int_st : RO; bitpos: [1]; default: 0;
+         *  error flag
+         */
+        uint32_t error_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pau_int_st_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  Date register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36705040;
+         *  REGDMA date information/ REGDMA version information.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} pau_date_reg_t;
+
+
+typedef struct {
+    volatile pau_regdma_conf_reg_t regdma_conf;
+    volatile pau_regdma_clk_conf_reg_t regdma_clk_conf;
+    volatile pau_regdma_etm_ctrl_reg_t regdma_etm_ctrl;
+    volatile pau_regdma_link_0_addr_reg_t regdma_link_0_addr;
+    volatile pau_regdma_link_1_addr_reg_t regdma_link_1_addr;
+    volatile pau_regdma_link_2_addr_reg_t regdma_link_2_addr;
+    volatile pau_regdma_link_3_addr_reg_t regdma_link_3_addr;
+    volatile pau_regdma_link_mac_addr_reg_t regdma_link_mac_addr;
+    volatile pau_regdma_current_link_addr_reg_t regdma_current_link_addr;
+    volatile pau_regdma_backup_addr_reg_t regdma_backup_addr;
+    volatile pau_regdma_mem_addr_reg_t regdma_mem_addr;
+    volatile pau_regdma_bkp_conf_reg_t regdma_bkp_conf;
+    volatile pau_int_ena_reg_t int_ena;
+    volatile pau_int_raw_reg_t int_raw;
+    volatile pau_int_clr_reg_t int_clr;
+    volatile pau_int_st_reg_t int_st;
+    uint32_t reserved_040[239];
+    volatile pau_date_reg_t date;
+} pau_dev_t;
+
+extern pau_dev_t PAU;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(pau_dev_t) == 0x400, "Invalid size of pau_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/pcnt_eco5_struct.h

@@ -0,0 +1,504 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Register */
+/** Type of un_conf0 register
+ *  Configuration register 0 for unit n
+ */
+typedef union {
+    struct {
+        /** filter_thres_un : R/W; bitpos: [9:0]; default: 16;
+         *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
+         *
+         *  Any pulses with width less than this will be ignored when the filter is enabled.
+         */
+        uint32_t filter_thres_un:10;
+        /** filter_en_un : R/W; bitpos: [10]; default: 1;
+         *  This is the enable bit for unit n's input filter.
+         */
+        uint32_t filter_en_un:1;
+        /** thr_zero_en_un : R/W; bitpos: [11]; default: 1;
+         *  This is the enable bit for unit n's zero comparator.
+         */
+        uint32_t thr_zero_en_un:1;
+        /** thr_h_lim_en_un : R/W; bitpos: [12]; default: 1;
+         *  This is the enable bit for unit n's thr_h_lim comparator. Configures it to enable
+         *  the high limit interrupt.
+         */
+        uint32_t thr_h_lim_en_un:1;
+        /** thr_l_lim_en_un : R/W; bitpos: [13]; default: 1;
+         *  This is the enable bit for unit n's thr_l_lim comparator. Configures it to enable
+         *  the low limit interrupt.
+         */
+        uint32_t thr_l_lim_en_un:1;
+        /** thr_thres0_en_un : R/W; bitpos: [14]; default: 0;
+         *  This is the enable bit for unit n's thres0 comparator.
+         */
+        uint32_t thr_thres0_en_un:1;
+        /** thr_thres1_en_un : R/W; bitpos: [15]; default: 0;
+         *  This is the enable bit for unit n's thres1 comparator.
+         */
+        uint32_t thr_thres1_en_un:1;
+        /** ch0_neg_mode_un : R/W; bitpos: [17:16]; default: 0;
+         *  This register sets the behavior when the signal input of channel 0 detects a
+         *  negative edge.
+         *
+         *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
+         */
+        uint32_t ch0_neg_mode_un:2;
+        /** ch0_pos_mode_un : R/W; bitpos: [19:18]; default: 0;
+         *  This register sets the behavior when the signal input of channel 0 detects a
+         *  positive edge.
+         *
+         *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
+         */
+        uint32_t ch0_pos_mode_un:2;
+        /** ch0_hctrl_mode_un : R/W; bitpos: [21:20]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is high.
+         *
+         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+         *  increase).2, 3: Inhibit counter modification
+         */
+        uint32_t ch0_hctrl_mode_un:2;
+        /** ch0_lctrl_mode_un : R/W; bitpos: [23:22]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is low.
+         *
+         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+         *  increase).2, 3: Inhibit counter modification
+         */
+        uint32_t ch0_lctrl_mode_un:2;
+        /** ch1_neg_mode_un : R/W; bitpos: [25:24]; default: 0;
+         *  This register sets the behavior when the signal input of channel 1 detects a
+         *  negative edge.
+         *
+         *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
+         */
+        uint32_t ch1_neg_mode_un:2;
+        /** ch1_pos_mode_un : R/W; bitpos: [27:26]; default: 0;
+         *  This register sets the behavior when the signal input of channel 1 detects a
+         *  positive edge.
+         *
+         *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
+         */
+        uint32_t ch1_pos_mode_un:2;
+        /** ch1_hctrl_mode_un : R/W; bitpos: [29:28]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is high.
+         *
+         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+         *  increase).2, 3: Inhibit counter modification
+         */
+        uint32_t ch1_hctrl_mode_un:2;
+        /** ch1_lctrl_mode_un : R/W; bitpos: [31:30]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is low.
+         *
+         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+         *  increase).2, 3: Inhibit counter modification
+         */
+        uint32_t ch1_lctrl_mode_un:2;
+    };
+    uint32_t val;
+} pcnt_un_conf0_reg_t;
+
+/** Type of un_conf1 register
+ *  Configuration register 1 for unit n
+ */
+typedef union {
+    struct {
+        /** cnt_thres0_un : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to configure the thres0 value for unit n.
+         */
+        uint32_t cnt_thres0_un:16;
+        /** cnt_thres1_un : R/W; bitpos: [31:16]; default: 0;
+         *  This register is used to configure the thres1 value for unit n.
+         */
+        uint32_t cnt_thres1_un:16;
+    };
+    uint32_t val;
+} pcnt_un_conf1_reg_t;
+
+/** Type of un_conf2 register
+ *  Configuration register 2 for unit n
+ */
+typedef union {
+    struct {
+        /** cnt_h_lim_un : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to configure the thr_h_lim value for unit n. When pcnt
+         *  reaches this value, the counter will be cleared to 0.
+         */
+        uint32_t cnt_h_lim_un:16;
+        /** cnt_l_lim_un : R/W; bitpos: [31:16]; default: 0;
+         *  This register is used to configure the thr_l_lim value for unit n. When pcnt
+         *  reaches this value, the counter will be cleared to 0.
+         */
+        uint32_t cnt_l_lim_un:16;
+    };
+    uint32_t val;
+} pcnt_un_conf2_reg_t;
+
+/** Type of ctrl register
+ *  Control register for all counters
+ */
+typedef union {
+    struct {
+        /** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to clear unit 0's counter.
+         */
+        uint32_t pulse_cnt_rst_u0:1;
+        /** cnt_pause_u0 : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to freeze unit 0's counter.
+         */
+        uint32_t cnt_pause_u0:1;
+        /** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to clear unit 1's counter.
+         */
+        uint32_t pulse_cnt_rst_u1:1;
+        /** cnt_pause_u1 : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to freeze unit 1's counter.
+         */
+        uint32_t cnt_pause_u1:1;
+        /** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to clear unit 2's counter.
+         */
+        uint32_t pulse_cnt_rst_u2:1;
+        /** cnt_pause_u2 : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to freeze unit 2's counter.
+         */
+        uint32_t cnt_pause_u2:1;
+        /** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1;
+         *  Set this bit to clear unit 3's counter.
+         */
+        uint32_t pulse_cnt_rst_u3:1;
+        /** cnt_pause_u3 : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to freeze unit 3's counter.
+         */
+        uint32_t cnt_pause_u3:1;
+        /** dalta_change_en_u0 : R/W; bitpos: [8]; default: 0;
+         *  Configures this bit to enable unit 0's step comparator.
+         */
+        uint32_t dalta_change_en_u0:1;
+        /** dalta_change_en_u1 : R/W; bitpos: [9]; default: 0;
+         *  Configures this bit to enable unit 1's step comparator.
+         */
+        uint32_t dalta_change_en_u1:1;
+        /** dalta_change_en_u2 : R/W; bitpos: [10]; default: 0;
+         *  Configures this bit to enable unit 2's step comparator.
+         */
+        uint32_t dalta_change_en_u2:1;
+        /** dalta_change_en_u3 : R/W; bitpos: [11]; default: 0;
+         *  Configures this bit to enable unit 3's step comparator.
+         */
+        uint32_t dalta_change_en_u3:1;
+        uint32_t reserved_12:4;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  The registers clock gate enable signal of PCNT module. 1: the registers can be read
+         *  and written by application. 0: the registers can not be read or written by
+         *  application
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} pcnt_ctrl_reg_t;
+
+/** Type of u3_change_conf register
+ *  Configuration register for unit $n's step value.
+ */
+typedef union {
+    struct {
+        /** cnt_step_u3 : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the step value for unit 3.
+         */
+        uint32_t cnt_step_u3:16;
+        /** cnt_step_lim_u3 : R/W; bitpos: [31:16]; default: 0;
+         *  Configures the step limit value for unit 3.
+         */
+        uint32_t cnt_step_lim_u3:16;
+    };
+    uint32_t val;
+} pcnt_u3_change_conf_reg_t;
+
+/** Type of u2_change_conf register
+ *  Configuration register for unit $n's step value.
+ */
+typedef union {
+    struct {
+        /** cnt_step_u2 : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the step value for unit 2.
+         */
+        uint32_t cnt_step_u2:16;
+        /** cnt_step_lim_u2 : R/W; bitpos: [31:16]; default: 0;
+         *  Configures the step limit value for unit 2.
+         */
+        uint32_t cnt_step_lim_u2:16;
+    };
+    uint32_t val;
+} pcnt_u2_change_conf_reg_t;
+
+/** Type of u1_change_conf register
+ *  Configuration register for unit $n's step value.
+ */
+typedef union {
+    struct {
+        /** cnt_step_u1 : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the step value for unit 1.
+         */
+        uint32_t cnt_step_u1:16;
+        /** cnt_step_lim_u1 : R/W; bitpos: [31:16]; default: 0;
+         *  Configures the step limit value for unit 1.
+         */
+        uint32_t cnt_step_lim_u1:16;
+    };
+    uint32_t val;
+} pcnt_u1_change_conf_reg_t;
+
+/** Type of u0_change_conf register
+ *  Configuration register for unit $n's step value.
+ */
+typedef union {
+    struct {
+        /** cnt_step_u0 : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the step value for unit 0.
+         */
+        uint32_t cnt_step_u0:16;
+        /** cnt_step_lim_u0 : R/W; bitpos: [31:16]; default: 0;
+         *  Configures the step limit value for unit 0.
+         */
+        uint32_t cnt_step_lim_u0:16;
+    };
+    uint32_t val;
+} pcnt_u0_change_conf_reg_t;
+
+
+/** Group: Status Register */
+/** Type of un_cnt register
+ *  Counter value for unit n
+ */
+typedef union {
+    struct {
+        /** pulse_cnt_un : RO; bitpos: [15:0]; default: 0;
+         *  This register stores the current pulse count value for unit n.
+         */
+        uint32_t pulse_cnt_un:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} pcnt_un_cnt_reg_t;
+
+/** Type of un_status register
+ *  PNCT UNITn status register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_zero_mode_un : RO; bitpos: [1:0]; default: 0;
+         *  The pulse counter status of PCNT_Un corresponding to 0. 0: pulse counter decreases
+         *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
+         *  is negative. 3: pulse counter is positive.
+         */
+        uint32_t cnt_thr_zero_mode_un:2;
+        /** cnt_thr_thres1_lat_un : RO; bitpos: [2]; default: 0;
+         *  The latched value of thres1 event of PCNT_Un when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
+         *  others
+         */
+        uint32_t cnt_thr_thres1_lat_un:1;
+        /** cnt_thr_thres0_lat_un : RO; bitpos: [3]; default: 0;
+         *  The latched value of thres0 event of PCNT_Un when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
+         *  others
+         */
+        uint32_t cnt_thr_thres0_lat_un:1;
+        /** cnt_thr_l_lim_lat_un : RO; bitpos: [4]; default: 0;
+         *  The latched value of low limit event of PCNT_Un when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
+         *  valid. 0: others
+         */
+        uint32_t cnt_thr_l_lim_lat_un:1;
+        /** cnt_thr_h_lim_lat_un : RO; bitpos: [5]; default: 0;
+         *  The latched value of high limit event of PCNT_Un when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
+         *  valid. 0: others
+         */
+        uint32_t cnt_thr_h_lim_lat_un:1;
+        /** cnt_thr_zero_lat_un : RO; bitpos: [6]; default: 0;
+         *  The latched value of zero threshold event of PCNT_Un when threshold event interrupt
+         *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
+         *  valid. 0: others
+         */
+        uint32_t cnt_thr_zero_lat_un:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} pcnt_un_status_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Interrupt raw status register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_raw:1;
+        /** cnt_thr_event_u1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_raw:1;
+        /** cnt_thr_event_u2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_raw:1;
+        /** cnt_thr_event_u3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcnt_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Interrupt status register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_st:1;
+        /** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_st:1;
+        /** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_st:1;
+        /** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcnt_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_ena:1;
+        /** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_ena:1;
+        /** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_ena:1;
+        /** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcnt_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_clr:1;
+        /** cnt_thr_event_u1_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_clr:1;
+        /** cnt_thr_event_u2_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_clr:1;
+        /** cnt_thr_event_u3_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcnt_int_clr_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  PCNT version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 35721985;
+         *  This is the PCNT version control register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} pcnt_date_reg_t;
+
+
+typedef struct {
+    volatile pcnt_un_conf0_reg_t u0_conf0;
+    volatile pcnt_un_conf1_reg_t u0_conf1;
+    volatile pcnt_un_conf2_reg_t u0_conf2;
+    volatile pcnt_un_conf0_reg_t u1_conf0;
+    volatile pcnt_un_conf1_reg_t u1_conf1;
+    volatile pcnt_un_conf2_reg_t u1_conf2;
+    volatile pcnt_un_conf0_reg_t u2_conf0;
+    volatile pcnt_un_conf1_reg_t u2_conf1;
+    volatile pcnt_un_conf2_reg_t u2_conf2;
+    volatile pcnt_un_conf0_reg_t u3_conf0;
+    volatile pcnt_un_conf1_reg_t u3_conf1;
+    volatile pcnt_un_conf2_reg_t u3_conf2;
+    volatile pcnt_un_cnt_reg_t un_cnt[4];
+    volatile pcnt_int_raw_reg_t int_raw;
+    volatile pcnt_int_st_reg_t int_st;
+    volatile pcnt_int_ena_reg_t int_ena;
+    volatile pcnt_int_clr_reg_t int_clr;
+    volatile pcnt_un_status_reg_t un_status[4];
+    volatile pcnt_ctrl_reg_t ctrl;
+    volatile pcnt_u3_change_conf_reg_t u3_change_conf;
+    volatile pcnt_u2_change_conf_reg_t u2_change_conf;
+    volatile pcnt_u1_change_conf_reg_t u1_change_conf;
+    volatile pcnt_u0_change_conf_reg_t u0_change_conf;
+    uint32_t reserved_074[34];
+    volatile pcnt_date_reg_t date;
+} pcnt_dev_t;
+
+extern pcnt_dev_t PCNT;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/pcnt_struct.h

@@ -0,0 +1,442 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Register */
+/** Type of un_conf0 register
+ *  Configuration register 0 for unit n
+ */
+typedef union {
+    struct {
+        /** filter_thres : R/W; bitpos: [9:0]; default: 16;
+         *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
+         *
+         *  Any pulses with width less than this will be ignored when the filter is enabled.
+         */
+        uint32_t filter_thres:10;
+        /** filter_en : R/W; bitpos: [10]; default: 1;
+         *  This is the enable bit for unit n's input filter.
+         */
+        uint32_t filter_en:1;
+        /** thr_zero_en : R/W; bitpos: [11]; default: 1;
+         *  This is the enable bit for unit n's zero comparator.
+         */
+        uint32_t thr_zero_en:1;
+        /** thr_h_lim_en : R/W; bitpos: [12]; default: 1;
+         *  This is the enable bit for unit n's thr_h_lim comparator. Configures it to enable
+         *  the high limit interrupt.
+         */
+        uint32_t thr_h_lim_en:1;
+        /** thr_l_lim_en : R/W; bitpos: [13]; default: 1;
+         *  This is the enable bit for unit n's thr_l_lim comparator. Configures it to enable
+         *  the low limit interrupt.
+         */
+        uint32_t thr_l_lim_en:1;
+        /** thr_thres0_en : R/W; bitpos: [14]; default: 0;
+         *  This is the enable bit for unit n's thres0 comparator.
+         */
+        uint32_t thr_thres0_en:1;
+        /** thr_thres1_en : R/W; bitpos: [15]; default: 0;
+         *  This is the enable bit for unit n's thres1 comparator.
+         */
+        uint32_t thr_thres1_en:1;
+        /** ch0_neg_mode : R/W; bitpos: [17:16]; default: 0;
+         *  This register sets the behavior when the signal input of channel 0 detects a
+         *  negative edge.
+         *
+         *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
+         */
+        uint32_t ch0_neg_mode:2;
+        /** ch0_pos_mode : R/W; bitpos: [19:18]; default: 0;
+         *  This register sets the behavior when the signal input of channel 0 detects a
+         *  positive edge.
+         *
+         *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
+         */
+        uint32_t ch0_pos_mode:2;
+        /** ch0_hctrl_mode : R/W; bitpos: [21:20]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is high.
+         *
+         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+         *  increase).2, 3: Inhibit counter modification
+         */
+        uint32_t ch0_hctrl_mode:2;
+        /** ch0_lctrl_mode : R/W; bitpos: [23:22]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is low.
+         *
+         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+         *  increase).2, 3: Inhibit counter modification
+         */
+        uint32_t ch0_lctrl_mode:2;
+        /** ch1_neg_mode : R/W; bitpos: [25:24]; default: 0;
+         *  This register sets the behavior when the signal input of channel 1 detects a
+         *  negative edge.
+         *
+         *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
+         */
+        uint32_t ch1_neg_mode:2;
+        /** ch1_pos_mode : R/W; bitpos: [27:26]; default: 0;
+         *  This register sets the behavior when the signal input of channel 1 detects a
+         *  positive edge.
+         *
+         *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
+         */
+        uint32_t ch1_pos_mode:2;
+        /** ch1_hctrl_mode : R/W; bitpos: [29:28]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is high.
+         *
+         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+         *  increase).2, 3: Inhibit counter modification
+         */
+        uint32_t ch1_hctrl_mode:2;
+        /** ch1_lctrl_mode : R/W; bitpos: [31:30]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is low.
+         *
+         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
+         *  increase).2, 3: Inhibit counter modification
+         */
+        uint32_t ch1_lctrl_mode:2;
+    };
+    uint32_t val;
+} pcnt_un_conf0_reg_t;
+
+/** Type of un_conf1 register
+ *  Configuration register 1 for unit n
+ */
+typedef union {
+    struct {
+        /** cnt_thres0 : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to configure the thres0 value for unit n.
+         */
+        uint32_t cnt_thres0:16;
+        /** cnt_thres1 : R/W; bitpos: [31:16]; default: 0;
+         *  This register is used to configure the thres1 value for unit n.
+         */
+        uint32_t cnt_thres1:16;
+    };
+    uint32_t val;
+} pcnt_un_conf1_reg_t;
+
+/** Type of un_conf2 register
+ *  Configuration register 2 for unit n
+ */
+typedef union {
+    struct {
+        /** cnt_h_lim : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to configure the thr_h_lim value for unit n. When pcnt
+         *  reaches this value, the counter will be cleared to 0.
+         */
+        uint32_t cnt_h_lim:16;
+        /** cnt_l_lim : R/W; bitpos: [31:16]; default: 0;
+         *  This register is used to configure the thr_l_lim value for unit n. When pcnt
+         *  reaches this value, the counter will be cleared to 0.
+         */
+        uint32_t cnt_l_lim:16;
+    };
+    uint32_t val;
+} pcnt_un_conf2_reg_t;
+
+/** Type of ctrl register
+ *  Control register for all counters
+ */
+typedef union {
+    struct {
+        /** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to clear unit 0's counter.
+         */
+        uint32_t pulse_cnt_rst_u0:1;
+        /** cnt_pause_u0 : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to freeze unit 0's counter.
+         */
+        uint32_t cnt_pause_u0:1;
+        /** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to clear unit 1's counter.
+         */
+        uint32_t pulse_cnt_rst_u1:1;
+        /** cnt_pause_u1 : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to freeze unit 1's counter.
+         */
+        uint32_t cnt_pause_u1:1;
+        /** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to clear unit 2's counter.
+         */
+        uint32_t pulse_cnt_rst_u2:1;
+        /** cnt_pause_u2 : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to freeze unit 2's counter.
+         */
+        uint32_t cnt_pause_u2:1;
+        /** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1;
+         *  Set this bit to clear unit 3's counter.
+         */
+        uint32_t pulse_cnt_rst_u3:1;
+        /** cnt_pause_u3 : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to freeze unit 3's counter.
+         */
+        uint32_t cnt_pause_u3:1;
+        /** delta_change_en_u0 : R/W; bitpos: [8]; default: 0;
+         *  Configures this bit to enable unit 0's step comparator.
+         */
+        uint32_t delta_change_en_u0:1;
+        /** delta_change_en_u1 : R/W; bitpos: [9]; default: 0;
+         *  Configures this bit to enable unit 1's step comparator.
+         */
+        uint32_t delta_change_en_u1:1;
+        /** delta_change_en_u2 : R/W; bitpos: [10]; default: 0;
+         *  Configures this bit to enable unit 2's step comparator.
+         */
+        uint32_t delta_change_en_u2:1;
+        /** delta_change_en_u3 : R/W; bitpos: [11]; default: 0;
+         *  Configures this bit to enable unit 3's step comparator.
+         */
+        uint32_t delta_change_en_u3:1;
+        uint32_t reserved_12:4;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  The registers clock gate enable signal of PCNT module. 1: the registers can be read
+         *  and written by application. 0: the registers can not be read or written by
+         *  application
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} pcnt_ctrl_reg_t;
+
+/** Type of change_conf register
+ *  Configuration register for unit $n's step value.
+ */
+typedef union {
+    struct {
+        /** cnt_step : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the step value for unit n.
+         */
+        uint32_t cnt_step:16;
+        /** cnt_step_lim : R/W; bitpos: [31:16]; default: 0;
+         *  Configures the step limit value for unit n.
+         */
+        uint32_t cnt_step_lim:16;
+    };
+    uint32_t val;
+} pcnt_un_change_conf_reg_t;
+
+
+/** Group: Status Register */
+/** Type of un_cnt register
+ *  Counter value for unit n
+ */
+typedef union {
+    struct {
+        /** pulse_cnt : RO; bitpos: [15:0]; default: 0;
+         *  This register stores the current pulse count value for unit n.
+         */
+        uint32_t pulse_cnt:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} pcnt_un_cnt_reg_t;
+
+/** Type of un_status register
+ *  PNCT UNITn status register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_zero_mode : RO; bitpos: [1:0]; default: 0;
+         *  The pulse counter status of PCNT corresponding to 0. 0: pulse counter decreases
+         *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
+         *  is negative. 3: pulse counter is positive.
+         */
+        uint32_t cnt_thr_zero_mode:2;
+        /** cnt_thr_thres1_lat : RO; bitpos: [2]; default: 0;
+         *  The latched value of thres1 event of PCNT when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
+         *  others
+         */
+        uint32_t cnt_thr_thres1_lat:1;
+        /** cnt_thr_thres0_lat : RO; bitpos: [3]; default: 0;
+         *  The latched value of thres0 event of PCNT when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
+         *  others
+         */
+        uint32_t cnt_thr_thres0_lat:1;
+        /** cnt_thr_l_lim_lat : RO; bitpos: [4]; default: 0;
+         *  The latched value of low limit event of PCNT when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
+         *  valid. 0: others
+         */
+        uint32_t cnt_thr_l_lim_lat:1;
+        /** cnt_thr_h_lim_lat : RO; bitpos: [5]; default: 0;
+         *  The latched value of high limit event of PCNT when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
+         *  valid. 0: others
+         */
+        uint32_t cnt_thr_h_lim_lat:1;
+        /** cnt_thr_zero_lat : RO; bitpos: [6]; default: 0;
+         *  The latched value of zero threshold event of PCNT when threshold event interrupt
+         *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
+         *  valid. 0: others
+         */
+        uint32_t cnt_thr_zero_lat:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} pcnt_un_status_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Interrupt raw status register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_raw:1;
+        /** cnt_thr_event_u1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_raw:1;
+        /** cnt_thr_event_u2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_raw:1;
+        /** cnt_thr_event_u3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcnt_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Interrupt status register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_st:1;
+        /** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_st:1;
+        /** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_st:1;
+        /** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcnt_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_ena:1;
+        /** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_ena:1;
+        /** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_ena:1;
+        /** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcnt_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_clr:1;
+        /** cnt_thr_event_u1_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_clr:1;
+        /** cnt_thr_event_u2_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_clr:1;
+        /** cnt_thr_event_u3_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcnt_int_clr_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  PCNT version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 571021568;
+         *  This is the PCNT version control register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} pcnt_date_reg_t;
+
+typedef struct pcnt_dev_t {
+    volatile struct {
+        pcnt_un_conf0_reg_t conf0;
+        pcnt_un_conf1_reg_t conf1;
+        pcnt_un_conf2_reg_t conf2;
+    } conf_unit[4];
+    volatile pcnt_un_cnt_reg_t cnt_unit[4];
+    volatile pcnt_int_raw_reg_t int_raw;
+    volatile pcnt_int_st_reg_t int_st;
+    volatile pcnt_int_ena_reg_t int_ena;
+    volatile pcnt_int_clr_reg_t int_clr;
+    volatile pcnt_un_status_reg_t status_unit[4];
+    volatile pcnt_ctrl_reg_t ctrl;
+    volatile pcnt_un_change_conf_reg_t change_conf_unit[4]; // Note the unit order is 3210
+    uint32_t reserved_074[34];
+    volatile pcnt_date_reg_t date;
+} pcnt_dev_t;
+
+extern pcnt_dev_t PCNT;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/pmu_struct.h

@@ -0,0 +1,942 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/pmu_reg.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: IDF-13420
+
+typedef union {
+    struct {
+        uint32_t reserved0    : 21;
+        uint32_t dcdc_switch_pd_en :1;
+        uint32_t mem_dslp     : 1;
+        uint32_t mem_pd_en    : 1;
+        uint32_t reserved1    : 6;
+        uint32_t cnnt_pd_en   : 1;
+        uint32_t top_pd_en    : 1;
+    };
+    uint32_t val;
+} pmu_hp_dig_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 23;
+        uint32_t power_det_bypass : 1;
+        uint32_t uart_wakeup_en : 1;
+        uint32_t lp_pad_hold_all: 1;
+        uint32_t hp_pad_hold_all: 1;
+        uint32_t dig_pad_slp_sel: 1;
+        uint32_t dig_pause_wdt  : 1;
+        uint32_t dig_cpu_stall  : 1;
+        uint32_t reserved1      : 2;
+    };
+    uint32_t val;
+} pmu_hp_sys_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0    : 21;
+        uint32_t i2c_iso_en   : 1;
+        uint32_t i2c_retention: 1;
+        uint32_t xpd_pll_i2c  : 4;
+        uint32_t xpd_pll      : 4;
+        uint32_t reserved1    : 1;
+    };
+    uint32_t val;
+} pmu_hp_clk_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 18;
+        uint32_t dcm_vset  : 5;
+        uint32_t dcm_mode  : 2;
+        uint32_t xpd_bias  : 1;
+        uint32_t dbg_atten : 4;
+        uint32_t pd_cur    : 1;
+        uint32_t bias_sleep: 1;
+    };
+    uint32_t val;
+} pmu_hp_bias_reg_t;
+
+typedef union {
+    struct {    /* HP: Active State */
+        uint32_t reserved0                            : 4;
+        uint32_t hp_sleep2active_backup_modem_clk_code: 2;
+        uint32_t hp_modem2active_backup_modem_clk_code: 2;
+        uint32_t reserved1                            : 2;
+        uint32_t hp_active_retention_mode             : 1;
+        uint32_t hp_sleep2active_retention_en         : 1;
+        uint32_t hp_modem2active_retention_en         : 1;
+        uint32_t reserved2                            : 1;
+        uint32_t hp_sleep2active_backup_clk_sel       : 2;
+        uint32_t hp_modem2active_backup_clk_sel       : 2;
+        uint32_t reserved3                            : 2;
+        uint32_t hp_sleep2active_backup_mode          : 3;
+        uint32_t hp_modem2active_backup_mode          : 3;
+        uint32_t reserved4                            : 3;
+        uint32_t hp_sleep2active_backup_en            : 1;
+        uint32_t hp_modem2active_backup_en            : 1;
+        uint32_t reserved5                            : 1;
+    };
+    struct {    /* HP: Modem State */
+        uint32_t reserved6                            : 32;
+    };
+    struct {    /* HP: Sleep State */
+        uint32_t reserved12                           : 6;
+        uint32_t hp_modem2sleep_backup_modem_clk_code : 2;
+        uint32_t hp_active2sleep_backup_modem_clk_code: 2;
+        uint32_t hp_sleep_retention_mode              : 1;
+        uint32_t reserved13                           : 1;
+        uint32_t hp_modem2sleep_retention_en          : 1;
+        uint32_t hp_active2sleep_retention_en         : 1;
+        uint32_t reserved14                           : 2;
+        uint32_t hp_modem2sleep_backup_clk_sel        : 2;
+        uint32_t hp_active2sleep_backup_clk_sel       : 2;
+        uint32_t reserved15                           : 3;
+        uint32_t hp_modem2sleep_backup_mode           : 3;
+        uint32_t hp_active2sleep_backup_mode          : 3;
+        uint32_t reserved16                           : 1;
+        uint32_t hp_modem2sleep_backup_en             : 1;
+        uint32_t hp_active2sleep_backup_en            : 1;
+    };
+    uint32_t val;
+} pmu_hp_backup_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0       : 26;
+        uint32_t dig_sysclk_nodiv: 1;
+        uint32_t icg_sysclk_en   : 1;
+        uint32_t sysclk_slp_sel  : 1;
+        uint32_t icg_slp_sel     : 1;
+        uint32_t dig_sysclk_sel  : 2;
+    };
+    uint32_t val;
+} pmu_hp_sysclk_reg_t;
+
+typedef union {
+    // For chip_revsion < 1.0
+    struct {
+        uint32_t reserved0      : 4;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t lp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t hp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t dbias_sel      : 1;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t dbias_init     : 1;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t slp_mem_xpd    : 1;
+        uint32_t slp_logic_xpd  : 1;
+        uint32_t xpd            : 1;
+        uint32_t slp_mem_dbias  : 4;    /* slp_mem_dbias is not used on chip_revision < 100 */
+        uint32_t slp_logic_dbias: 4;
+        uint32_t dbias          : 5;
+    };
+    // For chip revision >= 100
+    struct {
+        uint32_t reserved1      : 19;
+        uint32_t xpd_0p1a       : 4;    /* slp_mem_dbias[3] is used to control the volt output of VO1 on chip_revision >= 1.0 */
+        uint32_t reserved2      : 9;
+    };
+    uint32_t val;
+} pmu_hp_regulator0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 26;
+        uint32_t drv_b    : 6;
+    };
+    uint32_t val;
+} pmu_hp_regulator1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t xpd_xtal : 1;
+    };
+    uint32_t val;
+} pmu_hp_xtal_reg_t;
+
+typedef struct pmu_hp_hw_regmap_t {
+    pmu_hp_dig_power_reg_t     dig_power;
+    uint32_t                   icg_func;
+    uint32_t                   icg_apb;
+    uint32_t                   icg_modem;
+    pmu_hp_sys_cntl_reg_t      syscntl;
+    pmu_hp_clk_power_reg_t     clk_power;
+    pmu_hp_bias_reg_t          bias;
+    pmu_hp_backup_reg_t        backup;
+    uint32_t                   backup_clk;
+    pmu_hp_sysclk_reg_t        sysclk;
+    pmu_hp_regulator0_reg_t    regulator0;
+    pmu_hp_regulator1_reg_t    regulator1;
+    pmu_hp_xtal_reg_t          xtal;
+} pmu_hp_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 21;
+        uint32_t slp_xpd  : 1;
+        uint32_t xpd      : 1;
+        uint32_t slp_dbias: 4;
+        uint32_t dbias    : 5;
+    };
+    uint32_t val;
+} pmu_lp_regulator0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 26;
+        uint32_t drv_b    : 6;
+    };
+    uint32_t val;
+} pmu_lp_regulator1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t xpd_xtal : 1;
+    };
+    uint32_t val;
+} pmu_lp_xtal_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 26;
+        uint32_t lp_pad_slp_sel : 1;
+        uint32_t bod_source_sel : 1;
+        uint32_t vddbat_mode : 2;
+        uint32_t mem_dslp  : 1;
+        uint32_t peri_pd_en: 1;
+    };
+    uint32_t val;
+} pmu_lp_dig_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0  : 27;
+        uint32_t xpd_lppll  : 1;
+        uint32_t xpd_xtal32k: 1;
+        uint32_t xpd_rc32k  : 1;
+        uint32_t xpd_fosc   : 1;
+        uint32_t pd_osc     : 1;
+    };
+    uint32_t val;
+} pmu_lp_clk_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 25;
+        uint32_t xpd_bias  : 1;
+        uint32_t dbg_atten : 4;
+        uint32_t pd_cur    : 1;
+        uint32_t bias_sleep: 1;
+    };
+    uint32_t val;
+} pmu_lp_bias_reg_t;
+
+typedef struct pmu_lp_hw_regmap_t {
+    pmu_lp_regulator0_reg_t    regulator0;
+    pmu_lp_regulator1_reg_t    regulator1;
+    pmu_lp_xtal_reg_t          xtal;   /* Only LP_SLEEP mode under lp system is valid */
+    pmu_lp_dig_power_reg_t     dig_power;
+    pmu_lp_clk_power_reg_t     clk_power;
+    pmu_lp_bias_reg_t          bias;   /* Only LP_SLEEP mode under lp system is valid */
+} pmu_lp_hw_regmap_t;
+
+
+typedef union {
+    struct {
+        uint32_t tie_low_cali_xtal_icg      : 1;
+        uint32_t tie_low_global_pll_icg     : 4;
+        uint32_t tie_low_global_xtal_icg    : 1;
+        uint32_t tie_low_i2c_retention      : 1;
+        uint32_t tie_low_xpd_pll_i2c        : 4;
+        uint32_t tie_low_xpd_pll            : 4;
+        uint32_t tie_low_xpd_xtal           : 1;
+        uint32_t tie_high_cali_xtal_icg     : 1;
+        uint32_t tie_high_global_pll_icg    : 4;
+        uint32_t tie_high_global_xtal_icg   : 1;
+        uint32_t tie_high_i2c_retention     : 1;
+        uint32_t tie_high_xpd_pll_i2c       : 4;
+        uint32_t tie_high_xpd_pll           : 4;
+        uint32_t tie_high_xpd_xtal          : 1;
+    };
+    uint32_t val;
+} pmu_imm_hp_clk_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0            : 28;
+        uint32_t update_dig_icg_switch: 1;
+        uint32_t tie_low_icg_slp_sel  : 1;
+        uint32_t tie_high_icg_slp_sel : 1;
+        uint32_t update_dig_sysclk_sel: 1;
+    };
+    uint32_t val;
+} pmu_imm_sleep_sysclk_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0             : 31;
+        uint32_t update_dig_icg_func_en: 1;
+    };
+    uint32_t val;
+} pmu_imm_hp_func_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0            : 31;
+        uint32_t update_dig_icg_apb_en: 1;
+    };
+    uint32_t val;
+} pmu_imm_hp_apb_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0              : 31;
+        uint32_t update_dig_icg_modem_en: 1;
+    };
+    uint32_t val;
+} pmu_imm_modem_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0              : 30;
+        uint32_t tie_low_lp_rootclk_sel : 1;
+        uint32_t tie_high_lp_rootclk_sel: 1;
+    };
+    uint32_t val;
+} pmu_imm_lp_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t pad_slp_sel             : 1;
+        uint32_t lp_pad_hold_all         : 1;
+        uint32_t hp_pad_hold_all         : 1;
+        uint32_t reserved0               : 23;
+        uint32_t tie_high_pad_slp_sel    : 1;
+        uint32_t tie_low_pad_slp_sel     : 1;
+        uint32_t tie_high_lp_pad_hold_all: 1;
+        uint32_t tie_low_lp_pad_hold_all : 1;
+        uint32_t tie_high_hp_pad_hold_all: 1;
+        uint32_t tie_low_hp_pad_hold_all : 1;
+    };
+    uint32_t val;
+} pmu_imm_pad_hold_all_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0          : 30;
+        uint32_t tie_high_i2c_iso_en: 1;
+        uint32_t tie_low_i2c_iso_en : 1;
+    };
+    uint32_t val;
+} pmu_imm_i2c_isolate_reg_t;
+
+typedef struct pmu_imm_hw_regmap_t {
+    pmu_imm_hp_clk_power_reg_t     clk_power;
+    pmu_imm_sleep_sysclk_reg_t     sleep_sysclk;
+    pmu_imm_hp_func_icg_reg_t      hp_func_icg;
+    pmu_imm_hp_apb_icg_reg_t       hp_apb_icg;
+    pmu_imm_modem_icg_reg_t        modem_icg;
+    pmu_imm_lp_icg_reg_t           lp_icg;
+    pmu_imm_pad_hold_all_reg_t     pad_hold_all;
+    pmu_imm_i2c_isolate_reg_t      i2c_iso;
+} pmu_imm_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 5;
+        uint32_t powerdown_timer: 9;
+        uint32_t powerup_timer  : 9;
+        uint32_t wait_timer     : 9;
+    };
+    uint32_t val;
+} pmu_power_wait_timer0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 5;
+        uint32_t powerdown_timer: 9;
+        uint32_t powerup_timer  : 9;
+        uint32_t wait_timer     : 9;
+    };
+    uint32_t val;
+} pmu_power_wait_timer1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t force_reset   : 1;
+        uint32_t force_iso     : 1;
+        uint32_t force_pu      : 1;
+        uint32_t force_no_reset: 1;
+        uint32_t force_no_iso  : 1;
+        uint32_t force_pd      : 1;
+        uint32_t reserved0     : 26;    /* Invalid of lp peripherals */
+    };
+    uint32_t val;
+} pmu_power_domain_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t pd_top_mask   : 5;
+        uint32_t reserved0     : 22;    /* Invalid of lp peripherals */
+        uint32_t top_pd_mask   : 5;
+    };
+    uint32_t val;
+} pmu_power_domain_mask_reg_t;
+
+typedef union {
+    struct {
+        uint32_t force_pu      :    1;
+        uint32_t force_pd      :    1;
+        uint32_t reserved2     :    30;
+    };
+    uint32_t val;
+} pmu_power_dcdc_switch_reg_t;
+
+typedef union {
+    struct {
+        uint32_t force_hp_pad_no_iso_all: 1;
+        uint32_t force_hp_pad_iso_all   : 1;
+        uint32_t reserved0              : 30;
+    };
+    uint32_t val;
+} pmu_power_hp_pad_reg_t;
+
+typedef union {
+    struct {
+        uint32_t wait_xtal_stable: 16;
+        uint32_t wait_pll_stable : 16;
+    };
+    uint32_t val;
+} pmu_power_clk_wait_cntl_reg_t;
+
+typedef struct pmu_power_hw_regmap_t {
+    pmu_power_wait_timer0_reg_t    wait_timer0;
+    pmu_power_wait_timer1_reg_t    wait_timer1;
+    pmu_power_domain_cntl_reg_t    hp_pd[3];
+    pmu_power_domain_mask_reg_t    hp_pd_mask[3];
+    pmu_power_dcdc_switch_reg_t    dcdc_switch;
+    pmu_power_domain_cntl_reg_t    lp_peri;
+    pmu_power_domain_mask_reg_t    lp_peri_mask;
+    pmu_power_hp_pad_reg_t         hp_pad;
+    pmu_power_clk_wait_cntl_reg_t  clk_wait;
+} pmu_power_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t sleep_req: 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t sleep_reject_ena: 31;
+        uint32_t slp_reject_en   : 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t wakeup_ena: 31;
+        uint32_t reserved0 : 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl2_reg_t;
+
+typedef union {
+    struct {
+        uint32_t lp_min_slp_val: 8;
+        uint32_t hp_min_slp_val: 8;
+        uint32_t sleep_prt_sel : 2;
+        uint32_t reserved0     : 14;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl3_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0           : 31;
+        uint32_t slp_reject_cause_clr: 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl4_reg_t;
+
+typedef union {
+    struct {
+        uint32_t modem_wait_target : 20;
+        uint32_t reserved0         : 4;
+        uint32_t lp_ana_wait_target: 8;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl5_reg_t;
+
+typedef union {
+    struct {
+        uint32_t soc_wakeup_wait    : 20;
+        uint32_t reserved0          : 10;
+        uint32_t soc_wakeup_wait_cfg: 2;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl6_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 16;
+        uint32_t ana_wait_target: 16;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl7_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0          : 31;
+        uint32_t lp_lite_wakeup_ena : 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl8_reg_t;
+
+typedef struct pmu_wakeup_hw_regmap_t {
+    pmu_slp_wakeup_cntl0_reg_t     cntl0;
+    pmu_slp_wakeup_cntl1_reg_t     cntl1;
+    pmu_slp_wakeup_cntl2_reg_t     cntl2;
+    pmu_slp_wakeup_cntl3_reg_t     cntl3;
+    pmu_slp_wakeup_cntl4_reg_t     cntl4;
+    pmu_slp_wakeup_cntl5_reg_t     cntl5;
+    pmu_slp_wakeup_cntl6_reg_t     cntl6;
+    pmu_slp_wakeup_cntl7_reg_t     cntl7;
+    pmu_slp_wakeup_cntl8_reg_t     cntl8;
+    uint32_t                       status0;
+    uint32_t                       status1;
+    uint32_t                       status2;
+} pmu_wakeup_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t i2c_por_wait_target: 8;
+        uint32_t reserved0          : 24;
+    };
+    uint32_t val;
+} pmu_hp_clk_poweron_reg_t;
+
+typedef union {
+    struct {
+        uint32_t modify_icg_cntl_wait: 8;
+        uint32_t switch_icg_cntl_wait: 8;
+        uint32_t reserved0           : 16;
+    };
+    uint32_t val;
+} pmu_hp_clk_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t por_done : 1;
+    };
+    uint32_t val;
+} pmu_por_status_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0     : 24;
+        uint32_t mspi_phy_xpd  : 1;
+        uint32_t sdio_pll_xpd  : 1;
+        uint32_t perif_i2c_rstb: 1;
+        uint32_t xpd_perif_i2c : 1;
+        uint32_t xpd_txrf_i2c  : 1;
+        uint32_t xpd_rfrx_pbus : 1;
+        uint32_t xpd_ckgen_i2c : 1;
+        uint32_t reserved1     : 1;
+    };
+    uint32_t val;
+} pmu_rf_pwc_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0          : 31;
+        uint32_t backup_sysclk_nodiv: 1;
+    };
+    uint32_t val;
+} pmu_backup_cfg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0   : 14;
+        uint32_t pmu_0p1a_cnt_target0_reach_0 : 1;
+        uint32_t pmu_0p1a_cnt_target1_reach_0 : 1;
+        uint32_t pmu_0p1a_cnt_target0_reach_1 : 1;
+        uint32_t pmu_0p1a_cnt_target1_reach_1 : 1;
+        uint32_t pmu_0p2a_cnt_target0_reach_0 : 1;
+        uint32_t pmu_0p2a_cnt_target1_reach_0 : 1;
+        uint32_t pmu_0p2a_cnt_target0_reach_1 : 1;
+        uint32_t pmu_0p2a_cnt_target1_reach_1 : 1;
+        uint32_t pmu_0p3a_cnt_target0_reach_0 : 1;
+        uint32_t pmu_0p3a_cnt_target1_reach_0 : 1;
+        uint32_t pmu_0p3a_cnt_target0_reach_1 : 1;
+        uint32_t pmu_0p3a_cnt_target1_reach_1 : 1;
+        uint32_t reserved1   : 1;
+        uint32_t lp_exception: 1;
+        uint32_t sdio_idle: 1;
+        uint32_t sw       : 1;
+        uint32_t reject   : 1;
+        uint32_t wakeup   : 1;
+    };
+    uint32_t val;
+} pmu_hp_intr_reg_t;
+
+typedef struct pmu_hp_ext_hw_regmap_t {
+    pmu_hp_clk_poweron_reg_t   clk_poweron;
+    pmu_hp_clk_cntl_reg_t      clk_cntl;
+    pmu_por_status_reg_t       por_status;
+    pmu_rf_pwc_reg_t           rf_pwc;
+    pmu_backup_cfg_reg_t       backup_cfg;
+    pmu_hp_intr_reg_t          int_raw;
+    pmu_hp_intr_reg_t          int_st;
+    pmu_hp_intr_reg_t          int_ena;
+    pmu_hp_intr_reg_t          int_clr;
+} pmu_hp_ext_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0                    : 13;
+        uint32_t sleep_reject                 : 1;
+        uint32_t pmu_0p1a_cnt_target0_reach_0 : 1;
+        uint32_t pmu_0p1a_cnt_target1_reach_0 : 1;
+        uint32_t pmu_0p1a_cnt_target0_reach_1 : 1;
+        uint32_t pmu_0p1a_cnt_target1_reach_1 : 1;
+        uint32_t pmu_0p2a_cnt_target0_reach_0 : 1;
+        uint32_t pmu_0p2a_cnt_target1_reach_0 : 1;
+        uint32_t pmu_0p2a_cnt_target0_reach_1 : 1;
+        uint32_t pmu_0p2a_cnt_target1_reach_1 : 1;
+        uint32_t pmu_0p3a_cnt_target0_reach_0 : 1;
+        uint32_t pmu_0p3a_cnt_target1_reach_0 : 1;
+        uint32_t pmu_0p3a_cnt_target0_reach_1 : 1;
+        uint32_t pmu_0p3a_cnt_target1_reach_1 : 1;
+        uint32_t lp_wakeup                    : 1;
+        uint32_t sleep_switch_active_end      : 1;
+        uint32_t active_switch_sleep_end      : 1;
+        uint32_t sleep_switch_active_start    : 1;
+        uint32_t active_switch_sleep_start    : 1;
+        uint32_t hp_sw_trigger                : 1;
+    };
+    uint32_t val;
+} pmu_lp_intr_reg_t;
+
+typedef union {
+    struct {
+        uint32_t waiti_rdy         : 1;
+        uint32_t stall_rdy         : 1;
+        uint32_t reserved0         : 16;
+        uint32_t force_stall       : 1;
+        uint32_t slp_waiti_flag_en : 1;
+        uint32_t slp_stall_flag_en : 1;
+        uint32_t slp_stall_wait    : 8;
+        uint32_t slp_stall_en      : 1;
+        uint32_t slp_reset_en      : 1;
+        uint32_t slp_bypass_intr_en: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t sleep_req: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t wakeup_en: 31;
+        uint32_t reserved0: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr2_reg_t;
+
+typedef union {
+    struct {
+        uint32_t wakeup_cause: 31;
+        uint32_t reserved0: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr3_reg_t;
+
+typedef union {
+    struct {
+        uint32_t sleep_reject: 31;
+        uint32_t reserved0: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr4_reg_t;
+
+typedef union {
+    struct {
+        uint32_t sleep_reject_cause: 31;
+        uint32_t reserved0: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr5_reg_t;
+
+typedef struct pmu_lp_ext_hw_regmap_t {
+    pmu_lp_intr_reg_t          int_raw;
+    pmu_lp_intr_reg_t          int_st;
+    pmu_lp_intr_reg_t          int_ena;
+    pmu_lp_intr_reg_t          int_clr;
+    pmu_lp_cpu_pwr0_reg_t      pwr0;
+    pmu_lp_cpu_pwr1_reg_t      pwr1;
+    pmu_lp_cpu_pwr2_reg_t      pwr2;
+    pmu_lp_cpu_pwr3_reg_t      pwr3;
+    pmu_lp_cpu_pwr4_reg_t      pwr4;
+    pmu_lp_cpu_pwr5_reg_t      pwr5;
+} pmu_lp_ext_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved_0:7;
+        uint32_t force_tieh_sel:1;
+        uint32_t xpd:1;
+        uint32_t tieh_sel:3;
+        uint32_t tieh_pos_en:1;
+        uint32_t tieh_neg_en:1;
+        uint32_t tieh:1;
+        uint32_t target1:8;
+        uint32_t target0:8;
+        uint32_t ldo_cnt_prescaler_sel:1;
+    };
+    uint32_t val;
+} pmu_ext_ldo_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved_0:23;
+        uint32_t mul:3;
+        uint32_t en_vdet:1;
+        uint32_t en_cur_lim:1;
+        uint32_t dref:4;
+    };
+    uint32_t val;
+} pmu_ext_ldo_ana_reg_t;
+
+
+typedef struct pmu_ext_ldo_info_t {
+    pmu_ext_ldo_reg_t pmu_ext_ldo;
+    pmu_ext_ldo_ana_reg_t pmu_ext_ldo_ana;
+} pmu_ext_ldo_info_t;
+
+
+typedef union {
+    struct {
+        uint32_t on_req        : 1;
+        uint32_t off_req       : 1;
+        uint32_t lightslp_req  : 1;
+        uint32_t deepslp_req   : 1;
+        uint32_t reserved0     : 3;
+        uint32_t done_force    : 1;
+        uint32_t on_force_pu   : 1;
+        uint32_t on_force_pd   : 1;
+        uint32_t fb_res_force_pu   : 1;
+        uint32_t fb_res_force_pd   : 1;
+        uint32_t ls_force_pu   : 1;
+        uint32_t ls_force_pd   : 1;
+        uint32_t ds_force_pu   : 1;
+        uint32_t ds_force_pd   : 1;
+        uint32_t dcm_cur_st    : 8;
+        uint32_t reserved1     : 5;
+        uint32_t en_amux_test  : 1;
+        uint32_t reserved2     : 2;
+    };
+    uint32_t val;
+} pmu_dcm_ctrl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t pre_delay      : 8;
+        uint32_t res_off_delay  : 8;
+        uint32_t stable_delay   : 10;
+        uint32_t reserved0      : 6;
+    };
+    uint32_t val;
+} pmu_dcm_wait_delay_t;
+
+typedef union {
+    struct {
+        uint32_t ana_vddbat_mode    : 2;
+        uint32_t reserved1          : 29;
+        uint32_t sw_update          : 1;
+    };
+    uint32_t val;
+} pmu_vddbat_cfg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 5;
+        uint32_t wait_cycles    : 9;
+        uint32_t sleep_cycles   : 16;
+        uint32_t force_done     : 1;
+        uint32_t sleep_timer_en : 1;
+    };
+    uint32_t val;
+} pmu_touch_sensor_pwr_cntl_t;
+
+typedef struct pmu_dev_t {
+    volatile pmu_hp_hw_regmap_t     hp_sys[3];
+    volatile pmu_lp_hw_regmap_t     lp_sys[2];
+    volatile pmu_imm_hw_regmap_t    imm;
+    volatile pmu_power_hw_regmap_t  power;
+    volatile pmu_wakeup_hw_regmap_t wakeup;
+    volatile pmu_hp_ext_hw_regmap_t hp_ext;
+    volatile pmu_lp_ext_hw_regmap_t lp_ext;
+
+    union {
+        struct {
+            volatile uint32_t reserved0    : 30;
+            volatile uint32_t lp_trigger_hp: 1;
+            volatile uint32_t hp_trigger_lp: 1;
+        };
+        volatile uint32_t val;
+    } hp_lp_cpu_comm;
+
+    union {
+        struct {
+            volatile uint32_t reserved0           : 31;
+            volatile uint32_t dig_regulator_en_cal: 1;
+        };
+        volatile uint32_t val;
+    } hp_regulator_cfg;
+
+    union {
+        struct {
+            volatile uint32_t en_cali_pmu_cntl : 1;
+            volatile uint32_t reserved0 : 10;
+            volatile uint32_t last_st   : 7;
+            volatile uint32_t target_st : 7;
+            volatile uint32_t current_st: 7;
+        };
+        volatile uint32_t val;
+    } main_state;
+
+    union {
+        struct {
+            volatile uint32_t reserved0: 13;
+            volatile uint32_t backup_st: 5;
+            volatile uint32_t lp_pwr_st: 5;
+            volatile uint32_t hp_pwr_st: 9;
+        };
+        volatile int32_t val;
+    } pwr_state;
+
+    union {
+        struct {
+            volatile uint32_t stable_xpd_bbpll : 3;
+            volatile uint32_t stable_xpd_xtal  : 1;
+            volatile uint32_t ana_xpd_pll_i2c  : 3;
+            volatile uint32_t reserved0        : 3;
+            volatile uint32_t sysclk_slp_sel   : 1;
+            volatile uint32_t sysclk_sel       : 2;
+            volatile uint32_t sysclk_nodiv     : 1;
+            volatile uint32_t icg_sysclk_en    : 1;
+            volatile uint32_t icg_modem_switch : 1;
+            volatile uint32_t icg_modem_code   : 2;
+            volatile uint32_t icg_slp_sel      : 1;
+            volatile uint32_t icg_global_xtal  : 1;
+            volatile uint32_t icg_global_pll   : 4;
+            volatile uint32_t ana_i2c_iso_en   : 1;
+            volatile uint32_t ana_i2c_retention: 1;
+            volatile uint32_t reserved1        : 1;
+            volatile uint32_t ana_xpd_pll      : 4;
+            volatile uint32_t ana_xpd_xtal     : 1;
+        };
+        volatile uint32_t val;
+    } clk_state0;
+
+    volatile uint32_t clk_state1;
+    volatile uint32_t clk_state2;
+
+    volatile pmu_ext_ldo_info_t ext_ldo[6];
+
+    volatile uint32_t ext_wakeup_lv;
+    volatile uint32_t ext_wakeup_sel;
+    volatile uint32_t ext_wakeup_st;
+    union {
+        struct {
+            volatile uint32_t reserved0      : 30;
+            volatile uint32_t status_clr     : 1;
+            volatile uint32_t filter         : 1;
+        };
+        volatile uint32_t val;
+    } ext_wakeup_cntl;
+
+    union {
+        struct {
+            volatile uint32_t act_dnum   : 10;
+            volatile uint32_t reserved0  : 22;
+        };
+        volatile uint32_t val;
+    } sdio_wakeup_cntl;
+
+    union {
+        struct {
+            volatile uint32_t reserved0  : 16;
+            volatile uint32_t cnt_target : 16;
+        };
+        volatile uint32_t val;
+    } xtal_slp;
+
+    union {
+        struct {
+            volatile uint32_t reserved0  : 16;
+            volatile uint32_t hpcore1_stall_code : 8;
+            volatile uint32_t hpcore0_stall_code : 8;
+        };
+        volatile uint32_t val;
+    } cpu_sw_stall;
+
+    volatile pmu_dcm_ctrl_reg_t dcm_ctrl;
+    volatile pmu_dcm_wait_delay_t dcm_delay;
+    volatile pmu_vddbat_cfg_t vbat_cfg;
+    volatile pmu_touch_sensor_pwr_cntl_t touch_pwr_cntl;
+
+    union {
+        struct {
+            volatile uint32_t eco_result:1;
+            volatile uint32_t reserved0  : 30;
+            volatile uint32_t eco_en: 1;
+
+        };
+        volatile uint32_t val;
+    } pmu_rdn_eco;
+
+
+    uint32_t reserved[121];
+
+    union {
+        struct {
+            volatile uint32_t pmu_date: 31;
+            volatile uint32_t clk_en  : 1;
+        };
+        volatile uint32_t val;
+    } date;
+} pmu_dev_t;
+
+extern pmu_dev_t PMU;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure");
+
+_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_RDN_ECO_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/ppa_struct.h

@@ -0,0 +1,908 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of blend0_clut_data register
+ *  CLUT sram data read/write register in background plane of blender
+ */
+typedef union {
+    struct {
+        /** rdwr_word_blend0_clut : R/W; bitpos: [31:0]; default: 0;
+         *  Write and read data to/from CLUT RAM in background plane of blender engine through
+         *  this field in fifo mode.
+         */
+        uint32_t rdwr_word_blend0_clut:32;
+    };
+    uint32_t val;
+} ppa_blend0_clut_data_reg_t;
+
+/** Type of blend1_clut_data register
+ *  CLUT sram data read/write register in foreground plane of blender
+ */
+typedef union {
+    struct {
+        /** rdwr_word_blend1_clut : R/W; bitpos: [31:0]; default: 0;
+         *  Write and read data to/from CLUT RAM in foreground plane of blender engine through
+         *  this field in fifo mode.
+         */
+        uint32_t rdwr_word_blend1_clut:32;
+    };
+    uint32_t val;
+} ppa_blend1_clut_data_reg_t;
+
+/** Type of clut_conf register
+ *  CLUT configure register
+ */
+typedef union {
+    struct {
+        /** apb_fifo_mask : R/W; bitpos: [0]; default: 0;
+         *  1'b0: fifo mode to wr/rd clut0/clut1 RAM through register
+         *  PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1:
+         *  memory mode to wr/rd blend0/blend1 clut RAM. The bit 11 and 10 of the waddr
+         *  should be 01 to access blend0 clut and should be 10 to access blend1 clut in memory mode.
+         */
+        uint32_t apb_fifo_mask:1;
+        /** blend0_clut_mem_rst : R/W; bitpos: [1]; default: 0;
+         *  Write 1 then write 0 to this bit to reset BLEND0 CLUT.
+         */
+        uint32_t blend0_clut_mem_rst:1;
+        /** blend1_clut_mem_rst : R/W; bitpos: [2]; default: 0;
+         *  Write 1 then write 0 to this bit to reset BLEND1 CLUT.
+         */
+        uint32_t blend1_clut_mem_rst:1;
+        /** blend0_clut_mem_rdaddr_rst : R/W; bitpos: [3]; default: 0;
+         *  Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode.
+         */
+        uint32_t blend0_clut_mem_rdaddr_rst:1;
+        /** blend1_clut_mem_rdaddr_rst : R/W; bitpos: [4]; default: 0;
+         *  Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode.
+         */
+        uint32_t blend1_clut_mem_rdaddr_rst:1;
+        /** blend_clut_mem_force_pd : R/W; bitpos: [5]; default: 0;
+         *  1: force power down BLEND CLUT memory.
+         */
+        uint32_t blend_clut_mem_force_pd:1;
+        /** blend_clut_mem_force_pu : R/W; bitpos: [6]; default: 0;
+         *  1: force power up BLEND CLUT memory.
+         */
+        uint32_t blend_clut_mem_force_pu:1;
+        /** blend_clut_mem_clk_ena : R/W; bitpos: [7]; default: 0;
+         *  1: Force clock on for BLEND CLUT memory.
+         */
+        uint32_t blend_clut_mem_clk_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ppa_clut_conf_reg_t;
+
+/** Type of sr_color_mode register
+ *  Scaling and rotating engine color mode register
+ */
+typedef union {
+    struct {
+        /** sr_rx_cm : R/W; bitpos: [3:0]; default: 0;
+         *  The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1:
+         *  RGB888. 2: RGB565. 8: YUV420. others: Reserved.
+         */
+        uint32_t sr_rx_cm:4;
+        /** sr_tx_cm : R/W; bitpos: [7:4]; default: 0;
+         *  The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888.
+         *  1: RGB888. 2: RGB565. 8: YUV420. others: Reserved.
+         */
+        uint32_t sr_tx_cm:4;
+        /** yuv_rx_range : R/W; bitpos: [8]; default: 0;
+         *  YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range
+         */
+        uint32_t yuv_rx_range:1;
+        /** yuv_tx_range : R/W; bitpos: [9]; default: 0;
+         *  YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range
+         */
+        uint32_t yuv_tx_range:1;
+        /** yuv2rgb_protocol : R/W; bitpos: [10]; default: 0;
+         *  YUV to RGB protocol when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709
+         */
+        uint32_t yuv2rgb_protocol:1;
+        /** rgb2yuv_protocol : R/W; bitpos: [11]; default: 0;
+         *  RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709
+         */
+        uint32_t rgb2yuv_protocol:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} ppa_sr_color_mode_reg_t;
+
+/** Type of blend_color_mode register
+ *  blending engine color mode register
+ */
+typedef union {
+    struct {
+        /** blend0_rx_cm : R/W; bitpos: [3:0]; default: 0;
+         *  The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2:
+         *  RGB565. 3: Reserved. 4: L8. 5: L4.
+         */
+        uint32_t blend0_rx_cm:4;
+        /** blend1_rx_cm : R/W; bitpos: [7:4]; default: 0;
+         *  The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2:
+         *  RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4.
+         */
+        uint32_t blend1_rx_cm:4;
+        /** blend_tx_cm : R/W; bitpos: [11:8]; default: 0;
+         *  The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2:
+         *  RGB565. 3: Reserved..
+         */
+        uint32_t blend_tx_cm:4;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} ppa_blend_color_mode_reg_t;
+
+/** Type of sr_byte_order register
+ *  Scaling and rotating engine byte order register
+ */
+typedef union {
+    struct {
+        /** sr_rx_byte_swap_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1  the data into Rx channel 0 would be swapped in byte. The Byte0
+         *  and Byte1 would be swapped while byte 2 and byte 3 would be swappped.
+         */
+        uint32_t sr_rx_byte_swap_en:1;
+        /** sr_rx_rgb_swap_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to 1  the data into Rx channel 0 would be swapped in rgb. It means rgb
+         *  would be swap to bgr.
+         */
+        uint32_t sr_rx_rgb_swap_en:1;
+        /** sr_macro_bk_ro_bypass : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to bypass the macro block order function. This function is used
+         *  to improve efficient accessing external memory.
+         */
+        uint32_t sr_macro_bk_ro_bypass:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ppa_sr_byte_order_reg_t;
+
+/** Type of blend_byte_order register
+ *  Blending engine byte order register
+ */
+typedef union {
+    struct {
+        /** blend0_rx_byte_swap_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1  the data into Rx channel 0 would be swapped in byte. The Byte0
+         *  and Byte1 would be swapped while byte 2 and byte 3 would be swappped.
+         */
+        uint32_t blend0_rx_byte_swap_en:1;
+        /** blend1_rx_byte_swap_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to 1  the data into Rx channel 0 would be swapped in byte. The Byte0
+         *  and Byte1 would be swapped while byte 2 and byte 3 would be swappped.
+         */
+        uint32_t blend1_rx_byte_swap_en:1;
+        /** blend0_rx_rgb_swap_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1  the data into Rx channel 0 would be swapped in rgb. It means rgb
+         *  would be swap to bgr.
+         */
+        uint32_t blend0_rx_rgb_swap_en:1;
+        /** blend1_rx_rgb_swap_en : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to 1  the data into Rx channel 0 would be swapped in rgb. It means rgb
+         *  would be swap to bgr.
+         */
+        uint32_t blend1_rx_rgb_swap_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ppa_blend_byte_order_reg_t;
+
+/** Type of blend_trans_mode register
+ *  Blending engine mode configure register
+ */
+typedef union {
+    struct {
+        /** blend_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable alpha blending.
+         */
+        uint32_t blend_en:1;
+        /** blend_bypass : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to bypass blender. Then background date would be output.
+         */
+        uint32_t blend_bypass:1;
+        /** blend_fix_pixel_fill_en : R/W; bitpos: [2]; default: 0;
+         *  This bit is used to enable fix pixel filling. When this mode is enable  only Tx
+         *  channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL.
+         */
+        uint32_t blend_fix_pixel_fill_en:1;
+        /** blend_trans_mode_update : WT; bitpos: [3]; default: 0;
+         *  Set this bit to update the transfer mode. Only the bit is set  the transfer mode is
+         *  valid.
+         */
+        uint32_t blend_trans_mode_update:1;
+        /** blend_rst : R/W; bitpos: [4]; default: 0;
+         *  write 1 then write 0 to reset blending engine.
+         */
+        uint32_t blend_rst:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} ppa_blend_trans_mode_reg_t;
+
+/** Type of sr_fix_alpha register
+ *  Scaling and rotating engine alpha override register
+ */
+typedef union {
+    struct {
+        /** sr_rx_fix_alpha : R/W; bitpos: [7:0]; default: 128;
+         *  The value would replace the alpha value in received pixel for Scaling and Rotating
+         *  engine when PPA_SR_RX_ALPHA_CONF_EN is enabled.
+         */
+        uint32_t sr_rx_fix_alpha:8;
+        /** sr_rx_alpha_mod : R/W; bitpos: [9:8]; default: 0;
+         *  Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2:
+         *  Original alpha multiply with PPA_SR_FIX_ALPHA/256.
+         */
+        uint32_t sr_rx_alpha_mod:2;
+        /** sr_rx_alpha_inv : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to invert the original alpha value. When RX color mode is
+         *  RGB565/RGB88. The original alpha value is 255.
+         */
+        uint32_t sr_rx_alpha_inv:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} ppa_sr_fix_alpha_reg_t;
+
+/** Type of blend_tx_size register
+ *  Fix pixel filling mode image size register
+ */
+typedef union {
+    struct {
+        /** blend_hb : R/W; bitpos: [13:0]; default: 0;
+         *  The horizontal width of image block that would be filled in fix pixel filling mode.
+         *  The unit is pixel
+         */
+        uint32_t blend_hb:14;
+        /** blend_vb : R/W; bitpos: [27:14]; default: 0;
+         *  The vertical width of image block that would be filled in fix pixel filling mode.
+         *  The unit is pixel
+         */
+        uint32_t blend_vb:14;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ppa_blend_tx_size_reg_t;
+
+/** Type of blend_fix_alpha register
+ *  Blending engine alpha override register
+ */
+typedef union {
+    struct {
+        /** blend0_rx_fix_alpha : R/W; bitpos: [7:0]; default: 128;
+         *  The value would replace the alpha value in received pixel for background plane of
+         *  blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled.
+         */
+        uint32_t blend0_rx_fix_alpha:8;
+        /** blend1_rx_fix_alpha : R/W; bitpos: [15:8]; default: 128;
+         *  The value would replace the alpha value in received pixel for foreground plane of
+         *  blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled.
+         */
+        uint32_t blend1_rx_fix_alpha:8;
+        /** blend0_rx_alpha_mod : R/W; bitpos: [17:16]; default: 0;
+         *  Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2:
+         *  Original alpha multiply with PPA_SR_FIX_ALPHA/256.
+         */
+        uint32_t blend0_rx_alpha_mod:2;
+        /** blend1_rx_alpha_mod : R/W; bitpos: [19:18]; default: 0;
+         *  Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2:
+         *  Original alpha multiply with PPA_SR_FIX_ALPHA/256.
+         */
+        uint32_t blend1_rx_alpha_mod:2;
+        /** blend0_rx_alpha_inv : R/W; bitpos: [20]; default: 0;
+         *  Set this bit to invert the original alpha value. When RX color mode is
+         *  RGB565/RGB88. The original alpha value is 255.
+         */
+        uint32_t blend0_rx_alpha_inv:1;
+        /** blend1_rx_alpha_inv : R/W; bitpos: [21]; default: 0;
+         *  Set this bit to invert the original alpha value. When RX color mode is
+         *  RGB565/RGB88. The original alpha value is 255.
+         */
+        uint32_t blend1_rx_alpha_inv:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} ppa_blend_fix_alpha_reg_t;
+
+/** Type of blend_rgb register
+ *  RGB color register
+ */
+typedef union {
+    struct {
+        /** blend1_rx_b : R/W; bitpos: [7:0]; default: 128;
+         *  blue color for A4/A8 mode.
+         */
+        uint32_t blend1_rx_b:8;
+        /** blend1_rx_g : R/W; bitpos: [15:8]; default: 128;
+         *  green color for A4/A8 mode.
+         */
+        uint32_t blend1_rx_g:8;
+        /** blend1_rx_r : R/W; bitpos: [23:16]; default: 128;
+         *  red color for A4/A8 mode.
+         */
+        uint32_t blend1_rx_r:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} ppa_blend_rgb_reg_t;
+
+/** Type of blend_fix_pixel register
+ *  Blending engine fix pixel register
+ */
+typedef union {
+    struct {
+        /** blend_tx_fix_pixel : R/W; bitpos: [31:0]; default: 0;
+         *  The configure fix pixel in fix pixel filling mode for blender engine.
+         */
+        uint32_t blend_tx_fix_pixel:32;
+    };
+    uint32_t val;
+} ppa_blend_fix_pixel_reg_t;
+
+/** Type of ck_fg_low register
+ *  foreground color key lower threshold
+ */
+typedef union {
+    struct {
+        /** colorkey_fg_b_low : R/W; bitpos: [7:0]; default: 255;
+         *  color key lower threshold of foreground b channel
+         */
+        uint32_t colorkey_fg_b_low:8;
+        /** colorkey_fg_g_low : R/W; bitpos: [15:8]; default: 255;
+         *  color key lower threshold of foreground g channel
+         */
+        uint32_t colorkey_fg_g_low:8;
+        /** colorkey_fg_r_low : R/W; bitpos: [23:16]; default: 255;
+         *  color key lower threshold of foreground r channel
+         */
+        uint32_t colorkey_fg_r_low:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} ppa_ck_fg_low_reg_t;
+
+/** Type of ck_fg_high register
+ *  foreground color key higher threshold
+ */
+typedef union {
+    struct {
+        /** colorkey_fg_b_high : R/W; bitpos: [7:0]; default: 0;
+         *  color key higher threshold of foreground b channel
+         */
+        uint32_t colorkey_fg_b_high:8;
+        /** colorkey_fg_g_high : R/W; bitpos: [15:8]; default: 0;
+         *  color key higher threshold of foreground g channel
+         */
+        uint32_t colorkey_fg_g_high:8;
+        /** colorkey_fg_r_high : R/W; bitpos: [23:16]; default: 0;
+         *  color key higher threshold of foreground r channel
+         */
+        uint32_t colorkey_fg_r_high:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} ppa_ck_fg_high_reg_t;
+
+/** Type of ck_bg_low register
+ *  background color key lower threshold
+ */
+typedef union {
+    struct {
+        /** colorkey_bg_b_low : R/W; bitpos: [7:0]; default: 255;
+         *  color key lower threshold of background b channel
+         */
+        uint32_t colorkey_bg_b_low:8;
+        /** colorkey_bg_g_low : R/W; bitpos: [15:8]; default: 255;
+         *  color key lower threshold of background g channel
+         */
+        uint32_t colorkey_bg_g_low:8;
+        /** colorkey_bg_r_low : R/W; bitpos: [23:16]; default: 255;
+         *  color key lower threshold of background r channel
+         */
+        uint32_t colorkey_bg_r_low:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} ppa_ck_bg_low_reg_t;
+
+/** Type of ck_bg_high register
+ *  background color key higher threshold
+ */
+typedef union {
+    struct {
+        /** colorkey_bg_b_high : R/W; bitpos: [7:0]; default: 0;
+         *  color key higher threshold of background b channel
+         */
+        uint32_t colorkey_bg_b_high:8;
+        /** colorkey_bg_g_high : R/W; bitpos: [15:8]; default: 0;
+         *  color key higher threshold of background g channel
+         */
+        uint32_t colorkey_bg_g_high:8;
+        /** colorkey_bg_r_high : R/W; bitpos: [23:16]; default: 0;
+         *  color key higher threshold of background r channel
+         */
+        uint32_t colorkey_bg_r_high:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} ppa_ck_bg_high_reg_t;
+
+/** Type of ck_default register
+ *  default value when foreground and background both in color key range
+ */
+typedef union {
+    struct {
+        /** colorkey_default_b : R/W; bitpos: [7:0]; default: 0;
+         *  default B channel value of color key
+         */
+        uint32_t colorkey_default_b:8;
+        /** colorkey_default_g : R/W; bitpos: [15:8]; default: 0;
+         *  default G channel value of color key
+         */
+        uint32_t colorkey_default_g:8;
+        /** colorkey_default_r : R/W; bitpos: [23:16]; default: 0;
+         *  default R channel value of color key
+         */
+        uint32_t colorkey_default_r:8;
+        /** colorkey_fg_bg_reverse : R/W; bitpos: [24]; default: 0;
+         *  when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the
+         *  result is fg
+         */
+        uint32_t colorkey_fg_bg_reverse:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} ppa_ck_default_reg_t;
+
+/** Type of sr_scal_rotate register
+ *  Scaling and rotating coefficient register
+ */
+typedef union {
+    struct {
+        /** sr_scal_x_int : R/W; bitpos: [7:0]; default: 1;
+         *  The integrated part of scaling coefficient in X direction.
+         */
+        uint32_t sr_scal_x_int:8;
+        /** sr_scal_x_frag : R/W; bitpos: [11:8]; default: 0;
+         *  The fragment part of scaling coefficient in X direction.
+         */
+        uint32_t sr_scal_x_frag:4;
+        /** sr_scal_y_int : R/W; bitpos: [19:12]; default: 1;
+         *  The integrated part of scaling coefficient in Y direction.
+         */
+        uint32_t sr_scal_y_int:8;
+        /** sr_scal_y_frag : R/W; bitpos: [23:20]; default: 0;
+         *  The fragment part of scaling coefficient in Y direction.
+         */
+        uint32_t sr_scal_y_frag:4;
+        /** sr_rotate_angle : R/W; bitpos: [25:24]; default: 0;
+         *  The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree.
+         */
+        uint32_t sr_rotate_angle:2;
+        /** scal_rotate_rst : R/W; bitpos: [26]; default: 0;
+         *  Write 1 then write 0 to this bit to reset scaling and rotating engine.
+         */
+        uint32_t scal_rotate_rst:1;
+        /** scal_rotate_start : WT; bitpos: [27]; default: 0;
+         *  Write 1 to enable scaling and rotating engine after parameter is configured.
+         */
+        uint32_t scal_rotate_start:1;
+        /** sr_mirror_x : R/W; bitpos: [28]; default: 0;
+         *  Image mirror in X direction. 0: disable, 1: enable
+         */
+        uint32_t sr_mirror_x:1;
+        /** sr_mirror_y : R/W; bitpos: [29]; default: 0;
+         *  Image mirror in Y direction. 0: disable, 1: enable
+         */
+        uint32_t sr_mirror_y:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} ppa_sr_scal_rotate_reg_t;
+
+/** Type of sr_mem_pd register
+ *  SR memory power done register
+ */
+typedef union {
+    struct {
+        /** sr_mem_clk_ena : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force clock enable of scaling and rotating engine's data memory.
+         */
+        uint32_t sr_mem_clk_ena:1;
+        /** sr_mem_force_pd : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to force power down scaling and rotating engine's data memory.
+         */
+        uint32_t sr_mem_force_pd:1;
+        /** sr_mem_force_pu : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force power up scaling and rotating engine's data memory.
+         */
+        uint32_t sr_mem_force_pu:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ppa_sr_mem_pd_reg_t;
+
+/** Type of reg_conf register
+ *  Register clock enable register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  PPA register clock gate enable signal.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ppa_reg_conf_reg_t;
+
+/** Type of eco_low register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rnd_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rnd_eco_low:32;
+    };
+    uint32_t val;
+} ppa_eco_low_reg_t;
+
+/** Type of eco_high register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rnd_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Reserved.
+         */
+        uint32_t rnd_eco_high:32;
+    };
+    uint32_t val;
+} ppa_eco_high_reg_t;
+
+/** Type of sram_ctrl register
+ *  PPA SRAM Control Register
+ */
+typedef union {
+    struct {
+        /** mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896;
+         *  Control signals
+         */
+        uint32_t mem_aux_ctrl:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} ppa_sram_ctrl_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_raw register
+ *  Raw status interrupt
+ */
+typedef union {
+    struct {
+        /** sr_eof_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when scaling and rotating engine
+         *  calculate one frame image.
+         */
+        uint32_t sr_eof_int_raw:1;
+        /** blend_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when blending engine calculate one frame
+         *  image.
+         */
+        uint32_t blend_eof_int_raw:1;
+        /** sr_param_cfg_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when the configured scaling and rotating
+         *  coefficient is wrong. User can check the reasons through register
+         *  PPA_SR_PARAM_ERR_ST_REG.
+         */
+        uint32_t sr_param_cfg_err_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ppa_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt
+ */
+typedef union {
+    struct {
+        /** sr_eof_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the PPA_SR_EOF_INT interrupt.
+         */
+        uint32_t sr_eof_int_st:1;
+        /** blend_eof_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt.
+         */
+        uint32_t blend_eof_int_st:1;
+        /** sr_param_cfg_err_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt.
+         */
+        uint32_t sr_param_cfg_err_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ppa_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** sr_eof_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the PPA_SR_EOF_INT interrupt.
+         */
+        uint32_t sr_eof_int_ena:1;
+        /** blend_eof_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt.
+         */
+        uint32_t blend_eof_int_ena:1;
+        /** sr_param_cfg_err_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt.
+         */
+        uint32_t sr_param_cfg_err_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ppa_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** sr_eof_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the PPA_SR_EOF_INT interrupt.
+         */
+        uint32_t sr_eof_int_clr:1;
+        /** blend_eof_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the PPA_BLEND_EOF_INT interrupt.
+         */
+        uint32_t blend_eof_int_clr:1;
+        /** sr_param_cfg_err_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt.
+         */
+        uint32_t sr_param_cfg_err_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ppa_int_clr_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of clut_cnt register
+ *  BLEND CLUT write counter register
+ */
+typedef union {
+    struct {
+        /** blend0_clut_cnt : RO; bitpos: [8:0]; default: 0;
+         *  The write data counter of BLEND0 CLUT in fifo mode.
+         */
+        uint32_t blend0_clut_cnt:9;
+        /** blend1_clut_cnt : RO; bitpos: [17:9]; default: 0;
+         *  The write data counter of BLEND1 CLUT in fifo mode.
+         */
+        uint32_t blend1_clut_cnt:9;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} ppa_clut_cnt_reg_t;
+
+/** Type of blend_st register
+ *  Blending engine status register
+ */
+typedef union {
+    struct {
+        /** blend_size_diff_st : RO; bitpos: [0]; default: 0;
+         *  1: indicate the size of two image is different.
+         */
+        uint32_t blend_size_diff_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ppa_blend_st_reg_t;
+
+/** Type of sr_param_err_st register
+ *  Scaling and rotating coefficient error register
+ */
+typedef union {
+    struct {
+        /** tx_dscr_vb_err_st : RO; bitpos: [0]; default: 0;
+         *  The error is that the scaled VB plus the offset of Y coordinate in 2DDMA receive
+         *  descriptor is larger than VA in 2DDMA receive descriptor.
+         */
+        uint32_t tx_dscr_vb_err_st:1;
+        /** tx_dscr_hb_err_st : RO; bitpos: [1]; default: 0;
+         *  The error is that the scaled HB plus the offset of X coordinate in 2DDMA receive
+         *  descriptor is larger than HA in 2DDMA receive descriptor.
+         */
+        uint32_t tx_dscr_hb_err_st:1;
+        /** y_rx_scal_equal_0_err_st : RO; bitpos: [2]; default: 0;
+         *  The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG both are 0.
+         */
+        uint32_t y_rx_scal_equal_0_err_st:1;
+        /** rx_dscr_vb_err_st : RO; bitpos: [3]; default: 0;
+         *  The error is that VB in 2DDMA receive descriptor plus the offset of Y coordinate in
+         *  2DDMA transmit descriptor is larger than VA in 2DDMA transmit descriptor
+         */
+        uint32_t rx_dscr_vb_err_st:1;
+        /** ydst_len_too_samll_err_st : RO; bitpos: [4]; default: 0;
+         *  The error is that the scaled image width is 0. For example.  when source width is
+         *  14. scaled value is 1/16. and no rotate operation. then scaled width would be 0 as
+         *  the result would be floored.
+         */
+        uint32_t ydst_len_too_samll_err_st:1;
+        /** ydst_len_too_large_err_st : RO; bitpos: [5]; default: 0;
+         *  The error is that the scaled width is larger than (2^13 - 1).
+         */
+        uint32_t ydst_len_too_large_err_st:1;
+        /** x_rx_scal_equal_0_err_st : RO; bitpos: [6]; default: 0;
+         *  The error is that the scaled image height is 0.
+         */
+        uint32_t x_rx_scal_equal_0_err_st:1;
+        /** rx_dscr_hb_err_st : RO; bitpos: [7]; default: 0;
+         *  The error is that the HB in 2DDMA transmit descriptor plus the offset of X
+         *  coordinate in 2DDMA transmit descriptor is larger than HA in 2DDMA transmit
+         *  descriptor.
+         */
+        uint32_t rx_dscr_hb_err_st:1;
+        /** xdst_len_too_samll_err_st : RO; bitpos: [8]; default: 0;
+         *  The error is that the scaled image height is 0. For example.  when source height is
+         *  14. scaled value is 1/16. and no rotate operation. then scaled height would be 0 as
+         *  the result would be floored.
+         */
+        uint32_t xdst_len_too_samll_err_st:1;
+        /** xdst_len_too_large_err_st : RO; bitpos: [9]; default: 0;
+         *  The error is that the scaled image height is larger than (2^13 - 1).
+         */
+        uint32_t xdst_len_too_large_err_st:1;
+        /** x_yuv420_rx_scale_err_st : RO; bitpos: [10]; default: 0;
+         *  The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable
+         *  yuv420 rx
+         */
+        uint32_t x_yuv420_rx_scale_err_st:1;
+        /** y_yuv420_rx_scale_err_st : RO; bitpos: [11]; default: 0;
+         *  The error is that the va/vb/y param in dma2d descriptor is an odd num when enable
+         *  yuv420 rx
+         */
+        uint32_t y_yuv420_rx_scale_err_st:1;
+        /** x_yuv420_tx_scale_err_st : RO; bitpos: [12]; default: 0;
+         *  The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable
+         *  yuv420 tx
+         */
+        uint32_t x_yuv420_tx_scale_err_st:1;
+        /** y_yuv420_tx_scale_err_st : RO; bitpos: [13]; default: 0;
+         *  The error is that the va/vb/y param in dma2d descriptor is an odd num when enable
+         *  yuv420 tx
+         */
+        uint32_t y_yuv420_tx_scale_err_st:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} ppa_sr_param_err_st_reg_t;
+
+/** Type of sr_status register
+ *  SR FSM register
+ */
+typedef union {
+    struct {
+        /** sr_rx_dscr_sample_state : RO; bitpos: [1:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t sr_rx_dscr_sample_state:2;
+        /** sr_rx_scan_state : RO; bitpos: [3:2]; default: 0;
+         *  Reserved.
+         */
+        uint32_t sr_rx_scan_state:2;
+        /** sr_tx_dscr_sample_state : RO; bitpos: [5:4]; default: 0;
+         *  Reserved.
+         */
+        uint32_t sr_tx_dscr_sample_state:2;
+        /** sr_tx_scan_state : RO; bitpos: [8:6]; default: 0;
+         *  Reserved.
+         */
+        uint32_t sr_tx_scan_state:3;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} ppa_sr_status_reg_t;
+
+/** Type of eco_cell_ctrl register
+ *  Reserved.
+ */
+typedef union {
+    struct {
+        /** rdn_result : RO; bitpos: [0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rdn_result:1;
+        /** rdn_ena : R/W; bitpos: [1]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rdn_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ppa_eco_cell_ctrl_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  PPA Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36716609;
+         *  register version.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} ppa_date_reg_t;
+
+
+typedef struct ppa_dev_t {
+    volatile ppa_blend0_clut_data_reg_t blend0_clut_data;
+    volatile ppa_blend1_clut_data_reg_t blend1_clut_data;
+    uint32_t reserved_008;
+    volatile ppa_clut_conf_reg_t clut_conf;
+    volatile ppa_int_raw_reg_t int_raw;
+    volatile ppa_int_st_reg_t int_st;
+    volatile ppa_int_ena_reg_t int_ena;
+    volatile ppa_int_clr_reg_t int_clr;
+    volatile ppa_sr_color_mode_reg_t sr_color_mode;
+    volatile ppa_blend_color_mode_reg_t blend_color_mode;
+    volatile ppa_sr_byte_order_reg_t sr_byte_order;
+    volatile ppa_blend_byte_order_reg_t blend_byte_order;
+    uint32_t reserved_030;
+    volatile ppa_blend_trans_mode_reg_t blend_trans_mode;
+    volatile ppa_sr_fix_alpha_reg_t sr_fix_alpha;
+    volatile ppa_blend_tx_size_reg_t blend_tx_size;
+    volatile ppa_blend_fix_alpha_reg_t blend_fix_alpha;
+    uint32_t reserved_044;
+    volatile ppa_blend_rgb_reg_t blend_rgb;
+    volatile ppa_blend_fix_pixel_reg_t blend_fix_pixel;
+    volatile ppa_ck_fg_low_reg_t ck_fg_low;
+    volatile ppa_ck_fg_high_reg_t ck_fg_high;
+    volatile ppa_ck_bg_low_reg_t ck_bg_low;
+    volatile ppa_ck_bg_high_reg_t ck_bg_high;
+    volatile ppa_ck_default_reg_t ck_default;
+    volatile ppa_sr_scal_rotate_reg_t sr_scal_rotate;
+    volatile ppa_sr_mem_pd_reg_t sr_mem_pd;
+    volatile ppa_reg_conf_reg_t reg_conf;
+    volatile ppa_clut_cnt_reg_t clut_cnt;
+    volatile ppa_blend_st_reg_t blend_st;
+    volatile ppa_sr_param_err_st_reg_t sr_param_err_st;
+    volatile ppa_sr_status_reg_t sr_status;
+    volatile ppa_eco_low_reg_t eco_low;
+    volatile ppa_eco_high_reg_t eco_high;
+    volatile ppa_eco_cell_ctrl_reg_t eco_cell_ctrl;
+    volatile ppa_sram_ctrl_reg_t sram_ctrl;
+    uint32_t reserved_090[28];
+    volatile ppa_date_reg_t date;
+} ppa_dev_t;
+
+extern ppa_dev_t PPA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ppa_dev_t) == 0x104, "Invalid size of ppa_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/reg_base.h

@@ -0,0 +1,205 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Basic address */
+#define DR_REG_HPCPUTCP_BASE          0x3FF00000
+#define DR_REG_HPPERIPH0_BASE         0x50000000
+#define DR_REG_HPPERIPH1_BASE         0x500C0000
+#define DR_REG_LPAON_BASE             0x50110000
+#define DR_REG_LPPERIPH_BASE          0x50120000
+
+/* This is raw module base from digital team
+ * some of them may not be used in rom
+ * just keep them for a reference
+ */
+/*
+ * @module: CPU-PERIPHERAL
+ *
+ * @base: 0x3FF00000
+ *
+ * @size: 128KB
+ */
+#define DR_REG_TRACE0_BASE            (DR_REG_HPCPUTCP_BASE + 0x4000)
+#define DR_REG_TRACE1_BASE            (DR_REG_HPCPUTCP_BASE + 0x5000)
+#define DR_REG_CPU_BUS_MON_BASE       (DR_REG_HPCPUTCP_BASE + 0x6000)
+#define DR_REG_L2MEM_MON_BASE         (DR_REG_HPCPUTCP_BASE + 0xE000)
+#define DR_REG_TCM_MON_BASE           (DR_REG_HPCPUTCP_BASE + 0xF000)
+#define DR_REG_CACHE_BASE             (DR_REG_HPCPUTCP_BASE + 0x10000)
+
+/*
+ * @module: PERIPHERAL0
+ *
+ * @base: 0x50000000
+ *
+ * @size: 768KB
+ */
+#define DR_REG_USB2_BASE              (DR_REG_HPPERIPH0_BASE + 0x0)
+#define DR_REG_USB11_BASE             (DR_REG_HPPERIPH0_BASE + 0x40000)
+#define DR_REG_USB_WRAP_BASE          (DR_REG_HPPERIPH0_BASE + 0x80000)
+#define DR_REG_GDMA_BASE              (DR_REG_HPPERIPH0_BASE + 0x81000)
+#define DR_REG_REGDMA_BASE            (DR_REG_HPPERIPH0_BASE + 0x82000)
+#define DR_REG_SDMMC_BASE             (DR_REG_HPPERIPH0_BASE + 0x83000)
+#define DR_REG_H264_CORE_BASE         (DR_REG_HPPERIPH0_BASE + 0x84000)
+#define DR_REG_AHB_DMA_BASE           (DR_REG_HPPERIPH0_BASE + 0x85000)
+#define DR_REG_JPEG_BASE              (DR_REG_HPPERIPH0_BASE + 0x86000)
+#define DR_REG_PPA_BASE               (DR_REG_HPPERIPH0_BASE + 0x87000)
+#define DR_REG_DMA2D_BASE             (DR_REG_HPPERIPH0_BASE + 0x88000)
+#define DR_REG_KEYMNG_BASE            (DR_REG_HPPERIPH0_BASE + 0x89000)
+#define DR_REG_AXI_DMA_BASE           (DR_REG_HPPERIPH0_BASE + 0x8A000)
+#define DR_REG_FLASH_SPI0_BASE        (DR_REG_HPPERIPH0_BASE + 0x8C000)
+#define DR_REG_FLASH_SPI1_BASE        (DR_REG_HPPERIPH0_BASE + 0x8D000)
+#define DR_REG_PSRAM_MSPI0_BASE       (DR_REG_HPPERIPH0_BASE + 0x8E000)
+#define DR_REG_PSRAM_MSPI1_BASE       (DR_REG_HPPERIPH0_BASE + 0x8F000)
+#define DR_REG_CRYPTO_BASE            (DR_REG_HPPERIPH0_BASE + 0x90000)
+#define DR_REG_EMAC_BASE              (DR_REG_HPPERIPH0_BASE + 0x98000)
+#define DR_REG_USBPHY_BASE            (DR_REG_HPPERIPH0_BASE + 0x9C000)
+#define DR_REG_DDRPHY_BASE            (DR_REG_HPPERIPH0_BASE + 0x9D000)
+#define DR_REG_PVT_BASE               (DR_REG_HPPERIPH0_BASE + 0x9E000)
+#define DR_REG_CSI_HOST_BASE          (DR_REG_HPPERIPH0_BASE + 0x9F000)
+#define DR_REG_CSI_BRG_BASE           (DR_REG_HPPERIPH0_BASE + 0x9F800)
+#define DR_REG_DSI_HOST_BASE          (DR_REG_HPPERIPH0_BASE + 0xA0000)
+#define DR_REG_DSI_BRG_BASE           (DR_REG_HPPERIPH0_BASE + 0xA0800)
+#define DR_REG_ISP_BASE               (DR_REG_HPPERIPH0_BASE + 0xA1000)
+#define DR_REG_RMT_BASE               (DR_REG_HPPERIPH0_BASE + 0xA2000)
+#define DR_REG_BITSCRAMBLER_BASE      (DR_REG_HPPERIPH0_BASE + 0xA3000)
+#define DR_REG_AXI_ICM_BASE           (DR_REG_HPPERIPH0_BASE + 0xA4000)
+#define DR_REG_AXI_ICM_QOS_BASE       (DR_REG_AXI_ICM_BASE   + 0x400)
+#define DR_REG_HP_PERI_PMS_BASE       (DR_REG_HPPERIPH0_BASE + 0xA5000)
+#define DR_REG_LP2HP_PERI_PMS_BASE    (DR_REG_HPPERIPH0_BASE + 0xA5800)
+#define DR_REG_DMA_PMS_BASE           (DR_REG_HPPERIPH0_BASE + 0xA6000)
+#define DR_REG_H264_DMA_2D_BASE       (DR_REG_HPPERIPH0_BASE + 0xA7000)
+/*
+ * @module: PERIPHERAL1
+ *
+ * @base: 0x500C0000
+ *
+ * @size: 256KB
+ */
+#define DR_REG_MCPWM0_BASE            (DR_REG_HPPERIPH1_BASE + 0x0)
+#define DR_REG_MCPWM1_BASE            (DR_REG_HPPERIPH1_BASE + 0x1000)
+#define DR_REG_TIMG0_BASE             (DR_REG_HPPERIPH1_BASE + 0x2000)
+#define DR_REG_TIMG1_BASE             (DR_REG_HPPERIPH1_BASE + 0x3000)
+#define DR_REG_I2C0_BASE              (DR_REG_HPPERIPH1_BASE + 0x4000)
+#define DR_REG_I2C1_BASE              (DR_REG_HPPERIPH1_BASE + 0x5000)
+#define DR_REG_I2S0_BASE              (DR_REG_HPPERIPH1_BASE + 0x6000)
+#define DR_REG_I2S1_BASE              (DR_REG_HPPERIPH1_BASE + 0x7000)
+#define DR_REG_I2S2_BASE              (DR_REG_HPPERIPH1_BASE + 0x8000)
+#define DR_REG_PCNT_BASE              (DR_REG_HPPERIPH1_BASE + 0x9000)
+#define DR_REG_UART0_BASE             (DR_REG_HPPERIPH1_BASE + 0xA000)
+#define DR_REG_UART1_BASE             (DR_REG_HPPERIPH1_BASE + 0xB000)
+#define DR_REG_UART2_BASE             (DR_REG_HPPERIPH1_BASE + 0xC000)
+#define DR_REG_UART3_BASE             (DR_REG_HPPERIPH1_BASE + 0xD000)
+#define DR_REG_UART4_BASE             (DR_REG_HPPERIPH1_BASE + 0xE000)
+#define DR_REG_PARIO_BASE             (DR_REG_HPPERIPH1_BASE + 0xF000)
+#define DR_REG_SPI2_BASE              (DR_REG_HPPERIPH1_BASE + 0x10000)
+#define DR_REG_SPI3_BASE              (DR_REG_HPPERIPH1_BASE + 0x11000)
+#define DR_REG_USB2JTAG_BASE          (DR_REG_HPPERIPH1_BASE + 0x12000)
+#define DR_REG_LEDC_BASE              (DR_REG_HPPERIPH1_BASE + 0x13000)
+#define DR_REG_ETM_BASE               (DR_REG_HPPERIPH1_BASE + 0x15000)
+#define DR_REG_INTR_BASE              (DR_REG_HPPERIPH1_BASE + 0x16000)
+#define DR_REG_TWAI0_BASE             (DR_REG_HPPERIPH1_BASE + 0x17000)
+#define DR_REG_TWAI1_BASE             (DR_REG_HPPERIPH1_BASE + 0x18000)
+#define DR_REG_TWAI2_BASE             (DR_REG_HPPERIPH1_BASE + 0x19000)
+#define DR_REG_I3C_MST_BASE           (DR_REG_HPPERIPH1_BASE + 0x1A000)
+#define DR_REG_I3C_MST_MEM_BASE       (DR_REG_I3C_MST_BASE)
+#define DR_REG_I3C_SLV_BASE           (DR_REG_HPPERIPH1_BASE + 0x1B000)
+#define DR_REG_LCDCAM_BASE            (DR_REG_HPPERIPH1_BASE + 0x1C000)
+#define DR_REG_ADC_BASE               (DR_REG_HPPERIPH1_BASE + 0x1E000)
+#define DR_REG_UHCI_BASE              (DR_REG_HPPERIPH1_BASE + 0x1F000)
+#define DR_REG_GPIO_BASE              (DR_REG_HPPERIPH1_BASE + 0x20000)
+#define DR_REG_GPIO_EXT_BASE          (DR_REG_HPPERIPH1_BASE + 0x20F00)
+#define DR_REG_IO_MUX_BASE            (DR_REG_HPPERIPH1_BASE + 0x21000)
+#define DR_REG_IOMUX_MSPI_PIN_BASE    (DR_REG_HPPERIPH1_BASE + 0x21200)
+#define DR_REG_SYSTIMER_BASE          (DR_REG_HPPERIPH1_BASE + 0x22000)
+#define DR_REG_MEM_MON_BASE           (DR_REG_HPPERIPH1_BASE + 0x23000)
+#define DR_REG_AUDIO_ADDC_BASE        (DR_REG_HPPERIPH1_BASE + 0x24000)
+#define DR_REG_HP_SYS_BASE            (DR_REG_HPPERIPH1_BASE + 0x25000)
+#define DR_REG_HP_SYS_CLKRST_BASE     (DR_REG_HPPERIPH1_BASE + 0x26000)
+
+/*
+ * @module: LP AON
+ *
+ * @base: 0x50110000
+ *
+ * @size: 64KB
+ */
+#define DR_REG_LP_SYS_BASE            (DR_REG_LPAON_BASE + 0x0)
+#define DR_REG_LP_CLKRST_BASE         (DR_REG_LPAON_BASE + 0x1000)
+#define DR_REG_LP_TIMER_BASE          (DR_REG_LPAON_BASE + 0x2000)
+#define DR_REG_LP_ANALOG_PERI_BASE    (DR_REG_LPAON_BASE + 0x3000)
+#define DR_REG_LP_HUK_BASE            (DR_REG_LPAON_BASE + 0x4000)
+#define DR_REG_HUK_BASE               (DR_REG_LP_HUK_BASE)
+#define DR_REG_PMU_BASE               (DR_REG_LPAON_BASE + 0x5000)
+#define DR_REG_LP_WDT_BASE            (DR_REG_LPAON_BASE + 0x6000)
+#define DR_REG_LP_MB_BASE             (DR_REG_LPAON_BASE + 0x8000)
+#define DR_REG_RTC_BASE               (DR_REG_LPAON_BASE + 0x9000)
+
+/*
+ * @module: LP PERI
+ *
+ * @base: 0x50120000
+ *
+ * @size: 64KB
+ */
+#define DR_REG_LP_PERI_CLKRST_BASE    (DR_REG_LPPERIPH_BASE + 0x0)
+#define DR_REG_LP_PERI_BASE           (DR_REG_LPPERIPH_BASE + 0x0)
+#define DR_REG_LP_UART_BASE           (DR_REG_LPPERIPH_BASE + 0x1000)
+#define DR_REG_LP_I2C_BASE            (DR_REG_LPPERIPH_BASE + 0x2000)
+#define DR_REG_LP_SPI_BASE            (DR_REG_LPPERIPH_BASE + 0x3000)
+#define DR_REG_I2C_ANA_MST_BASE       (DR_REG_LPPERIPH_BASE + 0x4000)
+#define DR_REG_LP_I2S_BASE            (DR_REG_LPPERIPH_BASE + 0x5000)
+#define DR_REG_LP_ADC_BASE            (DR_REG_LPPERIPH_BASE + 0x7000)
+#define DR_REG_LP_TOUCH_BASE          (DR_REG_LPPERIPH_BASE + 0x8000)
+#define DR_REG_LP_GPIO_BASE           (DR_REG_LPPERIPH_BASE + 0xA000)
+#define DR_REG_LP_IOMUX_BASE          (DR_REG_LPPERIPH_BASE + 0xB000)
+#define DR_REG_LP_INTR_BASE           (DR_REG_LPPERIPH_BASE + 0xC000)
+#define DR_REG_EFUSE_BASE             (DR_REG_LPPERIPH_BASE + 0xD000)
+#define DR_REG_LP_PERI_PMS_BASE       (DR_REG_LPPERIPH_BASE + 0xE000)
+#define DR_REG_HP2LP_PERI_PMS_BASE    (DR_REG_LPPERIPH_BASE + 0xE800)
+#define DR_REG_LP_TSENSOR_BASE        (DR_REG_LPPERIPH_BASE + 0xF000)
+
+/**
+ * @brief: Special memory address
+ */
+#define LP_I2S_RAM_BASE               0x50125c00
+#define MIPI_CSI_BRG_MEM_BASE         0x50104000
+#define MIPI_DSI_BRG_MEM_BASE         0x50105000
+
+
+/**
+ * This are module helper MACROs for quick module reference
+ * including some module(renamed) address
+ */
+#define DR_REG_UART_BASE                        DR_REG_UART0_BASE
+#define DR_REG_UHCI0_BASE                       DR_REG_UHCI_BASE
+#define DR_REG_TIMERGROUP0_BASE                 DR_REG_TIMG0_BASE
+#define DR_REG_TIMERGROUP1_BASE                 DR_REG_TIMG1_BASE
+#define DR_REG_I2S_BASE                         DR_REG_I2S0_BASE
+#define DR_REG_USB_SERIAL_JTAG_BASE             DR_REG_USB2JTAG_BASE
+#define DR_REG_INTMTX_BASE                      DR_REG_INTR_BASE
+#define DR_REG_SOC_ETM_BASE                     DR_REG_ETM_BASE
+#define DR_REG_MCPWM_BASE                       DR_REG_MCPWM0_BASE
+#define DR_REG_PARL_IO_BASE                     DR_REG_PARIO_BASE
+#define DR_REG_PVT_MONITOR_BASE                 DR_REG_PVT_BASE
+#define DR_REG_AES_BASE                         (DR_REG_CRYPTO_BASE + 0x0)
+#define DR_REG_SHA_BASE                         (DR_REG_CRYPTO_BASE + 0x1000)
+#define DR_REG_RSA_BASE                         (DR_REG_CRYPTO_BASE + 0x2000)
+#define DR_REG_ECC_MULT_BASE                    (DR_REG_CRYPTO_BASE + 0x3000)
+#define DR_REG_DS_BASE                          (DR_REG_CRYPTO_BASE + 0x4000)
+#define DR_REG_DIGITAL_SIGNATURE_BASE           DR_REG_DS_BASE
+#define DR_REG_HMAC_BASE                        (DR_REG_CRYPTO_BASE + 0x5000)
+#define DR_REG_ECDSA_BASE                       (DR_REG_CRYPTO_BASE + 0x6000)
+#define DR_REG_MEM_MONITOR_BASE                 DR_REG_L2MEM_MON_BASE
+#define DR_REG_HP_CLKRST_BASE                   DR_REG_HP_SYS_CLKRST_BASE
+#define DR_REG_DSPI_MEM_BASE                    DR_REG_PSRAM_MSPI0_BASE
+#define DR_REG_INTERRUPT_CORE0_BASE             DR_REG_INTR_BASE
+#define DR_REG_INTERRUPT_CORE1_BASE             (DR_REG_INTR_BASE + 0x800)
+#define DR_REG_LPPERI_BASE                      DR_REG_LP_PERI_CLKRST_BASE
+#define DR_REG_CPU_BUS_MONITOR_BASE             DR_REG_CPU_BUS_MON_BASE
+#define DR_REG_ASSIST_DEBUG_BASE                DR_REG_CPU_BUS_MON_BASE
+#define DR_REG_PAU_BASE                         DR_REG_REGDMA_BASE
+#define DR_REG_SDHOST_BASE                      DR_REG_SDMMC_BASE
+#define DR_REG_TRACE_BASE                       DR_REG_TRACE0_BASE

components/soc/esp32p4/register/hw_ver2/soc/rsa_reg.h

@@ -0,0 +1,212 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** RSA_M_MEM register
+ *  Represents M
+ */
+#define RSA_M_MEM (DR_REG_RSA_BASE + 0x0)
+#define RSA_M_MEM_SIZE_BYTES 16
+
+/** RSA_Z_MEM register
+ *  Represents Z
+ */
+#define RSA_Z_MEM (DR_REG_RSA_BASE + 0x200)
+#define RSA_Z_MEM_SIZE_BYTES 16
+
+/** RSA_Y_MEM register
+ *  Represents Y
+ */
+#define RSA_Y_MEM (DR_REG_RSA_BASE + 0x400)
+#define RSA_Y_MEM_SIZE_BYTES 16
+
+/** RSA_X_MEM register
+ *  Represents X
+ */
+#define RSA_X_MEM (DR_REG_RSA_BASE + 0x600)
+#define RSA_X_MEM_SIZE_BYTES 16
+
+/** RSA_M_PRIME_REG register
+ *  Represents M'
+ */
+#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800)
+/** RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0;
+ *  Represents M'
+ */
+#define RSA_M_PRIME    0xFFFFFFFFU
+#define RSA_M_PRIME_M  (RSA_M_PRIME_V << RSA_M_PRIME_S)
+#define RSA_M_PRIME_V  0xFFFFFFFFU
+#define RSA_M_PRIME_S  0
+
+/** RSA_MODE_REG register
+ *  Configures RSA length
+ */
+#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804)
+/** RSA_MODE : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the RSA length.
+ */
+#define RSA_MODE    0x0000007FU
+#define RSA_MODE_M  (RSA_MODE_V << RSA_MODE_S)
+#define RSA_MODE_V  0x0000007FU
+#define RSA_MODE_S  0
+
+/** RSA_QUERY_CLEAN_REG register
+ *  RSA initialization status
+ */
+#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808)
+/** RSA_QUERY_CLEAN : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not the RSA memory completes initialization.
+ *  0: Not complete
+ *  1: Completed
+ */
+#define RSA_QUERY_CLEAN    (BIT(0))
+#define RSA_QUERY_CLEAN_M  (RSA_QUERY_CLEAN_V << RSA_QUERY_CLEAN_S)
+#define RSA_QUERY_CLEAN_V  0x00000001U
+#define RSA_QUERY_CLEAN_S  0
+
+/** RSA_SET_START_MODEXP_REG register
+ *  Starts modular exponentiation
+ */
+#define RSA_SET_START_MODEXP_REG (DR_REG_RSA_BASE + 0x80c)
+/** RSA_SET_START_MODEXP : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to starts the modular exponentiation.
+ *  0: No effect
+ *  1: Start
+ */
+#define RSA_SET_START_MODEXP    (BIT(0))
+#define RSA_SET_START_MODEXP_M  (RSA_SET_START_MODEXP_V << RSA_SET_START_MODEXP_S)
+#define RSA_SET_START_MODEXP_V  0x00000001U
+#define RSA_SET_START_MODEXP_S  0
+
+/** RSA_SET_START_MODMULT_REG register
+ *  Starts modular multiplication
+ */
+#define RSA_SET_START_MODMULT_REG (DR_REG_RSA_BASE + 0x810)
+/** RSA_SET_START_MODMULT : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to start the modular multiplication.
+ *  0: No effect
+ *  1: Start
+ */
+#define RSA_SET_START_MODMULT    (BIT(0))
+#define RSA_SET_START_MODMULT_M  (RSA_SET_START_MODMULT_V << RSA_SET_START_MODMULT_S)
+#define RSA_SET_START_MODMULT_V  0x00000001U
+#define RSA_SET_START_MODMULT_S  0
+
+/** RSA_SET_START_MULT_REG register
+ *  Starts multiplication
+ */
+#define RSA_SET_START_MULT_REG (DR_REG_RSA_BASE + 0x814)
+/** RSA_SET_START_MULT : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to start the multiplication.
+ *  0: No effect
+ *  1: Start
+ */
+#define RSA_SET_START_MULT    (BIT(0))
+#define RSA_SET_START_MULT_M  (RSA_SET_START_MULT_V << RSA_SET_START_MULT_S)
+#define RSA_SET_START_MULT_V  0x00000001U
+#define RSA_SET_START_MULT_S  0
+
+/** RSA_QUERY_IDLE_REG register
+ *  Represents the RSA status
+ */
+#define RSA_QUERY_IDLE_REG (DR_REG_RSA_BASE + 0x818)
+/** RSA_QUERY_IDLE : RO; bitpos: [0]; default: 0;
+ *  Represents the RSA status.
+ *  0: Busy
+ *  1: Idle
+ */
+#define RSA_QUERY_IDLE    (BIT(0))
+#define RSA_QUERY_IDLE_M  (RSA_QUERY_IDLE_V << RSA_QUERY_IDLE_S)
+#define RSA_QUERY_IDLE_V  0x00000001U
+#define RSA_QUERY_IDLE_S  0
+
+/** RSA_INT_CLR_REG register
+ *  Clears RSA interrupt
+ */
+#define RSA_INT_CLR_REG (DR_REG_RSA_BASE + 0x81c)
+/** RSA_CLEAR_INTERRUPT : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear the RSA interrupt.
+ */
+#define RSA_CLEAR_INTERRUPT    (BIT(0))
+#define RSA_CLEAR_INTERRUPT_M  (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S)
+#define RSA_CLEAR_INTERRUPT_V  0x00000001U
+#define RSA_CLEAR_INTERRUPT_S  0
+
+/** RSA_CONSTANT_TIME_REG register
+ *  Configures the constant_time option
+ */
+#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820)
+/** RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1;
+ *  Configures the constant_time option.
+ *  0: Acceleration
+ *  1: No acceleration (default)
+ */
+#define RSA_CONSTANT_TIME    (BIT(0))
+#define RSA_CONSTANT_TIME_M  (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S)
+#define RSA_CONSTANT_TIME_V  0x00000001U
+#define RSA_CONSTANT_TIME_S  0
+
+/** RSA_SEARCH_ENABLE_REG register
+ *  Configures the search option
+ */
+#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824)
+/** RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Configures the search option.
+ *  0: No acceleration (default)
+ *  1: Acceleration
+ *  This option should be used together with RSA_SEARCH_POS_REG.
+ */
+#define RSA_SEARCH_ENABLE    (BIT(0))
+#define RSA_SEARCH_ENABLE_M  (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S)
+#define RSA_SEARCH_ENABLE_V  0x00000001U
+#define RSA_SEARCH_ENABLE_S  0
+
+/** RSA_SEARCH_POS_REG register
+ *  Configures the search position
+ */
+#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828)
+/** RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0;
+ *  Configures the starting address to start search. This field should be used together
+ *  with RSA_SEARCH_ENABLE_REG. The field is only valid when RSA_SEARCH_ENABLE is high.
+ */
+#define RSA_SEARCH_POS    0x00000FFFU
+#define RSA_SEARCH_POS_M  (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S)
+#define RSA_SEARCH_POS_V  0x00000FFFU
+#define RSA_SEARCH_POS_S  0
+
+/** RSA_INT_ENA_REG register
+ *  Enables the RSA interrupt
+ */
+#define RSA_INT_ENA_REG (DR_REG_RSA_BASE + 0x82c)
+/** RSA_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable the RSA interrupt.
+ */
+#define RSA_INT_ENA    (BIT(0))
+#define RSA_INT_ENA_M  (RSA_INT_ENA_V << RSA_INT_ENA_S)
+#define RSA_INT_ENA_V  0x00000001U
+#define RSA_INT_ENA_S  0
+
+/** RSA_DATE_REG register
+ *  Version control register
+ */
+#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830)
+/** RSA_DATE : R/W; bitpos: [29:0]; default: 538969624;
+ *  Version control register.
+ */
+#define RSA_DATE    0x3FFFFFFFU
+#define RSA_DATE_M  (RSA_DATE_V << RSA_DATE_S)
+#define RSA_DATE_V  0x3FFFFFFFU
+#define RSA_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/rsa_struct.h

@@ -0,0 +1,252 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Memory */
+
+/** Group: Control / Configuration Registers */
+/** Type of m_prime register
+ *  Represents M'
+ */
+typedef union {
+    struct {
+        /** m_prime : R/W; bitpos: [31:0]; default: 0;
+         *  Represents M'
+         */
+        uint32_t m_prime:32;
+    };
+    uint32_t val;
+} rsa_m_prime_reg_t;
+
+/** Type of mode register
+ *  Configures RSA length
+ */
+typedef union {
+    struct {
+        /** mode : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the RSA length.
+         */
+        uint32_t mode:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} rsa_mode_reg_t;
+
+/** Type of set_start_modexp register
+ *  Starts modular exponentiation
+ */
+typedef union {
+    struct {
+        /** set_start_modexp : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to starts the modular exponentiation.
+         *  0: No effect
+         *  1: Start
+         */
+        uint32_t set_start_modexp:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rsa_set_start_modexp_reg_t;
+
+/** Type of set_start_modmult register
+ *  Starts modular multiplication
+ */
+typedef union {
+    struct {
+        /** set_start_modmult : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to start the modular multiplication.
+         *  0: No effect
+         *  1: Start
+         */
+        uint32_t set_start_modmult:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rsa_set_start_modmult_reg_t;
+
+/** Type of set_start_mult register
+ *  Starts multiplication
+ */
+typedef union {
+    struct {
+        /** set_start_mult : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to start the multiplication.
+         *  0: No effect
+         *  1: Start
+         */
+        uint32_t set_start_mult:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rsa_set_start_mult_reg_t;
+
+/** Type of query_idle register
+ *  Represents the RSA status
+ */
+typedef union {
+    struct {
+        /** query_idle : RO; bitpos: [0]; default: 0;
+         *  Represents the RSA status.
+         *  0: Busy
+         *  1: Idle
+         */
+        uint32_t query_idle:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rsa_query_idle_reg_t;
+
+/** Type of constant_time register
+ *  Configures the constant_time option
+ */
+typedef union {
+    struct {
+        /** constant_time : R/W; bitpos: [0]; default: 1;
+         *  Configures the constant_time option.
+         *  0: Acceleration
+         *  1: No acceleration (default)
+         */
+        uint32_t constant_time:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rsa_constant_time_reg_t;
+
+/** Type of search_enable register
+ *  Configures the search option
+ */
+typedef union {
+    struct {
+        /** search_enable : R/W; bitpos: [0]; default: 0;
+         *  Configures the search option.
+         *  0: No acceleration (default)
+         *  1: Acceleration
+         *  This option should be used together with RSA_SEARCH_POS_REG.
+         */
+        uint32_t search_enable:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rsa_search_enable_reg_t;
+
+/** Type of search_pos register
+ *  Configures the search position
+ */
+typedef union {
+    struct {
+        /** search_pos : R/W; bitpos: [11:0]; default: 0;
+         *  Configures the starting address to start search. This field should be used together
+         *  with RSA_SEARCH_ENABLE_REG. The field is only valid when RSA_SEARCH_ENABLE is high.
+         */
+        uint32_t search_pos:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} rsa_search_pos_reg_t;
+
+
+/** Group: Status Register */
+/** Type of query_clean register
+ *  RSA initialization status
+ */
+typedef union {
+    struct {
+        /** query_clean : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not the RSA memory completes initialization.
+         *  0: Not complete
+         *  1: Completed
+         */
+        uint32_t query_clean:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rsa_query_clean_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_clr register
+ *  Clears RSA interrupt
+ */
+typedef union {
+    struct {
+        /** clear_interrupt : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear the RSA interrupt.
+         */
+        uint32_t clear_interrupt:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rsa_int_clr_reg_t;
+
+/** Type of int_ena register
+ *  Enables the RSA interrupt
+ */
+typedef union {
+    struct {
+        /** int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable the RSA interrupt.
+         */
+        uint32_t int_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rsa_int_ena_reg_t;
+
+
+/** Group: Version Control Register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [29:0]; default: 538969624;
+         *  Version control register.
+         */
+        uint32_t date:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} rsa_date_reg_t;
+
+
+typedef struct {
+    volatile uint32_t m[4];
+    uint32_t reserved_010[124];
+    volatile uint32_t z[4];
+    uint32_t reserved_210[124];
+    volatile uint32_t y[4];
+    uint32_t reserved_410[124];
+    volatile uint32_t x[4];
+    uint32_t reserved_610[124];
+    volatile rsa_m_prime_reg_t m_prime;
+    volatile rsa_mode_reg_t mode;
+    volatile rsa_query_clean_reg_t query_clean;
+    volatile rsa_set_start_modexp_reg_t set_start_modexp;
+    volatile rsa_set_start_modmult_reg_t set_start_modmult;
+    volatile rsa_set_start_mult_reg_t set_start_mult;
+    volatile rsa_query_idle_reg_t query_idle;
+    volatile rsa_int_clr_reg_t int_clr;
+    volatile rsa_constant_time_reg_t constant_time;
+    volatile rsa_search_enable_reg_t search_enable;
+    volatile rsa_search_pos_reg_t search_pos;
+    volatile rsa_int_ena_reg_t int_ena;
+    volatile rsa_date_reg_t date;
+} rsa_dev_t;
+
+extern rsa_dev_t RSA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(rsa_dev_t) == 0x834, "Invalid size of rsa_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/rtclockcali_reg.h

@@ -0,0 +1,578 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** RTCLOCKCALI_LP_CALI_TIMER_REG register
+ *  need_des
+ */
+#define RTCLOCKCALI_LP_CALI_TIMER_REG (DR_REG_RTCLOCKCALI_BASE + 0x0)
+/** RTCLOCKCALI_TIMER_TARGET : R/W; bitpos: [29:0]; default: 4095;
+ *  need_des
+ */
+#define RTCLOCKCALI_TIMER_TARGET    0x3FFFFFFFU
+#define RTCLOCKCALI_TIMER_TARGET_M  (RTCLOCKCALI_TIMER_TARGET_V << RTCLOCKCALI_TIMER_TARGET_S)
+#define RTCLOCKCALI_TIMER_TARGET_V  0x3FFFFFFFU
+#define RTCLOCKCALI_TIMER_TARGET_S  0
+/** RTCLOCKCALI_TIMER_STOP : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define RTCLOCKCALI_TIMER_STOP    (BIT(30))
+#define RTCLOCKCALI_TIMER_STOP_M  (RTCLOCKCALI_TIMER_STOP_V << RTCLOCKCALI_TIMER_STOP_S)
+#define RTCLOCKCALI_TIMER_STOP_V  0x00000001U
+#define RTCLOCKCALI_TIMER_STOP_S  30
+/** RTCLOCKCALI_TIMER_START : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTCLOCKCALI_TIMER_START    (BIT(31))
+#define RTCLOCKCALI_TIMER_START_M  (RTCLOCKCALI_TIMER_START_V << RTCLOCKCALI_TIMER_START_S)
+#define RTCLOCKCALI_TIMER_START_V  0x00000001U
+#define RTCLOCKCALI_TIMER_START_S  31
+
+/** RTCLOCKCALI_RTCCALICFG_SLOW_REG register
+ *  RTC calibration configure register
+ */
+#define RTCLOCKCALI_RTCCALICFG_SLOW_REG (DR_REG_RTCLOCKCALI_BASE + 0x4)
+/** RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW : R/W; bitpos: [12]; default: 1;
+ *  0: one-shot frequency calculation,1: periodic frequency calculation,
+ */
+#define RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW    (BIT(12))
+#define RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_M  (RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_V << RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_S)
+#define RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_V  0x00000001U
+#define RTCLOCKCALI_RTC_CALI_START_CYCLING_SLOW_S  12
+/** RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW : R/W; bitpos: [14:13]; default: 0;
+ *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+ */
+#define RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW    0x00000003U
+#define RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_M  (RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_V << RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_S)
+#define RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_V  0x00000003U
+#define RTCLOCKCALI_RTC_CALI_CLK_SEL_SLOW_S  13
+/** RTCLOCKCALI_RTC_CALI_RDY_SLOW : RO; bitpos: [15]; default: 0;
+ *  indicate one-shot frequency calculation is done.
+ */
+#define RTCLOCKCALI_RTC_CALI_RDY_SLOW    (BIT(15))
+#define RTCLOCKCALI_RTC_CALI_RDY_SLOW_M  (RTCLOCKCALI_RTC_CALI_RDY_SLOW_V << RTCLOCKCALI_RTC_CALI_RDY_SLOW_S)
+#define RTCLOCKCALI_RTC_CALI_RDY_SLOW_V  0x00000001U
+#define RTCLOCKCALI_RTC_CALI_RDY_SLOW_S  15
+/** RTCLOCKCALI_RTC_CALI_MAX_SLOW : R/W; bitpos: [30:16]; default: 1;
+ *  Configure the time to calculate RTC slow clock's frequency.
+ */
+#define RTCLOCKCALI_RTC_CALI_MAX_SLOW    0x00007FFFU
+#define RTCLOCKCALI_RTC_CALI_MAX_SLOW_M  (RTCLOCKCALI_RTC_CALI_MAX_SLOW_V << RTCLOCKCALI_RTC_CALI_MAX_SLOW_S)
+#define RTCLOCKCALI_RTC_CALI_MAX_SLOW_V  0x00007FFFU
+#define RTCLOCKCALI_RTC_CALI_MAX_SLOW_S  16
+/** RTCLOCKCALI_RTC_CALI_START_SLOW : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to start one-shot frequency calculation.
+ */
+#define RTCLOCKCALI_RTC_CALI_START_SLOW    (BIT(31))
+#define RTCLOCKCALI_RTC_CALI_START_SLOW_M  (RTCLOCKCALI_RTC_CALI_START_SLOW_V << RTCLOCKCALI_RTC_CALI_START_SLOW_S)
+#define RTCLOCKCALI_RTC_CALI_START_SLOW_V  0x00000001U
+#define RTCLOCKCALI_RTC_CALI_START_SLOW_S  31
+
+/** RTCLOCKCALI_RTCCALICFG_FAST_REG register
+ *  RTC calibration configure register
+ */
+#define RTCLOCKCALI_RTCCALICFG_FAST_REG (DR_REG_RTCLOCKCALI_BASE + 0x8)
+/** RTCLOCKCALI_FOSC_DIV_NUM : R/W; bitpos: [11:4]; default: 0;
+ *  fosc clock divider number
+ */
+#define RTCLOCKCALI_FOSC_DIV_NUM    0x000000FFU
+#define RTCLOCKCALI_FOSC_DIV_NUM_M  (RTCLOCKCALI_FOSC_DIV_NUM_V << RTCLOCKCALI_FOSC_DIV_NUM_S)
+#define RTCLOCKCALI_FOSC_DIV_NUM_V  0x000000FFU
+#define RTCLOCKCALI_FOSC_DIV_NUM_S  4
+/** RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST : R/W; bitpos: [12]; default: 1;
+ *  0: one-shot frequency calculation,1: periodic frequency calculation,
+ */
+#define RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST    (BIT(12))
+#define RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_M  (RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_V << RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_S)
+#define RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_V  0x00000001U
+#define RTCLOCKCALI_RTC_CALI_START_CYCLING_FAST_S  12
+/** RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST : R/W; bitpos: [14:13]; default: 0;
+ *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+ */
+#define RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST    0x00000003U
+#define RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_M  (RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_V << RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_S)
+#define RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_V  0x00000003U
+#define RTCLOCKCALI_RTC_CALI_CLK_SEL_FAST_S  13
+/** RTCLOCKCALI_RTC_CALI_RDY_FAST : RO; bitpos: [15]; default: 0;
+ *  indicate one-shot frequency calculation is done.
+ */
+#define RTCLOCKCALI_RTC_CALI_RDY_FAST    (BIT(15))
+#define RTCLOCKCALI_RTC_CALI_RDY_FAST_M  (RTCLOCKCALI_RTC_CALI_RDY_FAST_V << RTCLOCKCALI_RTC_CALI_RDY_FAST_S)
+#define RTCLOCKCALI_RTC_CALI_RDY_FAST_V  0x00000001U
+#define RTCLOCKCALI_RTC_CALI_RDY_FAST_S  15
+/** RTCLOCKCALI_RTC_CALI_MAX_FAST : R/W; bitpos: [30:16]; default: 1;
+ *  Configure the time to calculate RTC slow clock's frequency.
+ */
+#define RTCLOCKCALI_RTC_CALI_MAX_FAST    0x00007FFFU
+#define RTCLOCKCALI_RTC_CALI_MAX_FAST_M  (RTCLOCKCALI_RTC_CALI_MAX_FAST_V << RTCLOCKCALI_RTC_CALI_MAX_FAST_S)
+#define RTCLOCKCALI_RTC_CALI_MAX_FAST_V  0x00007FFFU
+#define RTCLOCKCALI_RTC_CALI_MAX_FAST_S  16
+/** RTCLOCKCALI_RTC_CALI_START_FAST : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to start one-shot frequency calculation.
+ */
+#define RTCLOCKCALI_RTC_CALI_START_FAST    (BIT(31))
+#define RTCLOCKCALI_RTC_CALI_START_FAST_M  (RTCLOCKCALI_RTC_CALI_START_FAST_V << RTCLOCKCALI_RTC_CALI_START_FAST_S)
+#define RTCLOCKCALI_RTC_CALI_START_FAST_V  0x00000001U
+#define RTCLOCKCALI_RTC_CALI_START_FAST_S  31
+
+/** RTCLOCKCALI_RTCCALICFG1_SLOW_REG register
+ *  RTC calibration configure1 register
+ */
+#define RTCLOCKCALI_RTCCALICFG1_SLOW_REG (DR_REG_RTCLOCKCALI_BASE + 0xc)
+/** RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW : RO; bitpos: [0]; default: 0;
+ *  indicate periodic frequency calculation is done.
+ */
+#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW    (BIT(0))
+#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_M  (RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_V << RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_S)
+#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_V  0x00000001U
+#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_SLOW_S  0
+/** RTCLOCKCALI_RTC_CALI_VALUE_SLOW : RO; bitpos: [31:7]; default: 0;
+ *  When one-shot or periodic frequency calculation is done, read this value to
+ *  calculate RTC slow clock's frequency.
+ */
+#define RTCLOCKCALI_RTC_CALI_VALUE_SLOW    0x01FFFFFFU
+#define RTCLOCKCALI_RTC_CALI_VALUE_SLOW_M  (RTCLOCKCALI_RTC_CALI_VALUE_SLOW_V << RTCLOCKCALI_RTC_CALI_VALUE_SLOW_S)
+#define RTCLOCKCALI_RTC_CALI_VALUE_SLOW_V  0x01FFFFFFU
+#define RTCLOCKCALI_RTC_CALI_VALUE_SLOW_S  7
+
+/** RTCLOCKCALI_RTCCALICFG1_FAST_REG register
+ *  RTC calibration configure1 register
+ */
+#define RTCLOCKCALI_RTCCALICFG1_FAST_REG (DR_REG_RTCLOCKCALI_BASE + 0x10)
+/** RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST : RO; bitpos: [0]; default: 0;
+ *  indicate periodic frequency calculation is done.
+ */
+#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST    (BIT(0))
+#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_M  (RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_V << RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_S)
+#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_V  0x00000001U
+#define RTCLOCKCALI_RTC_CALI_CYCLING_DATA_VLD_FAST_S  0
+/** RTCLOCKCALI_RTC_CALI_VALUE_FAST : RO; bitpos: [31:7]; default: 0;
+ *  When one-shot or periodic frequency calculation is done, read this value to
+ *  calculate RTC slow clock's frequency.
+ */
+#define RTCLOCKCALI_RTC_CALI_VALUE_FAST    0x01FFFFFFU
+#define RTCLOCKCALI_RTC_CALI_VALUE_FAST_M  (RTCLOCKCALI_RTC_CALI_VALUE_FAST_V << RTCLOCKCALI_RTC_CALI_VALUE_FAST_S)
+#define RTCLOCKCALI_RTC_CALI_VALUE_FAST_V  0x01FFFFFFU
+#define RTCLOCKCALI_RTC_CALI_VALUE_FAST_S  7
+
+/** RTCLOCKCALI_RTCCALICFG2_REG register
+ *  Timer group calibration register
+ */
+#define RTCLOCKCALI_RTCCALICFG2_REG (DR_REG_RTCLOCKCALI_BASE + 0x14)
+/** RTCLOCKCALI_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
+ *  RTC calibration timeout indicator
+ */
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT    (BIT(0))
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_M  (RTCLOCKCALI_RTC_CALI_TIMEOUT_V << RTCLOCKCALI_RTC_CALI_TIMEOUT_S)
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_V  0x00000001U
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_S  0
+/** RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
+ *  Cycles that release calibration timeout reset
+ */
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT    0x0000000FU
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_M  (RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_V << RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_S)
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_V  0x0000000FU
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_RST_CNT_S  3
+/** RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
+ *  Threshold value for the RTC calibration timer. If the calibration timer's value
+ *  exceeds this threshold, a timeout is triggered.
+ */
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES    0x01FFFFFFU
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_M  (RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_V << RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_S)
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_V  0x01FFFFFFU
+#define RTCLOCKCALI_RTC_CALI_TIMEOUT_THRES_S  7
+
+/** RTCLOCKCALI_DFREQ_HIGH_LIMIT_SLOW_REG register
+ *  RTC slow clock dfreq high limit.
+ */
+#define RTCLOCKCALI_DFREQ_HIGH_LIMIT_SLOW_REG (DR_REG_RTCLOCKCALI_BASE + 0x18)
+/** RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW : R/W; bitpos: [7:0]; default: 16;
+ *  When rtc_cali_value upper/lower than reg_high/low_limit +/-
+ *  reg_coarse_limit_diff,the step of dfreq,will use reg_coarse_step.
+ */
+#define RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW    0x000000FFU
+#define RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_M  (RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_V << RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_S)
+#define RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_V  0x000000FFU
+#define RTCLOCKCALI_COARSE_LIMIT_DIFF_SLOW_S  0
+/** RTCLOCKCALI_HIGH_LIMIT_SLOW : R/W; bitpos: [31:8]; default: 267;
+ *  when rtc_cali_value upper than reg_high_limit,frequency of osc will  increase .
+ */
+#define RTCLOCKCALI_HIGH_LIMIT_SLOW    0x00FFFFFFU
+#define RTCLOCKCALI_HIGH_LIMIT_SLOW_M  (RTCLOCKCALI_HIGH_LIMIT_SLOW_V << RTCLOCKCALI_HIGH_LIMIT_SLOW_S)
+#define RTCLOCKCALI_HIGH_LIMIT_SLOW_V  0x00FFFFFFU
+#define RTCLOCKCALI_HIGH_LIMIT_SLOW_S  8
+
+/** RTCLOCKCALI_DFREQ_LOW_LIMIT_SLOW_REG register
+ *  RTC slow clock dfreq low limit.
+ */
+#define RTCLOCKCALI_DFREQ_LOW_LIMIT_SLOW_REG (DR_REG_RTCLOCKCALI_BASE + 0x1c)
+/** RTCLOCKCALI_LOW_LIMIT_SLOW : R/W; bitpos: [31:8]; default: 266;
+ *  when rtc_cali_value lower than reg_low_limit,frequency of osc will  decrease .
+ */
+#define RTCLOCKCALI_LOW_LIMIT_SLOW    0x00FFFFFFU
+#define RTCLOCKCALI_LOW_LIMIT_SLOW_M  (RTCLOCKCALI_LOW_LIMIT_SLOW_V << RTCLOCKCALI_LOW_LIMIT_SLOW_S)
+#define RTCLOCKCALI_LOW_LIMIT_SLOW_V  0x00FFFFFFU
+#define RTCLOCKCALI_LOW_LIMIT_SLOW_S  8
+
+/** RTCLOCKCALI_DFREQ_HIGH_LIMIT_FAST_REG register
+ *  RTC fast clock dfreq high limit.
+ */
+#define RTCLOCKCALI_DFREQ_HIGH_LIMIT_FAST_REG (DR_REG_RTCLOCKCALI_BASE + 0x20)
+/** RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST : R/W; bitpos: [7:0]; default: 16;
+ *  When rtc_cali_value upper/lower than reg_high/low_limit +/-
+ *  reg_coarse_limit_diff,the step of dfreq,will use reg_coarse_step.
+ */
+#define RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST    0x000000FFU
+#define RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_M  (RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_V << RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_S)
+#define RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_V  0x000000FFU
+#define RTCLOCKCALI_COARSE_LIMIT_DIFF_FAST_S  0
+/** RTCLOCKCALI_HIGH_LIMIT_FAST : R/W; bitpos: [31:8]; default: 267;
+ *  when rtc_cali_value upper than reg_high_limit,frequency of osc will  increase .
+ */
+#define RTCLOCKCALI_HIGH_LIMIT_FAST    0x00FFFFFFU
+#define RTCLOCKCALI_HIGH_LIMIT_FAST_M  (RTCLOCKCALI_HIGH_LIMIT_FAST_V << RTCLOCKCALI_HIGH_LIMIT_FAST_S)
+#define RTCLOCKCALI_HIGH_LIMIT_FAST_V  0x00FFFFFFU
+#define RTCLOCKCALI_HIGH_LIMIT_FAST_S  8
+
+/** RTCLOCKCALI_DFREQ_LOW_LIMIT_FAST_REG register
+ *  RTC fast clock dfreq low limit.
+ */
+#define RTCLOCKCALI_DFREQ_LOW_LIMIT_FAST_REG (DR_REG_RTCLOCKCALI_BASE + 0x24)
+/** RTCLOCKCALI_LOW_LIMIT_FAST : R/W; bitpos: [31:8]; default: 266;
+ *  when rtc_cali_value lower than reg_low_limit,frequency of osc will  decrease .
+ */
+#define RTCLOCKCALI_LOW_LIMIT_FAST    0x00FFFFFFU
+#define RTCLOCKCALI_LOW_LIMIT_FAST_M  (RTCLOCKCALI_LOW_LIMIT_FAST_V << RTCLOCKCALI_LOW_LIMIT_FAST_S)
+#define RTCLOCKCALI_LOW_LIMIT_FAST_V  0x00FFFFFFU
+#define RTCLOCKCALI_LOW_LIMIT_FAST_S  8
+
+/** RTCLOCKCALI_DFREQ_CONF2_REG register
+ *  RTC DFREQ CONF2
+ */
+#define RTCLOCKCALI_DFREQ_CONF2_REG (DR_REG_RTCLOCKCALI_BASE + 0x28)
+/** RTCLOCKCALI_DREQ_UPDATE : WT; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define RTCLOCKCALI_DREQ_UPDATE    (BIT(0))
+#define RTCLOCKCALI_DREQ_UPDATE_M  (RTCLOCKCALI_DREQ_UPDATE_V << RTCLOCKCALI_DREQ_UPDATE_S)
+#define RTCLOCKCALI_DREQ_UPDATE_V  0x00000001U
+#define RTCLOCKCALI_DREQ_UPDATE_S  0
+/** RTCLOCKCALI_DREQ_INIT_32K : WT; bitpos: [2]; default: 0;
+ *  Initialize the value of 32K OSC dfreq setting.
+ */
+#define RTCLOCKCALI_DREQ_INIT_32K    (BIT(2))
+#define RTCLOCKCALI_DREQ_INIT_32K_M  (RTCLOCKCALI_DREQ_INIT_32K_V << RTCLOCKCALI_DREQ_INIT_32K_S)
+#define RTCLOCKCALI_DREQ_INIT_32K_V  0x00000001U
+#define RTCLOCKCALI_DREQ_INIT_32K_S  2
+/** RTCLOCKCALI_DREQ_INIT_FOSC : WT; bitpos: [3]; default: 0;
+ *  Initialize the value of FOSC  dfreq setting.
+ */
+#define RTCLOCKCALI_DREQ_INIT_FOSC    (BIT(3))
+#define RTCLOCKCALI_DREQ_INIT_FOSC_M  (RTCLOCKCALI_DREQ_INIT_FOSC_V << RTCLOCKCALI_DREQ_INIT_FOSC_S)
+#define RTCLOCKCALI_DREQ_INIT_FOSC_V  0x00000001U
+#define RTCLOCKCALI_DREQ_INIT_FOSC_S  3
+/** RTCLOCKCALI_DREQ_INIT_SOSC : WT; bitpos: [4]; default: 0;
+ *  Initialize the value of SOSC  dfreq setting.
+ */
+#define RTCLOCKCALI_DREQ_INIT_SOSC    (BIT(4))
+#define RTCLOCKCALI_DREQ_INIT_SOSC_M  (RTCLOCKCALI_DREQ_INIT_SOSC_V << RTCLOCKCALI_DREQ_INIT_SOSC_S)
+#define RTCLOCKCALI_DREQ_INIT_SOSC_V  0x00000001U
+#define RTCLOCKCALI_DREQ_INIT_SOSC_S  4
+/** RTCLOCKCALI_32K_DFREQ_SEL : R/W; bitpos: [5]; default: 0;
+ *  1:Frequency of 32k controlled by calibration module.0:Frequency of 32k controlled
+ *  by register from system-register bank
+ */
+#define RTCLOCKCALI_32K_DFREQ_SEL    (BIT(5))
+#define RTCLOCKCALI_32K_DFREQ_SEL_M  (RTCLOCKCALI_32K_DFREQ_SEL_V << RTCLOCKCALI_32K_DFREQ_SEL_S)
+#define RTCLOCKCALI_32K_DFREQ_SEL_V  0x00000001U
+#define RTCLOCKCALI_32K_DFREQ_SEL_S  5
+/** RTCLOCKCALI_FOSC_DFREQ_SEL : R/W; bitpos: [6]; default: 0;
+ *  1:Frequency of FOSC controlled by calibration module.0:Frequency of FOSC controlled
+ *  by register from system-register bank
+ */
+#define RTCLOCKCALI_FOSC_DFREQ_SEL    (BIT(6))
+#define RTCLOCKCALI_FOSC_DFREQ_SEL_M  (RTCLOCKCALI_FOSC_DFREQ_SEL_V << RTCLOCKCALI_FOSC_DFREQ_SEL_S)
+#define RTCLOCKCALI_FOSC_DFREQ_SEL_V  0x00000001U
+#define RTCLOCKCALI_FOSC_DFREQ_SEL_S  6
+/** RTCLOCKCALI_SOSC_DFREQ_SEL : R/W; bitpos: [7]; default: 0;
+ *  1:Frequency of SOSC controlled by calibration module.0:Frequency of SOSC controlled
+ *  by register from system-register bank
+ */
+#define RTCLOCKCALI_SOSC_DFREQ_SEL    (BIT(7))
+#define RTCLOCKCALI_SOSC_DFREQ_SEL_M  (RTCLOCKCALI_SOSC_DFREQ_SEL_V << RTCLOCKCALI_SOSC_DFREQ_SEL_S)
+#define RTCLOCKCALI_SOSC_DFREQ_SEL_V  0x00000001U
+#define RTCLOCKCALI_SOSC_DFREQ_SEL_S  7
+/** RTCLOCKCALI_FINE_STEP : R/W; bitpos: [15:8]; default: 1;
+ *  Frequency fine step.
+ */
+#define RTCLOCKCALI_FINE_STEP    0x000000FFU
+#define RTCLOCKCALI_FINE_STEP_M  (RTCLOCKCALI_FINE_STEP_V << RTCLOCKCALI_FINE_STEP_S)
+#define RTCLOCKCALI_FINE_STEP_V  0x000000FFU
+#define RTCLOCKCALI_FINE_STEP_S  8
+/** RTCLOCKCALI_COARSE_STEP_FAST : R/W; bitpos: [23:16]; default: 8;
+ *  Frequency coarse step,use to decrease calibration time.
+ */
+#define RTCLOCKCALI_COARSE_STEP_FAST    0x000000FFU
+#define RTCLOCKCALI_COARSE_STEP_FAST_M  (RTCLOCKCALI_COARSE_STEP_FAST_V << RTCLOCKCALI_COARSE_STEP_FAST_S)
+#define RTCLOCKCALI_COARSE_STEP_FAST_V  0x000000FFU
+#define RTCLOCKCALI_COARSE_STEP_FAST_S  16
+/** RTCLOCKCALI_COARSE_STEP_SLOW : R/W; bitpos: [31:24]; default: 8;
+ *  Frequency coarse step,use to decrease calibration time.
+ */
+#define RTCLOCKCALI_COARSE_STEP_SLOW    0x000000FFU
+#define RTCLOCKCALI_COARSE_STEP_SLOW_M  (RTCLOCKCALI_COARSE_STEP_SLOW_V << RTCLOCKCALI_COARSE_STEP_SLOW_S)
+#define RTCLOCKCALI_COARSE_STEP_SLOW_V  0x000000FFU
+#define RTCLOCKCALI_COARSE_STEP_SLOW_S  24
+
+/** RTCLOCKCALI_CALI_EN_REG register
+ *  Configure register.
+ */
+#define RTCLOCKCALI_CALI_EN_REG (DR_REG_RTCLOCKCALI_BASE + 0x2c)
+/** RTCLOCKCALI_CALI_EN_32K : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define RTCLOCKCALI_CALI_EN_32K    (BIT(0))
+#define RTCLOCKCALI_CALI_EN_32K_M  (RTCLOCKCALI_CALI_EN_32K_V << RTCLOCKCALI_CALI_EN_32K_S)
+#define RTCLOCKCALI_CALI_EN_32K_V  0x00000001U
+#define RTCLOCKCALI_CALI_EN_32K_S  0
+/** RTCLOCKCALI_CALI_EN_FOSC : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define RTCLOCKCALI_CALI_EN_FOSC    (BIT(1))
+#define RTCLOCKCALI_CALI_EN_FOSC_M  (RTCLOCKCALI_CALI_EN_FOSC_V << RTCLOCKCALI_CALI_EN_FOSC_S)
+#define RTCLOCKCALI_CALI_EN_FOSC_V  0x00000001U
+#define RTCLOCKCALI_CALI_EN_FOSC_S  1
+/** RTCLOCKCALI_CALI_EN_SOSC : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define RTCLOCKCALI_CALI_EN_SOSC    (BIT(2))
+#define RTCLOCKCALI_CALI_EN_SOSC_M  (RTCLOCKCALI_CALI_EN_SOSC_V << RTCLOCKCALI_CALI_EN_SOSC_S)
+#define RTCLOCKCALI_CALI_EN_SOSC_V  0x00000001U
+#define RTCLOCKCALI_CALI_EN_SOSC_S  2
+
+/** RTCLOCKCALI_DFREQ_VALUE_REG register
+ *  Configure register.
+ */
+#define RTCLOCKCALI_DFREQ_VALUE_REG (DR_REG_RTCLOCKCALI_BASE + 0x30)
+/** RTCLOCKCALI_DREQ_32K : RO; bitpos: [11:2]; default: 172;
+ *  The value of dfreq num of 32k.
+ */
+#define RTCLOCKCALI_DREQ_32K    0x000003FFU
+#define RTCLOCKCALI_DREQ_32K_M  (RTCLOCKCALI_DREQ_32K_V << RTCLOCKCALI_DREQ_32K_S)
+#define RTCLOCKCALI_DREQ_32K_V  0x000003FFU
+#define RTCLOCKCALI_DREQ_32K_S  2
+/** RTCLOCKCALI_DREQ_FOSC : RO; bitpos: [21:12]; default: 512;
+ *  The value of dfreq num of FOSC.
+ */
+#define RTCLOCKCALI_DREQ_FOSC    0x000003FFU
+#define RTCLOCKCALI_DREQ_FOSC_M  (RTCLOCKCALI_DREQ_FOSC_V << RTCLOCKCALI_DREQ_FOSC_S)
+#define RTCLOCKCALI_DREQ_FOSC_V  0x000003FFU
+#define RTCLOCKCALI_DREQ_FOSC_S  12
+/** RTCLOCKCALI_DREQ_SOSC : RO; bitpos: [31:22]; default: 512;
+ *  The value of dfreq num of SOSC.
+ */
+#define RTCLOCKCALI_DREQ_SOSC    0x000003FFU
+#define RTCLOCKCALI_DREQ_SOSC_M  (RTCLOCKCALI_DREQ_SOSC_V << RTCLOCKCALI_DREQ_SOSC_S)
+#define RTCLOCKCALI_DREQ_SOSC_V  0x000003FFU
+#define RTCLOCKCALI_DREQ_SOSC_S  22
+
+/** RTCLOCKCALI_BYPASS_REG register
+ *  Configure register.
+ */
+#define RTCLOCKCALI_BYPASS_REG (DR_REG_RTCLOCKCALI_BASE + 0x34)
+/** RTCLOCKCALI_HP_SLEEP_AUTOCALI : R/W; bitpos: [30]; default: 0;
+ *  1:Chip begin to calibrating,when into hp_sleep.0:Disable this function.
+ */
+#define RTCLOCKCALI_HP_SLEEP_AUTOCALI    (BIT(30))
+#define RTCLOCKCALI_HP_SLEEP_AUTOCALI_M  (RTCLOCKCALI_HP_SLEEP_AUTOCALI_V << RTCLOCKCALI_HP_SLEEP_AUTOCALI_S)
+#define RTCLOCKCALI_HP_SLEEP_AUTOCALI_V  0x00000001U
+#define RTCLOCKCALI_HP_SLEEP_AUTOCALI_S  30
+/** RTCLOCKCALI_LP_SLEEP_AUTOCALI : R/W; bitpos: [31]; default: 0;
+ *  1:Chip begin to calibrating,when into lp_sleep.0:Disable this function.
+ */
+#define RTCLOCKCALI_LP_SLEEP_AUTOCALI    (BIT(31))
+#define RTCLOCKCALI_LP_SLEEP_AUTOCALI_M  (RTCLOCKCALI_LP_SLEEP_AUTOCALI_V << RTCLOCKCALI_LP_SLEEP_AUTOCALI_S)
+#define RTCLOCKCALI_LP_SLEEP_AUTOCALI_V  0x00000001U
+#define RTCLOCKCALI_LP_SLEEP_AUTOCALI_S  31
+
+/** RTCLOCKCALI_INT_RAW_REG register
+ *  Configure register.
+ */
+#define RTCLOCKCALI_INT_RAW_REG (DR_REG_RTCLOCKCALI_BASE + 0x38)
+/** RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  Indicate the xtal timeout  once happened .
+ */
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW    (BIT(29))
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_M  (RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_V << RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_S)
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_V  0x00000001U
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_S  29
+/** RTCLOCKCALI_CALI_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  Indicate the calibration timeout  once happened .
+ */
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW    (BIT(30))
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_M  (RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_V << RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_S)
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_V  0x00000001U
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_S  30
+/** RTCLOCKCALI_CALI_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  Indicate the finish of once calibration .
+ */
+#define RTCLOCKCALI_CALI_DONE_INT_RAW    (BIT(31))
+#define RTCLOCKCALI_CALI_DONE_INT_RAW_M  (RTCLOCKCALI_CALI_DONE_INT_RAW_V << RTCLOCKCALI_CALI_DONE_INT_RAW_S)
+#define RTCLOCKCALI_CALI_DONE_INT_RAW_V  0x00000001U
+#define RTCLOCKCALI_CALI_DONE_INT_RAW_S  31
+
+/** RTCLOCKCALI_INT_ST_REG register
+ *  Interrupt state register.
+ */
+#define RTCLOCKCALI_INT_ST_REG (DR_REG_RTCLOCKCALI_BASE + 0x3c)
+/** RTCLOCKCALI_XTAL_TIMEOUT_INT_ST : RO; bitpos: [29]; default: 0;
+ *  Interrupt state register.
+ */
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ST    (BIT(29))
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_M  (RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_V << RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_S)
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_V  0x00000001U
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ST_S  29
+/** RTCLOCKCALI_CALI_TIMEOUT_INT_ST : RO; bitpos: [30]; default: 0;
+ *  Interrupt state register.
+ */
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_ST    (BIT(30))
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_ST_M  (RTCLOCKCALI_CALI_TIMEOUT_INT_ST_V << RTCLOCKCALI_CALI_TIMEOUT_INT_ST_S)
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_ST_V  0x00000001U
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_ST_S  30
+/** RTCLOCKCALI_CALI_DONE_INT_ST : RO; bitpos: [31]; default: 0;
+ *  Interrupt state register.
+ */
+#define RTCLOCKCALI_CALI_DONE_INT_ST    (BIT(31))
+#define RTCLOCKCALI_CALI_DONE_INT_ST_M  (RTCLOCKCALI_CALI_DONE_INT_ST_V << RTCLOCKCALI_CALI_DONE_INT_ST_S)
+#define RTCLOCKCALI_CALI_DONE_INT_ST_V  0x00000001U
+#define RTCLOCKCALI_CALI_DONE_INT_ST_S  31
+
+/** RTCLOCKCALI_INT_ENA_REG register
+ *  Configure register.
+ */
+#define RTCLOCKCALI_INT_ENA_REG (DR_REG_RTCLOCKCALI_BASE + 0x40)
+/** RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  Interrupt enable signal.
+ */
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA    (BIT(29))
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_M  (RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_V << RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_S)
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_V  0x00000001U
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_ENA_S  29
+/** RTCLOCKCALI_CALI_TIMEOUT_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  Interrupt enable signal.
+ */
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_ENA    (BIT(30))
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_M  (RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_V << RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_S)
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_V  0x00000001U
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_ENA_S  30
+/** RTCLOCKCALI_CALI_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  Interrupt enable signal.
+ */
+#define RTCLOCKCALI_CALI_DONE_INT_ENA    (BIT(31))
+#define RTCLOCKCALI_CALI_DONE_INT_ENA_M  (RTCLOCKCALI_CALI_DONE_INT_ENA_V << RTCLOCKCALI_CALI_DONE_INT_ENA_S)
+#define RTCLOCKCALI_CALI_DONE_INT_ENA_V  0x00000001U
+#define RTCLOCKCALI_CALI_DONE_INT_ENA_S  31
+
+/** RTCLOCKCALI_INT_CLR_REG register
+ *  Configure register.
+ */
+#define RTCLOCKCALI_INT_CLR_REG (DR_REG_RTCLOCKCALI_BASE + 0x44)
+/** RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  interrupt clear signal.
+ */
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR    (BIT(29))
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_M  (RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_V << RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_S)
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_V  0x00000001U
+#define RTCLOCKCALI_XTAL_TIMEOUT_INT_CLR_S  29
+/** RTCLOCKCALI_CALI_TIMEOUT_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  interrupt clear signal.
+ */
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_CLR    (BIT(30))
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_M  (RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_V << RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_S)
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_V  0x00000001U
+#define RTCLOCKCALI_CALI_TIMEOUT_INT_CLR_S  30
+/** RTCLOCKCALI_CALI_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  interrupt clear signal.
+ */
+#define RTCLOCKCALI_CALI_DONE_INT_CLR    (BIT(31))
+#define RTCLOCKCALI_CALI_DONE_INT_CLR_M  (RTCLOCKCALI_CALI_DONE_INT_CLR_V << RTCLOCKCALI_CALI_DONE_INT_CLR_S)
+#define RTCLOCKCALI_CALI_DONE_INT_CLR_V  0x00000001U
+#define RTCLOCKCALI_CALI_DONE_INT_CLR_S  31
+
+/** RTCLOCKCALI_TIMEOUT_REG register
+ *  Configure register.
+ */
+#define RTCLOCKCALI_TIMEOUT_REG (DR_REG_RTCLOCKCALI_BASE + 0x48)
+/** RTCLOCKCALI_TIMEOUT_TARGET : R/W; bitpos: [29:0]; default: 0;
+ *  use to setting max calibration time .
+ */
+#define RTCLOCKCALI_TIMEOUT_TARGET    0x3FFFFFFFU
+#define RTCLOCKCALI_TIMEOUT_TARGET_M  (RTCLOCKCALI_TIMEOUT_TARGET_V << RTCLOCKCALI_TIMEOUT_TARGET_S)
+#define RTCLOCKCALI_TIMEOUT_TARGET_V  0x3FFFFFFFU
+#define RTCLOCKCALI_TIMEOUT_TARGET_S  0
+/** RTCLOCKCALI_TIMEOUT_EN : R/W; bitpos: [31]; default: 0;
+ *  use to enable calibration time-out function ,the calibration force stopping,when
+ *  timeout.
+ */
+#define RTCLOCKCALI_TIMEOUT_EN    (BIT(31))
+#define RTCLOCKCALI_TIMEOUT_EN_M  (RTCLOCKCALI_TIMEOUT_EN_V << RTCLOCKCALI_TIMEOUT_EN_S)
+#define RTCLOCKCALI_TIMEOUT_EN_V  0x00000001U
+#define RTCLOCKCALI_TIMEOUT_EN_S  31
+
+/** RTCLOCKCALI_XTAL_TIMEOUT_REG register
+ *  Configure register.
+ */
+#define RTCLOCKCALI_XTAL_TIMEOUT_REG (DR_REG_RTCLOCKCALI_BASE + 0x4c)
+/** RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET : R/W; bitpos: [29:14]; default: 65535;
+ *  use to setting max xtal monitor time .
+ */
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET    0x0000FFFFU
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_M  (RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_V << RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_S)
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_V  0x0000FFFFU
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_TARGET_S  14
+/** RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP : WT; bitpos: [30]; default: 0;
+ *  use to stop XTAL time-out function ,timeout happened when xtal invalid.
+ */
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP    (BIT(30))
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_M  (RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_V << RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_S)
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_V  0x00000001U
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_STOP_S  30
+/** RTCLOCKCALI_XTAL_TIMEOUT_CNT_START : WT; bitpos: [31]; default: 0;
+ *  use to start XTAL time-out function ,timeout happened when xtal invalid.
+ */
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_START    (BIT(31))
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_M  (RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_V << RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_S)
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_V  0x00000001U
+#define RTCLOCKCALI_XTAL_TIMEOUT_CNT_START_S  31
+
+/** RTCLOCKCALI_DATE_REG register
+ *  Configure register.
+ */
+#define RTCLOCKCALI_DATE_REG (DR_REG_RTCLOCKCALI_BASE + 0x3fc)
+/** RTCLOCKCALI_RTCLOCKCALI_DATE : R/W; bitpos: [30:0]; default: 36708448;
+ *  need_des
+ */
+#define RTCLOCKCALI_RTCLOCKCALI_DATE    0x7FFFFFFFU
+#define RTCLOCKCALI_RTCLOCKCALI_DATE_M  (RTCLOCKCALI_RTCLOCKCALI_DATE_V << RTCLOCKCALI_RTCLOCKCALI_DATE_S)
+#define RTCLOCKCALI_RTCLOCKCALI_DATE_V  0x7FFFFFFFU
+#define RTCLOCKCALI_RTCLOCKCALI_DATE_S  0
+/** RTCLOCKCALI_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTCLOCKCALI_CLK_EN    (BIT(31))
+#define RTCLOCKCALI_CLK_EN_M  (RTCLOCKCALI_CLK_EN_V << RTCLOCKCALI_CLK_EN_S)
+#define RTCLOCKCALI_CLK_EN_V  0x00000001U
+#define RTCLOCKCALI_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/rtclockcali_struct.h

@@ -0,0 +1,521 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of lp_cali_timer register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** timer_target : R/W; bitpos: [29:0]; default: 4095;
+         *  need_des
+         */
+        uint32_t timer_target:30;
+        /** timer_stop : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t timer_stop:1;
+        /** timer_start : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t timer_start:1;
+    };
+    uint32_t val;
+} rtclockcali_lp_cali_timer_reg_t;
+
+/** Type of dfreq_high_limit_slow register
+ *  RTC slow clock dfreq high limit.
+ */
+typedef union {
+    struct {
+        /** coarse_limit_diff_slow : R/W; bitpos: [7:0]; default: 16;
+         *  When rtc_cali_value upper/lower than reg_high/low_limit +/-
+         *  reg_coarse_limit_diff,the step of dfreq,will use reg_coarse_step.
+         */
+        uint32_t coarse_limit_diff_slow:8;
+        /** high_limit_slow : R/W; bitpos: [31:8]; default: 267;
+         *  when rtc_cali_value upper than reg_high_limit,frequency of osc will  increase .
+         */
+        uint32_t high_limit_slow:24;
+    };
+    uint32_t val;
+} rtclockcali_dfreq_high_limit_slow_reg_t;
+
+/** Type of dfreq_low_limit_slow register
+ *  RTC slow clock dfreq low limit.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** low_limit_slow : R/W; bitpos: [31:8]; default: 266;
+         *  when rtc_cali_value lower than reg_low_limit,frequency of osc will  decrease .
+         */
+        uint32_t low_limit_slow:24;
+    };
+    uint32_t val;
+} rtclockcali_dfreq_low_limit_slow_reg_t;
+
+/** Type of dfreq_high_limit_fast register
+ *  RTC fast clock dfreq high limit.
+ */
+typedef union {
+    struct {
+        /** coarse_limit_diff_fast : R/W; bitpos: [7:0]; default: 16;
+         *  When rtc_cali_value upper/lower than reg_high/low_limit +/-
+         *  reg_coarse_limit_diff,the step of dfreq,will use reg_coarse_step.
+         */
+        uint32_t coarse_limit_diff_fast:8;
+        /** high_limit_fast : R/W; bitpos: [31:8]; default: 267;
+         *  when rtc_cali_value upper than reg_high_limit,frequency of osc will  increase .
+         */
+        uint32_t high_limit_fast:24;
+    };
+    uint32_t val;
+} rtclockcali_dfreq_high_limit_fast_reg_t;
+
+/** Type of dfreq_low_limit_fast register
+ *  RTC fast clock dfreq low limit.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** low_limit_fast : R/W; bitpos: [31:8]; default: 266;
+         *  when rtc_cali_value lower than reg_low_limit,frequency of osc will  decrease .
+         */
+        uint32_t low_limit_fast:24;
+    };
+    uint32_t val;
+} rtclockcali_dfreq_low_limit_fast_reg_t;
+
+/** Type of dfreq_conf2 register
+ *  RTC DFREQ CONF2
+ */
+typedef union {
+    struct {
+        /** dreq_update : WT; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t dreq_update:1;
+        uint32_t reserved_1:1;
+        /** dreq_init_32k : WT; bitpos: [2]; default: 0;
+         *  Initialize the value of 32K OSC dfreq setting.
+         */
+        uint32_t dreq_init_32k:1;
+        /** dreq_init_fosc : WT; bitpos: [3]; default: 0;
+         *  Initialize the value of FOSC  dfreq setting.
+         */
+        uint32_t dreq_init_fosc:1;
+        /** dreq_init_sosc : WT; bitpos: [4]; default: 0;
+         *  Initialize the value of SOSC  dfreq setting.
+         */
+        uint32_t dreq_init_sosc:1;
+        /** rc32k_dfreq_sel : R/W; bitpos: [5]; default: 0;
+         *  1:Frequency of 32k controlled by calibration module.0:Frequency of 32k controlled
+         *  by register from system-register bank
+         */
+        uint32_t rc32k_dfreq_sel:1;
+        /** fosc_dfreq_sel : R/W; bitpos: [6]; default: 0;
+         *  1:Frequency of FOSC controlled by calibration module.0:Frequency of FOSC controlled
+         *  by register from system-register bank
+         */
+        uint32_t fosc_dfreq_sel:1;
+        /** sosc_dfreq_sel : R/W; bitpos: [7]; default: 0;
+         *  1:Frequency of SOSC controlled by calibration module.0:Frequency of SOSC controlled
+         *  by register from system-register bank
+         */
+        uint32_t sosc_dfreq_sel:1;
+        /** fine_step : R/W; bitpos: [15:8]; default: 1;
+         *  Frequency fine step.
+         */
+        uint32_t fine_step:8;
+        /** coarse_step_fast : R/W; bitpos: [23:16]; default: 8;
+         *  Frequency coarse step,use to decrease calibration time.
+         */
+        uint32_t coarse_step_fast:8;
+        /** coarse_step_slow : R/W; bitpos: [31:24]; default: 8;
+         *  Frequency coarse step,use to decrease calibration time.
+         */
+        uint32_t coarse_step_slow:8;
+    };
+    uint32_t val;
+} rtclockcali_dfreq_conf2_reg_t;
+
+/** Type of cali_en register
+ *  Configure register.
+ */
+typedef union {
+    struct {
+        /** cali_en_32k : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t cali_en_32k:1;
+        /** cali_en_fosc : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t cali_en_fosc:1;
+        /** cali_en_sosc : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t cali_en_sosc:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} rtclockcali_cali_en_reg_t;
+
+/** Type of dfreq_value register
+ *  Configure register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** dreq_32k : RO; bitpos: [11:2]; default: 172;
+         *  The value of dfreq num of 32k.
+         */
+        uint32_t dreq_32k:10;
+        /** dreq_fosc : RO; bitpos: [21:12]; default: 512;
+         *  The value of dfreq num of FOSC.
+         */
+        uint32_t dreq_fosc:10;
+        /** dreq_sosc : RO; bitpos: [31:22]; default: 512;
+         *  The value of dfreq num of SOSC.
+         */
+        uint32_t dreq_sosc:10;
+    };
+    uint32_t val;
+} rtclockcali_dfreq_value_reg_t;
+
+/** Type of bypass register
+ *  Configure register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** hp_sleep_autocali : R/W; bitpos: [30]; default: 0;
+         *  1:Chip begin to calibrating,when into hp_sleep.0:Disable this function.
+         */
+        uint32_t hp_sleep_autocali:1;
+        /** lp_sleep_autocali : R/W; bitpos: [31]; default: 0;
+         *  1:Chip begin to calibrating,when into lp_sleep.0:Disable this function.
+         */
+        uint32_t lp_sleep_autocali:1;
+    };
+    uint32_t val;
+} rtclockcali_bypass_reg_t;
+
+/** Type of int_raw register
+ *  Configure register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:29;
+        /** xtal_timeout_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  Indicate the xtal timeout  once happened .
+         */
+        uint32_t xtal_timeout_int_raw:1;
+        /** cali_timeout_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  Indicate the calibration timeout  once happened .
+         */
+        uint32_t cali_timeout_int_raw:1;
+        /** cali_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  Indicate the finish of once calibration .
+         */
+        uint32_t cali_done_int_raw:1;
+    };
+    uint32_t val;
+} rtclockcali_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Interrupt state register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:29;
+        /** xtal_timeout_int_st : RO; bitpos: [29]; default: 0;
+         *  Interrupt state register.
+         */
+        uint32_t xtal_timeout_int_st:1;
+        /** cali_timeout_int_st : RO; bitpos: [30]; default: 0;
+         *  Interrupt state register.
+         */
+        uint32_t cali_timeout_int_st:1;
+        /** cali_done_int_st : RO; bitpos: [31]; default: 0;
+         *  Interrupt state register.
+         */
+        uint32_t cali_done_int_st:1;
+    };
+    uint32_t val;
+} rtclockcali_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Configure register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:29;
+        /** xtal_timeout_int_ena : R/W; bitpos: [29]; default: 0;
+         *  Interrupt enable signal.
+         */
+        uint32_t xtal_timeout_int_ena:1;
+        /** cali_timeout_int_ena : R/W; bitpos: [30]; default: 0;
+         *  Interrupt enable signal.
+         */
+        uint32_t cali_timeout_int_ena:1;
+        /** cali_done_int_ena : R/W; bitpos: [31]; default: 0;
+         *  Interrupt enable signal.
+         */
+        uint32_t cali_done_int_ena:1;
+    };
+    uint32_t val;
+} rtclockcali_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Configure register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:29;
+        /** xtal_timeout_int_clr : WT; bitpos: [29]; default: 0;
+         *  interrupt clear signal.
+         */
+        uint32_t xtal_timeout_int_clr:1;
+        /** cali_timeout_int_clr : WT; bitpos: [30]; default: 0;
+         *  interrupt clear signal.
+         */
+        uint32_t cali_timeout_int_clr:1;
+        /** cali_done_int_clr : WT; bitpos: [31]; default: 0;
+         *  interrupt clear signal.
+         */
+        uint32_t cali_done_int_clr:1;
+    };
+    uint32_t val;
+} rtclockcali_int_clr_reg_t;
+
+/** Type of timeout register
+ *  Configure register.
+ */
+typedef union {
+    struct {
+        /** timeout_target : R/W; bitpos: [29:0]; default: 0;
+         *  use to setting max calibration time .
+         */
+        uint32_t timeout_target:30;
+        uint32_t reserved_30:1;
+        /** timeout_en : R/W; bitpos: [31]; default: 0;
+         *  use to enable calibration time-out function ,the calibration force stopping,when
+         *  timeout.
+         */
+        uint32_t timeout_en:1;
+    };
+    uint32_t val;
+} rtclockcali_timeout_reg_t;
+
+/** Type of xtal_timeout register
+ *  Configure register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:14;
+        /** xtal_timeout_cnt_target : R/W; bitpos: [29:14]; default: 65535;
+         *  use to setting max xtal monitor time .
+         */
+        uint32_t xtal_timeout_cnt_target:16;
+        /** xtal_timeout_cnt_stop : WT; bitpos: [30]; default: 0;
+         *  use to stop XTAL time-out function ,timeout happened when xtal invalid.
+         */
+        uint32_t xtal_timeout_cnt_stop:1;
+        /** xtal_timeout_cnt_start : WT; bitpos: [31]; default: 0;
+         *  use to start XTAL time-out function ,timeout happened when xtal invalid.
+         */
+        uint32_t xtal_timeout_cnt_start:1;
+    };
+    uint32_t val;
+} rtclockcali_xtal_timeout_reg_t;
+
+/** Type of date register
+ *  Configure register.
+ */
+typedef union {
+    struct {
+        /** rtclockcali_date : R/W; bitpos: [30:0]; default: 36708448;
+         *  need_des
+         */
+        uint32_t rtclockcali_date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} rtclockcali_date_reg_t;
+
+
+/** Group: RTC CALI Control and configuration registers */
+/** Type of rtccalicfg_slow register
+ *  RTC calibration configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** rtc_cali_start_cycling_slow : R/W; bitpos: [12]; default: 1;
+         *  0: one-shot frequency calculation,1: periodic frequency calculation,
+         */
+        uint32_t rtc_cali_start_cycling_slow:1;
+        /** rtc_cali_clk_sel_slow : R/W; bitpos: [14:13]; default: 0;
+         *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+         */
+        uint32_t rtc_cali_clk_sel_slow:2;
+        /** rtc_cali_rdy_slow : RO; bitpos: [15]; default: 0;
+         *  indicate one-shot frequency calculation is done.
+         */
+        uint32_t rtc_cali_rdy_slow:1;
+        /** rtc_cali_max_slow : R/W; bitpos: [30:16]; default: 1;
+         *  Configure the time to calculate RTC slow clock's frequency.
+         */
+        uint32_t rtc_cali_max_slow:15;
+        /** rtc_cali_start_slow : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to start one-shot frequency calculation.
+         */
+        uint32_t rtc_cali_start_slow:1;
+    };
+    uint32_t val;
+} rtclockcali_rtccalicfg_slow_reg_t;
+
+/** Type of rtccalicfg_fast register
+ *  RTC calibration configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** fosc_div_num : R/W; bitpos: [11:4]; default: 0;
+         *  fosc clock divider number
+         */
+        uint32_t fosc_div_num:8;
+        /** rtc_cali_start_cycling_fast : R/W; bitpos: [12]; default: 1;
+         *  0: one-shot frequency calculation,1: periodic frequency calculation,
+         */
+        uint32_t rtc_cali_start_cycling_fast:1;
+        /** rtc_cali_clk_sel_fast : R/W; bitpos: [14:13]; default: 0;
+         *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+         */
+        uint32_t rtc_cali_clk_sel_fast:2;
+        /** rtc_cali_rdy_fast : RO; bitpos: [15]; default: 0;
+         *  indicate one-shot frequency calculation is done.
+         */
+        uint32_t rtc_cali_rdy_fast:1;
+        /** rtc_cali_max_fast : R/W; bitpos: [30:16]; default: 1;
+         *  Configure the time to calculate RTC slow clock's frequency.
+         */
+        uint32_t rtc_cali_max_fast:15;
+        /** rtc_cali_start_fast : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to start one-shot frequency calculation.
+         */
+        uint32_t rtc_cali_start_fast:1;
+    };
+    uint32_t val;
+} rtclockcali_rtccalicfg_fast_reg_t;
+
+/** Type of rtccalicfg1_slow register
+ *  RTC calibration configure1 register
+ */
+typedef union {
+    struct {
+        /** rtc_cali_cycling_data_vld_slow : RO; bitpos: [0]; default: 0;
+         *  indicate periodic frequency calculation is done.
+         */
+        uint32_t rtc_cali_cycling_data_vld_slow:1;
+        uint32_t reserved_1:6;
+        /** rtc_cali_value_slow : RO; bitpos: [31:7]; default: 0;
+         *  When one-shot or periodic frequency calculation is done, read this value to
+         *  calculate RTC slow clock's frequency.
+         */
+        uint32_t rtc_cali_value_slow:25;
+    };
+    uint32_t val;
+} rtclockcali_rtccalicfg1_slow_reg_t;
+
+/** Type of rtccalicfg1_fast register
+ *  RTC calibration configure1 register
+ */
+typedef union {
+    struct {
+        /** rtc_cali_cycling_data_vld_fast : RO; bitpos: [0]; default: 0;
+         *  indicate periodic frequency calculation is done.
+         */
+        uint32_t rtc_cali_cycling_data_vld_fast:1;
+        uint32_t reserved_1:6;
+        /** rtc_cali_value_fast : RO; bitpos: [31:7]; default: 0;
+         *  When one-shot or periodic frequency calculation is done, read this value to
+         *  calculate RTC slow clock's frequency.
+         */
+        uint32_t rtc_cali_value_fast:25;
+    };
+    uint32_t val;
+} rtclockcali_rtccalicfg1_fast_reg_t;
+
+/** Type of rtccalicfg2 register
+ *  Timer group calibration register
+ */
+typedef union {
+    struct {
+        /** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
+         *  RTC calibration timeout indicator
+         */
+        uint32_t rtc_cali_timeout:1;
+        uint32_t reserved_1:2;
+        /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
+         *  Cycles that release calibration timeout reset
+         */
+        uint32_t rtc_cali_timeout_rst_cnt:4;
+        /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
+         *  Threshold value for the RTC calibration timer. If the calibration timer's value
+         *  exceeds this threshold, a timeout is triggered.
+         */
+        uint32_t rtc_cali_timeout_thres:25;
+    };
+    uint32_t val;
+} rtclockcali_rtccalicfg2_reg_t;
+
+
+typedef struct {
+    volatile rtclockcali_lp_cali_timer_reg_t lp_cali_timer;
+    volatile rtclockcali_rtccalicfg_slow_reg_t rtccalicfg_slow;
+    volatile rtclockcali_rtccalicfg_fast_reg_t rtccalicfg_fast;
+    volatile rtclockcali_rtccalicfg1_slow_reg_t rtccalicfg1_slow;
+    volatile rtclockcali_rtccalicfg1_fast_reg_t rtccalicfg1_fast;
+    volatile rtclockcali_rtccalicfg2_reg_t rtccalicfg2;
+    volatile rtclockcali_dfreq_high_limit_slow_reg_t dfreq_high_limit_slow;
+    volatile rtclockcali_dfreq_low_limit_slow_reg_t dfreq_low_limit_slow;
+    volatile rtclockcali_dfreq_high_limit_fast_reg_t dfreq_high_limit_fast;
+    volatile rtclockcali_dfreq_low_limit_fast_reg_t dfreq_low_limit_fast;
+    volatile rtclockcali_dfreq_conf2_reg_t dfreq_conf2;
+    volatile rtclockcali_cali_en_reg_t cali_en;
+    volatile rtclockcali_dfreq_value_reg_t dfreq_value;
+    volatile rtclockcali_bypass_reg_t bypass;
+    volatile rtclockcali_int_raw_reg_t int_raw;
+    volatile rtclockcali_int_st_reg_t int_st;
+    volatile rtclockcali_int_ena_reg_t int_ena;
+    volatile rtclockcali_int_clr_reg_t int_clr;
+    volatile rtclockcali_timeout_reg_t timeout;
+    volatile rtclockcali_xtal_timeout_reg_t xtal_timeout;
+    uint32_t reserved_050[235];
+    volatile rtclockcali_date_reg_t date;
+} rtclockcali_dev_t;
+
+extern rtclockcali_dev_t RTCLOCKCALI;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(rtclockcali_dev_t) == 0x400, "Invalid size of rtclockcali_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/sha_eco5_reg.h

@@ -0,0 +1,170 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SHA_MODE_REG register
+ *  Configures SHA algorithm
+ */
+#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
+/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Configures the SHA algorithm.
+ *  0: SHA-1
+ *  1: SHA-224
+ *  2: SHA-256
+ *  3: SHA2-384
+ *  4: SHA2-512
+ *  5: SHA2-512/224
+ *  6: SHA2-512/256
+ *  7: SHA2-512/t
+ */
+#define SHA_MODE    0x00000007U
+#define SHA_MODE_M  (SHA_MODE_V << SHA_MODE_S)
+#define SHA_MODE_V  0x00000007U
+#define SHA_MODE_S  0
+
+/** SHA_DMA_BLOCK_NUM_REG register
+ *  Block number register (only effective for DMA-SHA)
+ */
+#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
+/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the DMA-SHA block number.
+ */
+#define SHA_DMA_BLOCK_NUM    0x0000FFFFU
+#define SHA_DMA_BLOCK_NUM_M  (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
+#define SHA_DMA_BLOCK_NUM_V  0x0000FFFFU
+#define SHA_DMA_BLOCK_NUM_S  0
+
+/** SHA_START_REG register
+ *  Starts the SHA accelerator for Typical SHA operation
+ */
+#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
+/** SHA_START : WO; bitpos: [0]; default: 0;
+ *  Write 1 to start Typical SHA calculation.
+ */
+#define SHA_START    (BIT(0))
+#define SHA_START_M  (SHA_START_V << SHA_START_S)
+#define SHA_START_V  0x00000001U
+#define SHA_START_S  0
+
+/** SHA_CONTINUE_REG register
+ *  Continues SHA operation (only effective in Typical SHA mode)
+ */
+#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
+/** SHA_CONTINUE : WO; bitpos: [0]; default: 0;
+ *  Write 1 to continue Typical SHA calculation.
+ */
+#define SHA_CONTINUE    (BIT(0))
+#define SHA_CONTINUE_M  (SHA_CONTINUE_V << SHA_CONTINUE_S)
+#define SHA_CONTINUE_V  0x00000001U
+#define SHA_CONTINUE_S  0
+
+/** SHA_BUSY_REG register
+ *  Represents if SHA Accelerator is busy or not
+ */
+#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
+/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
+ *  Represents the states of SHA accelerator.
+ *  0: idle
+ *  1: busy
+ */
+#define SHA_BUSY_STATE    (BIT(0))
+#define SHA_BUSY_STATE_M  (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
+#define SHA_BUSY_STATE_V  0x00000001U
+#define SHA_BUSY_STATE_S  0
+
+/** SHA_DMA_START_REG register
+ *  Starts the SHA accelerator for DMA-SHA operation
+ */
+#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
+/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
+ *  Write 1 to start DMA-SHA calculation.
+ */
+#define SHA_DMA_START    (BIT(0))
+#define SHA_DMA_START_M  (SHA_DMA_START_V << SHA_DMA_START_S)
+#define SHA_DMA_START_V  0x00000001U
+#define SHA_DMA_START_S  0
+
+/** SHA_DMA_CONTINUE_REG register
+ *  Continues SHA operation (only effective in DMA-SHA mode)
+ */
+#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
+/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
+ *  Write 1 to continue DMA-SHA calculation.
+ */
+#define SHA_DMA_CONTINUE    (BIT(0))
+#define SHA_DMA_CONTINUE_M  (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
+#define SHA_DMA_CONTINUE_V  0x00000001U
+#define SHA_DMA_CONTINUE_S  0
+
+/** SHA_CLEAR_IRQ_REG register
+ *  DMA-SHA interrupt clear register
+ */
+#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
+/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
+ *  Write 1 to clear DMA-SHA interrupt.
+ */
+#define SHA_CLEAR_INTERRUPT    (BIT(0))
+#define SHA_CLEAR_INTERRUPT_M  (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
+#define SHA_CLEAR_INTERRUPT_V  0x00000001U
+#define SHA_CLEAR_INTERRUPT_S  0
+
+/** SHA_IRQ_ENA_REG register
+ *  DMA-SHA interrupt enable register
+ */
+#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
+/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable DMA-SHA interrupt.
+ */
+#define SHA_INTERRUPT_ENA    (BIT(0))
+#define SHA_INTERRUPT_ENA_M  (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
+#define SHA_INTERRUPT_ENA_V  0x00000001U
+#define SHA_INTERRUPT_ENA_S  0
+
+/** SHA_DATE_REG register
+ *  Version control register
+ */
+#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
+/** SHA_DATE : R/W; bitpos: [29:0]; default: 539232291;
+ *  Version control register.
+ */
+#define SHA_DATE    0x3FFFFFFFU
+#define SHA_DATE_M  (SHA_DATE_V << SHA_DATE_S)
+#define SHA_DATE_V  0x3FFFFFFFU
+#define SHA_DATE_S  0
+
+/** SHA_DMA_RX_RESET_REG register
+ *  DMA RX FIFO Reset Signal
+ */
+#define SHA_DMA_RX_RESET_REG (DR_REG_SHA_BASE + 0x30)
+/** SHA_DMA_RX_RESET : WO; bitpos: [0]; default: 0;
+ *  Write 1 to reset DMA RX FIFO
+ */
+#define SHA_DMA_RX_RESET    (BIT(0))
+#define SHA_DMA_RX_RESET_M  (SHA_DMA_RX_RESET_V << SHA_DMA_RX_RESET_S)
+#define SHA_DMA_RX_RESET_V  0x00000001U
+#define SHA_DMA_RX_RESET_S  0
+
+/** SHA_H_MEM register
+ *  Sha H memory which contains intermediate hash or final hash.
+ */
+#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
+#define SHA_H_MEM_SIZE_BYTES 64
+
+/** SHA_M_MEM register
+ *  Sha M memory which contains message.
+ */
+#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
+#define SHA_M_MEM_SIZE_BYTES 128
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/sha_reg.h

@@ -0,0 +1,172 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SHA_MODE_REG register
+ *  Initial configuration register.
+ */
+#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
+/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Sha mode.
+ */
+#define SHA_MODE    0x00000007U
+#define SHA_MODE_M  (SHA_MODE_V << SHA_MODE_S)
+#define SHA_MODE_V  0x00000007U
+#define SHA_MODE_S  0
+
+/** SHA_T_STRING_REG register
+ *  SHA 512/t configuration register 0.
+ */
+#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4)
+/** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0;
+ *  Sha t_string (used if and only if mode == SHA_512/t).
+ */
+#define SHA_T_STRING    0xFFFFFFFFU
+#define SHA_T_STRING_M  (SHA_T_STRING_V << SHA_T_STRING_S)
+#define SHA_T_STRING_V  0xFFFFFFFFU
+#define SHA_T_STRING_S  0
+
+/** SHA_T_LENGTH_REG register
+ *  SHA 512/t configuration register 1.
+ */
+#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8)
+/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0;
+ *  Sha t_length (used if and only if mode == SHA_512/t).
+ */
+#define SHA_T_LENGTH    0x0000003FU
+#define SHA_T_LENGTH_M  (SHA_T_LENGTH_V << SHA_T_LENGTH_S)
+#define SHA_T_LENGTH_V  0x0000003FU
+#define SHA_T_LENGTH_S  0
+
+/** SHA_DMA_BLOCK_NUM_REG register
+ *  DMA configuration register 0.
+ */
+#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
+/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
+ *  Dma-sha block number.
+ */
+#define SHA_DMA_BLOCK_NUM    0x0000003FU
+#define SHA_DMA_BLOCK_NUM_M  (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
+#define SHA_DMA_BLOCK_NUM_V  0x0000003FU
+#define SHA_DMA_BLOCK_NUM_S  0
+
+/** SHA_START_REG register
+ *  Typical SHA configuration register 0.
+ */
+#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
+/** SHA_START : RO; bitpos: [31:1]; default: 0;
+ *  Reserved.
+ */
+#define SHA_START    0x7FFFFFFFU
+#define SHA_START_M  (SHA_START_V << SHA_START_S)
+#define SHA_START_V  0x7FFFFFFFU
+#define SHA_START_S  1
+
+/** SHA_CONTINUE_REG register
+ *  Typical SHA configuration register 1.
+ */
+#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
+/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0;
+ *  Reserved.
+ */
+#define SHA_CONTINUE    0x7FFFFFFFU
+#define SHA_CONTINUE_M  (SHA_CONTINUE_V << SHA_CONTINUE_S)
+#define SHA_CONTINUE_V  0x7FFFFFFFU
+#define SHA_CONTINUE_S  1
+
+/** SHA_BUSY_REG register
+ *  Busy register.
+ */
+#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
+/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
+ *  Sha busy state. 1'b0: idle. 1'b1: busy.
+ */
+#define SHA_BUSY_STATE    (BIT(0))
+#define SHA_BUSY_STATE_M  (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
+#define SHA_BUSY_STATE_V  0x00000001U
+#define SHA_BUSY_STATE_S  0
+
+/** SHA_DMA_START_REG register
+ *  DMA configuration register 1.
+ */
+#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
+/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
+ *  Start dma-sha.
+ */
+#define SHA_DMA_START    (BIT(0))
+#define SHA_DMA_START_M  (SHA_DMA_START_V << SHA_DMA_START_S)
+#define SHA_DMA_START_V  0x00000001U
+#define SHA_DMA_START_S  0
+
+/** SHA_DMA_CONTINUE_REG register
+ *  DMA configuration register 2.
+ */
+#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
+/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
+ *  Continue dma-sha.
+ */
+#define SHA_DMA_CONTINUE    (BIT(0))
+#define SHA_DMA_CONTINUE_M  (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
+#define SHA_DMA_CONTINUE_V  0x00000001U
+#define SHA_DMA_CONTINUE_S  0
+
+/** SHA_CLEAR_IRQ_REG register
+ *  Interrupt clear register.
+ */
+#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
+/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
+ *  Clear sha interrupt.
+ */
+#define SHA_CLEAR_INTERRUPT    (BIT(0))
+#define SHA_CLEAR_INTERRUPT_M  (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
+#define SHA_CLEAR_INTERRUPT_V  0x00000001U
+#define SHA_CLEAR_INTERRUPT_S  0
+
+/** SHA_IRQ_ENA_REG register
+ *  Interrupt enable register.
+ */
+#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
+/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
+ */
+#define SHA_INTERRUPT_ENA    (BIT(0))
+#define SHA_INTERRUPT_ENA_M  (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
+#define SHA_INTERRUPT_ENA_V  0x00000001U
+#define SHA_INTERRUPT_ENA_S  0
+
+/** SHA_DATE_REG register
+ *  Date register.
+ */
+#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
+/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713;
+ *  Sha date information/ sha version information.
+ */
+#define SHA_DATE    0x3FFFFFFFU
+#define SHA_DATE_M  (SHA_DATE_V << SHA_DATE_S)
+#define SHA_DATE_V  0x3FFFFFFFU
+#define SHA_DATE_S  0
+
+/** SHA_H_MEM register
+ *  Sha H memory which contains intermediate hash or final hash.
+ */
+#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
+#define SHA_H_MEM_SIZE_BYTES 64
+
+/** SHA_M_MEM register
+ *  Sha M memory which contains message.
+ */
+#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
+#define SHA_M_MEM_SIZE_BYTES 64
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/sha_struct.h

@@ -0,0 +1,213 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control/Configuration Registers */
+/** Type of mode register
+ *  Configures SHA algorithm
+ */
+typedef union {
+    struct {
+        /** mode : R/W; bitpos: [2:0]; default: 0;
+         *  Configures the SHA algorithm.
+         *  0: SHA-1
+         *  1: SHA-224
+         *  2: SHA-256
+         *  3: SHA2-384
+         *  4: SHA2-512
+         *  5: SHA2-512/224
+         *  6: SHA2-512/256
+         *  7: SHA2-512/t
+         */
+        uint32_t mode:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} sha_mode_reg_t;
+
+/** Type of dma_block_num register
+ *  Block number register (only effective for DMA-SHA)
+ */
+typedef union {
+    struct {
+        /** dma_block_num : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the DMA-SHA block number.
+         */
+        uint32_t dma_block_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} sha_dma_block_num_reg_t;
+
+/** Type of start register
+ *  Starts the SHA accelerator for Typical SHA operation
+ */
+typedef union {
+    struct {
+        /** start : WO; bitpos: [0]; default: 0;
+         *  Write 1 to start Typical SHA calculation.
+         */
+        uint32_t start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sha_start_reg_t;
+
+/** Type of continue register
+ *  Continues SHA operation (only effective in Typical SHA mode)
+ */
+typedef union {
+    struct {
+        /** continue : WO; bitpos: [0]; default: 0;
+         *  Write 1 to continue Typical SHA calculation.
+         */
+        uint32_t conti:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sha_continue_reg_t;
+
+/** Type of dma_start register
+ *  Starts the SHA accelerator for DMA-SHA operation
+ */
+typedef union {
+    struct {
+        /** dma_start : WO; bitpos: [0]; default: 0;
+         *  Write 1 to start DMA-SHA calculation.
+         */
+        uint32_t dma_start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sha_dma_start_reg_t;
+
+/** Type of dma_continue register
+ *  Continues SHA operation (only effective in DMA-SHA mode)
+ */
+typedef union {
+    struct {
+        /** dma_continue : WO; bitpos: [0]; default: 0;
+         *  Write 1 to continue DMA-SHA calculation.
+         */
+        uint32_t dma_continue:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sha_dma_continue_reg_t;
+
+/** Type of dma_rx_reset register
+ *  DMA RX FIFO Reset Signal
+ */
+typedef union {
+    struct {
+        /** dma_rx_reset : WO; bitpos: [0]; default: 0;
+         *  Write 1 to reset DMA RX FIFO
+         */
+        uint32_t dma_rx_reset:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sha_dma_rx_reset_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of busy register
+ *  Represents if SHA Accelerator is busy or not
+ */
+typedef union {
+    struct {
+        /** busy_state : RO; bitpos: [0]; default: 0;
+         *  Represents the states of SHA accelerator.
+         *  0: idle
+         *  1: busy
+         */
+        uint32_t busy_state:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sha_busy_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of clear_irq register
+ *  DMA-SHA interrupt clear register
+ */
+typedef union {
+    struct {
+        /** clear_interrupt : WO; bitpos: [0]; default: 0;
+         *  Write 1 to clear DMA-SHA interrupt.
+         */
+        uint32_t clear_interrupt:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sha_clear_irq_reg_t;
+
+/** Type of irq_ena register
+ *  DMA-SHA interrupt enable register
+ */
+typedef union {
+    struct {
+        /** interrupt_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable DMA-SHA interrupt.
+         */
+        uint32_t interrupt_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sha_irq_ena_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [29:0]; default: 539232291;
+         *  Version control register.
+         */
+        uint32_t date:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} sha_date_reg_t;
+
+
+/** Group: memory type */
+
+typedef struct {
+    volatile sha_mode_reg_t mode;
+    uint32_t reserved_004[2];
+    volatile sha_dma_block_num_reg_t dma_block_num;
+    volatile sha_start_reg_t start;
+    volatile sha_continue_reg_t conti;
+    volatile sha_busy_reg_t busy;
+    volatile sha_dma_start_reg_t dma_start;
+    volatile sha_dma_continue_reg_t dma_continue;
+    volatile sha_clear_irq_reg_t clear_irq;
+    volatile sha_irq_ena_reg_t irq_ena;
+    volatile sha_date_reg_t date;
+    volatile sha_dma_rx_reset_reg_t dma_rx_reset;
+    uint32_t reserved_034[3];
+    volatile uint32_t h[16];
+    volatile uint32_t m[32];
+} sha_dev_t;
+
+extern sha_dev_t SHA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(sha_dev_t) == 0x100, "Invalid size of sha_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/systimer_reg.h

@@ -0,0 +1,630 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SYSTIMER_CONF_REG register
+ *  Configure system timer clock
+ */
+#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
+/** SYSTIMER_ETM_EN : R/W; bitpos: [1]; default: 0;
+ *  enable systimer's etm task and event
+ */
+#define SYSTIMER_ETM_EN    (BIT(1))
+#define SYSTIMER_ETM_EN_M  (SYSTIMER_ETM_EN_V << SYSTIMER_ETM_EN_S)
+#define SYSTIMER_ETM_EN_V  0x00000001U
+#define SYSTIMER_ETM_EN_S  1
+/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
+ *  target2 work enable
+ */
+#define SYSTIMER_TARGET2_WORK_EN    (BIT(22))
+#define SYSTIMER_TARGET2_WORK_EN_M  (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
+#define SYSTIMER_TARGET2_WORK_EN_V  0x00000001U
+#define SYSTIMER_TARGET2_WORK_EN_S  22
+/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
+ *  target1 work enable
+ */
+#define SYSTIMER_TARGET1_WORK_EN    (BIT(23))
+#define SYSTIMER_TARGET1_WORK_EN_M  (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
+#define SYSTIMER_TARGET1_WORK_EN_V  0x00000001U
+#define SYSTIMER_TARGET1_WORK_EN_S  23
+/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
+ *  target0 work enable
+ */
+#define SYSTIMER_TARGET0_WORK_EN    (BIT(24))
+#define SYSTIMER_TARGET0_WORK_EN_M  (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
+#define SYSTIMER_TARGET0_WORK_EN_V  0x00000001U
+#define SYSTIMER_TARGET0_WORK_EN_S  24
+/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
+ *  If timer unit1 is stalled when core1 stalled
+ */
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN    (BIT(25))
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S  25
+/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
+ *  If timer unit1 is stalled when core0 stalled
+ */
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN    (BIT(26))
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S  26
+/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
+ *  If timer unit0 is stalled when core1 stalled
+ */
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN    (BIT(27))
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S  27
+/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
+ *  If timer unit0 is stalled when core0 stalled
+ */
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN    (BIT(28))
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S  28
+/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
+ *  timer unit1 work enable
+ */
+#define SYSTIMER_TIMER_UNIT1_WORK_EN    (BIT(29))
+#define SYSTIMER_TIMER_UNIT1_WORK_EN_M  (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
+#define SYSTIMER_TIMER_UNIT1_WORK_EN_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT1_WORK_EN_S  29
+/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
+ *  timer unit0 work enable
+ */
+#define SYSTIMER_TIMER_UNIT0_WORK_EN    (BIT(30))
+#define SYSTIMER_TIMER_UNIT0_WORK_EN_M  (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
+#define SYSTIMER_TIMER_UNIT0_WORK_EN_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT0_WORK_EN_S  30
+/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  register file clk gating
+ */
+#define SYSTIMER_CLK_EN    (BIT(31))
+#define SYSTIMER_CLK_EN_M  (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
+#define SYSTIMER_CLK_EN_V  0x00000001U
+#define SYSTIMER_CLK_EN_S  31
+
+/** SYSTIMER_UNIT0_OP_REG register
+ *  system timer unit0 value update register
+ */
+#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
+/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
+ *  timer value is sync and valid
+ */
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID    (BIT(29))
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S  29
+/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
+ *  update timer_unit0
+ */
+#define SYSTIMER_TIMER_UNIT0_UPDATE    (BIT(30))
+#define SYSTIMER_TIMER_UNIT0_UPDATE_M  (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
+#define SYSTIMER_TIMER_UNIT0_UPDATE_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT0_UPDATE_S  30
+
+/** SYSTIMER_UNIT1_OP_REG register
+ *  system timer unit1 value update register
+ */
+#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
+/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
+ *  timer value is sync and valid
+ */
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID    (BIT(29))
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S  29
+/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
+ *  update timer unit1
+ */
+#define SYSTIMER_TIMER_UNIT1_UPDATE    (BIT(30))
+#define SYSTIMER_TIMER_UNIT1_UPDATE_M  (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
+#define SYSTIMER_TIMER_UNIT1_UPDATE_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT1_UPDATE_S  30
+
+/** SYSTIMER_UNIT0_LOAD_HI_REG register
+ *  system timer unit0 value high load register
+ */
+#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
+/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer unit0 load high 20 bits
+ */
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI    0x000FFFFFU
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M  (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V  0x000FFFFFU
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S  0
+
+/** SYSTIMER_UNIT0_LOAD_LO_REG register
+ *  system timer unit0 value low load register
+ */
+#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
+/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer unit0 load low 32 bits
+ */
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO    0xFFFFFFFFU
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M  (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V  0xFFFFFFFFU
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S  0
+
+/** SYSTIMER_UNIT1_LOAD_HI_REG register
+ *  system timer unit1 value high load register
+ */
+#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
+/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer unit1 load high 20 bits
+ */
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI    0x000FFFFFU
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M  (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V  0x000FFFFFU
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S  0
+
+/** SYSTIMER_UNIT1_LOAD_LO_REG register
+ *  system timer unit1 value low load register
+ */
+#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
+/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer unit1 load low 32 bits
+ */
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO    0xFFFFFFFFU
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M  (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V  0xFFFFFFFFU
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S  0
+
+/** SYSTIMER_TARGET0_HI_REG register
+ *  system timer comp0 value high register
+ */
+#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
+/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer taget0 high 20 bits
+ */
+#define SYSTIMER_TIMER_TARGET0_HI    0x000FFFFFU
+#define SYSTIMER_TIMER_TARGET0_HI_M  (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
+#define SYSTIMER_TIMER_TARGET0_HI_V  0x000FFFFFU
+#define SYSTIMER_TIMER_TARGET0_HI_S  0
+
+/** SYSTIMER_TARGET0_LO_REG register
+ *  system timer comp0 value low register
+ */
+#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
+/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer taget0 low 32 bits
+ */
+#define SYSTIMER_TIMER_TARGET0_LO    0xFFFFFFFFU
+#define SYSTIMER_TIMER_TARGET0_LO_M  (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
+#define SYSTIMER_TIMER_TARGET0_LO_V  0xFFFFFFFFU
+#define SYSTIMER_TIMER_TARGET0_LO_S  0
+
+/** SYSTIMER_TARGET1_HI_REG register
+ *  system timer comp1 value high register
+ */
+#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
+/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer taget1 high 20 bits
+ */
+#define SYSTIMER_TIMER_TARGET1_HI    0x000FFFFFU
+#define SYSTIMER_TIMER_TARGET1_HI_M  (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
+#define SYSTIMER_TIMER_TARGET1_HI_V  0x000FFFFFU
+#define SYSTIMER_TIMER_TARGET1_HI_S  0
+
+/** SYSTIMER_TARGET1_LO_REG register
+ *  system timer comp1 value low register
+ */
+#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
+/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer taget1 low 32 bits
+ */
+#define SYSTIMER_TIMER_TARGET1_LO    0xFFFFFFFFU
+#define SYSTIMER_TIMER_TARGET1_LO_M  (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
+#define SYSTIMER_TIMER_TARGET1_LO_V  0xFFFFFFFFU
+#define SYSTIMER_TIMER_TARGET1_LO_S  0
+
+/** SYSTIMER_TARGET2_HI_REG register
+ *  system timer comp2 value high register
+ */
+#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
+/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer taget2 high 20 bits
+ */
+#define SYSTIMER_TIMER_TARGET2_HI    0x000FFFFFU
+#define SYSTIMER_TIMER_TARGET2_HI_M  (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
+#define SYSTIMER_TIMER_TARGET2_HI_V  0x000FFFFFU
+#define SYSTIMER_TIMER_TARGET2_HI_S  0
+
+/** SYSTIMER_TARGET2_LO_REG register
+ *  system timer comp2 value low register
+ */
+#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
+/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer taget2 low 32 bits
+ */
+#define SYSTIMER_TIMER_TARGET2_LO    0xFFFFFFFFU
+#define SYSTIMER_TIMER_TARGET2_LO_M  (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
+#define SYSTIMER_TIMER_TARGET2_LO_V  0xFFFFFFFFU
+#define SYSTIMER_TIMER_TARGET2_LO_S  0
+
+/** SYSTIMER_TARGET0_CONF_REG register
+ *  system timer comp0 target mode register
+ */
+#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
+/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
+ *  target0 period
+ */
+#define SYSTIMER_TARGET0_PERIOD    0x03FFFFFFU
+#define SYSTIMER_TARGET0_PERIOD_M  (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
+#define SYSTIMER_TARGET0_PERIOD_V  0x03FFFFFFU
+#define SYSTIMER_TARGET0_PERIOD_S  0
+/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
+ *  Set target0 to period mode
+ */
+#define SYSTIMER_TARGET0_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET0_PERIOD_MODE_M  (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
+#define SYSTIMER_TARGET0_PERIOD_MODE_V  0x00000001U
+#define SYSTIMER_TARGET0_PERIOD_MODE_S  30
+/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
+ *  select which unit to compare
+ */
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V  0x00000001U
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S  31
+
+/** SYSTIMER_TARGET1_CONF_REG register
+ *  system timer comp1 target mode register
+ */
+#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
+/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
+ *  target1 period
+ */
+#define SYSTIMER_TARGET1_PERIOD    0x03FFFFFFU
+#define SYSTIMER_TARGET1_PERIOD_M  (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
+#define SYSTIMER_TARGET1_PERIOD_V  0x03FFFFFFU
+#define SYSTIMER_TARGET1_PERIOD_S  0
+/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
+ *  Set target1 to period mode
+ */
+#define SYSTIMER_TARGET1_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET1_PERIOD_MODE_M  (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
+#define SYSTIMER_TARGET1_PERIOD_MODE_V  0x00000001U
+#define SYSTIMER_TARGET1_PERIOD_MODE_S  30
+/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
+ *  select which unit to compare
+ */
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V  0x00000001U
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S  31
+
+/** SYSTIMER_TARGET2_CONF_REG register
+ *  system timer comp2 target mode register
+ */
+#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
+/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
+ *  target2 period
+ */
+#define SYSTIMER_TARGET2_PERIOD    0x03FFFFFFU
+#define SYSTIMER_TARGET2_PERIOD_M  (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
+#define SYSTIMER_TARGET2_PERIOD_V  0x03FFFFFFU
+#define SYSTIMER_TARGET2_PERIOD_S  0
+/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
+ *  Set target2 to period mode
+ */
+#define SYSTIMER_TARGET2_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET2_PERIOD_MODE_M  (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
+#define SYSTIMER_TARGET2_PERIOD_MODE_V  0x00000001U
+#define SYSTIMER_TARGET2_PERIOD_MODE_S  30
+/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
+ *  select which unit to compare
+ */
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V  0x00000001U
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S  31
+
+/** SYSTIMER_UNIT0_VALUE_HI_REG register
+ *  system timer unit0 value high register
+ */
+#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
+/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
+ *  timer read value high 20bits
+ */
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI    0x000FFFFFU
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M  (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V  0x000FFFFFU
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S  0
+
+/** SYSTIMER_UNIT0_VALUE_LO_REG register
+ *  system timer unit0 value low register
+ */
+#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
+/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
+ *  timer read value low 32bits
+ */
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO    0xFFFFFFFFU
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M  (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V  0xFFFFFFFFU
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S  0
+
+/** SYSTIMER_UNIT1_VALUE_HI_REG register
+ *  system timer unit1 value high register
+ */
+#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
+/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
+ *  timer read value high 20bits
+ */
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI    0x000FFFFFU
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M  (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V  0x000FFFFFU
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S  0
+
+/** SYSTIMER_UNIT1_VALUE_LO_REG register
+ *  system timer unit1 value low register
+ */
+#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
+/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
+ *  timer read value low 32bits
+ */
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO    0xFFFFFFFFU
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M  (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V  0xFFFFFFFFU
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S  0
+
+/** SYSTIMER_COMP0_LOAD_REG register
+ *  system timer comp0 conf sync register
+ */
+#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
+/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer comp0 sync enable signal
+ */
+#define SYSTIMER_TIMER_COMP0_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_COMP0_LOAD_M  (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
+#define SYSTIMER_TIMER_COMP0_LOAD_V  0x00000001U
+#define SYSTIMER_TIMER_COMP0_LOAD_S  0
+
+/** SYSTIMER_COMP1_LOAD_REG register
+ *  system timer comp1 conf sync register
+ */
+#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
+/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer comp1 sync enable signal
+ */
+#define SYSTIMER_TIMER_COMP1_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_COMP1_LOAD_M  (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
+#define SYSTIMER_TIMER_COMP1_LOAD_V  0x00000001U
+#define SYSTIMER_TIMER_COMP1_LOAD_S  0
+
+/** SYSTIMER_COMP2_LOAD_REG register
+ *  system timer comp2 conf sync register
+ */
+#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
+/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer comp2 sync enable signal
+ */
+#define SYSTIMER_TIMER_COMP2_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_COMP2_LOAD_M  (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
+#define SYSTIMER_TIMER_COMP2_LOAD_V  0x00000001U
+#define SYSTIMER_TIMER_COMP2_LOAD_S  0
+
+/** SYSTIMER_UNIT0_LOAD_REG register
+ *  system timer unit0 conf sync register
+ */
+#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
+/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer unit0 sync enable signal
+ */
+#define SYSTIMER_TIMER_UNIT0_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_UNIT0_LOAD_M  (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
+#define SYSTIMER_TIMER_UNIT0_LOAD_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT0_LOAD_S  0
+
+/** SYSTIMER_UNIT1_LOAD_REG register
+ *  system timer unit1 conf sync register
+ */
+#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
+/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer unit1 sync enable signal
+ */
+#define SYSTIMER_TIMER_UNIT1_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_UNIT1_LOAD_M  (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
+#define SYSTIMER_TIMER_UNIT1_LOAD_V  0x00000001U
+#define SYSTIMER_TIMER_UNIT1_LOAD_S  0
+
+/** SYSTIMER_INT_ENA_REG register
+ *  systimer interrupt enable register
+ */
+#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
+/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  interupt0 enable
+ */
+#define SYSTIMER_TARGET0_INT_ENA    (BIT(0))
+#define SYSTIMER_TARGET0_INT_ENA_M  (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
+#define SYSTIMER_TARGET0_INT_ENA_V  0x00000001U
+#define SYSTIMER_TARGET0_INT_ENA_S  0
+/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  interupt1 enable
+ */
+#define SYSTIMER_TARGET1_INT_ENA    (BIT(1))
+#define SYSTIMER_TARGET1_INT_ENA_M  (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
+#define SYSTIMER_TARGET1_INT_ENA_V  0x00000001U
+#define SYSTIMER_TARGET1_INT_ENA_S  1
+/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  interupt2 enable
+ */
+#define SYSTIMER_TARGET2_INT_ENA    (BIT(2))
+#define SYSTIMER_TARGET2_INT_ENA_M  (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
+#define SYSTIMER_TARGET2_INT_ENA_V  0x00000001U
+#define SYSTIMER_TARGET2_INT_ENA_S  2
+
+/** SYSTIMER_INT_RAW_REG register
+ *  systimer interrupt raw register
+ */
+#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
+/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  interupt0 raw
+ */
+#define SYSTIMER_TARGET0_INT_RAW    (BIT(0))
+#define SYSTIMER_TARGET0_INT_RAW_M  (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
+#define SYSTIMER_TARGET0_INT_RAW_V  0x00000001U
+#define SYSTIMER_TARGET0_INT_RAW_S  0
+/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  interupt1 raw
+ */
+#define SYSTIMER_TARGET1_INT_RAW    (BIT(1))
+#define SYSTIMER_TARGET1_INT_RAW_M  (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
+#define SYSTIMER_TARGET1_INT_RAW_V  0x00000001U
+#define SYSTIMER_TARGET1_INT_RAW_S  1
+/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  interupt2 raw
+ */
+#define SYSTIMER_TARGET2_INT_RAW    (BIT(2))
+#define SYSTIMER_TARGET2_INT_RAW_M  (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
+#define SYSTIMER_TARGET2_INT_RAW_V  0x00000001U
+#define SYSTIMER_TARGET2_INT_RAW_S  2
+
+/** SYSTIMER_INT_CLR_REG register
+ *  systimer interrupt clear register
+ */
+#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
+/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  interupt0 clear
+ */
+#define SYSTIMER_TARGET0_INT_CLR    (BIT(0))
+#define SYSTIMER_TARGET0_INT_CLR_M  (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
+#define SYSTIMER_TARGET0_INT_CLR_V  0x00000001U
+#define SYSTIMER_TARGET0_INT_CLR_S  0
+/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  interupt1 clear
+ */
+#define SYSTIMER_TARGET1_INT_CLR    (BIT(1))
+#define SYSTIMER_TARGET1_INT_CLR_M  (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
+#define SYSTIMER_TARGET1_INT_CLR_V  0x00000001U
+#define SYSTIMER_TARGET1_INT_CLR_S  1
+/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  interupt2 clear
+ */
+#define SYSTIMER_TARGET2_INT_CLR    (BIT(2))
+#define SYSTIMER_TARGET2_INT_CLR_M  (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
+#define SYSTIMER_TARGET2_INT_CLR_V  0x00000001U
+#define SYSTIMER_TARGET2_INT_CLR_S  2
+
+/** SYSTIMER_INT_ST_REG register
+ *  systimer interrupt status register
+ */
+#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
+/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  interupt0 status
+ */
+#define SYSTIMER_TARGET0_INT_ST    (BIT(0))
+#define SYSTIMER_TARGET0_INT_ST_M  (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
+#define SYSTIMER_TARGET0_INT_ST_V  0x00000001U
+#define SYSTIMER_TARGET0_INT_ST_S  0
+/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  interupt1 status
+ */
+#define SYSTIMER_TARGET1_INT_ST    (BIT(1))
+#define SYSTIMER_TARGET1_INT_ST_M  (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
+#define SYSTIMER_TARGET1_INT_ST_V  0x00000001U
+#define SYSTIMER_TARGET1_INT_ST_S  1
+/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  interupt2 status
+ */
+#define SYSTIMER_TARGET2_INT_ST    (BIT(2))
+#define SYSTIMER_TARGET2_INT_ST_M  (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
+#define SYSTIMER_TARGET2_INT_ST_V  0x00000001U
+#define SYSTIMER_TARGET2_INT_ST_S  2
+
+/** SYSTIMER_REAL_TARGET0_LO_REG register
+ *  system timer comp0 actual target value low register
+ */
+#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74)
+/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0;
+ *  actual target value value low 32bits
+ */
+#define SYSTIMER_TARGET0_LO_RO    0xFFFFFFFFU
+#define SYSTIMER_TARGET0_LO_RO_M  (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S)
+#define SYSTIMER_TARGET0_LO_RO_V  0xFFFFFFFFU
+#define SYSTIMER_TARGET0_LO_RO_S  0
+
+/** SYSTIMER_REAL_TARGET0_HI_REG register
+ *  system timer comp0 actual target value high register
+ */
+#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78)
+/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0;
+ *  actual target value value high 20bits
+ */
+#define SYSTIMER_TARGET0_HI_RO    0x000FFFFFU
+#define SYSTIMER_TARGET0_HI_RO_M  (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S)
+#define SYSTIMER_TARGET0_HI_RO_V  0x000FFFFFU
+#define SYSTIMER_TARGET0_HI_RO_S  0
+
+/** SYSTIMER_REAL_TARGET1_LO_REG register
+ *  system timer comp1 actual target value low register
+ */
+#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c)
+/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0;
+ *  actual target value value low 32bits
+ */
+#define SYSTIMER_TARGET1_LO_RO    0xFFFFFFFFU
+#define SYSTIMER_TARGET1_LO_RO_M  (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S)
+#define SYSTIMER_TARGET1_LO_RO_V  0xFFFFFFFFU
+#define SYSTIMER_TARGET1_LO_RO_S  0
+
+/** SYSTIMER_REAL_TARGET1_HI_REG register
+ *  system timer comp1 actual target value high register
+ */
+#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80)
+/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0;
+ *  actual target value value high 20bits
+ */
+#define SYSTIMER_TARGET1_HI_RO    0x000FFFFFU
+#define SYSTIMER_TARGET1_HI_RO_M  (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S)
+#define SYSTIMER_TARGET1_HI_RO_V  0x000FFFFFU
+#define SYSTIMER_TARGET1_HI_RO_S  0
+
+/** SYSTIMER_REAL_TARGET2_LO_REG register
+ *  system timer comp2 actual target value low register
+ */
+#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84)
+/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0;
+ *  actual target value value low 32bits
+ */
+#define SYSTIMER_TARGET2_LO_RO    0xFFFFFFFFU
+#define SYSTIMER_TARGET2_LO_RO_M  (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S)
+#define SYSTIMER_TARGET2_LO_RO_V  0xFFFFFFFFU
+#define SYSTIMER_TARGET2_LO_RO_S  0
+
+/** SYSTIMER_REAL_TARGET2_HI_REG register
+ *  system timer comp2 actual target value high register
+ */
+#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88)
+/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0;
+ *  actual target value value high 20bits
+ */
+#define SYSTIMER_TARGET2_HI_RO    0x000FFFFFU
+#define SYSTIMER_TARGET2_HI_RO_M  (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S)
+#define SYSTIMER_TARGET2_HI_RO_V  0x000FFFFFU
+#define SYSTIMER_TARGET2_HI_RO_S  0
+
+/** SYSTIMER_DATE_REG register
+ *  system timer version control register
+ */
+#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
+/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 35655795;
+ *  systimer register version
+ */
+#define SYSTIMER_DATE    0xFFFFFFFFU
+#define SYSTIMER_DATE_M  (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
+#define SYSTIMER_DATE_V  0xFFFFFFFFU
+#define SYSTIMER_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/systimer_struct.h

@@ -0,0 +1,376 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: SYSTEM TIMER CLK CONTROL REGISTER */
+/** Type of conf register
+ *  Configure system timer clock
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** etm_en : R/W; bitpos: [1]; default: 0;
+         *  enable systimer's etm task and event
+         */
+        uint32_t etm_en:1;
+        uint32_t reserved_2:20;
+        /** target2_work_en : R/W; bitpos: [22]; default: 0;
+         *  target2 work enable
+         */
+        uint32_t target2_work_en:1;
+        /** target1_work_en : R/W; bitpos: [23]; default: 0;
+         *  target1 work enable
+         */
+        uint32_t target1_work_en:1;
+        /** target0_work_en : R/W; bitpos: [24]; default: 0;
+         *  target0 work enable
+         */
+        uint32_t target0_work_en:1;
+        /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
+         *  If timer unit1 is stalled when core1 stalled
+         */
+        uint32_t timer_unit1_core1_stall_en:1;
+        /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
+         *  If timer unit1 is stalled when core0 stalled
+         */
+        uint32_t timer_unit1_core0_stall_en:1;
+        /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
+         *  If timer unit0 is stalled when core1 stalled
+         */
+        uint32_t timer_unit0_core1_stall_en:1;
+        /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
+         *  If timer unit0 is stalled when core0 stalled
+         */
+        uint32_t timer_unit0_core0_stall_en:1;
+        /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
+         *  timer unit1 work enable
+         */
+        uint32_t timer_unit1_work_en:1;
+        /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
+         *  timer unit0 work enable
+         */
+        uint32_t timer_unit0_work_en:1;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  register file clk gating
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} systimer_conf_reg_t;
+
+
+/** Group: SYSTEM TIMER UNIT CONTROL AND CONFIGURATION REGISTER */
+/** Type of unit_op register
+ *  system timer unit value update register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 29;
+        /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
+         *  timer value is sync and valid
+         */
+        uint32_t timer_unit_value_valid: 1;
+        /** timer_unit_update : WT; bitpos: [30]; default: 0;
+         *  update timer_unit
+         */
+        uint32_t timer_unit_update: 1;
+        uint32_t reserved31: 1;
+    };
+    uint32_t val;
+} systimer_unit_op_reg_t;
+
+/** Type of unit_load register
+ *  system timer unit value high and low load register
+ */
+typedef struct {
+    union {
+        struct {
+            /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0;
+             *  timer unit load high 20 bit
+             */
+            uint32_t timer_unit_load_hi: 20;
+            uint32_t reserved20: 12;
+        };
+        uint32_t val;
+    } hi;
+    union {
+        struct {
+            /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0;
+             *  timer unit load low 32 bit
+             */
+            uint32_t timer_unit_load_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+} systimer_unit_load_val_reg_t;
+
+/** Type of unit_value_hi register
+ *  system timer unit value high and low register
+ */
+typedef struct {
+    union {
+        struct {
+            /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0;
+             *  timer read value high 20 bit
+             */
+            uint32_t timer_unit_value_hi: 20;
+            uint32_t reserved20: 12;
+        };
+        uint32_t val;
+    } hi;
+    union {
+        struct {
+            /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0;
+             *  timer read value low 32 bit
+             */
+            uint32_t timer_unit_value_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+} systimer_unit_value_reg_t;
+
+/** Type of unit_load register
+ *  system timer unit conf sync register
+ */
+typedef union {
+    struct {
+        /** timer_unit_load : WT; bitpos: [0]; default: 0;
+         *  timer unit load value
+         */
+        uint32_t timer_unit_load: 1;
+        uint32_t reserved1: 31;
+    };
+    uint32_t val;
+} systimer_unit_load_reg_t;
+
+
+/** Group: SYSTEM TIMER COMP CONTROL AND CONFIGURATION REGISTER */
+/** Type of target register
+ *  system timer comp value high and low register
+ */
+typedef struct {
+    union {
+        struct {
+            /** timer_target_hi : R/W; bitpos: [19:0]; default: 0;
+             *  timer target high 20 bit
+             */
+            uint32_t timer_target_hi: 20;
+            uint32_t reserved20: 12;
+        };
+        uint32_t val;
+    } hi;
+    union {
+        struct {
+            /** timer_target_lo : R/W; bitpos: [31:0]; default: 0;
+             *  timer target low 32 bit
+             */
+            uint32_t timer_target_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+} systimer_target_val_reg_t;
+
+/** Type of target_conf register
+ *  system timer comp target mode register
+ */
+typedef union {
+    struct {
+        /** target_period : R/W; bitpos: [25:0]; default: 0;
+         *  target period
+         */
+        uint32_t target_period: 26;
+        uint32_t reserved_26: 4;
+        /** target_period_mode : R/W; bitpos: [30]; default: 0;
+         *  Set target to period mode
+         */
+        uint32_t target_period_mode: 1;
+        /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0;
+         *  select which unit to compare
+         */
+        uint32_t target_timer_unit_sel: 1;
+    };
+    uint32_t val;
+} systimer_target_conf_reg_t;
+
+/** Type of comp_load register
+ *  system timer comp conf sync register
+ */
+typedef union {
+    struct {
+        /** timer_comp_load : WT; bitpos: [0]; default: 0;
+         *  timer comp sync enable signal
+         */
+        uint32_t timer_comp_load: 1;
+        uint32_t reserved1: 31;
+    };
+    uint32_t val;
+} systimer_comp_load_reg_t;
+
+
+/** Group: SYSTEM TIMER INTERRUPT REGISTER */
+/** Type of int_ena register
+ *  systimer interrupt enable register
+ */
+typedef union {
+    struct {
+        /** target0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  interupt0 enable
+         */
+        uint32_t target0_int_ena:1;
+        /** target1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  interupt1 enable
+         */
+        uint32_t target1_int_ena:1;
+        /** target2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  interupt2 enable
+         */
+        uint32_t target2_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} systimer_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  systimer interrupt raw register
+ */
+typedef union {
+    struct {
+        /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  interupt0 raw
+         */
+        uint32_t target0_int_raw:1;
+        /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  interupt1 raw
+         */
+        uint32_t target1_int_raw:1;
+        /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  interupt2 raw
+         */
+        uint32_t target2_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} systimer_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  systimer interrupt clear register
+ */
+typedef union {
+    struct {
+        /** target0_int_clr : WT; bitpos: [0]; default: 0;
+         *  interupt0 clear
+         */
+        uint32_t target0_int_clr:1;
+        /** target1_int_clr : WT; bitpos: [1]; default: 0;
+         *  interupt1 clear
+         */
+        uint32_t target1_int_clr:1;
+        /** target2_int_clr : WT; bitpos: [2]; default: 0;
+         *  interupt2 clear
+         */
+        uint32_t target2_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} systimer_int_clr_reg_t;
+
+/** Type of int_st register
+ *  systimer interrupt status register
+ */
+typedef union {
+    struct {
+        /** target0_int_st : RO; bitpos: [0]; default: 0;
+         *  interupt0 status
+         */
+        uint32_t target0_int_st:1;
+        /** target1_int_st : RO; bitpos: [1]; default: 0;
+         *  interupt1 status
+         */
+        uint32_t target1_int_st:1;
+        /** target2_int_st : RO; bitpos: [2]; default: 0;
+         *  interupt2 status
+         */
+        uint32_t target2_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} systimer_int_st_reg_t;
+
+
+/** Group: SYSTEM TIMER COMP STATUS REGISTER */
+/** Type of real_target_hi/lo register
+ *  system timer comp actual target value low register
+ */
+typedef struct {
+    union {
+        struct {
+            /** target_lo_ro : RO; bitpos: [31:0]; default: 0;
+             *  actual target value value low 32 bits
+             */
+            uint32_t target_lo_ro: 32;
+        };
+        uint32_t val;
+    } lo;
+    union {
+        struct {
+            /** target_hi_ro : RO; bitpos: [19:0]; default: 0;
+             *  actual target value value high 20 bits
+             */
+            uint32_t target_hi_ro: 20;
+            uint32_t reserved20: 12;
+        };
+        uint32_t val;
+    } hi;
+} systimer_real_target_reg_t;
+
+
+/** Group: VERSION REGISTER */
+/** Type of date register
+ *  system timer version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 35655795;
+         *  systimer register version
+         */
+        uint32_t date: 32;
+    };
+    uint32_t val;
+} systimer_date_reg_t;
+
+
+typedef struct systimer_dev_t {
+    volatile systimer_conf_reg_t conf;
+    volatile systimer_unit_op_reg_t unit_op[2];
+    volatile systimer_unit_load_val_reg_t unit_load_val[2];
+    volatile systimer_target_val_reg_t target_val[3];
+    volatile systimer_target_conf_reg_t target_conf[3];
+    volatile systimer_unit_value_reg_t unit_val[2];
+    volatile systimer_comp_load_reg_t comp_load[3];
+    volatile systimer_unit_load_reg_t unit_load[2];
+    volatile systimer_int_ena_reg_t int_ena;
+    volatile systimer_int_raw_reg_t int_raw;
+    volatile systimer_int_clr_reg_t int_clr;
+    volatile systimer_int_st_reg_t int_st;
+    volatile systimer_real_target_reg_t real_target[3];
+    uint32_t reserved_08c[28];
+    volatile systimer_date_reg_t date;
+} systimer_dev_t;
+
+extern systimer_dev_t SYSTIMER;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(systimer_dev_t) == 0x100, "Invalid size of systimer_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/timer_group_eco5_reg.h

@@ -0,0 +1,716 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TIMG_T0CONFIG_REG register
+ *  Timer 0 configuration register
+ */
+#define TIMG_T0CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x0)
+/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
+ *  When set, the alarm is enabled. This bit is automatically cleared once an
+ *  alarm occurs.
+ */
+#define TIMG_T0_ALARM_EN    (BIT(10))
+#define TIMG_T0_ALARM_EN_M  (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
+#define TIMG_T0_ALARM_EN_V  0x00000001U
+#define TIMG_T0_ALARM_EN_S  10
+/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
+ *  When set, Timer 0 's clock divider counter will be reset.
+ */
+#define TIMG_T0_DIVCNT_RST    (BIT(12))
+#define TIMG_T0_DIVCNT_RST_M  (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
+#define TIMG_T0_DIVCNT_RST_V  0x00000001U
+#define TIMG_T0_DIVCNT_RST_S  12
+/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
+ *  Timer 0 clock (T0_clk) prescaler value.
+ */
+#define TIMG_T0_DIVIDER    0x0000FFFFU
+#define TIMG_T0_DIVIDER_M  (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
+#define TIMG_T0_DIVIDER_V  0x0000FFFFU
+#define TIMG_T0_DIVIDER_S  13
+/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
+ *  When set, timer 0 auto-reload at alarm is enabled.
+ */
+#define TIMG_T0_AUTORELOAD    (BIT(29))
+#define TIMG_T0_AUTORELOAD_M  (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
+#define TIMG_T0_AUTORELOAD_V  0x00000001U
+#define TIMG_T0_AUTORELOAD_S  29
+/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
+ *  When set, the timer 0 time-base counter will increment every clock tick. When
+ *  cleared, the timer 0 time-base counter will decrement.
+ */
+#define TIMG_T0_INCREASE    (BIT(30))
+#define TIMG_T0_INCREASE_M  (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
+#define TIMG_T0_INCREASE_V  0x00000001U
+#define TIMG_T0_INCREASE_S  30
+/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0;
+ *  When set, the timer 0 time-base counter is enabled.
+ */
+#define TIMG_T0_EN    (BIT(31))
+#define TIMG_T0_EN_M  (TIMG_T0_EN_V << TIMG_T0_EN_S)
+#define TIMG_T0_EN_V  0x00000001U
+#define TIMG_T0_EN_S  31
+
+/** TIMG_T0LO_REG register
+ *  Timer 0 current value, low 32 bits
+ */
+#define TIMG_T0LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x4)
+/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
+ *  After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
+ *  of timer 0 can be read here.
+ */
+#define TIMG_T0_LO    0xFFFFFFFFU
+#define TIMG_T0_LO_M  (TIMG_T0_LO_V << TIMG_T0_LO_S)
+#define TIMG_T0_LO_V  0xFFFFFFFFU
+#define TIMG_T0_LO_S  0
+
+/** TIMG_T0HI_REG register
+ *  Timer 0 current value, high 22 bits
+ */
+#define TIMG_T0HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x8)
+/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
+ *  After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter
+ *  of timer 0 can be read here.
+ */
+#define TIMG_T0_HI    0x003FFFFFU
+#define TIMG_T0_HI_M  (TIMG_T0_HI_V << TIMG_T0_HI_S)
+#define TIMG_T0_HI_V  0x003FFFFFU
+#define TIMG_T0_HI_S  0
+
+/** TIMG_T0UPDATE_REG register
+ *  Write to copy current timer value to TIMGn_T0_(LO/HI)_REG
+ */
+#define TIMG_T0UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xc)
+/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
+ *  After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched.
+ */
+#define TIMG_T0_UPDATE    (BIT(31))
+#define TIMG_T0_UPDATE_M  (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
+#define TIMG_T0_UPDATE_V  0x00000001U
+#define TIMG_T0_UPDATE_S  31
+
+/** TIMG_T0ALARMLO_REG register
+ *  Timer 0 alarm value, low 32 bits
+ */
+#define TIMG_T0ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x10)
+/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Timer 0 alarm trigger time-base counter value, low 32 bits.
+ */
+#define TIMG_T0_ALARM_LO    0xFFFFFFFFU
+#define TIMG_T0_ALARM_LO_M  (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
+#define TIMG_T0_ALARM_LO_V  0xFFFFFFFFU
+#define TIMG_T0_ALARM_LO_S  0
+
+/** TIMG_T0ALARMHI_REG register
+ *  Timer 0 alarm value, high bits
+ */
+#define TIMG_T0ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x14)
+/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
+ *  Timer 0 alarm trigger time-base counter value, high 22 bits.
+ */
+#define TIMG_T0_ALARM_HI    0x003FFFFFU
+#define TIMG_T0_ALARM_HI_M  (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
+#define TIMG_T0_ALARM_HI_V  0x003FFFFFU
+#define TIMG_T0_ALARM_HI_S  0
+
+/** TIMG_T0LOADLO_REG register
+ *  Timer 0 reload value, low 32 bits
+ */
+#define TIMG_T0LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x18)
+/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Low 32 bits of the value that a reload will load onto timer 0 time-base
+ *  Counter.
+ */
+#define TIMG_T0_LOAD_LO    0xFFFFFFFFU
+#define TIMG_T0_LOAD_LO_M  (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
+#define TIMG_T0_LOAD_LO_V  0xFFFFFFFFU
+#define TIMG_T0_LOAD_LO_S  0
+
+/** TIMG_T0LOADHI_REG register
+ *  Timer 0 reload value, high 22 bits
+ */
+#define TIMG_T0LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x1c)
+/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
+ *  High 22 bits of the value that a reload will load onto timer 0 time-base
+ *  counter.
+ */
+#define TIMG_T0_LOAD_HI    0x003FFFFFU
+#define TIMG_T0_LOAD_HI_M  (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
+#define TIMG_T0_LOAD_HI_V  0x003FFFFFU
+#define TIMG_T0_LOAD_HI_S  0
+
+/** TIMG_T0LOAD_REG register
+ *  Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG
+ */
+#define TIMG_T0LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x20)
+/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
+ *
+ *  Write any value to trigger a timer 0 time-base counter reload.
+ */
+#define TIMG_T0_LOAD    0xFFFFFFFFU
+#define TIMG_T0_LOAD_M  (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
+#define TIMG_T0_LOAD_V  0xFFFFFFFFU
+#define TIMG_T0_LOAD_S  0
+
+/** TIMG_T1CONFIG_REG register
+ *  Timer 1 configuration register
+ */
+#define TIMG_T1CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x24)
+/** TIMG_T1_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
+ *  When set, the alarm is enabled. This bit is automatically cleared once an
+ *  alarm occurs.
+ */
+#define TIMG_T1_ALARM_EN    (BIT(10))
+#define TIMG_T1_ALARM_EN_M  (TIMG_T1_ALARM_EN_V << TIMG_T1_ALARM_EN_S)
+#define TIMG_T1_ALARM_EN_V  0x00000001U
+#define TIMG_T1_ALARM_EN_S  10
+/** TIMG_T1_DIVCNT_RST : WT; bitpos: [12]; default: 0;
+ *  When set, Timer 1 's clock divider counter will be reset.
+ */
+#define TIMG_T1_DIVCNT_RST    (BIT(12))
+#define TIMG_T1_DIVCNT_RST_M  (TIMG_T1_DIVCNT_RST_V << TIMG_T1_DIVCNT_RST_S)
+#define TIMG_T1_DIVCNT_RST_V  0x00000001U
+#define TIMG_T1_DIVCNT_RST_S  12
+/** TIMG_T1_DIVIDER : R/W; bitpos: [28:13]; default: 1;
+ *  Timer 1 clock (T1_clk) prescaler value.
+ */
+#define TIMG_T1_DIVIDER    0x0000FFFFU
+#define TIMG_T1_DIVIDER_M  (TIMG_T1_DIVIDER_V << TIMG_T1_DIVIDER_S)
+#define TIMG_T1_DIVIDER_V  0x0000FFFFU
+#define TIMG_T1_DIVIDER_S  13
+/** TIMG_T1_AUTORELOAD : R/W; bitpos: [29]; default: 1;
+ *  When set, timer 1 auto-reload at alarm is enabled.
+ */
+#define TIMG_T1_AUTORELOAD    (BIT(29))
+#define TIMG_T1_AUTORELOAD_M  (TIMG_T1_AUTORELOAD_V << TIMG_T1_AUTORELOAD_S)
+#define TIMG_T1_AUTORELOAD_V  0x00000001U
+#define TIMG_T1_AUTORELOAD_S  29
+/** TIMG_T1_INCREASE : R/W; bitpos: [30]; default: 1;
+ *  When set, the timer 1 time-base counter will increment every clock tick. When
+ *  cleared, the timer 1 time-base counter will decrement.
+ */
+#define TIMG_T1_INCREASE    (BIT(30))
+#define TIMG_T1_INCREASE_M  (TIMG_T1_INCREASE_V << TIMG_T1_INCREASE_S)
+#define TIMG_T1_INCREASE_V  0x00000001U
+#define TIMG_T1_INCREASE_S  30
+/** TIMG_T1_EN : R/W/SS/SC; bitpos: [31]; default: 0;
+ *  When set, the timer 1 time-base counter is enabled.
+ */
+#define TIMG_T1_EN    (BIT(31))
+#define TIMG_T1_EN_M  (TIMG_T1_EN_V << TIMG_T1_EN_S)
+#define TIMG_T1_EN_V  0x00000001U
+#define TIMG_T1_EN_S  31
+
+/** TIMG_T1LO_REG register
+ *  Timer 1 current value, low 32 bits
+ */
+#define TIMG_T1LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x28)
+/** TIMG_T1_LO : RO; bitpos: [31:0]; default: 0;
+ *  After writing to TIMG_T1UPDATE_REG, the low 32 bits of the time-base counter
+ *  of timer 1 can be read here.
+ */
+#define TIMG_T1_LO    0xFFFFFFFFU
+#define TIMG_T1_LO_M  (TIMG_T1_LO_V << TIMG_T1_LO_S)
+#define TIMG_T1_LO_V  0xFFFFFFFFU
+#define TIMG_T1_LO_S  0
+
+/** TIMG_T1HI_REG register
+ *  Timer 1 current value, high 22 bits
+ */
+#define TIMG_T1HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x2c)
+/** TIMG_T1_HI : RO; bitpos: [21:0]; default: 0;
+ *  After writing to TIMG_T1UPDATE_REG, the high 22 bits of the time-base counter
+ *  of timer 1 can be read here.
+ */
+#define TIMG_T1_HI    0x003FFFFFU
+#define TIMG_T1_HI_M  (TIMG_T1_HI_V << TIMG_T1_HI_S)
+#define TIMG_T1_HI_V  0x003FFFFFU
+#define TIMG_T1_HI_S  0
+
+/** TIMG_T1UPDATE_REG register
+ *  Write to copy current timer value to TIMGn_T1_(LO/HI)_REG
+ */
+#define TIMG_T1UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0x30)
+/** TIMG_T1_UPDATE : R/W/SC; bitpos: [31]; default: 0;
+ *  After writing 0 or 1 to TIMG_T1UPDATE_REG, the counter value is latched.
+ */
+#define TIMG_T1_UPDATE    (BIT(31))
+#define TIMG_T1_UPDATE_M  (TIMG_T1_UPDATE_V << TIMG_T1_UPDATE_S)
+#define TIMG_T1_UPDATE_V  0x00000001U
+#define TIMG_T1_UPDATE_S  31
+
+/** TIMG_T1ALARMLO_REG register
+ *  Timer 1 alarm value, low 32 bits
+ */
+#define TIMG_T1ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x34)
+/** TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Timer 1 alarm trigger time-base counter value, low 32 bits.
+ */
+#define TIMG_T1_ALARM_LO    0xFFFFFFFFU
+#define TIMG_T1_ALARM_LO_M  (TIMG_T1_ALARM_LO_V << TIMG_T1_ALARM_LO_S)
+#define TIMG_T1_ALARM_LO_V  0xFFFFFFFFU
+#define TIMG_T1_ALARM_LO_S  0
+
+/** TIMG_T1ALARMHI_REG register
+ *  Timer 1 alarm value, high bits
+ */
+#define TIMG_T1ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x38)
+/** TIMG_T1_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
+ *  Timer 1 alarm trigger time-base counter value, high 22 bits.
+ */
+#define TIMG_T1_ALARM_HI    0x003FFFFFU
+#define TIMG_T1_ALARM_HI_M  (TIMG_T1_ALARM_HI_V << TIMG_T1_ALARM_HI_S)
+#define TIMG_T1_ALARM_HI_V  0x003FFFFFU
+#define TIMG_T1_ALARM_HI_S  0
+
+/** TIMG_T1LOADLO_REG register
+ *  Timer 1 reload value, low 32 bits
+ */
+#define TIMG_T1LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x3c)
+/** TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Low 32 bits of the value that a reload will load onto timer 1 time-base
+ *  Counter.
+ */
+#define TIMG_T1_LOAD_LO    0xFFFFFFFFU
+#define TIMG_T1_LOAD_LO_M  (TIMG_T1_LOAD_LO_V << TIMG_T1_LOAD_LO_S)
+#define TIMG_T1_LOAD_LO_V  0xFFFFFFFFU
+#define TIMG_T1_LOAD_LO_S  0
+
+/** TIMG_T1LOADHI_REG register
+ *  Timer 1 reload value, high 22 bits
+ */
+#define TIMG_T1LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x40)
+/** TIMG_T1_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
+ *  High 22 bits of the value that a reload will load onto timer 1 time-base
+ *  counter.
+ */
+#define TIMG_T1_LOAD_HI    0x003FFFFFU
+#define TIMG_T1_LOAD_HI_M  (TIMG_T1_LOAD_HI_V << TIMG_T1_LOAD_HI_S)
+#define TIMG_T1_LOAD_HI_V  0x003FFFFFU
+#define TIMG_T1_LOAD_HI_S  0
+
+/** TIMG_T1LOAD_REG register
+ *  Write to reload timer from TIMG_T1_(LOADLOLOADHI)_REG
+ */
+#define TIMG_T1LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x44)
+/** TIMG_T1_LOAD : WT; bitpos: [31:0]; default: 0;
+ *
+ *  Write any value to trigger a timer 1 time-base counter reload.
+ */
+#define TIMG_T1_LOAD    0xFFFFFFFFU
+#define TIMG_T1_LOAD_M  (TIMG_T1_LOAD_V << TIMG_T1_LOAD_S)
+#define TIMG_T1_LOAD_V  0xFFFFFFFFU
+#define TIMG_T1_LOAD_S  0
+
+/** TIMG_WDTCONFIG0_REG register
+ *  Watchdog timer configuration register
+ */
+#define TIMG_WDTCONFIG0_REG(i) (DR_REG_TIMG_BASE(i) + 0x48)
+/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
+ *  WDT reset CPU enable.
+ */
+#define TIMG_WDT_APPCPU_RESET_EN    (BIT(12))
+#define TIMG_WDT_APPCPU_RESET_EN_M  (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
+#define TIMG_WDT_APPCPU_RESET_EN_V  0x00000001U
+#define TIMG_WDT_APPCPU_RESET_EN_S  12
+/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
+ *  WDT reset CPU enable.
+ */
+#define TIMG_WDT_PROCPU_RESET_EN    (BIT(13))
+#define TIMG_WDT_PROCPU_RESET_EN_M  (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
+#define TIMG_WDT_PROCPU_RESET_EN_V  0x00000001U
+#define TIMG_WDT_PROCPU_RESET_EN_S  13
+/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
+ *  When set, Flash boot protection is enabled.
+ */
+#define TIMG_WDT_FLASHBOOT_MOD_EN    (BIT(14))
+#define TIMG_WDT_FLASHBOOT_MOD_EN_M  (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
+#define TIMG_WDT_FLASHBOOT_MOD_EN_V  0x00000001U
+#define TIMG_WDT_FLASHBOOT_MOD_EN_S  14
+/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
+ *  System reset signal length selection. 0: 100 ns, 1: 200 ns,
+ *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+ */
+#define TIMG_WDT_SYS_RESET_LENGTH    0x00000007U
+#define TIMG_WDT_SYS_RESET_LENGTH_M  (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
+#define TIMG_WDT_SYS_RESET_LENGTH_V  0x00000007U
+#define TIMG_WDT_SYS_RESET_LENGTH_S  15
+/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
+ *  CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
+ *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+ */
+#define TIMG_WDT_CPU_RESET_LENGTH    0x00000007U
+#define TIMG_WDT_CPU_RESET_LENGTH_M  (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
+#define TIMG_WDT_CPU_RESET_LENGTH_V  0x00000007U
+#define TIMG_WDT_CPU_RESET_LENGTH_S  18
+/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
+ *  update the WDT configuration registers
+ */
+#define TIMG_WDT_CONF_UPDATE_EN    (BIT(22))
+#define TIMG_WDT_CONF_UPDATE_EN_M  (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
+#define TIMG_WDT_CONF_UPDATE_EN_V  0x00000001U
+#define TIMG_WDT_CONF_UPDATE_EN_S  22
+/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
+ *  Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG3    0x00000003U
+#define TIMG_WDT_STG3_M  (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
+#define TIMG_WDT_STG3_V  0x00000003U
+#define TIMG_WDT_STG3_S  23
+/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
+ *  Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG2    0x00000003U
+#define TIMG_WDT_STG2_M  (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
+#define TIMG_WDT_STG2_V  0x00000003U
+#define TIMG_WDT_STG2_S  25
+/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
+ *  Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG1    0x00000003U
+#define TIMG_WDT_STG1_M  (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
+#define TIMG_WDT_STG1_V  0x00000003U
+#define TIMG_WDT_STG1_S  27
+/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
+ *  Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG0    0x00000003U
+#define TIMG_WDT_STG0_M  (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
+#define TIMG_WDT_STG0_V  0x00000003U
+#define TIMG_WDT_STG0_S  29
+/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
+ *  When set, MWDT is enabled.
+ */
+#define TIMG_WDT_EN    (BIT(31))
+#define TIMG_WDT_EN_M  (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
+#define TIMG_WDT_EN_V  0x00000001U
+#define TIMG_WDT_EN_S  31
+
+/** TIMG_WDTCONFIG1_REG register
+ *  Watchdog timer prescaler register
+ */
+#define TIMG_WDTCONFIG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x4c)
+/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
+ *  When set, WDT 's clock divider counter will be reset.
+ */
+#define TIMG_WDT_DIVCNT_RST    (BIT(0))
+#define TIMG_WDT_DIVCNT_RST_M  (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
+#define TIMG_WDT_DIVCNT_RST_V  0x00000001U
+#define TIMG_WDT_DIVCNT_RST_S  0
+/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
+ *  MWDT clock prescaler value. MWDT clock period = 12.5 ns *
+ *  TIMG_WDT_CLK_PRESCALE.
+ */
+#define TIMG_WDT_CLK_PRESCALE    0x0000FFFFU
+#define TIMG_WDT_CLK_PRESCALE_M  (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
+#define TIMG_WDT_CLK_PRESCALE_V  0x0000FFFFU
+#define TIMG_WDT_CLK_PRESCALE_S  16
+
+/** TIMG_WDTCONFIG2_REG register
+ *  Watchdog timer stage 0 timeout value
+ */
+#define TIMG_WDTCONFIG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x50)
+/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
+ *  Stage 0 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG0_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG0_HOLD_M  (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
+#define TIMG_WDT_STG0_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG0_HOLD_S  0
+
+/** TIMG_WDTCONFIG3_REG register
+ *  Watchdog timer stage 1 timeout value
+ */
+#define TIMG_WDTCONFIG3_REG(i) (DR_REG_TIMG_BASE(i) + 0x54)
+/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
+ *  Stage 1 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG1_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG1_HOLD_M  (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
+#define TIMG_WDT_STG1_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG1_HOLD_S  0
+
+/** TIMG_WDTCONFIG4_REG register
+ *  Watchdog timer stage 2 timeout value
+ */
+#define TIMG_WDTCONFIG4_REG(i) (DR_REG_TIMG_BASE(i) + 0x58)
+/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
+ *  Stage 2 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG2_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG2_HOLD_M  (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
+#define TIMG_WDT_STG2_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG2_HOLD_S  0
+
+/** TIMG_WDTCONFIG5_REG register
+ *  Watchdog timer stage 3 timeout value
+ */
+#define TIMG_WDTCONFIG5_REG(i) (DR_REG_TIMG_BASE(i) + 0x5c)
+/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
+ *  Stage 3 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG3_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG3_HOLD_M  (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
+#define TIMG_WDT_STG3_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG3_HOLD_S  0
+
+/** TIMG_WDTFEED_REG register
+ *  Write to feed the watchdog timer
+ */
+#define TIMG_WDTFEED_REG(i) (DR_REG_TIMG_BASE(i) + 0x60)
+/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
+ *  Write any value to feed the MWDT. (WO)
+ */
+#define TIMG_WDT_FEED    0xFFFFFFFFU
+#define TIMG_WDT_FEED_M  (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
+#define TIMG_WDT_FEED_V  0xFFFFFFFFU
+#define TIMG_WDT_FEED_S  0
+
+/** TIMG_WDTWPROTECT_REG register
+ *  Watchdog write protect register
+ */
+#define TIMG_WDTWPROTECT_REG(i) (DR_REG_TIMG_BASE(i) + 0x64)
+/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
+ *  If the register contains a different value than its reset value, write
+ *  protection is enabled.
+ */
+#define TIMG_WDT_WKEY    0xFFFFFFFFU
+#define TIMG_WDT_WKEY_M  (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
+#define TIMG_WDT_WKEY_V  0xFFFFFFFFU
+#define TIMG_WDT_WKEY_S  0
+
+/** TIMG_RTCCALICFG_REG register
+ *  RTC calibration configure register
+ */
+#define TIMG_RTCCALICFG_REG(i) (DR_REG_TIMG_BASE(i) + 0x68)
+/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
+ *  0: one-shot frequency calculation,1: periodic frequency calculation,
+ */
+#define TIMG_RTC_CALI_START_CYCLING    (BIT(12))
+#define TIMG_RTC_CALI_START_CYCLING_M  (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
+#define TIMG_RTC_CALI_START_CYCLING_V  0x00000001U
+#define TIMG_RTC_CALI_START_CYCLING_S  12
+/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0;
+ *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+ */
+#define TIMG_RTC_CALI_CLK_SEL    0x00000003U
+#define TIMG_RTC_CALI_CLK_SEL_M  (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
+#define TIMG_RTC_CALI_CLK_SEL_V  0x00000003U
+#define TIMG_RTC_CALI_CLK_SEL_S  13
+/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
+ *  indicate one-shot frequency calculation is done.
+ */
+#define TIMG_RTC_CALI_RDY    (BIT(15))
+#define TIMG_RTC_CALI_RDY_M  (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
+#define TIMG_RTC_CALI_RDY_V  0x00000001U
+#define TIMG_RTC_CALI_RDY_S  15
+/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
+ *  Configure the time to calculate RTC slow clock's frequency.
+ */
+#define TIMG_RTC_CALI_MAX    0x00007FFFU
+#define TIMG_RTC_CALI_MAX_M  (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
+#define TIMG_RTC_CALI_MAX_V  0x00007FFFU
+#define TIMG_RTC_CALI_MAX_S  16
+/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to start one-shot frequency calculation.
+ */
+#define TIMG_RTC_CALI_START    (BIT(31))
+#define TIMG_RTC_CALI_START_M  (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
+#define TIMG_RTC_CALI_START_V  0x00000001U
+#define TIMG_RTC_CALI_START_S  31
+
+/** TIMG_RTCCALICFG1_REG register
+ *  RTC calibration configure1 register
+ */
+#define TIMG_RTCCALICFG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x6c)
+/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
+ *  indicate periodic frequency calculation is done.
+ */
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD    (BIT(0))
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M  (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V  0x00000001U
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S  0
+/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
+ *  When one-shot or periodic frequency calculation is done, read this value to
+ *  calculate RTC slow clock's frequency.
+ */
+#define TIMG_RTC_CALI_VALUE    0x01FFFFFFU
+#define TIMG_RTC_CALI_VALUE_M  (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
+#define TIMG_RTC_CALI_VALUE_V  0x01FFFFFFU
+#define TIMG_RTC_CALI_VALUE_S  7
+
+/** TIMG_INT_ENA_TIMERS_REG register
+ *  Interrupt enable bits
+ */
+#define TIMG_INT_ENA_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x70)
+/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_ENA    (BIT(0))
+#define TIMG_T0_INT_ENA_M  (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
+#define TIMG_T0_INT_ENA_V  0x00000001U
+#define TIMG_T0_INT_ENA_S  0
+/** TIMG_T1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T1_INT_ENA    (BIT(1))
+#define TIMG_T1_INT_ENA_M  (TIMG_T1_INT_ENA_V << TIMG_T1_INT_ENA_S)
+#define TIMG_T1_INT_ENA_V  0x00000001U
+#define TIMG_T1_INT_ENA_S  1
+/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_ENA    (BIT(2))
+#define TIMG_WDT_INT_ENA_M  (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
+#define TIMG_WDT_INT_ENA_V  0x00000001U
+#define TIMG_WDT_INT_ENA_S  2
+
+/** TIMG_INT_RAW_TIMERS_REG register
+ *  Raw interrupt status
+ */
+#define TIMG_INT_RAW_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x74)
+/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_RAW    (BIT(0))
+#define TIMG_T0_INT_RAW_M  (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
+#define TIMG_T0_INT_RAW_V  0x00000001U
+#define TIMG_T0_INT_RAW_S  0
+/** TIMG_T1_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T1_INT_RAW    (BIT(1))
+#define TIMG_T1_INT_RAW_M  (TIMG_T1_INT_RAW_V << TIMG_T1_INT_RAW_S)
+#define TIMG_T1_INT_RAW_V  0x00000001U
+#define TIMG_T1_INT_RAW_S  1
+/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_RAW    (BIT(2))
+#define TIMG_WDT_INT_RAW_M  (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
+#define TIMG_WDT_INT_RAW_V  0x00000001U
+#define TIMG_WDT_INT_RAW_S  2
+
+/** TIMG_INT_ST_TIMERS_REG register
+ *  Masked interrupt status
+ */
+#define TIMG_INT_ST_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x78)
+/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_ST    (BIT(0))
+#define TIMG_T0_INT_ST_M  (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
+#define TIMG_T0_INT_ST_V  0x00000001U
+#define TIMG_T0_INT_ST_S  0
+/** TIMG_T1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T1_INT_ST    (BIT(1))
+#define TIMG_T1_INT_ST_M  (TIMG_T1_INT_ST_V << TIMG_T1_INT_ST_S)
+#define TIMG_T1_INT_ST_V  0x00000001U
+#define TIMG_T1_INT_ST_S  1
+/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit for the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_ST    (BIT(2))
+#define TIMG_WDT_INT_ST_M  (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
+#define TIMG_WDT_INT_ST_V  0x00000001U
+#define TIMG_WDT_INT_ST_S  2
+
+/** TIMG_INT_CLR_TIMERS_REG register
+ *  Interrupt clear bits
+ */
+#define TIMG_INT_CLR_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x7c)
+/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_CLR    (BIT(0))
+#define TIMG_T0_INT_CLR_M  (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
+#define TIMG_T0_INT_CLR_V  0x00000001U
+#define TIMG_T0_INT_CLR_S  0
+/** TIMG_T1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T1_INT_CLR    (BIT(1))
+#define TIMG_T1_INT_CLR_M  (TIMG_T1_INT_CLR_V << TIMG_T1_INT_CLR_S)
+#define TIMG_T1_INT_CLR_V  0x00000001U
+#define TIMG_T1_INT_CLR_S  1
+/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_CLR    (BIT(2))
+#define TIMG_WDT_INT_CLR_M  (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
+#define TIMG_WDT_INT_CLR_V  0x00000001U
+#define TIMG_WDT_INT_CLR_S  2
+
+/** TIMG_RTCCALICFG2_REG register
+ *  Timer group calibration register
+ */
+#define TIMG_RTCCALICFG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x80)
+/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
+ *  RTC calibration timeout indicator
+ */
+#define TIMG_RTC_CALI_TIMEOUT    (BIT(0))
+#define TIMG_RTC_CALI_TIMEOUT_M  (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
+#define TIMG_RTC_CALI_TIMEOUT_V  0x00000001U
+#define TIMG_RTC_CALI_TIMEOUT_S  0
+/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
+ *  Cycles that release calibration timeout reset
+ */
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT    0x0000000FU
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M  (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V  0x0000000FU
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S  3
+/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
+ *  Threshold value for the RTC calibration timer. If the calibration timer's value
+ *  exceeds this threshold, a timeout is triggered.
+ */
+#define TIMG_RTC_CALI_TIMEOUT_THRES    0x01FFFFFFU
+#define TIMG_RTC_CALI_TIMEOUT_THRES_M  (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
+#define TIMG_RTC_CALI_TIMEOUT_THRES_V  0x01FFFFFFU
+#define TIMG_RTC_CALI_TIMEOUT_THRES_S  7
+
+/** TIMG_NTIMERS_DATE_REG register
+ *  Timer version control register
+ */
+#define TIMG_NTIMERS_DATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xf8)
+/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770;
+ *  Timer version control register
+ */
+#define TIMG_NTIMGS_DATE    0x0FFFFFFFU
+#define TIMG_NTIMGS_DATE_M  (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
+#define TIMG_NTIMGS_DATE_V  0x0FFFFFFFU
+#define TIMG_NTIMGS_DATE_S  0
+
+/** TIMG_REGCLK_REG register
+ *  Timer group clock gate register
+ */
+#define TIMG_REGCLK_REG(i) (DR_REG_TIMG_BASE(i) + 0xfc)
+/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1;
+ *  enable timer's etm task and event
+ */
+#define TIMG_ETM_EN    (BIT(28))
+#define TIMG_ETM_EN_M  (TIMG_ETM_EN_V << TIMG_ETM_EN_S)
+#define TIMG_ETM_EN_V  0x00000001U
+#define TIMG_ETM_EN_S  28
+/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Register clock gate signal. 1: Registers can be read and written to by software. 0:
+ *  Registers can not be read or written to by software.
+ */
+#define TIMG_CLK_EN    (BIT(31))
+#define TIMG_CLK_EN_M  (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
+#define TIMG_CLK_EN_V  0x00000001U
+#define TIMG_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/timer_group_eco5_struct.h

@@ -0,0 +1,571 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: T0 Control and configuration registers */
+/** Type of txconfig register
+ *  Timer x configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
+         *  When set, the alarm is enabled. This bit is automatically cleared once an
+         *  alarm occurs.
+         */
+        uint32_t tx_alarm_en:1;
+        uint32_t reserved_11:1;
+        /** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
+         *  When set, Timer x 's clock divider counter will be reset.
+         */
+        uint32_t tx_divcnt_rst:1;
+        /** tx_divider : R/W; bitpos: [28:13]; default: 1;
+         *  Timer x clock (Tx_clk) prescaler value.
+         */
+        uint32_t tx_divider:16;
+        /** tx_autoreload : R/W; bitpos: [29]; default: 1;
+         *  When set, timer x auto-reload at alarm is enabled.
+         */
+        uint32_t tx_autoreload:1;
+        /** tx_increase : R/W; bitpos: [30]; default: 1;
+         *  When set, the timer x time-base counter will increment every clock tick. When
+         *  cleared, the timer x time-base counter will decrement.
+         */
+        uint32_t tx_increase:1;
+        /** tx_en : R/W/SS/SC; bitpos: [31]; default: 0;
+         *  When set, the timer x time-base counter is enabled.
+         */
+        uint32_t tx_en:1;
+    };
+    uint32_t val;
+} timg_txconfig_reg_t;
+
+/** Type of txlo register
+ *  Timer x current value, low 32 bits
+ */
+typedef union {
+    struct {
+        /** tx_lo : RO; bitpos: [31:0]; default: 0;
+         *  After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
+         *  of timer x can be read here.
+         */
+        uint32_t tx_lo:32;
+    };
+    uint32_t val;
+} timg_txlo_reg_t;
+
+/** Type of txhi register
+ *  Timer x current value, high 22 bits
+ */
+typedef union {
+    struct {
+        /** tx_hi : RO; bitpos: [21:0]; default: 0;
+         *  After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter
+         *  of timer x can be read here.
+         */
+        uint32_t tx_hi:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} timg_txhi_reg_t;
+
+/** Type of txupdate register
+ *  Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tx_update : R/W/SC; bitpos: [31]; default: 0;
+         *  After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched.
+         */
+        uint32_t tx_update:1;
+    };
+    uint32_t val;
+} timg_txupdate_reg_t;
+
+/** Type of txalarmlo register
+ *  Timer x alarm value, low 32 bits
+ */
+typedef union {
+    struct {
+        /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
+         *  Timer x alarm trigger time-base counter value, low 32 bits.
+         */
+        uint32_t tx_alarm_lo:32;
+    };
+    uint32_t val;
+} timg_txalarmlo_reg_t;
+
+/** Type of txalarmhi register
+ *  Timer x alarm value, high bits
+ */
+typedef union {
+    struct {
+        /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
+         *  Timer x alarm trigger time-base counter value, high 22 bits.
+         */
+        uint32_t tx_alarm_hi:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} timg_txalarmhi_reg_t;
+
+/** Type of txloadlo register
+ *  Timer x reload value, low 32 bits
+ */
+typedef union {
+    struct {
+        /** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
+         *  Low 32 bits of the value that a reload will load onto timer x time-base
+         *  Counter.
+         */
+        uint32_t tx_load_lo:32;
+    };
+    uint32_t val;
+} timg_txloadlo_reg_t;
+
+/** Type of txloadhi register
+ *  Timer x reload value, high 22 bits
+ */
+typedef union {
+    struct {
+        /** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
+         *  High 22 bits of the value that a reload will load onto timer x time-base
+         *  counter.
+         */
+        uint32_t tx_load_hi:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} timg_txloadhi_reg_t;
+
+/** Type of txload register
+ *  Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG
+ */
+typedef union {
+    struct {
+        /** tx_load : WT; bitpos: [31:0]; default: 0;
+         *
+         *  Write any value to trigger a timer x time-base counter reload.
+         */
+        uint32_t tx_load:32;
+    };
+    uint32_t val;
+} timg_txload_reg_t;
+
+/** Group: WDT Control and configuration registers */
+/** Type of wdtconfig0 register
+ *  Watchdog timer configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
+         *  WDT reset CPU enable.
+         */
+        uint32_t wdt_appcpu_reset_en:1;
+        /** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
+         *  WDT reset CPU enable.
+         */
+        uint32_t wdt_procpu_reset_en:1;
+        /** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
+         *  When set, Flash boot protection is enabled.
+         */
+        uint32_t wdt_flashboot_mod_en:1;
+        /** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
+         *  System reset signal length selection. 0: 100 ns, 1: 200 ns,
+         *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+         */
+        uint32_t wdt_sys_reset_length:3;
+        /** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
+         *  CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
+         *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+         */
+        uint32_t wdt_cpu_reset_length:3;
+        uint32_t reserved_21:1;
+        /** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
+         *  update the WDT configuration registers
+         */
+        uint32_t wdt_conf_update_en:1;
+        /** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
+         *  Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg3:2;
+        /** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
+         *  Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg2:2;
+        /** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
+         *  Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg1:2;
+        /** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
+         *  Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg0:2;
+        /** wdt_en : R/W; bitpos: [31]; default: 0;
+         *  When set, MWDT is enabled.
+         */
+        uint32_t wdt_en:1;
+    };
+    uint32_t val;
+} timg_wdtconfig0_reg_t;
+
+/** Type of wdtconfig1 register
+ *  Watchdog timer prescaler register
+ */
+typedef union {
+    struct {
+        /** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
+         *  When set, WDT 's clock divider counter will be reset.
+         */
+        uint32_t wdt_divcnt_rst:1;
+        uint32_t reserved_1:15;
+        /** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
+         *  MWDT clock prescaler value. MWDT clock period = 12.5 ns *
+         *  TIMG_WDT_CLK_PRESCALE.
+         */
+        uint32_t wdt_clk_prescale:16;
+    };
+    uint32_t val;
+} timg_wdtconfig1_reg_t;
+
+/** Type of wdtconfig2 register
+ *  Watchdog timer stage 0 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
+         *  Stage 0 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg0_hold:32;
+    };
+    uint32_t val;
+} timg_wdtconfig2_reg_t;
+
+/** Type of wdtconfig3 register
+ *  Watchdog timer stage 1 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
+         *  Stage 1 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg1_hold:32;
+    };
+    uint32_t val;
+} timg_wdtconfig3_reg_t;
+
+/** Type of wdtconfig4 register
+ *  Watchdog timer stage 2 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
+         *  Stage 2 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg2_hold:32;
+    };
+    uint32_t val;
+} timg_wdtconfig4_reg_t;
+
+/** Type of wdtconfig5 register
+ *  Watchdog timer stage 3 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
+         *  Stage 3 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg3_hold:32;
+    };
+    uint32_t val;
+} timg_wdtconfig5_reg_t;
+
+/** Type of wdtfeed register
+ *  Write to feed the watchdog timer
+ */
+typedef union {
+    struct {
+        /** wdt_feed : WT; bitpos: [31:0]; default: 0;
+         *  Write any value to feed the MWDT. (WO)
+         */
+        uint32_t wdt_feed:32;
+    };
+    uint32_t val;
+} timg_wdtfeed_reg_t;
+
+/** Type of wdtwprotect register
+ *  Watchdog write protect register
+ */
+typedef union {
+    struct {
+        /** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
+         *  If the register contains a different value than its reset value, write
+         *  protection is enabled.
+         */
+        uint32_t wdt_wkey:32;
+    };
+    uint32_t val;
+} timg_wdtwprotect_reg_t;
+
+
+/** Group: RTC CALI Control and configuration registers */
+/** Type of rtccalicfg register
+ *  RTC calibration configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
+         *  0: one-shot frequency calculation,1: periodic frequency calculation,
+         */
+        uint32_t rtc_cali_start_cycling:1;
+        /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
+         *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+         */
+        uint32_t rtc_cali_clk_sel:2;
+        /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
+         *  indicate one-shot frequency calculation is done.
+         */
+        uint32_t rtc_cali_rdy:1;
+        /** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
+         *  Configure the time to calculate RTC slow clock's frequency.
+         */
+        uint32_t rtc_cali_max:15;
+        /** rtc_cali_start : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to start one-shot frequency calculation.
+         */
+        uint32_t rtc_cali_start:1;
+    };
+    uint32_t val;
+} timg_rtccalicfg_reg_t;
+
+/** Type of rtccalicfg1 register
+ *  RTC calibration configure1 register
+ */
+typedef union {
+    struct {
+        /** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
+         *  indicate periodic frequency calculation is done.
+         */
+        uint32_t rtc_cali_cycling_data_vld:1;
+        uint32_t reserved_1:6;
+        /** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
+         *  When one-shot or periodic frequency calculation is done, read this value to
+         *  calculate RTC slow clock's frequency.
+         */
+        uint32_t rtc_cali_value:25;
+    };
+    uint32_t val;
+} timg_rtccalicfg1_reg_t;
+
+/** Type of rtccalicfg2 register
+ *  Timer group calibration register
+ */
+typedef union {
+    struct {
+        /** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
+         *  RTC calibration timeout indicator
+         */
+        uint32_t rtc_cali_timeout:1;
+        uint32_t reserved_1:2;
+        /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
+         *  Cycles that release calibration timeout reset
+         */
+        uint32_t rtc_cali_timeout_rst_cnt:4;
+        /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
+         *  Threshold value for the RTC calibration timer. If the calibration timer's value
+         *  exceeds this threshold, a timeout is triggered.
+         */
+        uint32_t rtc_cali_timeout_thres:25;
+    };
+    uint32_t val;
+} timg_rtccalicfg2_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_ena_timers register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** t0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t0_int_ena:1;
+        /** t1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t1_int_ena:1;
+        /** wdt_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} timg_int_ena_timers_reg_t;
+
+/** Type of int_raw_timers register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t0_int_raw:1;
+        /** t1_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t1_int_raw:1;
+        /** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} timg_int_raw_timers_reg_t;
+
+/** Type of int_st_timers register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** t0_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t0_int_st:1;
+        /** t1_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t1_int_st:1;
+        /** wdt_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit for the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} timg_int_st_timers_reg_t;
+
+/** Type of int_clr_timers register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** t0_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t0_int_clr:1;
+        /** t1_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t1_int_clr:1;
+        /** wdt_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} timg_int_clr_timers_reg_t;
+
+
+/** Group: Version register */
+/** Type of ntimers_date register
+ *  Timer version control register
+ */
+typedef union {
+    struct {
+        /** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770;
+         *  Timer version control register
+         */
+        uint32_t ntimgs_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} timg_ntimers_date_reg_t;
+
+
+/** Group: Clock configuration registers */
+/** Type of regclk register
+ *  Timer group clock gate register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** etm_en : R/W; bitpos: [28]; default: 1;
+         *  enable timer's etm task and event
+         */
+        uint32_t etm_en:1;
+        uint32_t reserved_29:2;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Register clock gate signal. 1: Registers can be read and written to by software. 0:
+         *  Registers can not be read or written to by software.
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} timg_regclk_reg_t;
+
+
+typedef struct {
+    volatile timg_txconfig_reg_t t0config;
+    volatile timg_txlo_reg_t t0lo;
+    volatile timg_txhi_reg_t t0hi;
+    volatile timg_txupdate_reg_t t0update;
+    volatile timg_txalarmlo_reg_t t0alarmlo;
+    volatile timg_txalarmhi_reg_t t0alarmhi;
+    volatile timg_txloadlo_reg_t t0loadlo;
+    volatile timg_txloadhi_reg_t t0loadhi;
+    volatile timg_txload_reg_t t0load;
+    volatile timg_txconfig_reg_t t1config;
+    volatile timg_txlo_reg_t t1lo;
+    volatile timg_txhi_reg_t t1hi;
+    volatile timg_txupdate_reg_t t1update;
+    volatile timg_txalarmlo_reg_t t1alarmlo;
+    volatile timg_txalarmhi_reg_t t1alarmhi;
+    volatile timg_txloadlo_reg_t t1loadlo;
+    volatile timg_txloadhi_reg_t t1loadhi;
+    volatile timg_txload_reg_t t1load;
+    volatile timg_wdtconfig0_reg_t wdtconfig0;
+    volatile timg_wdtconfig1_reg_t wdtconfig1;
+    volatile timg_wdtconfig2_reg_t wdtconfig2;
+    volatile timg_wdtconfig3_reg_t wdtconfig3;
+    volatile timg_wdtconfig4_reg_t wdtconfig4;
+    volatile timg_wdtconfig5_reg_t wdtconfig5;
+    volatile timg_wdtfeed_reg_t wdtfeed;
+    volatile timg_wdtwprotect_reg_t wdtwprotect;
+    volatile timg_rtccalicfg_reg_t rtccalicfg;
+    volatile timg_rtccalicfg1_reg_t rtccalicfg1;
+    volatile timg_int_ena_timers_reg_t int_ena_timers;
+    volatile timg_int_raw_timers_reg_t int_raw_timers;
+    volatile timg_int_st_timers_reg_t int_st_timers;
+    volatile timg_int_clr_timers_reg_t int_clr_timers;
+    volatile timg_rtccalicfg2_reg_t rtccalicfg2;
+    uint32_t reserved_084[29];
+    volatile timg_ntimers_date_reg_t ntimers_date;
+    volatile timg_regclk_reg_t regclk;
+} timg_dev_t;
+
+extern timg_dev_t TIMERG0;
+extern timg_dev_t TIMERG1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/timer_group_reg.h

@@ -0,0 +1,718 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13422
+
+/** TIMG_T0CONFIG_REG register
+ *  Timer 0 configuration register
+ */
+#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0)
+/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
+ *  When set, the alarm is enabled. This bit is automatically cleared once an
+ *  alarm occurs.
+ */
+#define TIMG_T0_ALARM_EN    (BIT(10))
+#define TIMG_T0_ALARM_EN_M  (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
+#define TIMG_T0_ALARM_EN_V  0x00000001U
+#define TIMG_T0_ALARM_EN_S  10
+/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
+ *  When set, Timer 0 's clock divider counter will be reset.
+ */
+#define TIMG_T0_DIVCNT_RST    (BIT(12))
+#define TIMG_T0_DIVCNT_RST_M  (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
+#define TIMG_T0_DIVCNT_RST_V  0x00000001U
+#define TIMG_T0_DIVCNT_RST_S  12
+/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
+ *  Timer 0 clock (T0_clk) prescaler value.
+ */
+#define TIMG_T0_DIVIDER    0x0000FFFFU
+#define TIMG_T0_DIVIDER_M  (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
+#define TIMG_T0_DIVIDER_V  0x0000FFFFU
+#define TIMG_T0_DIVIDER_S  13
+/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
+ *  When set, timer 0 auto-reload at alarm is enabled.
+ */
+#define TIMG_T0_AUTORELOAD    (BIT(29))
+#define TIMG_T0_AUTORELOAD_M  (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
+#define TIMG_T0_AUTORELOAD_V  0x00000001U
+#define TIMG_T0_AUTORELOAD_S  29
+/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
+ *  When set, the timer 0 time-base counter will increment every clock tick. When
+ *  cleared, the timer 0 time-base counter will decrement.
+ */
+#define TIMG_T0_INCREASE    (BIT(30))
+#define TIMG_T0_INCREASE_M  (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
+#define TIMG_T0_INCREASE_V  0x00000001U
+#define TIMG_T0_INCREASE_S  30
+/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0;
+ *  When set, the timer 0 time-base counter is enabled.
+ */
+#define TIMG_T0_EN    (BIT(31))
+#define TIMG_T0_EN_M  (TIMG_T0_EN_V << TIMG_T0_EN_S)
+#define TIMG_T0_EN_V  0x00000001U
+#define TIMG_T0_EN_S  31
+
+/** TIMG_T0LO_REG register
+ *  Timer 0 current value, low 32 bits
+ */
+#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4)
+/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
+ *  After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
+ *  of timer 0 can be read here.
+ */
+#define TIMG_T0_LO    0xFFFFFFFFU
+#define TIMG_T0_LO_M  (TIMG_T0_LO_V << TIMG_T0_LO_S)
+#define TIMG_T0_LO_V  0xFFFFFFFFU
+#define TIMG_T0_LO_S  0
+
+/** TIMG_T0HI_REG register
+ *  Timer 0 current value, high 22 bits
+ */
+#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8)
+/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
+ *  After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter
+ *  of timer 0 can be read here.
+ */
+#define TIMG_T0_HI    0x003FFFFFU
+#define TIMG_T0_HI_M  (TIMG_T0_HI_V << TIMG_T0_HI_S)
+#define TIMG_T0_HI_V  0x003FFFFFU
+#define TIMG_T0_HI_S  0
+
+/** TIMG_T0UPDATE_REG register
+ *  Write to copy current timer value to TIMGn_T0_(LO/HI)_REG
+ */
+#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc)
+/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
+ *  After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched.
+ */
+#define TIMG_T0_UPDATE    (BIT(31))
+#define TIMG_T0_UPDATE_M  (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
+#define TIMG_T0_UPDATE_V  0x00000001U
+#define TIMG_T0_UPDATE_S  31
+
+/** TIMG_T0ALARMLO_REG register
+ *  Timer 0 alarm value, low 32 bits
+ */
+#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10)
+/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Timer 0 alarm trigger time-base counter value, low 32 bits.
+ */
+#define TIMG_T0_ALARM_LO    0xFFFFFFFFU
+#define TIMG_T0_ALARM_LO_M  (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
+#define TIMG_T0_ALARM_LO_V  0xFFFFFFFFU
+#define TIMG_T0_ALARM_LO_S  0
+
+/** TIMG_T0ALARMHI_REG register
+ *  Timer 0 alarm value, high bits
+ */
+#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14)
+/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
+ *  Timer 0 alarm trigger time-base counter value, high 22 bits.
+ */
+#define TIMG_T0_ALARM_HI    0x003FFFFFU
+#define TIMG_T0_ALARM_HI_M  (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
+#define TIMG_T0_ALARM_HI_V  0x003FFFFFU
+#define TIMG_T0_ALARM_HI_S  0
+
+/** TIMG_T0LOADLO_REG register
+ *  Timer 0 reload value, low 32 bits
+ */
+#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18)
+/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Low 32 bits of the value that a reload will load onto timer 0 time-base
+ *  Counter.
+ */
+#define TIMG_T0_LOAD_LO    0xFFFFFFFFU
+#define TIMG_T0_LOAD_LO_M  (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
+#define TIMG_T0_LOAD_LO_V  0xFFFFFFFFU
+#define TIMG_T0_LOAD_LO_S  0
+
+/** TIMG_T0LOADHI_REG register
+ *  Timer 0 reload value, high 22 bits
+ */
+#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c)
+/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
+ *  High 22 bits of the value that a reload will load onto timer 0 time-base
+ *  counter.
+ */
+#define TIMG_T0_LOAD_HI    0x003FFFFFU
+#define TIMG_T0_LOAD_HI_M  (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
+#define TIMG_T0_LOAD_HI_V  0x003FFFFFU
+#define TIMG_T0_LOAD_HI_S  0
+
+/** TIMG_T0LOAD_REG register
+ *  Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG
+ */
+#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20)
+/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
+ *
+ *  Write any value to trigger a timer 0 time-base counter reload.
+ */
+#define TIMG_T0_LOAD    0xFFFFFFFFU
+#define TIMG_T0_LOAD_M  (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
+#define TIMG_T0_LOAD_V  0xFFFFFFFFU
+#define TIMG_T0_LOAD_S  0
+
+/** TIMG_T1CONFIG_REG register
+ *  Timer 1 configuration register
+ */
+#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x24)
+/** TIMG_T1_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
+ *  When set, the alarm is enabled. This bit is automatically cleared once an
+ *  alarm occurs.
+ */
+#define TIMG_T1_ALARM_EN    (BIT(10))
+#define TIMG_T1_ALARM_EN_M  (TIMG_T1_ALARM_EN_V << TIMG_T1_ALARM_EN_S)
+#define TIMG_T1_ALARM_EN_V  0x00000001U
+#define TIMG_T1_ALARM_EN_S  10
+/** TIMG_T1_DIVCNT_RST : WT; bitpos: [12]; default: 0;
+ *  When set, Timer 1 's clock divider counter will be reset.
+ */
+#define TIMG_T1_DIVCNT_RST    (BIT(12))
+#define TIMG_T1_DIVCNT_RST_M  (TIMG_T1_DIVCNT_RST_V << TIMG_T1_DIVCNT_RST_S)
+#define TIMG_T1_DIVCNT_RST_V  0x00000001U
+#define TIMG_T1_DIVCNT_RST_S  12
+/** TIMG_T1_DIVIDER : R/W; bitpos: [28:13]; default: 1;
+ *  Timer 1 clock (T1_clk) prescaler value.
+ */
+#define TIMG_T1_DIVIDER    0x0000FFFFU
+#define TIMG_T1_DIVIDER_M  (TIMG_T1_DIVIDER_V << TIMG_T1_DIVIDER_S)
+#define TIMG_T1_DIVIDER_V  0x0000FFFFU
+#define TIMG_T1_DIVIDER_S  13
+/** TIMG_T1_AUTORELOAD : R/W; bitpos: [29]; default: 1;
+ *  When set, timer 1 auto-reload at alarm is enabled.
+ */
+#define TIMG_T1_AUTORELOAD    (BIT(29))
+#define TIMG_T1_AUTORELOAD_M  (TIMG_T1_AUTORELOAD_V << TIMG_T1_AUTORELOAD_S)
+#define TIMG_T1_AUTORELOAD_V  0x00000001U
+#define TIMG_T1_AUTORELOAD_S  29
+/** TIMG_T1_INCREASE : R/W; bitpos: [30]; default: 1;
+ *  When set, the timer 1 time-base counter will increment every clock tick. When
+ *  cleared, the timer 1 time-base counter will decrement.
+ */
+#define TIMG_T1_INCREASE    (BIT(30))
+#define TIMG_T1_INCREASE_M  (TIMG_T1_INCREASE_V << TIMG_T1_INCREASE_S)
+#define TIMG_T1_INCREASE_V  0x00000001U
+#define TIMG_T1_INCREASE_S  30
+/** TIMG_T1_EN : R/W/SS/SC; bitpos: [31]; default: 0;
+ *  When set, the timer 1 time-base counter is enabled.
+ */
+#define TIMG_T1_EN    (BIT(31))
+#define TIMG_T1_EN_M  (TIMG_T1_EN_V << TIMG_T1_EN_S)
+#define TIMG_T1_EN_V  0x00000001U
+#define TIMG_T1_EN_S  31
+
+/** TIMG_T1LO_REG register
+ *  Timer 1 current value, low 32 bits
+ */
+#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x28)
+/** TIMG_T1_LO : RO; bitpos: [31:0]; default: 0;
+ *  After writing to TIMG_T1UPDATE_REG, the low 32 bits of the time-base counter
+ *  of timer 1 can be read here.
+ */
+#define TIMG_T1_LO    0xFFFFFFFFU
+#define TIMG_T1_LO_M  (TIMG_T1_LO_V << TIMG_T1_LO_S)
+#define TIMG_T1_LO_V  0xFFFFFFFFU
+#define TIMG_T1_LO_S  0
+
+/** TIMG_T1HI_REG register
+ *  Timer 1 current value, high 22 bits
+ */
+#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x2c)
+/** TIMG_T1_HI : RO; bitpos: [21:0]; default: 0;
+ *  After writing to TIMG_T1UPDATE_REG, the high 22 bits of the time-base counter
+ *  of timer 1 can be read here.
+ */
+#define TIMG_T1_HI    0x003FFFFFU
+#define TIMG_T1_HI_M  (TIMG_T1_HI_V << TIMG_T1_HI_S)
+#define TIMG_T1_HI_V  0x003FFFFFU
+#define TIMG_T1_HI_S  0
+
+/** TIMG_T1UPDATE_REG register
+ *  Write to copy current timer value to TIMGn_T1_(LO/HI)_REG
+ */
+#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x30)
+/** TIMG_T1_UPDATE : R/W/SC; bitpos: [31]; default: 0;
+ *  After writing 0 or 1 to TIMG_T1UPDATE_REG, the counter value is latched.
+ */
+#define TIMG_T1_UPDATE    (BIT(31))
+#define TIMG_T1_UPDATE_M  (TIMG_T1_UPDATE_V << TIMG_T1_UPDATE_S)
+#define TIMG_T1_UPDATE_V  0x00000001U
+#define TIMG_T1_UPDATE_S  31
+
+/** TIMG_T1ALARMLO_REG register
+ *  Timer 1 alarm value, low 32 bits
+ */
+#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x34)
+/** TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Timer 1 alarm trigger time-base counter value, low 32 bits.
+ */
+#define TIMG_T1_ALARM_LO    0xFFFFFFFFU
+#define TIMG_T1_ALARM_LO_M  (TIMG_T1_ALARM_LO_V << TIMG_T1_ALARM_LO_S)
+#define TIMG_T1_ALARM_LO_V  0xFFFFFFFFU
+#define TIMG_T1_ALARM_LO_S  0
+
+/** TIMG_T1ALARMHI_REG register
+ *  Timer 1 alarm value, high bits
+ */
+#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x38)
+/** TIMG_T1_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
+ *  Timer 1 alarm trigger time-base counter value, high 22 bits.
+ */
+#define TIMG_T1_ALARM_HI    0x003FFFFFU
+#define TIMG_T1_ALARM_HI_M  (TIMG_T1_ALARM_HI_V << TIMG_T1_ALARM_HI_S)
+#define TIMG_T1_ALARM_HI_V  0x003FFFFFU
+#define TIMG_T1_ALARM_HI_S  0
+
+/** TIMG_T1LOADLO_REG register
+ *  Timer 1 reload value, low 32 bits
+ */
+#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x3c)
+/** TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Low 32 bits of the value that a reload will load onto timer 1 time-base
+ *  Counter.
+ */
+#define TIMG_T1_LOAD_LO    0xFFFFFFFFU
+#define TIMG_T1_LOAD_LO_M  (TIMG_T1_LOAD_LO_V << TIMG_T1_LOAD_LO_S)
+#define TIMG_T1_LOAD_LO_V  0xFFFFFFFFU
+#define TIMG_T1_LOAD_LO_S  0
+
+/** TIMG_T1LOADHI_REG register
+ *  Timer 1 reload value, high 22 bits
+ */
+#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x40)
+/** TIMG_T1_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
+ *  High 22 bits of the value that a reload will load onto timer 1 time-base
+ *  counter.
+ */
+#define TIMG_T1_LOAD_HI    0x003FFFFFU
+#define TIMG_T1_LOAD_HI_M  (TIMG_T1_LOAD_HI_V << TIMG_T1_LOAD_HI_S)
+#define TIMG_T1_LOAD_HI_V  0x003FFFFFU
+#define TIMG_T1_LOAD_HI_S  0
+
+/** TIMG_T1LOAD_REG register
+ *  Write to reload timer from TIMG_T1_(LOADLOLOADHI)_REG
+ */
+#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x44)
+/** TIMG_T1_LOAD : WT; bitpos: [31:0]; default: 0;
+ *
+ *  Write any value to trigger a timer 1 time-base counter reload.
+ */
+#define TIMG_T1_LOAD    0xFFFFFFFFU
+#define TIMG_T1_LOAD_M  (TIMG_T1_LOAD_V << TIMG_T1_LOAD_S)
+#define TIMG_T1_LOAD_V  0xFFFFFFFFU
+#define TIMG_T1_LOAD_S  0
+
+/** TIMG_WDTCONFIG0_REG register
+ *  Watchdog timer configuration register
+ */
+#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48)
+/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
+ *  WDT reset CPU enable.
+ */
+#define TIMG_WDT_APPCPU_RESET_EN    (BIT(12))
+#define TIMG_WDT_APPCPU_RESET_EN_M  (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
+#define TIMG_WDT_APPCPU_RESET_EN_V  0x00000001U
+#define TIMG_WDT_APPCPU_RESET_EN_S  12
+/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
+ *  WDT reset CPU enable.
+ */
+#define TIMG_WDT_PROCPU_RESET_EN    (BIT(13))
+#define TIMG_WDT_PROCPU_RESET_EN_M  (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
+#define TIMG_WDT_PROCPU_RESET_EN_V  0x00000001U
+#define TIMG_WDT_PROCPU_RESET_EN_S  13
+/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
+ *  When set, Flash boot protection is enabled.
+ */
+#define TIMG_WDT_FLASHBOOT_MOD_EN    (BIT(14))
+#define TIMG_WDT_FLASHBOOT_MOD_EN_M  (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
+#define TIMG_WDT_FLASHBOOT_MOD_EN_V  0x00000001U
+#define TIMG_WDT_FLASHBOOT_MOD_EN_S  14
+/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
+ *  System reset signal length selection. 0: 100 ns, 1: 200 ns,
+ *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+ */
+#define TIMG_WDT_SYS_RESET_LENGTH    0x00000007U
+#define TIMG_WDT_SYS_RESET_LENGTH_M  (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
+#define TIMG_WDT_SYS_RESET_LENGTH_V  0x00000007U
+#define TIMG_WDT_SYS_RESET_LENGTH_S  15
+/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
+ *  CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
+ *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+ */
+#define TIMG_WDT_CPU_RESET_LENGTH    0x00000007U
+#define TIMG_WDT_CPU_RESET_LENGTH_M  (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
+#define TIMG_WDT_CPU_RESET_LENGTH_V  0x00000007U
+#define TIMG_WDT_CPU_RESET_LENGTH_S  18
+/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
+ *  update the WDT configuration registers
+ */
+#define TIMG_WDT_CONF_UPDATE_EN    (BIT(22))
+#define TIMG_WDT_CONF_UPDATE_EN_M  (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
+#define TIMG_WDT_CONF_UPDATE_EN_V  0x00000001U
+#define TIMG_WDT_CONF_UPDATE_EN_S  22
+/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
+ *  Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG3    0x00000003U
+#define TIMG_WDT_STG3_M  (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
+#define TIMG_WDT_STG3_V  0x00000003U
+#define TIMG_WDT_STG3_S  23
+/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
+ *  Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG2    0x00000003U
+#define TIMG_WDT_STG2_M  (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
+#define TIMG_WDT_STG2_V  0x00000003U
+#define TIMG_WDT_STG2_S  25
+/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
+ *  Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG1    0x00000003U
+#define TIMG_WDT_STG1_M  (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
+#define TIMG_WDT_STG1_V  0x00000003U
+#define TIMG_WDT_STG1_S  27
+/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
+ *  Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG0    0x00000003U
+#define TIMG_WDT_STG0_M  (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
+#define TIMG_WDT_STG0_V  0x00000003U
+#define TIMG_WDT_STG0_S  29
+/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
+ *  When set, MWDT is enabled.
+ */
+#define TIMG_WDT_EN    (BIT(31))
+#define TIMG_WDT_EN_M  (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
+#define TIMG_WDT_EN_V  0x00000001U
+#define TIMG_WDT_EN_S  31
+
+/** TIMG_WDTCONFIG1_REG register
+ *  Watchdog timer prescaler register
+ */
+#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4c)
+/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
+ *  When set, WDT 's clock divider counter will be reset.
+ */
+#define TIMG_WDT_DIVCNT_RST    (BIT(0))
+#define TIMG_WDT_DIVCNT_RST_M  (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
+#define TIMG_WDT_DIVCNT_RST_V  0x00000001U
+#define TIMG_WDT_DIVCNT_RST_S  0
+/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
+ *  MWDT clock prescaler value. MWDT clock period = 12.5 ns *
+ *  TIMG_WDT_CLK_PRESCALE.
+ */
+#define TIMG_WDT_CLK_PRESCALE    0x0000FFFFU
+#define TIMG_WDT_CLK_PRESCALE_M  (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
+#define TIMG_WDT_CLK_PRESCALE_V  0x0000FFFFU
+#define TIMG_WDT_CLK_PRESCALE_S  16
+
+/** TIMG_WDTCONFIG2_REG register
+ *  Watchdog timer stage 0 timeout value
+ */
+#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50)
+/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
+ *  Stage 0 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG0_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG0_HOLD_M  (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
+#define TIMG_WDT_STG0_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG0_HOLD_S  0
+
+/** TIMG_WDTCONFIG3_REG register
+ *  Watchdog timer stage 1 timeout value
+ */
+#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54)
+/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
+ *  Stage 1 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG1_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG1_HOLD_M  (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
+#define TIMG_WDT_STG1_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG1_HOLD_S  0
+
+/** TIMG_WDTCONFIG4_REG register
+ *  Watchdog timer stage 2 timeout value
+ */
+#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58)
+/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
+ *  Stage 2 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG2_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG2_HOLD_M  (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
+#define TIMG_WDT_STG2_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG2_HOLD_S  0
+
+/** TIMG_WDTCONFIG5_REG register
+ *  Watchdog timer stage 3 timeout value
+ */
+#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5c)
+/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
+ *  Stage 3 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG3_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG3_HOLD_M  (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
+#define TIMG_WDT_STG3_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG3_HOLD_S  0
+
+/** TIMG_WDTFEED_REG register
+ *  Write to feed the watchdog timer
+ */
+#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x60)
+/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
+ *  Write any value to feed the MWDT. (WO)
+ */
+#define TIMG_WDT_FEED    0xFFFFFFFFU
+#define TIMG_WDT_FEED_M  (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
+#define TIMG_WDT_FEED_V  0xFFFFFFFFU
+#define TIMG_WDT_FEED_S  0
+
+/** TIMG_WDTWPROTECT_REG register
+ *  Watchdog write protect register
+ */
+#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x64)
+/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
+ *  If the register contains a different value than its reset value, write
+ *  protection is enabled.
+ */
+#define TIMG_WDT_WKEY    0xFFFFFFFFU
+#define TIMG_WDT_WKEY_M  (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
+#define TIMG_WDT_WKEY_V  0xFFFFFFFFU
+#define TIMG_WDT_WKEY_S  0
+
+/** TIMG_RTCCALICFG_REG register
+ *  RTC calibration configure register
+ */
+#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68)
+/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
+ *  0: one-shot frequency calculation,1: periodic frequency calculation,
+ */
+#define TIMG_RTC_CALI_START_CYCLING    (BIT(12))
+#define TIMG_RTC_CALI_START_CYCLING_M  (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
+#define TIMG_RTC_CALI_START_CYCLING_V  0x00000001U
+#define TIMG_RTC_CALI_START_CYCLING_S  12
+/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0;
+ *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+ */
+#define TIMG_RTC_CALI_CLK_SEL    0x00000003U
+#define TIMG_RTC_CALI_CLK_SEL_M  (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
+#define TIMG_RTC_CALI_CLK_SEL_V  0x00000003U
+#define TIMG_RTC_CALI_CLK_SEL_S  13
+/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
+ *  indicate one-shot frequency calculation is done.
+ */
+#define TIMG_RTC_CALI_RDY    (BIT(15))
+#define TIMG_RTC_CALI_RDY_M  (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
+#define TIMG_RTC_CALI_RDY_V  0x00000001U
+#define TIMG_RTC_CALI_RDY_S  15
+/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
+ *  Configure the time to calculate RTC slow clock's frequency.
+ */
+#define TIMG_RTC_CALI_MAX    0x00007FFFU
+#define TIMG_RTC_CALI_MAX_M  (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
+#define TIMG_RTC_CALI_MAX_V  0x00007FFFU
+#define TIMG_RTC_CALI_MAX_S  16
+/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to start one-shot frequency calculation.
+ */
+#define TIMG_RTC_CALI_START    (BIT(31))
+#define TIMG_RTC_CALI_START_M  (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
+#define TIMG_RTC_CALI_START_V  0x00000001U
+#define TIMG_RTC_CALI_START_S  31
+
+/** TIMG_RTCCALICFG1_REG register
+ *  RTC calibration configure1 register
+ */
+#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6c)
+/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
+ *  indicate periodic frequency calculation is done.
+ */
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD    (BIT(0))
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M  (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V  0x00000001U
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S  0
+/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
+ *  When one-shot or periodic frequency calculation is done, read this value to
+ *  calculate RTC slow clock's frequency.
+ */
+#define TIMG_RTC_CALI_VALUE    0x01FFFFFFU
+#define TIMG_RTC_CALI_VALUE_M  (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
+#define TIMG_RTC_CALI_VALUE_V  0x01FFFFFFU
+#define TIMG_RTC_CALI_VALUE_S  7
+
+/** TIMG_INT_ENA_TIMERS_REG register
+ *  Interrupt enable bits
+ */
+#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x70)
+/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_ENA    (BIT(0))
+#define TIMG_T0_INT_ENA_M  (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
+#define TIMG_T0_INT_ENA_V  0x00000001U
+#define TIMG_T0_INT_ENA_S  0
+/** TIMG_T1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T1_INT_ENA    (BIT(1))
+#define TIMG_T1_INT_ENA_M  (TIMG_T1_INT_ENA_V << TIMG_T1_INT_ENA_S)
+#define TIMG_T1_INT_ENA_V  0x00000001U
+#define TIMG_T1_INT_ENA_S  1
+/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_ENA    (BIT(2))
+#define TIMG_WDT_INT_ENA_M  (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
+#define TIMG_WDT_INT_ENA_V  0x00000001U
+#define TIMG_WDT_INT_ENA_S  2
+
+/** TIMG_INT_RAW_TIMERS_REG register
+ *  Raw interrupt status
+ */
+#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x74)
+/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_RAW    (BIT(0))
+#define TIMG_T0_INT_RAW_M  (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
+#define TIMG_T0_INT_RAW_V  0x00000001U
+#define TIMG_T0_INT_RAW_S  0
+/** TIMG_T1_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T1_INT_RAW    (BIT(1))
+#define TIMG_T1_INT_RAW_M  (TIMG_T1_INT_RAW_V << TIMG_T1_INT_RAW_S)
+#define TIMG_T1_INT_RAW_V  0x00000001U
+#define TIMG_T1_INT_RAW_S  1
+/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_RAW    (BIT(2))
+#define TIMG_WDT_INT_RAW_M  (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
+#define TIMG_WDT_INT_RAW_V  0x00000001U
+#define TIMG_WDT_INT_RAW_S  2
+
+/** TIMG_INT_ST_TIMERS_REG register
+ *  Masked interrupt status
+ */
+#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x78)
+/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_ST    (BIT(0))
+#define TIMG_T0_INT_ST_M  (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
+#define TIMG_T0_INT_ST_V  0x00000001U
+#define TIMG_T0_INT_ST_S  0
+/** TIMG_T1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T1_INT_ST    (BIT(1))
+#define TIMG_T1_INT_ST_M  (TIMG_T1_INT_ST_V << TIMG_T1_INT_ST_S)
+#define TIMG_T1_INT_ST_V  0x00000001U
+#define TIMG_T1_INT_ST_S  1
+/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit for the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_ST    (BIT(2))
+#define TIMG_WDT_INT_ST_M  (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
+#define TIMG_WDT_INT_ST_V  0x00000001U
+#define TIMG_WDT_INT_ST_S  2
+
+/** TIMG_INT_CLR_TIMERS_REG register
+ *  Interrupt clear bits
+ */
+#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x7c)
+/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_CLR    (BIT(0))
+#define TIMG_T0_INT_CLR_M  (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
+#define TIMG_T0_INT_CLR_V  0x00000001U
+#define TIMG_T0_INT_CLR_S  0
+/** TIMG_T1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T1_INT_CLR    (BIT(1))
+#define TIMG_T1_INT_CLR_M  (TIMG_T1_INT_CLR_V << TIMG_T1_INT_CLR_S)
+#define TIMG_T1_INT_CLR_V  0x00000001U
+#define TIMG_T1_INT_CLR_S  1
+/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_CLR    (BIT(2))
+#define TIMG_WDT_INT_CLR_M  (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
+#define TIMG_WDT_INT_CLR_V  0x00000001U
+#define TIMG_WDT_INT_CLR_S  2
+
+/** TIMG_RTCCALICFG2_REG register
+ *  Timer group calibration register
+ */
+#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80)
+/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
+ *  RTC calibration timeout indicator
+ */
+#define TIMG_RTC_CALI_TIMEOUT    (BIT(0))
+#define TIMG_RTC_CALI_TIMEOUT_M  (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
+#define TIMG_RTC_CALI_TIMEOUT_V  0x00000001U
+#define TIMG_RTC_CALI_TIMEOUT_S  0
+/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
+ *  Cycles that release calibration timeout reset
+ */
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT    0x0000000FU
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M  (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V  0x0000000FU
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S  3
+/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
+ *  Threshold value for the RTC calibration timer. If the calibration timer's value
+ *  exceeds this threshold, a timeout is triggered.
+ */
+#define TIMG_RTC_CALI_TIMEOUT_THRES    0x01FFFFFFU
+#define TIMG_RTC_CALI_TIMEOUT_THRES_M  (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
+#define TIMG_RTC_CALI_TIMEOUT_THRES_V  0x01FFFFFFU
+#define TIMG_RTC_CALI_TIMEOUT_THRES_S  7
+
+/** TIMG_NTIMERS_DATE_REG register
+ *  Timer version control register
+ */
+#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0xf8)
+/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770;
+ *  Timer version control register
+ */
+#define TIMG_NTIMGS_DATE    0x0FFFFFFFU
+#define TIMG_NTIMGS_DATE_M  (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
+#define TIMG_NTIMGS_DATE_V  0x0FFFFFFFU
+#define TIMG_NTIMGS_DATE_S  0
+
+/** TIMG_REGCLK_REG register
+ *  Timer group clock gate register
+ */
+#define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xfc)
+/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1;
+ *  enable timer's etm task and event
+ */
+#define TIMG_ETM_EN    (BIT(28))
+#define TIMG_ETM_EN_M  (TIMG_ETM_EN_V << TIMG_ETM_EN_S)
+#define TIMG_ETM_EN_V  0x00000001U
+#define TIMG_ETM_EN_S  28
+/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Register clock gate signal. 1: Registers can be read and written to by software. 0:
+ *  Registers can not be read or written to by software.
+ */
+#define TIMG_CLK_EN    (BIT(31))
+#define TIMG_CLK_EN_M  (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
+#define TIMG_CLK_EN_V  0x00000001U
+#define TIMG_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/timer_group_struct.h

@@ -0,0 +1,563 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13422
+
+/** Group: T0 Control and configuration registers */
+/** Type of txconfig register
+ *  Timer x configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 10;
+        /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
+         *  When set, the alarm is enabled. This bit is automatically cleared once an
+         *  alarm occurs.
+         */
+        uint32_t tx_alarm_en: 1;
+        uint32_t reserved_11: 1;
+        /** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
+         *  When set, Timer x 's clock divider counter will be reset.
+         */
+        uint32_t tx_divcnt_rst: 1;
+        /** tx_divider : R/W; bitpos: [28:13]; default: 1;
+         *  Timer x clock (Tx_clk) prescaler value.
+         */
+        uint32_t tx_divider: 16;
+        /** tx_autoreload : R/W; bitpos: [29]; default: 1;
+         *  When set, timer x auto-reload at alarm is enabled.
+         */
+        uint32_t tx_autoreload: 1;
+        /** tx_increase : R/W; bitpos: [30]; default: 1;
+         *  When set, the timer x time-base counter will increment every clock tick. When
+         *  cleared, the timer x time-base counter will decrement.
+         */
+        uint32_t tx_increase: 1;
+        /** tx_en : R/W/SS/SC; bitpos: [31]; default: 0;
+         *  When set, the timer x time-base counter is enabled.
+         */
+        uint32_t tx_en: 1;
+    };
+    uint32_t val;
+} timg_txconfig_reg_t;
+
+/** Type of txlo register
+ *  Timer x current value, low 32 bits
+ */
+typedef union {
+    struct {
+        /** tx_lo : RO; bitpos: [31:0]; default: 0;
+         *  After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
+         *  of timer x can be read here.
+         */
+        uint32_t tx_lo: 32;
+    };
+    uint32_t val;
+} timg_txlo_reg_t;
+
+/** Type of txhi register
+ *  Timer x current value, high 22 bits
+ */
+typedef union {
+    struct {
+        /** tx_hi : RO; bitpos: [21:0]; default: 0;
+         *  After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter
+         *  of timer x can be read here.
+         */
+        uint32_t tx_hi: 22;
+        uint32_t reserved_22: 10;
+    };
+    uint32_t val;
+} timg_txhi_reg_t;
+
+/** Type of txupdate register
+ *  Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 31;
+        /** tx_update : R/W/SC; bitpos: [31]; default: 0;
+         *  After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched.
+         */
+        uint32_t tx_update: 1;
+    };
+    uint32_t val;
+} timg_txupdate_reg_t;
+
+/** Type of txalarmlo register
+ *  Timer x alarm value, low 32 bits
+ */
+typedef union {
+    struct {
+        /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
+         *  Timer x alarm trigger time-base counter value, low 32 bits.
+         */
+        uint32_t tx_alarm_lo: 32;
+    };
+    uint32_t val;
+} timg_txalarmlo_reg_t;
+
+/** Type of txalarmhi register
+ *  Timer x alarm value, high bits
+ */
+typedef union {
+    struct {
+        /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
+         *  Timer x alarm trigger time-base counter value, high 22 bits.
+         */
+        uint32_t tx_alarm_hi: 22;
+        uint32_t reserved_22: 10;
+    };
+    uint32_t val;
+} timg_txalarmhi_reg_t;
+
+/** Type of txloadlo register
+ *  Timer x reload value, low 32 bits
+ */
+typedef union {
+    struct {
+        /** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
+         *  Low 32 bits of the value that a reload will load onto timer x time-base
+         *  Counter.
+         */
+        uint32_t tx_load_lo: 32;
+    };
+    uint32_t val;
+} timg_txloadlo_reg_t;
+
+/** Type of txloadhi register
+ *  Timer x reload value, high 22 bits
+ */
+typedef union {
+    struct {
+        /** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
+         *  High 22 bits of the value that a reload will load onto timer x time-base
+         *  counter.
+         */
+        uint32_t tx_load_hi: 22;
+        uint32_t reserved_22: 10;
+    };
+    uint32_t val;
+} timg_txloadhi_reg_t;
+
+/** Type of txload register
+ *  Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG
+ */
+typedef union {
+    struct {
+        /** tx_load : WT; bitpos: [31:0]; default: 0;
+         *
+         *  Write any value to trigger a timer x time-base counter reload.
+         */
+        uint32_t tx_load: 32;
+    };
+    uint32_t val;
+} timg_txload_reg_t;
+
+/** Group: WDT Control and configuration registers */
+/** Type of wdtconfig0 register
+ *  Watchdog timer configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 12;
+        /** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
+         *  WDT reset CPU enable.
+         */
+        uint32_t wdt_appcpu_reset_en: 1;
+        /** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
+         *  WDT reset CPU enable.
+         */
+        uint32_t wdt_procpu_reset_en: 1;
+        /** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
+         *  When set, Flash boot protection is enabled.
+         */
+        uint32_t wdt_flashboot_mod_en: 1;
+        /** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
+         *  System reset signal length selection. 0: 100 ns, 1: 200 ns,
+         *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+         */
+        uint32_t wdt_sys_reset_length: 3;
+        /** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
+         *  CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
+         *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+         */
+        uint32_t wdt_cpu_reset_length: 3;
+        uint32_t reserved_21: 1;
+        /** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
+         *  update the WDT configuration registers
+         */
+        uint32_t wdt_conf_update_en: 1;
+        /** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
+         *  Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg3: 2;
+        /** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
+         *  Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg2: 2;
+        /** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
+         *  Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg1: 2;
+        /** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
+         *  Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg0: 2;
+        /** wdt_en : R/W; bitpos: [31]; default: 0;
+         *  When set, MWDT is enabled.
+         */
+        uint32_t wdt_en: 1;
+    };
+    uint32_t val;
+} timg_wdtconfig0_reg_t;
+
+/** Type of wdtconfig1 register
+ *  Watchdog timer prescaler register
+ */
+typedef union {
+    struct {
+        /** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
+         *  When set, WDT 's clock divider counter will be reset.
+         */
+        uint32_t wdt_divcnt_rst: 1;
+        uint32_t reserved_1: 15;
+        /** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
+         *  MWDT clock prescaler value. MWDT clock period = 12.5 ns *
+         *  TIMG_WDT_CLK_PRESCALE.
+         */
+        uint32_t wdt_clk_prescale: 16;
+    };
+    uint32_t val;
+} timg_wdtconfig1_reg_t;
+
+/** Type of wdtconfig2 register
+ *  Watchdog timer stage 0 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
+         *  Stage 0 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg0_hold: 32;
+    };
+    uint32_t val;
+} timg_wdtconfig2_reg_t;
+
+/** Type of wdtconfig3 register
+ *  Watchdog timer stage 1 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
+         *  Stage 1 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg1_hold: 32;
+    };
+    uint32_t val;
+} timg_wdtconfig3_reg_t;
+
+/** Type of wdtconfig4 register
+ *  Watchdog timer stage 2 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
+         *  Stage 2 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg2_hold: 32;
+    };
+    uint32_t val;
+} timg_wdtconfig4_reg_t;
+
+/** Type of wdtconfig5 register
+ *  Watchdog timer stage 3 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
+         *  Stage 3 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg3_hold: 32;
+    };
+    uint32_t val;
+} timg_wdtconfig5_reg_t;
+
+/** Type of wdtfeed register
+ *  Write to feed the watchdog timer
+ */
+typedef union {
+    struct {
+        /** wdt_feed : WT; bitpos: [31:0]; default: 0;
+         *  Write any value to feed the MWDT. (WO)
+         */
+        uint32_t wdt_feed: 32;
+    };
+    uint32_t val;
+} timg_wdtfeed_reg_t;
+
+/** Type of wdtwprotect register
+ *  Watchdog write protect register
+ */
+typedef union {
+    struct {
+        /** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
+         *  If the register contains a different value than its reset value, write
+         *  protection is enabled.
+         */
+        uint32_t wdt_wkey: 32;
+    };
+    uint32_t val;
+} timg_wdtwprotect_reg_t;
+
+/** Group: RTC CALI Control and configuration registers */
+/** Type of rtccalicfg register
+ *  RTC calibration configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 12;
+        /** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
+         *  0: one-shot frequency calculation,1: periodic frequency calculation,
+         */
+        uint32_t rtc_cali_start_cycling: 1;
+        /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
+         *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+         */
+        uint32_t rtc_cali_clk_sel: 2;
+        /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
+         *  indicate one-shot frequency calculation is done.
+         */
+        uint32_t rtc_cali_rdy: 1;
+        /** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
+         *  Configure the time to calculate RTC slow clock's frequency.
+         */
+        uint32_t rtc_cali_max: 15;
+        /** rtc_cali_start : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to start one-shot frequency calculation.
+         */
+        uint32_t rtc_cali_start: 1;
+    };
+    uint32_t val;
+} timg_rtccalicfg_reg_t;
+
+/** Type of rtccalicfg1 register
+ *  RTC calibration configure1 register
+ */
+typedef union {
+    struct {
+        /** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
+         *  indicate periodic frequency calculation is done.
+         */
+        uint32_t rtc_cali_cycling_data_vld: 1;
+        uint32_t reserved_1: 6;
+        /** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
+         *  When one-shot or periodic frequency calculation is done, read this value to
+         *  calculate RTC slow clock's frequency.
+         */
+        uint32_t rtc_cali_value: 25;
+    };
+    uint32_t val;
+} timg_rtccalicfg1_reg_t;
+
+/** Type of rtccalicfg2 register
+ *  Timer group calibration register
+ */
+typedef union {
+    struct {
+        /** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
+         *  RTC calibration timeout indicator
+         */
+        uint32_t rtc_cali_timeout: 1;
+        uint32_t reserved_1: 2;
+        /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
+         *  Cycles that release calibration timeout reset
+         */
+        uint32_t rtc_cali_timeout_rst_cnt: 4;
+        /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
+         *  Threshold value for the RTC calibration timer. If the calibration timer's value
+         *  exceeds this threshold, a timeout is triggered.
+         */
+        uint32_t rtc_cali_timeout_thres: 25;
+    };
+    uint32_t val;
+} timg_rtccalicfg2_reg_t;
+
+/** Group: Interrupt registers */
+/** Type of int_ena_timers register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** t0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t0_int_ena: 1;
+        /** t1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t1_int_ena: 1;
+        /** wdt_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_ena: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} timg_int_ena_timers_reg_t;
+
+/** Type of int_raw_timers register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t0_int_raw: 1;
+        /** t1_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t1_int_raw: 1;
+        /** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_raw: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} timg_int_raw_timers_reg_t;
+
+/** Type of int_st_timers register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** t0_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t0_int_st: 1;
+        /** t1_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t1_int_st: 1;
+        /** wdt_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit for the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_st: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} timg_int_st_timers_reg_t;
+
+/** Type of int_clr_timers register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** t0_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t0_int_clr: 1;
+        /** t1_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the TIMG_T$x_INT interrupt.
+         */
+        uint32_t t1_int_clr: 1;
+        /** wdt_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_clr: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} timg_int_clr_timers_reg_t;
+
+/** Group: Version register */
+/** Type of ntimers_date register
+ *  Timer version control register
+ */
+typedef union {
+    struct {
+        /** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770;
+         *  Timer version control register
+         */
+        uint32_t ntimgs_date: 28;
+        uint32_t reserved_28: 4;
+    };
+    uint32_t val;
+} timg_ntimers_date_reg_t;
+
+/** Group: Clock configuration registers */
+/** Type of regclk register
+ *  Timer group clock gate register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 28;
+        /** etm_en : R/W; bitpos: [28]; default: 1;
+         *  enable timer's etm task and event
+         */
+        uint32_t etm_en: 1;
+        uint32_t reserved_29: 2;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Register clock gate signal. 1: Registers can be read and written to by software. 0:
+         *  Registers can not be read or written to by software.
+         */
+        uint32_t clk_en: 1;
+    };
+    uint32_t val;
+} timg_regclk_reg_t;
+
+typedef struct {
+    volatile timg_txconfig_reg_t config;
+    volatile timg_txlo_reg_t lo;
+    volatile timg_txhi_reg_t hi;
+    volatile timg_txupdate_reg_t update;
+    volatile timg_txalarmlo_reg_t alarmlo;
+    volatile timg_txalarmhi_reg_t alarmhi;
+    volatile timg_txloadlo_reg_t loadlo;
+    volatile timg_txloadhi_reg_t loadhi;
+    volatile timg_txload_reg_t load;
+} timg_hwtimer_reg_t;
+
+typedef struct timg_dev_t {
+    volatile timg_hwtimer_reg_t hw_timer[2];
+    volatile timg_wdtconfig0_reg_t wdtconfig0;
+    volatile timg_wdtconfig1_reg_t wdtconfig1;
+    volatile timg_wdtconfig2_reg_t wdtconfig2;
+    volatile timg_wdtconfig3_reg_t wdtconfig3;
+    volatile timg_wdtconfig4_reg_t wdtconfig4;
+    volatile timg_wdtconfig5_reg_t wdtconfig5;
+    volatile timg_wdtfeed_reg_t wdtfeed;
+    volatile timg_wdtwprotect_reg_t wdtwprotect;
+    volatile timg_rtccalicfg_reg_t rtccalicfg;
+    volatile timg_rtccalicfg1_reg_t rtccalicfg1;
+    volatile timg_int_ena_timers_reg_t int_ena_timers;
+    volatile timg_int_raw_timers_reg_t int_raw_timers;
+    volatile timg_int_st_timers_reg_t int_st_timers;
+    volatile timg_int_clr_timers_reg_t int_clr_timers;
+    volatile timg_rtccalicfg2_reg_t rtccalicfg2;
+    uint32_t reserved_084[29];
+    volatile timg_ntimers_date_reg_t ntimers_date;
+    volatile timg_regclk_reg_t regclk;
+} timg_dev_t;
+
+extern timg_dev_t TIMERG0;
+extern timg_dev_t TIMERG1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/touch_reg.h

@@ -0,0 +1,766 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13423
+
+/** RTC_TOUCH_INT_RAW_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_INT_RAW_REG (DR_REG_LP_TOUCH_BASE + 0x0)
+/** RTC_TOUCH_SCAN_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SCAN_DONE_INT_RAW    (BIT(0))
+#define RTC_TOUCH_SCAN_DONE_INT_RAW_M  (RTC_TOUCH_SCAN_DONE_INT_RAW_V << RTC_TOUCH_SCAN_DONE_INT_RAW_S)
+#define RTC_TOUCH_SCAN_DONE_INT_RAW_V  0x00000001U
+#define RTC_TOUCH_SCAN_DONE_INT_RAW_S  0
+/** RTC_TOUCH_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DONE_INT_RAW    (BIT(1))
+#define RTC_TOUCH_DONE_INT_RAW_M  (RTC_TOUCH_DONE_INT_RAW_V << RTC_TOUCH_DONE_INT_RAW_S)
+#define RTC_TOUCH_DONE_INT_RAW_V  0x00000001U
+#define RTC_TOUCH_DONE_INT_RAW_S  1
+/** RTC_TOUCH_ACTIVE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_ACTIVE_INT_RAW    (BIT(2))
+#define RTC_TOUCH_ACTIVE_INT_RAW_M  (RTC_TOUCH_ACTIVE_INT_RAW_V << RTC_TOUCH_ACTIVE_INT_RAW_S)
+#define RTC_TOUCH_ACTIVE_INT_RAW_V  0x00000001U
+#define RTC_TOUCH_ACTIVE_INT_RAW_S  2
+/** RTC_TOUCH_INACTIVE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_INACTIVE_INT_RAW    (BIT(3))
+#define RTC_TOUCH_INACTIVE_INT_RAW_M  (RTC_TOUCH_INACTIVE_INT_RAW_V << RTC_TOUCH_INACTIVE_INT_RAW_S)
+#define RTC_TOUCH_INACTIVE_INT_RAW_V  0x00000001U
+#define RTC_TOUCH_INACTIVE_INT_RAW_S  3
+/** RTC_TOUCH_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_TIMEOUT_INT_RAW    (BIT(4))
+#define RTC_TOUCH_TIMEOUT_INT_RAW_M  (RTC_TOUCH_TIMEOUT_INT_RAW_V << RTC_TOUCH_TIMEOUT_INT_RAW_S)
+#define RTC_TOUCH_TIMEOUT_INT_RAW_V  0x00000001U
+#define RTC_TOUCH_TIMEOUT_INT_RAW_S  4
+/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW    (BIT(5))
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M  (RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S)
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V  0x00000001U
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S  5
+
+/** RTC_TOUCH_INT_ST_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_INT_ST_REG (DR_REG_LP_TOUCH_BASE + 0x4)
+/** RTC_TOUCH_SCAN_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SCAN_DONE_INT_ST    (BIT(0))
+#define RTC_TOUCH_SCAN_DONE_INT_ST_M  (RTC_TOUCH_SCAN_DONE_INT_ST_V << RTC_TOUCH_SCAN_DONE_INT_ST_S)
+#define RTC_TOUCH_SCAN_DONE_INT_ST_V  0x00000001U
+#define RTC_TOUCH_SCAN_DONE_INT_ST_S  0
+/** RTC_TOUCH_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DONE_INT_ST    (BIT(1))
+#define RTC_TOUCH_DONE_INT_ST_M  (RTC_TOUCH_DONE_INT_ST_V << RTC_TOUCH_DONE_INT_ST_S)
+#define RTC_TOUCH_DONE_INT_ST_V  0x00000001U
+#define RTC_TOUCH_DONE_INT_ST_S  1
+/** RTC_TOUCH_ACTIVE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_ACTIVE_INT_ST    (BIT(2))
+#define RTC_TOUCH_ACTIVE_INT_ST_M  (RTC_TOUCH_ACTIVE_INT_ST_V << RTC_TOUCH_ACTIVE_INT_ST_S)
+#define RTC_TOUCH_ACTIVE_INT_ST_V  0x00000001U
+#define RTC_TOUCH_ACTIVE_INT_ST_S  2
+/** RTC_TOUCH_INACTIVE_INT_ST : RO; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_INACTIVE_INT_ST    (BIT(3))
+#define RTC_TOUCH_INACTIVE_INT_ST_M  (RTC_TOUCH_INACTIVE_INT_ST_V << RTC_TOUCH_INACTIVE_INT_ST_S)
+#define RTC_TOUCH_INACTIVE_INT_ST_V  0x00000001U
+#define RTC_TOUCH_INACTIVE_INT_ST_S  3
+/** RTC_TOUCH_TIMEOUT_INT_ST : RO; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_TIMEOUT_INT_ST    (BIT(4))
+#define RTC_TOUCH_TIMEOUT_INT_ST_M  (RTC_TOUCH_TIMEOUT_INT_ST_V << RTC_TOUCH_TIMEOUT_INT_ST_S)
+#define RTC_TOUCH_TIMEOUT_INT_ST_V  0x00000001U
+#define RTC_TOUCH_TIMEOUT_INT_ST_S  4
+/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST    (BIT(5))
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_M  (RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_S)
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_V  0x00000001U
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_S  5
+
+/** RTC_TOUCH_INT_ENA_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_INT_ENA_REG (DR_REG_LP_TOUCH_BASE + 0x8)
+/** RTC_TOUCH_SCAN_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SCAN_DONE_INT_ENA    (BIT(0))
+#define RTC_TOUCH_SCAN_DONE_INT_ENA_M  (RTC_TOUCH_SCAN_DONE_INT_ENA_V << RTC_TOUCH_SCAN_DONE_INT_ENA_S)
+#define RTC_TOUCH_SCAN_DONE_INT_ENA_V  0x00000001U
+#define RTC_TOUCH_SCAN_DONE_INT_ENA_S  0
+/** RTC_TOUCH_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DONE_INT_ENA    (BIT(1))
+#define RTC_TOUCH_DONE_INT_ENA_M  (RTC_TOUCH_DONE_INT_ENA_V << RTC_TOUCH_DONE_INT_ENA_S)
+#define RTC_TOUCH_DONE_INT_ENA_V  0x00000001U
+#define RTC_TOUCH_DONE_INT_ENA_S  1
+/** RTC_TOUCH_ACTIVE_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_ACTIVE_INT_ENA    (BIT(2))
+#define RTC_TOUCH_ACTIVE_INT_ENA_M  (RTC_TOUCH_ACTIVE_INT_ENA_V << RTC_TOUCH_ACTIVE_INT_ENA_S)
+#define RTC_TOUCH_ACTIVE_INT_ENA_V  0x00000001U
+#define RTC_TOUCH_ACTIVE_INT_ENA_S  2
+/** RTC_TOUCH_INACTIVE_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_INACTIVE_INT_ENA    (BIT(3))
+#define RTC_TOUCH_INACTIVE_INT_ENA_M  (RTC_TOUCH_INACTIVE_INT_ENA_V << RTC_TOUCH_INACTIVE_INT_ENA_S)
+#define RTC_TOUCH_INACTIVE_INT_ENA_V  0x00000001U
+#define RTC_TOUCH_INACTIVE_INT_ENA_S  3
+/** RTC_TOUCH_TIMEOUT_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_TIMEOUT_INT_ENA    (BIT(4))
+#define RTC_TOUCH_TIMEOUT_INT_ENA_M  (RTC_TOUCH_TIMEOUT_INT_ENA_V << RTC_TOUCH_TIMEOUT_INT_ENA_S)
+#define RTC_TOUCH_TIMEOUT_INT_ENA_V  0x00000001U
+#define RTC_TOUCH_TIMEOUT_INT_ENA_S  4
+/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA    (BIT(5))
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M  (RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S)
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V  0x00000001U
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S  5
+
+/** RTC_TOUCH_INT_CLR_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_INT_CLR_REG (DR_REG_LP_TOUCH_BASE + 0xc)
+/** RTC_TOUCH_SCAN_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SCAN_DONE_INT_CLR    (BIT(0))
+#define RTC_TOUCH_SCAN_DONE_INT_CLR_M  (RTC_TOUCH_SCAN_DONE_INT_CLR_V << RTC_TOUCH_SCAN_DONE_INT_CLR_S)
+#define RTC_TOUCH_SCAN_DONE_INT_CLR_V  0x00000001U
+#define RTC_TOUCH_SCAN_DONE_INT_CLR_S  0
+/** RTC_TOUCH_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DONE_INT_CLR    (BIT(1))
+#define RTC_TOUCH_DONE_INT_CLR_M  (RTC_TOUCH_DONE_INT_CLR_V << RTC_TOUCH_DONE_INT_CLR_S)
+#define RTC_TOUCH_DONE_INT_CLR_V  0x00000001U
+#define RTC_TOUCH_DONE_INT_CLR_S  1
+/** RTC_TOUCH_ACTIVE_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_ACTIVE_INT_CLR    (BIT(2))
+#define RTC_TOUCH_ACTIVE_INT_CLR_M  (RTC_TOUCH_ACTIVE_INT_CLR_V << RTC_TOUCH_ACTIVE_INT_CLR_S)
+#define RTC_TOUCH_ACTIVE_INT_CLR_V  0x00000001U
+#define RTC_TOUCH_ACTIVE_INT_CLR_S  2
+/** RTC_TOUCH_INACTIVE_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_INACTIVE_INT_CLR    (BIT(3))
+#define RTC_TOUCH_INACTIVE_INT_CLR_M  (RTC_TOUCH_INACTIVE_INT_CLR_V << RTC_TOUCH_INACTIVE_INT_CLR_S)
+#define RTC_TOUCH_INACTIVE_INT_CLR_V  0x00000001U
+#define RTC_TOUCH_INACTIVE_INT_CLR_S  3
+/** RTC_TOUCH_TIMEOUT_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_TIMEOUT_INT_CLR    (BIT(4))
+#define RTC_TOUCH_TIMEOUT_INT_CLR_M  (RTC_TOUCH_TIMEOUT_INT_CLR_V << RTC_TOUCH_TIMEOUT_INT_CLR_S)
+#define RTC_TOUCH_TIMEOUT_INT_CLR_V  0x00000001U
+#define RTC_TOUCH_TIMEOUT_INT_CLR_S  4
+/** RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR    (BIT(5))
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M  (RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S)
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V  0x00000001U
+#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S  5
+
+/** RTC_TOUCH_CHN_STATUS_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_CHN_STATUS_REG (DR_REG_LP_TOUCH_BASE + 0x10)
+/** RTC_TOUCH_PAD_ACTIVE : RO; bitpos: [14:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD_ACTIVE    0x00007FFFU
+#define RTC_TOUCH_PAD_ACTIVE_M  (RTC_TOUCH_PAD_ACTIVE_V << RTC_TOUCH_PAD_ACTIVE_S)
+#define RTC_TOUCH_PAD_ACTIVE_V  0x00007FFFU
+#define RTC_TOUCH_PAD_ACTIVE_S  0
+/** RTC_TOUCH_MEAS_DONE : RO; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_MEAS_DONE    (BIT(15))
+#define RTC_TOUCH_MEAS_DONE_M  (RTC_TOUCH_MEAS_DONE_V << RTC_TOUCH_MEAS_DONE_S)
+#define RTC_TOUCH_MEAS_DONE_V  0x00000001U
+#define RTC_TOUCH_MEAS_DONE_S  15
+/** RTC_TOUCH_SCAN_CURR : RO; bitpos: [19:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SCAN_CURR    0x0000000FU
+#define RTC_TOUCH_SCAN_CURR_M  (RTC_TOUCH_SCAN_CURR_V << RTC_TOUCH_SCAN_CURR_S)
+#define RTC_TOUCH_SCAN_CURR_V  0x0000000FU
+#define RTC_TOUCH_SCAN_CURR_S  16
+
+/** RTC_TOUCH_STATUS_0_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_0_REG (DR_REG_LP_TOUCH_BASE + 0x14)
+/** RTC_TOUCH_PAD0_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD0_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD0_DATA_M  (RTC_TOUCH_PAD0_DATA_V << RTC_TOUCH_PAD0_DATA_S)
+#define RTC_TOUCH_PAD0_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD0_DATA_S  0
+/** RTC_TOUCH_PAD0_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD0_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD0_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD0_DEBOUNCE_CNT_V << RTC_TOUCH_PAD0_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD0_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD0_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD0_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD0_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD0_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD0_NEG_NOISE_CNT_V << RTC_TOUCH_PAD0_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD0_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD0_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_1_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_1_REG (DR_REG_LP_TOUCH_BASE + 0x18)
+/** RTC_TOUCH_PAD1_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD1_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD1_DATA_M  (RTC_TOUCH_PAD1_DATA_V << RTC_TOUCH_PAD1_DATA_S)
+#define RTC_TOUCH_PAD1_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD1_DATA_S  0
+/** RTC_TOUCH_PAD1_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD1_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD1_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD1_DEBOUNCE_CNT_V << RTC_TOUCH_PAD1_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD1_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD1_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD1_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD1_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD1_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD1_NEG_NOISE_CNT_V << RTC_TOUCH_PAD1_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD1_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD1_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_2_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_2_REG (DR_REG_LP_TOUCH_BASE + 0x1c)
+/** RTC_TOUCH_PAD2_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD2_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD2_DATA_M  (RTC_TOUCH_PAD2_DATA_V << RTC_TOUCH_PAD2_DATA_S)
+#define RTC_TOUCH_PAD2_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD2_DATA_S  0
+/** RTC_TOUCH_PAD2_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD2_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD2_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD2_DEBOUNCE_CNT_V << RTC_TOUCH_PAD2_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD2_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD2_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD2_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD2_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD2_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD2_NEG_NOISE_CNT_V << RTC_TOUCH_PAD2_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD2_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD2_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_3_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_3_REG (DR_REG_LP_TOUCH_BASE + 0x20)
+/** RTC_TOUCH_PAD3_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD3_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD3_DATA_M  (RTC_TOUCH_PAD3_DATA_V << RTC_TOUCH_PAD3_DATA_S)
+#define RTC_TOUCH_PAD3_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD3_DATA_S  0
+/** RTC_TOUCH_PAD3_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD3_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD3_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD3_DEBOUNCE_CNT_V << RTC_TOUCH_PAD3_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD3_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD3_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD3_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD3_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD3_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD3_NEG_NOISE_CNT_V << RTC_TOUCH_PAD3_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD3_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD3_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_4_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_4_REG (DR_REG_LP_TOUCH_BASE + 0x24)
+/** RTC_TOUCH_PAD4_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD4_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD4_DATA_M  (RTC_TOUCH_PAD4_DATA_V << RTC_TOUCH_PAD4_DATA_S)
+#define RTC_TOUCH_PAD4_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD4_DATA_S  0
+/** RTC_TOUCH_PAD4_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD4_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD4_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD4_DEBOUNCE_CNT_V << RTC_TOUCH_PAD4_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD4_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD4_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD4_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD4_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD4_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD4_NEG_NOISE_CNT_V << RTC_TOUCH_PAD4_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD4_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD4_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_5_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_5_REG (DR_REG_LP_TOUCH_BASE + 0x28)
+/** RTC_TOUCH_PAD5_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD5_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD5_DATA_M  (RTC_TOUCH_PAD5_DATA_V << RTC_TOUCH_PAD5_DATA_S)
+#define RTC_TOUCH_PAD5_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD5_DATA_S  0
+/** RTC_TOUCH_PAD5_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD5_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD5_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD5_DEBOUNCE_CNT_V << RTC_TOUCH_PAD5_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD5_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD5_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD5_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD5_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD5_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD5_NEG_NOISE_CNT_V << RTC_TOUCH_PAD5_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD5_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD5_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_6_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_6_REG (DR_REG_LP_TOUCH_BASE + 0x2c)
+/** RTC_TOUCH_PAD6_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD6_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD6_DATA_M  (RTC_TOUCH_PAD6_DATA_V << RTC_TOUCH_PAD6_DATA_S)
+#define RTC_TOUCH_PAD6_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD6_DATA_S  0
+/** RTC_TOUCH_PAD6_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD6_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD6_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD6_DEBOUNCE_CNT_V << RTC_TOUCH_PAD6_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD6_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD6_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD6_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD6_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD6_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD6_NEG_NOISE_CNT_V << RTC_TOUCH_PAD6_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD6_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD6_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_7_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_7_REG (DR_REG_LP_TOUCH_BASE + 0x30)
+/** RTC_TOUCH_PAD7_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD7_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD7_DATA_M  (RTC_TOUCH_PAD7_DATA_V << RTC_TOUCH_PAD7_DATA_S)
+#define RTC_TOUCH_PAD7_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD7_DATA_S  0
+/** RTC_TOUCH_PAD7_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD7_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD7_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD7_DEBOUNCE_CNT_V << RTC_TOUCH_PAD7_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD7_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD7_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD7_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD7_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD7_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD7_NEG_NOISE_CNT_V << RTC_TOUCH_PAD7_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD7_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD7_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_8_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_8_REG (DR_REG_LP_TOUCH_BASE + 0x34)
+/** RTC_TOUCH_PAD8_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD8_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD8_DATA_M  (RTC_TOUCH_PAD8_DATA_V << RTC_TOUCH_PAD8_DATA_S)
+#define RTC_TOUCH_PAD8_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD8_DATA_S  0
+/** RTC_TOUCH_PAD8_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD8_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD8_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD8_DEBOUNCE_CNT_V << RTC_TOUCH_PAD8_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD8_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD8_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD8_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD8_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD8_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD8_NEG_NOISE_CNT_V << RTC_TOUCH_PAD8_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD8_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD8_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_9_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_9_REG (DR_REG_LP_TOUCH_BASE + 0x38)
+/** RTC_TOUCH_PAD9_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD9_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD9_DATA_M  (RTC_TOUCH_PAD9_DATA_V << RTC_TOUCH_PAD9_DATA_S)
+#define RTC_TOUCH_PAD9_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD9_DATA_S  0
+/** RTC_TOUCH_PAD9_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD9_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD9_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD9_DEBOUNCE_CNT_V << RTC_TOUCH_PAD9_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD9_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD9_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD9_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD9_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD9_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD9_NEG_NOISE_CNT_V << RTC_TOUCH_PAD9_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD9_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD9_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_10_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_10_REG (DR_REG_LP_TOUCH_BASE + 0x3c)
+/** RTC_TOUCH_PAD10_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD10_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD10_DATA_M  (RTC_TOUCH_PAD10_DATA_V << RTC_TOUCH_PAD10_DATA_S)
+#define RTC_TOUCH_PAD10_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD10_DATA_S  0
+/** RTC_TOUCH_PAD10_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD10_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD10_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD10_DEBOUNCE_CNT_V << RTC_TOUCH_PAD10_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD10_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD10_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD10_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD10_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD10_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD10_NEG_NOISE_CNT_V << RTC_TOUCH_PAD10_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD10_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD10_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_11_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_11_REG (DR_REG_LP_TOUCH_BASE + 0x40)
+/** RTC_TOUCH_PAD11_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD11_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD11_DATA_M  (RTC_TOUCH_PAD11_DATA_V << RTC_TOUCH_PAD11_DATA_S)
+#define RTC_TOUCH_PAD11_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD11_DATA_S  0
+/** RTC_TOUCH_PAD11_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD11_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD11_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD11_DEBOUNCE_CNT_V << RTC_TOUCH_PAD11_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD11_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD11_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD11_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD11_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD11_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD11_NEG_NOISE_CNT_V << RTC_TOUCH_PAD11_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD11_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD11_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_12_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_12_REG (DR_REG_LP_TOUCH_BASE + 0x44)
+/** RTC_TOUCH_PAD12_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD12_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD12_DATA_M  (RTC_TOUCH_PAD12_DATA_V << RTC_TOUCH_PAD12_DATA_S)
+#define RTC_TOUCH_PAD12_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD12_DATA_S  0
+/** RTC_TOUCH_PAD12_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD12_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD12_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD12_DEBOUNCE_CNT_V << RTC_TOUCH_PAD12_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD12_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD12_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD12_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD12_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD12_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD12_NEG_NOISE_CNT_V << RTC_TOUCH_PAD12_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD12_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD12_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_13_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_13_REG (DR_REG_LP_TOUCH_BASE + 0x48)
+/** RTC_TOUCH_PAD13_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD13_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD13_DATA_M  (RTC_TOUCH_PAD13_DATA_V << RTC_TOUCH_PAD13_DATA_S)
+#define RTC_TOUCH_PAD13_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD13_DATA_S  0
+/** RTC_TOUCH_PAD13_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD13_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD13_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD13_DEBOUNCE_CNT_V << RTC_TOUCH_PAD13_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD13_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD13_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD13_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD13_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD13_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD13_NEG_NOISE_CNT_V << RTC_TOUCH_PAD13_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD13_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD13_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_14_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_14_REG (DR_REG_LP_TOUCH_BASE + 0x4c)
+/** RTC_TOUCH_PAD14_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD14_DATA    0x0000FFFFU
+#define RTC_TOUCH_PAD14_DATA_M  (RTC_TOUCH_PAD14_DATA_V << RTC_TOUCH_PAD14_DATA_S)
+#define RTC_TOUCH_PAD14_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_PAD14_DATA_S  0
+/** RTC_TOUCH_PAD14_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD14_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_PAD14_DEBOUNCE_CNT_M  (RTC_TOUCH_PAD14_DEBOUNCE_CNT_V << RTC_TOUCH_PAD14_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_PAD14_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_PAD14_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_PAD14_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD14_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_PAD14_NEG_NOISE_CNT_M  (RTC_TOUCH_PAD14_NEG_NOISE_CNT_V << RTC_TOUCH_PAD14_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_PAD14_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_PAD14_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_15_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_15_REG (DR_REG_LP_TOUCH_BASE + 0x50)
+/** RTC_TOUCH_SLP_DATA : RO; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SLP_DATA    0x0000FFFFU
+#define RTC_TOUCH_SLP_DATA_M  (RTC_TOUCH_SLP_DATA_V << RTC_TOUCH_SLP_DATA_S)
+#define RTC_TOUCH_SLP_DATA_V  0x0000FFFFU
+#define RTC_TOUCH_SLP_DATA_S  0
+/** RTC_TOUCH_SLP_DEBOUNCE_CNT : RO; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SLP_DEBOUNCE_CNT    0x00000007U
+#define RTC_TOUCH_SLP_DEBOUNCE_CNT_M  (RTC_TOUCH_SLP_DEBOUNCE_CNT_V << RTC_TOUCH_SLP_DEBOUNCE_CNT_S)
+#define RTC_TOUCH_SLP_DEBOUNCE_CNT_V  0x00000007U
+#define RTC_TOUCH_SLP_DEBOUNCE_CNT_S  16
+/** RTC_TOUCH_SLP_NEG_NOISE_CNT : RO; bitpos: [22:19]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SLP_NEG_NOISE_CNT    0x0000000FU
+#define RTC_TOUCH_SLP_NEG_NOISE_CNT_M  (RTC_TOUCH_SLP_NEG_NOISE_CNT_V << RTC_TOUCH_SLP_NEG_NOISE_CNT_S)
+#define RTC_TOUCH_SLP_NEG_NOISE_CNT_V  0x0000000FU
+#define RTC_TOUCH_SLP_NEG_NOISE_CNT_S  19
+
+/** RTC_TOUCH_STATUS_16_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_16_REG (DR_REG_LP_TOUCH_BASE + 0x54)
+/** RTC_TOUCH_APPROACH_PAD2_CNT : RO; bitpos: [7:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_PAD2_CNT    0x000000FFU
+#define RTC_TOUCH_APPROACH_PAD2_CNT_M  (RTC_TOUCH_APPROACH_PAD2_CNT_V << RTC_TOUCH_APPROACH_PAD2_CNT_S)
+#define RTC_TOUCH_APPROACH_PAD2_CNT_V  0x000000FFU
+#define RTC_TOUCH_APPROACH_PAD2_CNT_S  0
+/** RTC_TOUCH_APPROACH_PAD1_CNT : RO; bitpos: [15:8]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_PAD1_CNT    0x000000FFU
+#define RTC_TOUCH_APPROACH_PAD1_CNT_M  (RTC_TOUCH_APPROACH_PAD1_CNT_V << RTC_TOUCH_APPROACH_PAD1_CNT_S)
+#define RTC_TOUCH_APPROACH_PAD1_CNT_V  0x000000FFU
+#define RTC_TOUCH_APPROACH_PAD1_CNT_S  8
+/** RTC_TOUCH_APPROACH_PAD0_CNT : RO; bitpos: [23:16]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_APPROACH_PAD0_CNT    0x000000FFU
+#define RTC_TOUCH_APPROACH_PAD0_CNT_M  (RTC_TOUCH_APPROACH_PAD0_CNT_V << RTC_TOUCH_APPROACH_PAD0_CNT_S)
+#define RTC_TOUCH_APPROACH_PAD0_CNT_V  0x000000FFU
+#define RTC_TOUCH_APPROACH_PAD0_CNT_S  16
+/** RTC_TOUCH_SLP_APPROACH_CNT : RO; bitpos: [31:24]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_SLP_APPROACH_CNT    0x000000FFU
+#define RTC_TOUCH_SLP_APPROACH_CNT_M  (RTC_TOUCH_SLP_APPROACH_CNT_V << RTC_TOUCH_SLP_APPROACH_CNT_S)
+#define RTC_TOUCH_SLP_APPROACH_CNT_V  0x000000FFU
+#define RTC_TOUCH_SLP_APPROACH_CNT_S  24
+
+/** RTC_TOUCH_STATUS_17_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_STATUS_17_REG (DR_REG_LP_TOUCH_BASE + 0x58)
+/** RTC_TOUCH_DCAP_LPF : RO; bitpos: [6:0]; default: 0;
+ *  Reserved
+ */
+#define RTC_TOUCH_DCAP_LPF    0x0000007FU
+#define RTC_TOUCH_DCAP_LPF_M  (RTC_TOUCH_DCAP_LPF_V << RTC_TOUCH_DCAP_LPF_S)
+#define RTC_TOUCH_DCAP_LPF_V  0x0000007FU
+#define RTC_TOUCH_DCAP_LPF_S  0
+/** RTC_TOUCH_DRES_LPF : RO; bitpos: [8:7]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DRES_LPF    0x00000003U
+#define RTC_TOUCH_DRES_LPF_M  (RTC_TOUCH_DRES_LPF_V << RTC_TOUCH_DRES_LPF_S)
+#define RTC_TOUCH_DRES_LPF_V  0x00000003U
+#define RTC_TOUCH_DRES_LPF_S  7
+/** RTC_TOUCH_DRV_LS : RO; bitpos: [12:9]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DRV_LS    0x0000000FU
+#define RTC_TOUCH_DRV_LS_M  (RTC_TOUCH_DRV_LS_V << RTC_TOUCH_DRV_LS_S)
+#define RTC_TOUCH_DRV_LS_V  0x0000000FU
+#define RTC_TOUCH_DRV_LS_S  9
+/** RTC_TOUCH_DRV_HS : RO; bitpos: [17:13]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DRV_HS    0x0000001FU
+#define RTC_TOUCH_DRV_HS_M  (RTC_TOUCH_DRV_HS_V << RTC_TOUCH_DRV_HS_S)
+#define RTC_TOUCH_DRV_HS_V  0x0000001FU
+#define RTC_TOUCH_DRV_HS_S  13
+/** RTC_TOUCH_DBIAS : RO; bitpos: [22:18]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_DBIAS    0x0000001FU
+#define RTC_TOUCH_DBIAS_M  (RTC_TOUCH_DBIAS_V << RTC_TOUCH_DBIAS_S)
+#define RTC_TOUCH_DBIAS_V  0x0000001FU
+#define RTC_TOUCH_DBIAS_S  18
+/** RTC_TOUCH_FREQ_SCAN_CNT : RO; bitpos: [24:23]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_FREQ_SCAN_CNT    0x00000003U
+#define RTC_TOUCH_FREQ_SCAN_CNT_M  (RTC_TOUCH_FREQ_SCAN_CNT_V << RTC_TOUCH_FREQ_SCAN_CNT_S)
+#define RTC_TOUCH_FREQ_SCAN_CNT_V  0x00000003U
+#define RTC_TOUCH_FREQ_SCAN_CNT_S  23
+
+/** RTC_TOUCH_CHN_TMP_STATUS_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_CHN_TMP_STATUS_REG (DR_REG_LP_TOUCH_BASE + 0x5c)
+/** RTC_TOUCH_PAD_INACTIVE_STATUS : RO; bitpos: [14:0]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD_INACTIVE_STATUS    0x00007FFFU
+#define RTC_TOUCH_PAD_INACTIVE_STATUS_M  (RTC_TOUCH_PAD_INACTIVE_STATUS_V << RTC_TOUCH_PAD_INACTIVE_STATUS_S)
+#define RTC_TOUCH_PAD_INACTIVE_STATUS_V  0x00007FFFU
+#define RTC_TOUCH_PAD_INACTIVE_STATUS_S  0
+/** RTC_TOUCH_PAD_ACTIVE_STATUS : RO; bitpos: [29:15]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_PAD_ACTIVE_STATUS    0x00007FFFU
+#define RTC_TOUCH_PAD_ACTIVE_STATUS_M  (RTC_TOUCH_PAD_ACTIVE_STATUS_V << RTC_TOUCH_PAD_ACTIVE_STATUS_S)
+#define RTC_TOUCH_PAD_ACTIVE_STATUS_V  0x00007FFFU
+#define RTC_TOUCH_PAD_ACTIVE_STATUS_S  15
+
+/** RTC_TOUCH_DATE_REG register
+ *  need_des
+ */
+#define RTC_TOUCH_DATE_REG (DR_REG_LP_TOUCH_BASE + 0x100)
+/** RTC_TOUCH_DATE : R/W; bitpos: [27:0]; default: 2294548;
+ *  need_des
+ */
+#define RTC_TOUCH_DATE    0x0FFFFFFFU
+#define RTC_TOUCH_DATE_M  (RTC_TOUCH_DATE_V << RTC_TOUCH_DATE_S)
+#define RTC_TOUCH_DATE_V  0x0FFFFFFFU
+#define RTC_TOUCH_DATE_S  0
+/** RTC_TOUCH_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RTC_TOUCH_CLK_EN    (BIT(31))
+#define RTC_TOUCH_CLK_EN_M  (RTC_TOUCH_CLK_EN_V << RTC_TOUCH_CLK_EN_S)
+#define RTC_TOUCH_CLK_EN_V  0x00000001U
+#define RTC_TOUCH_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/touch_struct.h

@@ -0,0 +1,339 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13423
+
+/** Group: configure_register */
+/** Type of int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** scan_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t scan_done_int_raw:1;
+        /** done_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t done_int_raw:1;
+        /** active_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t active_int_raw:1;
+        /** inactive_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t inactive_int_raw:1;
+        /** timeout_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t timeout_int_raw:1;
+        /** approach_loop_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_loop_done_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtc_touch_int_raw_reg_t;
+
+/** Type of int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** scan_done_int_st : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t scan_done_int_st:1;
+        /** done_int_st : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t done_int_st:1;
+        /** active_int_st : RO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t active_int_st:1;
+        /** inactive_int_st : RO; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t inactive_int_st:1;
+        /** timeout_int_st : RO; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t timeout_int_st:1;
+        /** approach_loop_done_int_st : RO; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_loop_done_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtc_touch_int_st_reg_t;
+
+/** Type of int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** scan_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t scan_done_int_ena:1;
+        /** done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t done_int_ena:1;
+        /** active_int_ena : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t active_int_ena:1;
+        /** inactive_int_ena : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t inactive_int_ena:1;
+        /** timeout_int_ena : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t timeout_int_ena:1;
+        /** approach_loop_done_int_ena : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_loop_done_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtc_touch_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** scan_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t scan_done_int_clr:1;
+        /** done_int_clr : WT; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t done_int_clr:1;
+        /** active_int_clr : WT; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t active_int_clr:1;
+        /** inactive_int_clr : WT; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t inactive_int_clr:1;
+        /** timeout_int_clr : WT; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t timeout_int_clr:1;
+        /** approach_loop_done_int_clr : WT; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_loop_done_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtc_touch_int_clr_reg_t;
+
+/** Type of chn_status register
+ *  Latched channel status
+ */
+typedef union {
+    struct {
+        /** pad_active : RO; bitpos: [14:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad_active:15;
+        /** meas_done : RO; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t meas_done:1;
+        /** scan_curr : RO; bitpos: [19:16]; default: 0;
+         *  need_des
+         */
+        uint32_t scan_curr:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} rtc_touch_chn_status_reg_t;
+
+/** Type of chn_data register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** pad_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad_data:16;
+        /** pad_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t pad_debounce_cnt:3;
+        /** pad_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t pad_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_chn_data_reg_t;
+
+/** Type of slp_ch_data register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** slp_data : RO; bitpos: [15:0]; default: 0;
+         *  need_des
+         */
+        uint32_t slp_data:16;
+        /** slp_debounce_cnt : RO; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t slp_debounce_cnt:3;
+        /** slp_neg_noise_cnt : RO; bitpos: [22:19]; default: 0;
+         *  need_des
+         */
+        uint32_t slp_neg_noise_cnt:4;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_touch_slp_ch_data_reg_t;
+
+/** Type of aprch_ch_data register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** approach_pad2_cnt : RO; bitpos: [7:0]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_pad2_cnt:8;
+        /** approach_pad1_cnt : RO; bitpos: [15:8]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_pad1_cnt:8;
+        /** approach_pad0_cnt : RO; bitpos: [23:16]; default: 0;
+         *  need_des
+         */
+        uint32_t approach_pad0_cnt:8;
+        /** slp_approach_cnt : RO; bitpos: [31:24]; default: 0;
+         *  need_des
+         */
+        uint32_t slp_approach_cnt:8;
+    };
+    uint32_t val;
+} rtc_touch_aprch_ch_data_reg_t;
+
+/** Type of config register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** dcap_lpf : RO; bitpos: [6:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t dcap_lpf:7;
+        /** dres_lpf : RO; bitpos: [8:7]; default: 0;
+         *  need_des
+         */
+        uint32_t dres_lpf:2;
+        /** drv_ls : RO; bitpos: [12:9]; default: 0;
+         *  need_des
+         */
+        uint32_t drv_ls:4;
+        /** drv_hs : RO; bitpos: [17:13]; default: 0;
+         *  need_des
+         */
+        uint32_t drv_hs:5;
+        /** dbias : RO; bitpos: [22:18]; default: 0;
+         *  need_des
+         */
+        uint32_t dbias:5;
+        /** freq_scan_cnt : RO; bitpos: [24:23]; default: 0;
+         *  need_des
+         */
+        uint32_t freq_scan_cnt:2;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} rtc_touch_sample_status_reg_t;
+
+/** Type of chn_tmp_status register
+ *  Realtime channel status
+ */
+typedef union {
+    struct {
+        /** pad_inactive_status : RO; bitpos: [14:0]; default: 0;
+         *  need_des
+         */
+        uint32_t pad_inactive_status:15;
+        /** pad_active_status : RO; bitpos: [29:15]; default: 0;
+         *  need_des
+         */
+        uint32_t pad_active_status:15;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} rtc_touch_chn_tmp_status_reg_t;
+
+
+/** Group: Version */
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 2294548;
+         *  need_des
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:3;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} rtc_touch_date_reg_t;
+
+
+typedef struct {
+    volatile rtc_touch_int_raw_reg_t int_raw;
+    volatile rtc_touch_int_st_reg_t int_st;
+    volatile rtc_touch_int_ena_reg_t int_ena;
+    volatile rtc_touch_int_clr_reg_t int_clr;
+    volatile rtc_touch_chn_status_reg_t chn_status;
+    volatile rtc_touch_chn_data_reg_t chn_data[15];
+    volatile rtc_touch_slp_ch_data_reg_t slp_ch_data;
+    volatile rtc_touch_aprch_ch_data_reg_t aprch_ch_data;
+    volatile rtc_touch_sample_status_reg_t sample_status;
+    volatile rtc_touch_chn_tmp_status_reg_t chn_tmp_status;
+    uint32_t reserved_060[40];
+    volatile rtc_touch_date_reg_t date;
+} rtc_touch_dev_t;
+
+extern rtc_touch_dev_t LP_TOUCH;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(rtc_touch_dev_t) == 0x104, "Invalid size of rtc_touch_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/trace_reg.h

@@ -0,0 +1,503 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TRACE_MEM_START_ADDR_REG register
+ *  mem start addr
+ */
+#define TRACE_MEM_START_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x0)
+/** TRACE_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  The start address of trace memory
+ */
+#define TRACE_MEM_START_ADDR    0xFFFFFFFFU
+#define TRACE_MEM_START_ADDR_M  (TRACE_MEM_START_ADDR_V << TRACE_MEM_START_ADDR_S)
+#define TRACE_MEM_START_ADDR_V  0xFFFFFFFFU
+#define TRACE_MEM_START_ADDR_S  0
+
+/** TRACE_MEM_END_ADDR_REG register
+ *  mem end addr
+ */
+#define TRACE_MEM_END_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x4)
+/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
+ *  The end address of trace memory
+ */
+#define TRACE_MEM_END_ADDR    0xFFFFFFFFU
+#define TRACE_MEM_END_ADDR_M  (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S)
+#define TRACE_MEM_END_ADDR_V  0xFFFFFFFFU
+#define TRACE_MEM_END_ADDR_S  0
+
+/** TRACE_MEM_CURRENT_ADDR_REG register
+ *  mem current addr
+ */
+#define TRACE_MEM_CURRENT_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x8)
+/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  current_mem_addr,indicate that next writing addr
+ */
+#define TRACE_MEM_CURRENT_ADDR    0xFFFFFFFFU
+#define TRACE_MEM_CURRENT_ADDR_M  (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S)
+#define TRACE_MEM_CURRENT_ADDR_V  0xFFFFFFFFU
+#define TRACE_MEM_CURRENT_ADDR_S  0
+
+/** TRACE_MEM_ADDR_UPDATE_REG register
+ *  mem addr update
+ */
+#define TRACE_MEM_ADDR_UPDATE_REG(i) (DR_REG_TRACE_BASE(i) + 0xc)
+/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
+ *  when set, the  will
+ *  \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to
+ *  \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.
+ */
+#define TRACE_MEM_CURRENT_ADDR_UPDATE    (BIT(0))
+#define TRACE_MEM_CURRENT_ADDR_UPDATE_M  (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S)
+#define TRACE_MEM_CURRENT_ADDR_UPDATE_V  0x00000001U
+#define TRACE_MEM_CURRENT_ADDR_UPDATE_S  0
+
+/** TRACE_FIFO_STATUS_REG register
+ *  fifo status register
+ */
+#define TRACE_FIFO_STATUS_REG(i) (DR_REG_TRACE_BASE(i) + 0x10)
+/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1;
+ *  Represent whether the fifo is empty.
+ *  1: empty
+ *  0: not empty
+ */
+#define TRACE_FIFO_EMPTY    (BIT(0))
+#define TRACE_FIFO_EMPTY_M  (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S)
+#define TRACE_FIFO_EMPTY_V  0x00000001U
+#define TRACE_FIFO_EMPTY_S  0
+/** TRACE_WORK_STATUS : RO; bitpos: [2:1]; default: 0;
+ *  Represent trace work status:
+ *  0: idle state
+ *  1: working state
+ *  2: wait state due to hart halted or havereset
+ *  3: lost state
+ */
+#define TRACE_WORK_STATUS    0x00000003U
+#define TRACE_WORK_STATUS_M  (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S)
+#define TRACE_WORK_STATUS_V  0x00000003U
+#define TRACE_WORK_STATUS_S  1
+
+/** TRACE_INTR_ENA_REG register
+ *  interrupt enable register
+ */
+#define TRACE_INTR_ENA_REG(i) (DR_REG_TRACE_BASE(i) + 0x14)
+/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0;
+ *  Set 1 enable fifo_overflow interrupt
+ */
+#define TRACE_FIFO_OVERFLOW_INTR_ENA    (BIT(0))
+#define TRACE_FIFO_OVERFLOW_INTR_ENA_M  (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S)
+#define TRACE_FIFO_OVERFLOW_INTR_ENA_V  0x00000001U
+#define TRACE_FIFO_OVERFLOW_INTR_ENA_S  0
+/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Set 1 enable mem_full interrupt
+ */
+#define TRACE_MEM_FULL_INTR_ENA    (BIT(1))
+#define TRACE_MEM_FULL_INTR_ENA_M  (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S)
+#define TRACE_MEM_FULL_INTR_ENA_V  0x00000001U
+#define TRACE_MEM_FULL_INTR_ENA_S  1
+
+/** TRACE_INTR_RAW_REG register
+ *  interrupt status register
+ */
+#define TRACE_INTR_RAW_REG(i) (DR_REG_TRACE_BASE(i) + 0x18)
+/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0;
+ *  fifo_overflow interrupt status
+ */
+#define TRACE_FIFO_OVERFLOW_INTR_RAW    (BIT(0))
+#define TRACE_FIFO_OVERFLOW_INTR_RAW_M  (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S)
+#define TRACE_FIFO_OVERFLOW_INTR_RAW_V  0x00000001U
+#define TRACE_FIFO_OVERFLOW_INTR_RAW_S  0
+/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0;
+ *  mem_full interrupt status
+ */
+#define TRACE_MEM_FULL_INTR_RAW    (BIT(1))
+#define TRACE_MEM_FULL_INTR_RAW_M  (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S)
+#define TRACE_MEM_FULL_INTR_RAW_V  0x00000001U
+#define TRACE_MEM_FULL_INTR_RAW_S  1
+
+/** TRACE_INTR_CLR_REG register
+ *  interrupt clear register
+ */
+#define TRACE_INTR_CLR_REG(i) (DR_REG_TRACE_BASE(i) + 0x1c)
+/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0;
+ *  Set 1 clear fifo overflow interrupt
+ */
+#define TRACE_FIFO_OVERFLOW_INTR_CLR    (BIT(0))
+#define TRACE_FIFO_OVERFLOW_INTR_CLR_M  (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S)
+#define TRACE_FIFO_OVERFLOW_INTR_CLR_V  0x00000001U
+#define TRACE_FIFO_OVERFLOW_INTR_CLR_S  0
+/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0;
+ *  Set 1 clear mem full interrupt
+ */
+#define TRACE_MEM_FULL_INTR_CLR    (BIT(1))
+#define TRACE_MEM_FULL_INTR_CLR_M  (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S)
+#define TRACE_MEM_FULL_INTR_CLR_V  0x00000001U
+#define TRACE_MEM_FULL_INTR_CLR_S  1
+
+/** TRACE_TRIGGER_REG register
+ *  trigger register
+ */
+#define TRACE_TRIGGER_REG(i) (DR_REG_TRACE_BASE(i) + 0x20)
+/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0;
+ *  Configure whether or not start trace.
+ *  1: start trace
+ *  0: invalid
+ */
+#define TRACE_TRIGGER_ON    (BIT(0))
+#define TRACE_TRIGGER_ON_M  (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S)
+#define TRACE_TRIGGER_ON_V  0x00000001U
+#define TRACE_TRIGGER_ON_S  0
+/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0;
+ *  Configure whether or not stop trace.
+ *  1: stop trace
+ *  0: invalid
+ */
+#define TRACE_TRIGGER_OFF    (BIT(1))
+#define TRACE_TRIGGER_OFF_M  (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S)
+#define TRACE_TRIGGER_OFF_V  0x00000001U
+#define TRACE_TRIGGER_OFF_S  1
+/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1;
+ *  Configure memory loop mode.
+ *  1: trace will loop write trace_mem.
+ *  0: when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr
+ */
+#define TRACE_MEM_LOOP    (BIT(2))
+#define TRACE_MEM_LOOP_M  (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S)
+#define TRACE_MEM_LOOP_V  0x00000001U
+#define TRACE_MEM_LOOP_S  2
+/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1;
+ *  Configure whether or not enable auto-restart.
+ *  1: enable
+ *  0: disable
+ */
+#define TRACE_RESTART_ENA    (BIT(3))
+#define TRACE_RESTART_ENA_M  (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S)
+#define TRACE_RESTART_ENA_V  0x00000001U
+#define TRACE_RESTART_ENA_S  3
+
+/** TRACE_CONFIG_REG register
+ *  trace configuration register
+ */
+#define TRACE_CONFIG_REG(i) (DR_REG_TRACE_BASE(i) + 0x24)
+/** TRACE_DM_TRIGGER_ENA : R/W; bitpos: [0]; default: 0;
+ *  Configure whether or not enable cpu trigger action.
+ *  1: enable
+ *  0:disable
+ */
+#define TRACE_DM_TRIGGER_ENA    (BIT(0))
+#define TRACE_DM_TRIGGER_ENA_M  (TRACE_DM_TRIGGER_ENA_V << TRACE_DM_TRIGGER_ENA_S)
+#define TRACE_DM_TRIGGER_ENA_V  0x00000001U
+#define TRACE_DM_TRIGGER_ENA_S  0
+/** TRACE_RESET_ENA : R/W; bitpos: [1]; default: 0;
+ *  Configure whether or not enable trace cpu haverest, when enabled, if cpu have
+ *  reset, the encoder will output a packet to report the address of the last
+ *  instruction, and upon reset deassertion, the encoder start again.
+ *  1: enabled
+ *  0: disabled
+ */
+#define TRACE_RESET_ENA    (BIT(1))
+#define TRACE_RESET_ENA_M  (TRACE_RESET_ENA_V << TRACE_RESET_ENA_S)
+#define TRACE_RESET_ENA_V  0x00000001U
+#define TRACE_RESET_ENA_S  1
+/** TRACE_HALT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Configure whether or not enable trace cpu is halted, when enabled, if the cpu
+ *  halted, the encoder will output a packet to report the address of the last
+ *  instruction, and upon halted deassertion, the encoder start again.When disabled,
+ *  encoder will not report the last address before halted and first address after
+ *  halted, cpu halted information will not be tracked.
+ *  1: enabled
+ *  0: disabled
+ */
+#define TRACE_HALT_ENA    (BIT(2))
+#define TRACE_HALT_ENA_M  (TRACE_HALT_ENA_V << TRACE_HALT_ENA_S)
+#define TRACE_HALT_ENA_V  0x00000001U
+#define TRACE_HALT_ENA_S  2
+/** TRACE_STALL_ENA : R/W; bitpos: [3]; default: 0;
+ *  Configure whether or not enable stall cpu. When enabled, when the fifo almost full,
+ *  the cpu will be stalled until the packets is able to write to fifo.
+ *  1: enabled.
+ *  0: disabled
+ */
+#define TRACE_STALL_ENA    (BIT(3))
+#define TRACE_STALL_ENA_M  (TRACE_STALL_ENA_V << TRACE_STALL_ENA_S)
+#define TRACE_STALL_ENA_V  0x00000001U
+#define TRACE_STALL_ENA_S  3
+/** TRACE_FULL_ADDRESS : R/W; bitpos: [4]; default: 0;
+ *  Configure whether or not enable full-address mode.
+ *  1: full address mode.
+ *  0: delta address mode
+ */
+#define TRACE_FULL_ADDRESS    (BIT(4))
+#define TRACE_FULL_ADDRESS_M  (TRACE_FULL_ADDRESS_V << TRACE_FULL_ADDRESS_S)
+#define TRACE_FULL_ADDRESS_V  0x00000001U
+#define TRACE_FULL_ADDRESS_S  4
+/** TRACE_IMPLICIT_EXCEPT : R/W; bitpos: [5]; default: 0;
+ *  Configure whether or not enable implicit exception mode. When enabled,, do not sent
+ *  exception address, only exception cause in exception packets.
+ *  1: enabled
+ *  0: disabled
+ */
+#define TRACE_IMPLICIT_EXCEPT    (BIT(5))
+#define TRACE_IMPLICIT_EXCEPT_M  (TRACE_IMPLICIT_EXCEPT_V << TRACE_IMPLICIT_EXCEPT_S)
+#define TRACE_IMPLICIT_EXCEPT_V  0x00000001U
+#define TRACE_IMPLICIT_EXCEPT_S  5
+
+/** TRACE_FILTER_CONTROL_REG register
+ *  filter control register
+ */
+#define TRACE_FILTER_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x28)
+/** TRACE_FILTER_EN : R/W; bitpos: [0]; default: 0;
+ *  Configure whether or not enable filter unit.
+ *  1: enable filter.
+ *  0: always match
+ */
+#define TRACE_FILTER_EN    (BIT(0))
+#define TRACE_FILTER_EN_M  (TRACE_FILTER_EN_V << TRACE_FILTER_EN_S)
+#define TRACE_FILTER_EN_V  0x00000001U
+#define TRACE_FILTER_EN_S  0
+/** TRACE_MATCH_COMP : R/W; bitpos: [1]; default: 0;
+ *  when set, the comparator must be high in order for the filter to match
+ */
+#define TRACE_MATCH_COMP    (BIT(1))
+#define TRACE_MATCH_COMP_M  (TRACE_MATCH_COMP_V << TRACE_MATCH_COMP_S)
+#define TRACE_MATCH_COMP_V  0x00000001U
+#define TRACE_MATCH_COMP_S  1
+/** TRACE_MATCH_PRIVILEGE : R/W; bitpos: [2]; default: 0;
+ *  when set, match privilege levels specified by
+ *  \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}.
+ */
+#define TRACE_MATCH_PRIVILEGE    (BIT(2))
+#define TRACE_MATCH_PRIVILEGE_M  (TRACE_MATCH_PRIVILEGE_V << TRACE_MATCH_PRIVILEGE_S)
+#define TRACE_MATCH_PRIVILEGE_V  0x00000001U
+#define TRACE_MATCH_PRIVILEGE_S  2
+/** TRACE_MATCH_ECAUSE : R/W; bitpos: [3]; default: 0;
+ *  when set, start matching from exception cause codes specified by
+ *  \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop
+ *  matching upon return from the 1st matching exception.
+ */
+#define TRACE_MATCH_ECAUSE    (BIT(3))
+#define TRACE_MATCH_ECAUSE_M  (TRACE_MATCH_ECAUSE_V << TRACE_MATCH_ECAUSE_S)
+#define TRACE_MATCH_ECAUSE_V  0x00000001U
+#define TRACE_MATCH_ECAUSE_S  3
+/** TRACE_MATCH_INTERRUPT : R/W; bitpos: [4]; default: 0;
+ *  when set, start matching from a trap with the interrupt level codes specified by
+ *  \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and
+ *  stop matching upon return from the 1st matching trap.
+ */
+#define TRACE_MATCH_INTERRUPT    (BIT(4))
+#define TRACE_MATCH_INTERRUPT_M  (TRACE_MATCH_INTERRUPT_V << TRACE_MATCH_INTERRUPT_S)
+#define TRACE_MATCH_INTERRUPT_V  0x00000001U
+#define TRACE_MATCH_INTERRUPT_S  4
+
+/** TRACE_FILTER_MATCH_CONTROL_REG register
+ *  filter match control register
+ */
+#define TRACE_FILTER_MATCH_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x2c)
+/** TRACE_MATCH_CHOICE_PRIVILEGE : R/W; bitpos: [0]; default: 0;
+ *  Select match which privilege level when
+ *  \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set.
+ *  1: machine mode.
+ *  0: user mode
+ */
+#define TRACE_MATCH_CHOICE_PRIVILEGE    (BIT(0))
+#define TRACE_MATCH_CHOICE_PRIVILEGE_M  (TRACE_MATCH_CHOICE_PRIVILEGE_V << TRACE_MATCH_CHOICE_PRIVILEGE_S)
+#define TRACE_MATCH_CHOICE_PRIVILEGE_V  0x00000001U
+#define TRACE_MATCH_CHOICE_PRIVILEGE_S  0
+/** TRACE_MATCH_VALUE_INTERRUPT : R/W; bitpos: [1]; default: 0;
+ *  Select which match which itype when
+ *  \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set.
+ *  1: match itype of 2.
+ *  0: match itype or 1.
+ */
+#define TRACE_MATCH_VALUE_INTERRUPT    (BIT(1))
+#define TRACE_MATCH_VALUE_INTERRUPT_M  (TRACE_MATCH_VALUE_INTERRUPT_V << TRACE_MATCH_VALUE_INTERRUPT_S)
+#define TRACE_MATCH_VALUE_INTERRUPT_V  0x00000001U
+#define TRACE_MATCH_VALUE_INTERRUPT_S  1
+/** TRACE_MATCH_CHOICE_ECAUSE : R/W; bitpos: [7:2]; default: 0;
+ *  specified which ecause matched.
+ */
+#define TRACE_MATCH_CHOICE_ECAUSE    0x0000003FU
+#define TRACE_MATCH_CHOICE_ECAUSE_M  (TRACE_MATCH_CHOICE_ECAUSE_V << TRACE_MATCH_CHOICE_ECAUSE_S)
+#define TRACE_MATCH_CHOICE_ECAUSE_V  0x0000003FU
+#define TRACE_MATCH_CHOICE_ECAUSE_S  2
+
+/** TRACE_FILTER_COMPARATOR_CONTROL_REG register
+ *  filter comparator match control register
+ */
+#define TRACE_FILTER_COMPARATOR_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x30)
+/** TRACE_P_INPUT : R/W; bitpos: [0]; default: 0;
+ *  Determines which input to compare against the primary comparator,
+ *  0: iaddr,
+ *  1: tval.
+ */
+#define TRACE_P_INPUT    (BIT(0))
+#define TRACE_P_INPUT_M  (TRACE_P_INPUT_V << TRACE_P_INPUT_S)
+#define TRACE_P_INPUT_V  0x00000001U
+#define TRACE_P_INPUT_S  0
+/** TRACE_P_FUNCTION : R/W; bitpos: [4:2]; default: 0;
+ *  Select the primary comparator function.
+ *  0: equal,
+ *  1: not equal,
+ *  2: less than,
+ *  3: less than or equal,
+ *  4: greater than,
+ *  5: greater than or equal,
+ *  other: always match
+ */
+#define TRACE_P_FUNCTION    0x00000007U
+#define TRACE_P_FUNCTION_M  (TRACE_P_FUNCTION_V << TRACE_P_FUNCTION_S)
+#define TRACE_P_FUNCTION_V  0x00000007U
+#define TRACE_P_FUNCTION_S  2
+/** TRACE_P_NOTIFY : R/W; bitpos: [5]; default: 0;
+ *  Generate a trace packet explicitly reporting the address that cause the primary
+ *  match
+ */
+#define TRACE_P_NOTIFY    (BIT(5))
+#define TRACE_P_NOTIFY_M  (TRACE_P_NOTIFY_V << TRACE_P_NOTIFY_S)
+#define TRACE_P_NOTIFY_V  0x00000001U
+#define TRACE_P_NOTIFY_S  5
+/** TRACE_S_INPUT : R/W; bitpos: [8]; default: 0;
+ *  Determines which input to compare against the secondary comparator,
+ *  0: iaddr,
+ *  1: tval.
+ */
+#define TRACE_S_INPUT    (BIT(8))
+#define TRACE_S_INPUT_M  (TRACE_S_INPUT_V << TRACE_S_INPUT_S)
+#define TRACE_S_INPUT_V  0x00000001U
+#define TRACE_S_INPUT_S  8
+/** TRACE_S_FUNCTION : R/W; bitpos: [12:10]; default: 0;
+ *  Select the secondary comparator function.
+ *  0: equal,
+ *  1: not equal,
+ *  2: less than,
+ *  3: less than or equal,
+ *  4: greater than,
+ *  5: greater than or equal,
+ *  other: always match
+ */
+#define TRACE_S_FUNCTION    0x00000007U
+#define TRACE_S_FUNCTION_M  (TRACE_S_FUNCTION_V << TRACE_S_FUNCTION_S)
+#define TRACE_S_FUNCTION_V  0x00000007U
+#define TRACE_S_FUNCTION_S  10
+/** TRACE_S_NOTIFY : R/W; bitpos: [13]; default: 0;
+ *  Generate a trace packet explicitly reporting the address that cause the secondary
+ *  match
+ */
+#define TRACE_S_NOTIFY    (BIT(13))
+#define TRACE_S_NOTIFY_M  (TRACE_S_NOTIFY_V << TRACE_S_NOTIFY_S)
+#define TRACE_S_NOTIFY_V  0x00000001U
+#define TRACE_S_NOTIFY_S  13
+/** TRACE_MATCH_MODE : R/W; bitpos: [17:16]; default: 0;
+ *  0: only primary matches,
+ *  1: primary and secondary comparator both matches(P\&\&S),
+ *  2:either primary or secondary comparator matches !(P\&\&S),
+ *  3: set when primary matches and continue to match until after secondary comparator
+ *  matches
+ */
+#define TRACE_MATCH_MODE    0x00000003U
+#define TRACE_MATCH_MODE_M  (TRACE_MATCH_MODE_V << TRACE_MATCH_MODE_S)
+#define TRACE_MATCH_MODE_V  0x00000003U
+#define TRACE_MATCH_MODE_S  16
+
+/** TRACE_FILTER_P_COMPARATOR_MATCH_REG register
+ *  primary comparator match value
+ */
+#define TRACE_FILTER_P_COMPARATOR_MATCH_REG(i) (DR_REG_TRACE_BASE(i) + 0x34)
+/** TRACE_P_MATCH : R/W; bitpos: [31:0]; default: 0;
+ *  primary comparator match value
+ */
+#define TRACE_P_MATCH    0xFFFFFFFFU
+#define TRACE_P_MATCH_M  (TRACE_P_MATCH_V << TRACE_P_MATCH_S)
+#define TRACE_P_MATCH_V  0xFFFFFFFFU
+#define TRACE_P_MATCH_S  0
+
+/** TRACE_FILTER_S_COMPARATOR_MATCH_REG register
+ *  secondary comparator match value
+ */
+#define TRACE_FILTER_S_COMPARATOR_MATCH_REG(i) (DR_REG_TRACE_BASE(i) + 0x38)
+/** TRACE_S_MATCH : R/W; bitpos: [31:0]; default: 0;
+ *  secondary comparator match value
+ */
+#define TRACE_S_MATCH    0xFFFFFFFFU
+#define TRACE_S_MATCH_M  (TRACE_S_MATCH_V << TRACE_S_MATCH_S)
+#define TRACE_S_MATCH_V  0xFFFFFFFFU
+#define TRACE_S_MATCH_S  0
+
+/** TRACE_RESYNC_PROLONGED_REG register
+ *  resync configuration register
+ */
+#define TRACE_RESYNC_PROLONGED_REG(i) (DR_REG_TRACE_BASE(i) + 0x3c)
+/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128;
+ *  count number, when count to this value, send a sync package
+ */
+#define TRACE_RESYNC_PROLONGED    0x00FFFFFFU
+#define TRACE_RESYNC_PROLONGED_M  (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S)
+#define TRACE_RESYNC_PROLONGED_V  0x00FFFFFFU
+#define TRACE_RESYNC_PROLONGED_S  0
+/** TRACE_RESYNC_MODE : R/W; bitpos: [25:24]; default: 0;
+ *  resyc mode sel:
+ *  0: off,
+ *  2: cycle count
+ *  3: package num count
+ */
+#define TRACE_RESYNC_MODE    0x00000003U
+#define TRACE_RESYNC_MODE_M  (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S)
+#define TRACE_RESYNC_MODE_V  0x00000003U
+#define TRACE_RESYNC_MODE_S  24
+
+/** TRACE_AHB_CONFIG_REG register
+ *  AHB config register
+ */
+#define TRACE_AHB_CONFIG_REG(i) (DR_REG_TRACE_BASE(i) + 0x40)
+/** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0;
+ *  set hburst
+ */
+#define TRACE_HBURST    0x00000007U
+#define TRACE_HBURST_M  (TRACE_HBURST_V << TRACE_HBURST_S)
+#define TRACE_HBURST_V  0x00000007U
+#define TRACE_HBURST_S  0
+/** TRACE_MAX_INCR : R/W; bitpos: [5:3]; default: 0;
+ *  set max continuous access for incr mode
+ */
+#define TRACE_MAX_INCR    0x00000007U
+#define TRACE_MAX_INCR_M  (TRACE_MAX_INCR_V << TRACE_MAX_INCR_S)
+#define TRACE_MAX_INCR_V  0x00000007U
+#define TRACE_MAX_INCR_S  3
+
+/** TRACE_CLOCK_GATE_REG register
+ *  Clock gate control register
+ */
+#define TRACE_CLOCK_GATE_REG(i) (DR_REG_TRACE_BASE(i) + 0x44)
+/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable clock gate when access all registers in this module.
+ */
+#define TRACE_CLK_EN    (BIT(0))
+#define TRACE_CLK_EN_M  (TRACE_CLK_EN_V << TRACE_CLK_EN_S)
+#define TRACE_CLK_EN_V  0x00000001U
+#define TRACE_CLK_EN_S  0
+
+/** TRACE_DATE_REG register
+ *  Version control register
+ */
+#define TRACE_DATE_REG(i) (DR_REG_TRACE_BASE(i) + 0x3fc)
+/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35721984;
+ *  version control register. Note that this default value stored is the latest date
+ *  when the hardware logic was updated.
+ */
+#define TRACE_DATE    0x0FFFFFFFU
+#define TRACE_DATE_M  (TRACE_DATE_V << TRACE_DATE_S)
+#define TRACE_DATE_V  0x0FFFFFFFU
+#define TRACE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/trace_struct.h

@@ -0,0 +1,503 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Trace memory configuration registers */
+/** Type of mem_start_addr register
+ *  mem start addr
+ */
+typedef union {
+    struct {
+        /** mem_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  The start address of trace memory
+         */
+        uint32_t mem_start_addr:32;
+    };
+    uint32_t val;
+} trace_mem_start_addr_reg_t;
+
+/** Type of mem_end_addr register
+ *  mem end addr
+ */
+typedef union {
+    struct {
+        /** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The end address of trace memory
+         */
+        uint32_t mem_end_addr:32;
+    };
+    uint32_t val;
+} trace_mem_end_addr_reg_t;
+
+/** Type of mem_current_addr register
+ *  mem current addr
+ */
+typedef union {
+    struct {
+        /** mem_current_addr : RO; bitpos: [31:0]; default: 0;
+         *  current_mem_addr,indicate that next writing addr
+         */
+        uint32_t mem_current_addr:32;
+    };
+    uint32_t val;
+} trace_mem_current_addr_reg_t;
+
+/** Type of mem_addr_update register
+ *  mem addr update
+ */
+typedef union {
+    struct {
+        /** mem_current_addr_update : WT; bitpos: [0]; default: 0;
+         *  when set, the  will
+         *  \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to
+         *  \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.
+         */
+        uint32_t mem_current_addr_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} trace_mem_addr_update_reg_t;
+
+
+/** Group: Trace fifo status register */
+/** Type of fifo_status register
+ *  fifo status register
+ */
+typedef union {
+    struct {
+        /** fifo_empty : RO; bitpos: [0]; default: 1;
+         *  Represent whether the fifo is empty.
+         *  1: empty
+         *  0: not empty
+         */
+        uint32_t fifo_empty:1;
+        /** work_status : RO; bitpos: [2:1]; default: 0;
+         *  Represent trace work status:
+         *  0: idle state
+         *  1: working state
+         *  2: wait state due to hart halted or havereset
+         *  3: lost state
+         */
+        uint32_t work_status:2;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} trace_fifo_status_reg_t;
+
+
+/** Group: Trace interrupt configuration registers */
+/** Type of intr_ena register
+ *  interrupt enable register
+ */
+typedef union {
+    struct {
+        /** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0;
+         *  Set 1 enable fifo_overflow interrupt
+         */
+        uint32_t fifo_overflow_intr_ena:1;
+        /** mem_full_intr_ena : R/W; bitpos: [1]; default: 0;
+         *  Set 1 enable mem_full interrupt
+         */
+        uint32_t mem_full_intr_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_intr_ena_reg_t;
+
+/** Type of intr_raw register
+ *  interrupt status register
+ */
+typedef union {
+    struct {
+        /** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0;
+         *  fifo_overflow interrupt status
+         */
+        uint32_t fifo_overflow_intr_raw:1;
+        /** mem_full_intr_raw : RO; bitpos: [1]; default: 0;
+         *  mem_full interrupt status
+         */
+        uint32_t mem_full_intr_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_intr_raw_reg_t;
+
+/** Type of intr_clr register
+ *  interrupt clear register
+ */
+typedef union {
+    struct {
+        /** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0;
+         *  Set 1 clear fifo overflow interrupt
+         */
+        uint32_t fifo_overflow_intr_clr:1;
+        /** mem_full_intr_clr : WT; bitpos: [1]; default: 0;
+         *  Set 1 clear mem full interrupt
+         */
+        uint32_t mem_full_intr_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_intr_clr_reg_t;
+
+
+/** Group: Trace configuration register */
+/** Type of trigger register
+ *  trigger register
+ */
+typedef union {
+    struct {
+        /** trigger_on : WT; bitpos: [0]; default: 0;
+         *  Configure whether or not start trace.
+         *  1: start trace
+         *  0: invalid
+         */
+        uint32_t trigger_on:1;
+        /** trigger_off : WT; bitpos: [1]; default: 0;
+         *  Configure whether or not stop trace.
+         *  1: stop trace
+         *  0: invalid
+         */
+        uint32_t trigger_off:1;
+        /** mem_loop : R/W; bitpos: [2]; default: 1;
+         *  Configure memory loop mode.
+         *  1: trace will loop write trace_mem.
+         *  0: when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr
+         */
+        uint32_t mem_loop:1;
+        /** restart_ena : R/W; bitpos: [3]; default: 1;
+         *  Configure whether or not enable auto-restart.
+         *  1: enable
+         *  0: disable
+         */
+        uint32_t restart_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} trace_trigger_reg_t;
+
+/** Type of config register
+ *  trace configuration register
+ */
+typedef union {
+    struct {
+        /** dm_trigger_ena : R/W; bitpos: [0]; default: 0;
+         *  Configure whether or not enable cpu trigger action.
+         *  1: enable
+         *  0:disable
+         */
+        uint32_t dm_trigger_ena:1;
+        /** reset_ena : R/W; bitpos: [1]; default: 0;
+         *  Configure whether or not enable trace cpu haverest, when enabled, if cpu have
+         *  reset, the encoder will output a packet to report the address of the last
+         *  instruction, and upon reset deassertion, the encoder start again.
+         *  1: enabled
+         *  0: disabled
+         */
+        uint32_t reset_ena:1;
+        /** halt_ena : R/W; bitpos: [2]; default: 0;
+         *  Configure whether or not enable trace cpu is halted, when enabled, if the cpu
+         *  halted, the encoder will output a packet to report the address of the last
+         *  instruction, and upon halted deassertion, the encoder start again.When disabled,
+         *  encoder will not report the last address before halted and first address after
+         *  halted, cpu halted information will not be tracked.
+         *  1: enabled
+         *  0: disabled
+         */
+        uint32_t halt_ena:1;
+        /** stall_ena : R/W; bitpos: [3]; default: 0;
+         *  Configure whether or not enable stall cpu. When enabled, when the fifo almost full,
+         *  the cpu will be stalled until the packets is able to write to fifo.
+         *  1: enabled.
+         *  0: disabled
+         */
+        uint32_t stall_ena:1;
+        /** full_address : R/W; bitpos: [4]; default: 0;
+         *  Configure whether or not enable full-address mode.
+         *  1: full address mode.
+         *  0: delta address mode
+         */
+        uint32_t full_address:1;
+        /** implicit_except : R/W; bitpos: [5]; default: 0;
+         *  Configure whether or not enable implicit exception mode. When enabled,, do not sent
+         *  exception address, only exception cause in exception packets.
+         *  1: enabled
+         *  0: disabled
+         */
+        uint32_t implicit_except:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} trace_config_reg_t;
+
+/** Type of filter_control register
+ *  filter control register
+ */
+typedef union {
+    struct {
+        /** filter_en : R/W; bitpos: [0]; default: 0;
+         *  Configure whether or not enable filter unit.
+         *  1: enable filter.
+         *  0: always match
+         */
+        uint32_t filter_en:1;
+        /** match_comp : R/W; bitpos: [1]; default: 0;
+         *  when set, the comparator must be high in order for the filter to match
+         */
+        uint32_t match_comp:1;
+        /** match_privilege : R/W; bitpos: [2]; default: 0;
+         *  when set, match privilege levels specified by
+         *  \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}.
+         */
+        uint32_t match_privilege:1;
+        /** match_ecause : R/W; bitpos: [3]; default: 0;
+         *  when set, start matching from exception cause codes specified by
+         *  \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop
+         *  matching upon return from the 1st matching exception.
+         */
+        uint32_t match_ecause:1;
+        /** match_interrupt : R/W; bitpos: [4]; default: 0;
+         *  when set, start matching from a trap with the interrupt level codes specified by
+         *  \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and
+         *  stop matching upon return from the 1st matching trap.
+         */
+        uint32_t match_interrupt:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} trace_filter_control_reg_t;
+
+/** Type of filter_match_control register
+ *  filter match control register
+ */
+typedef union {
+    struct {
+        /** match_choice_privilege : R/W; bitpos: [0]; default: 0;
+         *  Select match which privilege level when
+         *  \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set.
+         *  1: machine mode.
+         *  0: user mode
+         */
+        uint32_t match_choice_privilege:1;
+        /** match_value_interrupt : R/W; bitpos: [1]; default: 0;
+         *  Select which match which itype when
+         *  \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set.
+         *  1: match itype of 2.
+         *  0: match itype or 1.
+         */
+        uint32_t match_value_interrupt:1;
+        /** match_choice_ecause : R/W; bitpos: [7:2]; default: 0;
+         *  specified which ecause matched.
+         */
+        uint32_t match_choice_ecause:6;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} trace_filter_match_control_reg_t;
+
+/** Type of filter_comparator_control register
+ *  filter comparator match control register
+ */
+typedef union {
+    struct {
+        /** p_input : R/W; bitpos: [0]; default: 0;
+         *  Determines which input to compare against the primary comparator,
+         *  0: iaddr,
+         *  1: tval.
+         */
+        uint32_t p_input:1;
+        uint32_t reserved_1:1;
+        /** p_function : R/W; bitpos: [4:2]; default: 0;
+         *  Select the primary comparator function.
+         *  0: equal,
+         *  1: not equal,
+         *  2: less than,
+         *  3: less than or equal,
+         *  4: greater than,
+         *  5: greater than or equal,
+         *  other: always match
+         */
+        uint32_t p_function:3;
+        /** p_notify : R/W; bitpos: [5]; default: 0;
+         *  Generate a trace packet explicitly reporting the address that cause the primary
+         *  match
+         */
+        uint32_t p_notify:1;
+        uint32_t reserved_6:2;
+        /** s_input : R/W; bitpos: [8]; default: 0;
+         *  Determines which input to compare against the secondary comparator,
+         *  0: iaddr,
+         *  1: tval.
+         */
+        uint32_t s_input:1;
+        uint32_t reserved_9:1;
+        /** s_function : R/W; bitpos: [12:10]; default: 0;
+         *  Select the secondary comparator function.
+         *  0: equal,
+         *  1: not equal,
+         *  2: less than,
+         *  3: less than or equal,
+         *  4: greater than,
+         *  5: greater than or equal,
+         *  other: always match
+         */
+        uint32_t s_function:3;
+        /** s_notify : R/W; bitpos: [13]; default: 0;
+         *  Generate a trace packet explicitly reporting the address that cause the secondary
+         *  match
+         */
+        uint32_t s_notify:1;
+        uint32_t reserved_14:2;
+        /** match_mode : R/W; bitpos: [17:16]; default: 0;
+         *  0: only primary matches,
+         *  1: primary and secondary comparator both matches(P\&\&S),
+         *  2:either primary or secondary comparator matches !(P\&\&S),
+         *  3: set when primary matches and continue to match until after secondary comparator
+         *  matches
+         */
+        uint32_t match_mode:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} trace_filter_comparator_control_reg_t;
+
+/** Type of filter_p_comparator_match register
+ *  primary comparator match value
+ */
+typedef union {
+    struct {
+        /** p_match : R/W; bitpos: [31:0]; default: 0;
+         *  primary comparator match value
+         */
+        uint32_t p_match:32;
+    };
+    uint32_t val;
+} trace_filter_p_comparator_match_reg_t;
+
+/** Type of filter_s_comparator_match register
+ *  secondary comparator match value
+ */
+typedef union {
+    struct {
+        /** s_match : R/W; bitpos: [31:0]; default: 0;
+         *  secondary comparator match value
+         */
+        uint32_t s_match:32;
+    };
+    uint32_t val;
+} trace_filter_s_comparator_match_reg_t;
+
+/** Type of resync_prolonged register
+ *  resync configuration register
+ */
+typedef union {
+    struct {
+        /** resync_prolonged : R/W; bitpos: [23:0]; default: 128;
+         *  count number, when count to this value, send a sync package
+         */
+        uint32_t resync_prolonged:24;
+        /** resync_mode : R/W; bitpos: [25:24]; default: 0;
+         *  resyc mode sel:
+         *  0: off,
+         *  2: cycle count
+         *  3: package num count
+         */
+        uint32_t resync_mode:2;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} trace_resync_prolonged_reg_t;
+
+/** Type of ahb_config register
+ *  AHB config register
+ */
+typedef union {
+    struct {
+        /** hburst : R/W; bitpos: [2:0]; default: 0;
+         *  set hburst
+         */
+        uint32_t hburst:3;
+        /** max_incr : R/W; bitpos: [5:3]; default: 0;
+         *  set max continuous access for incr mode
+         */
+        uint32_t max_incr:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} trace_ahb_config_reg_t;
+
+
+/** Group: Clock Gate Control and configuration register */
+/** Type of clock_gate register
+ *  Clock gate control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to enable clock gate when access all registers in this module.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} trace_clock_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35721984;
+         *  version control register. Note that this default value stored is the latest date
+         *  when the hardware logic was updated.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} trace_date_reg_t;
+
+
+typedef struct {
+    volatile trace_mem_start_addr_reg_t mem_start_addr;
+    volatile trace_mem_end_addr_reg_t mem_end_addr;
+    volatile trace_mem_current_addr_reg_t mem_current_addr;
+    volatile trace_mem_addr_update_reg_t mem_addr_update;
+    volatile trace_fifo_status_reg_t fifo_status;
+    volatile trace_intr_ena_reg_t intr_ena;
+    volatile trace_intr_raw_reg_t intr_raw;
+    volatile trace_intr_clr_reg_t intr_clr;
+    volatile trace_trigger_reg_t trigger;
+    volatile trace_config_reg_t config;
+    volatile trace_filter_control_reg_t filter_control;
+    volatile trace_filter_match_control_reg_t filter_match_control;
+    volatile trace_filter_comparator_control_reg_t filter_comparator_control;
+    volatile trace_filter_p_comparator_match_reg_t filter_p_comparator_match;
+    volatile trace_filter_s_comparator_match_reg_t filter_s_comparator_match;
+    volatile trace_resync_prolonged_reg_t resync_prolonged;
+    volatile trace_ahb_config_reg_t ahb_config;
+    volatile trace_clock_gate_reg_t clock_gate;
+    uint32_t reserved_048[237];
+    volatile trace_date_reg_t date;
+} trace_dev_t;
+
+extern trace_dev_t TRACE0;
+extern trace_dev_t TRACE1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/trng_reg.h

@@ -0,0 +1,94 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** RNG_CFG_REG register
+ *  configure rng register
+ */
+#define RNG_CFG_REG (DR_REG_RNG_BASE + 0x0)
+/** RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  enable rng RO
+ *  1: enable RO
+ *  0: disable RO
+ */
+#define RNG_SAMPLE_ENABLE    (BIT(0))
+#define RNG_SAMPLE_ENABLE_M  (RNG_SAMPLE_ENABLE_V << RNG_SAMPLE_ENABLE_S)
+#define RNG_SAMPLE_ENABLE_V  0x00000001U
+#define RNG_SAMPLE_ENABLE_S  0
+/** RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 255;
+ *  configure rng timer clk div
+ */
+#define RNG_TIMER_PSCALE    0x000000FFU
+#define RNG_TIMER_PSCALE_M  (RNG_TIMER_PSCALE_V << RNG_TIMER_PSCALE_S)
+#define RNG_TIMER_PSCALE_V  0x000000FFU
+#define RNG_TIMER_PSCALE_S  1
+/** RNG_TIMER_EN : R/W; bitpos: [9]; default: 1;
+ *  enable rng xor async rng timer
+ */
+#define RNG_TIMER_EN    (BIT(9))
+#define RNG_TIMER_EN_M  (RNG_TIMER_EN_V << RNG_TIMER_EN_S)
+#define RNG_TIMER_EN_V  0x00000001U
+#define RNG_TIMER_EN_S  9
+/** RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0;
+ *  get rng RO sample cnt
+ */
+#define RNG_SAMPLE_CNT    0x000000FFU
+#define RNG_SAMPLE_CNT_M  (RNG_SAMPLE_CNT_V << RNG_SAMPLE_CNT_S)
+#define RNG_SAMPLE_CNT_V  0x000000FFU
+#define RNG_SAMPLE_CNT_S  24
+
+/** RNG_DATA_REG register
+ *  RNG result register
+ */
+#define RNG_DATA_REG (DR_REG_RNG_BASE + 0x4)
+/** RNG_DATA : RO; bitpos: [31:0]; default: 0;
+ *  get rng data
+ */
+#define RNG_DATA    0xFFFFFFFFU
+#define RNG_DATA_M  (RNG_DATA_V << RNG_DATA_S)
+#define RNG_DATA_V  0xFFFFFFFFU
+#define RNG_DATA_S  0
+
+/** RNG_RSTN_REG register
+ *  rng rstn register
+ */
+#define RNG_RSTN_REG (DR_REG_RNG_BASE + 0x8)
+/** RNG_RSTN : R/W; bitpos: [0]; default: 1;
+ *  enable rng system reset: 1: not reset, 0: reset
+ */
+#define RNG_RSTN    (BIT(0))
+#define RNG_RSTN_M  (RNG_RSTN_V << RNG_RSTN_S)
+#define RNG_RSTN_V  0x00000001U
+#define RNG_RSTN_S  0
+
+/** RNG_DATE_REG register
+ *  need_des
+ */
+#define RNG_DATE_REG (DR_REG_RNG_BASE + 0xc)
+/** RNG_DATE : R/W; bitpos: [30:0]; default: 2425091;
+ *  need_des
+ */
+#define RNG_DATE    0x7FFFFFFFU
+#define RNG_DATE_M  (RNG_DATE_V << RNG_DATE_S)
+#define RNG_DATE_V  0x7FFFFFFFU
+#define RNG_DATE_S  0
+/** RNG_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define RNG_CLK_EN    (BIT(31))
+#define RNG_CLK_EN_M  (RNG_CLK_EN_V << RNG_CLK_EN_S)
+#define RNG_CLK_EN_V  0x00000001U
+#define RNG_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/trng_struct.h

@@ -0,0 +1,102 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of cfg register
+ *  configure rng register
+ */
+typedef union {
+    struct {
+        /** sample_enable : R/W; bitpos: [0]; default: 0;
+         *  enable rng RO
+         *  1: enable RO
+         *  0: disable RO
+         */
+        uint32_t sample_enable:1;
+        /** timer_pscale : R/W; bitpos: [8:1]; default: 255;
+         *  configure rng timer clk div
+         */
+        uint32_t timer_pscale:8;
+        /** timer_en : R/W; bitpos: [9]; default: 1;
+         *  enable rng xor async rng timer
+         */
+        uint32_t timer_en:1;
+        uint32_t reserved_10:14;
+        /** sample_cnt : RO; bitpos: [31:24]; default: 0;
+         *  get rng RO sample cnt
+         */
+        uint32_t sample_cnt:8;
+    };
+    uint32_t val;
+} rng_cfg_reg_t;
+
+/** Type of data register
+ *  RNG result register
+ */
+typedef union {
+    struct {
+        /** data : RO; bitpos: [31:0]; default: 0;
+         *  get rng data
+         */
+        uint32_t data:32;
+    };
+    uint32_t val;
+} rng_data_reg_t;
+
+/** Type of rstn register
+ *  rng rstn register
+ */
+typedef union {
+    struct {
+        /** rstn : R/W; bitpos: [0]; default: 1;
+         *  enable rng system reset: 1: not reset, 0: reset
+         */
+        uint32_t rstn:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rng_rstn_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [30:0]; default: 2425091;
+         *  need_des
+         */
+        uint32_t date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} rng_date_reg_t;
+
+
+typedef struct {
+    volatile rng_cfg_reg_t cfg;
+    volatile rng_data_reg_t data;
+    volatile rng_rstn_reg_t rstn;
+    volatile rng_date_reg_t date;
+} rng_dev_t;
+
+extern rng_dev_t LP_TRNG;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(rng_dev_t) == 0x10, "Invalid size of rng_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/tsens_reg.h

@@ -0,0 +1,220 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TSENS_CTRL_REG register
+ *  Tsens configuration.
+ */
+#define TSENS_CTRL_REG (DR_REG_TSENS_BASE + 0x0)
+/** TSENS_OUT : RO; bitpos: [7:0]; default: 0;
+ *  Temperature sensor data out.
+ */
+#define TSENS_OUT    0x000000FFU
+#define TSENS_OUT_M  (TSENS_OUT_V << TSENS_OUT_S)
+#define TSENS_OUT_V  0x000000FFU
+#define TSENS_OUT_S  0
+/** TSENS_READY : RO; bitpos: [8]; default: 0;
+ *  Indicate temperature sensor out ready.
+ */
+#define TSENS_READY    (BIT(8))
+#define TSENS_READY_M  (TSENS_READY_V << TSENS_READY_S)
+#define TSENS_READY_V  0x00000001U
+#define TSENS_READY_S  8
+/** TSENS_SAMPLE_EN : R/W; bitpos: [9]; default: 0;
+ *  Enable sample signal for wakeup module.
+ */
+#define TSENS_SAMPLE_EN    (BIT(9))
+#define TSENS_SAMPLE_EN_M  (TSENS_SAMPLE_EN_V << TSENS_SAMPLE_EN_S)
+#define TSENS_SAMPLE_EN_V  0x00000001U
+#define TSENS_SAMPLE_EN_S  9
+/** TSENS_WAKEUP_MASK : R/W; bitpos: [10]; default: 1;
+ *  Wake up signal  mask.
+ */
+#define TSENS_WAKEUP_MASK    (BIT(10))
+#define TSENS_WAKEUP_MASK_M  (TSENS_WAKEUP_MASK_V << TSENS_WAKEUP_MASK_S)
+#define TSENS_WAKEUP_MASK_V  0x00000001U
+#define TSENS_WAKEUP_MASK_S  10
+/** TSENS_INT_EN : R/W; bitpos: [12]; default: 1;
+ *  Enable temperature sensor to send out interrupt.
+ */
+#define TSENS_INT_EN    (BIT(12))
+#define TSENS_INT_EN_M  (TSENS_INT_EN_V << TSENS_INT_EN_S)
+#define TSENS_INT_EN_V  0x00000001U
+#define TSENS_INT_EN_S  12
+/** TSENS_IN_INV : R/W; bitpos: [13]; default: 0;
+ *  Invert temperature sensor data.
+ */
+#define TSENS_IN_INV    (BIT(13))
+#define TSENS_IN_INV_M  (TSENS_IN_INV_V << TSENS_IN_INV_S)
+#define TSENS_IN_INV_V  0x00000001U
+#define TSENS_IN_INV_S  13
+/** TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6;
+ *  Temperature sensor clock divider.
+ */
+#define TSENS_CLK_DIV    0x000000FFU
+#define TSENS_CLK_DIV_M  (TSENS_CLK_DIV_V << TSENS_CLK_DIV_S)
+#define TSENS_CLK_DIV_V  0x000000FFU
+#define TSENS_CLK_DIV_S  14
+/** TSENS_POWER_UP : R/W; bitpos: [22]; default: 0;
+ *  Temperature sensor power up.
+ */
+#define TSENS_POWER_UP    (BIT(22))
+#define TSENS_POWER_UP_M  (TSENS_POWER_UP_V << TSENS_POWER_UP_S)
+#define TSENS_POWER_UP_V  0x00000001U
+#define TSENS_POWER_UP_S  22
+/** TSENS_POWER_UP_FORCE : R/W; bitpos: [23]; default: 0;
+ *  1: dump out & power up controlled by SW,  0: by FSM.
+ */
+#define TSENS_POWER_UP_FORCE    (BIT(23))
+#define TSENS_POWER_UP_FORCE_M  (TSENS_POWER_UP_FORCE_V << TSENS_POWER_UP_FORCE_S)
+#define TSENS_POWER_UP_FORCE_V  0x00000001U
+#define TSENS_POWER_UP_FORCE_S  23
+
+/** TSENS_INT_RAW_REG register
+ *  Tsens interrupt raw registers.
+ */
+#define TSENS_INT_RAW_REG (DR_REG_TSENS_BASE + 0x8)
+/** TSENS_COCPU_TSENS_WAKE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Tsens wakeup interrupt raw.
+ */
+#define TSENS_COCPU_TSENS_WAKE_INT_RAW    (BIT(0))
+#define TSENS_COCPU_TSENS_WAKE_INT_RAW_M  (TSENS_COCPU_TSENS_WAKE_INT_RAW_V << TSENS_COCPU_TSENS_WAKE_INT_RAW_S)
+#define TSENS_COCPU_TSENS_WAKE_INT_RAW_V  0x00000001U
+#define TSENS_COCPU_TSENS_WAKE_INT_RAW_S  0
+
+/** TSENS_INT_ST_REG register
+ *  Tsens interrupt status registers.
+ */
+#define TSENS_INT_ST_REG (DR_REG_TSENS_BASE + 0xc)
+/** TSENS_COCPU_TSENS_WAKE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  Tsens wakeup interrupt status.
+ */
+#define TSENS_COCPU_TSENS_WAKE_INT_ST    (BIT(0))
+#define TSENS_COCPU_TSENS_WAKE_INT_ST_M  (TSENS_COCPU_TSENS_WAKE_INT_ST_V << TSENS_COCPU_TSENS_WAKE_INT_ST_S)
+#define TSENS_COCPU_TSENS_WAKE_INT_ST_V  0x00000001U
+#define TSENS_COCPU_TSENS_WAKE_INT_ST_S  0
+
+/** TSENS_INT_ENA_REG register
+ *  Tsens interrupt enable registers.
+ */
+#define TSENS_INT_ENA_REG (DR_REG_TSENS_BASE + 0x10)
+/** TSENS_COCPU_TSENS_WAKE_INT_ENA : R/WTC; bitpos: [0]; default: 0;
+ *  Tsens wakeup interrupt enable.
+ */
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA    (BIT(0))
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_M  (TSENS_COCPU_TSENS_WAKE_INT_ENA_V << TSENS_COCPU_TSENS_WAKE_INT_ENA_S)
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_V  0x00000001U
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_S  0
+
+/** TSENS_INT_CLR_REG register
+ *  Tsens interrupt clear registers.
+ */
+#define TSENS_INT_CLR_REG (DR_REG_TSENS_BASE + 0x14)
+/** TSENS_COCPU_TSENS_WAKE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Tsens wakeup interrupt clear.
+ */
+#define TSENS_COCPU_TSENS_WAKE_INT_CLR    (BIT(0))
+#define TSENS_COCPU_TSENS_WAKE_INT_CLR_M  (TSENS_COCPU_TSENS_WAKE_INT_CLR_V << TSENS_COCPU_TSENS_WAKE_INT_CLR_S)
+#define TSENS_COCPU_TSENS_WAKE_INT_CLR_V  0x00000001U
+#define TSENS_COCPU_TSENS_WAKE_INT_CLR_S  0
+
+/** TSENS_CLK_CONF_REG register
+ *  Tsens regbank configuration registers.
+ */
+#define TSENS_CLK_CONF_REG (DR_REG_TSENS_BASE + 0x18)
+/** TSENS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Tsens regbank clock gating enable.
+ */
+#define TSENS_CLK_EN    (BIT(0))
+#define TSENS_CLK_EN_M  (TSENS_CLK_EN_V << TSENS_CLK_EN_S)
+#define TSENS_CLK_EN_V  0x00000001U
+#define TSENS_CLK_EN_S  0
+
+/** TSENS_INT_ENA_W1TS_REG register
+ *  Tsens wakeup interrupt enable assert.
+ */
+#define TSENS_INT_ENA_W1TS_REG (DR_REG_TSENS_BASE + 0x1c)
+/** TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS : WT; bitpos: [0]; default: 0;
+ *  Write 1 to this field to assert interrupt enable.
+ */
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS    (BIT(0))
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_M  (TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_V << TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_S)
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_V  0x00000001U
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_S  0
+
+/** TSENS_INT_ENA_W1TC_REG register
+ *  Tsens wakeup interrupt enable deassert.
+ */
+#define TSENS_INT_ENA_W1TC_REG (DR_REG_TSENS_BASE + 0x20)
+/** TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC : WT; bitpos: [0]; default: 0;
+ *  Write 1 to this field to deassert interrupt enable.
+ */
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC    (BIT(0))
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_M  (TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_V << TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_S)
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_V  0x00000001U
+#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_S  0
+
+/** TSENS_WAKEUP_CTRL_REG register
+ *  Tsens wakeup control registers.
+ */
+#define TSENS_WAKEUP_CTRL_REG (DR_REG_TSENS_BASE + 0x24)
+/** TSENS_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0;
+ *  Lower threshold.
+ */
+#define TSENS_WAKEUP_TH_LOW    0x000000FFU
+#define TSENS_WAKEUP_TH_LOW_M  (TSENS_WAKEUP_TH_LOW_V << TSENS_WAKEUP_TH_LOW_S)
+#define TSENS_WAKEUP_TH_LOW_V  0x000000FFU
+#define TSENS_WAKEUP_TH_LOW_S  0
+/** TSENS_WAKEUP_TH_HIGH : R/W; bitpos: [21:14]; default: 255;
+ *  Upper threshold.
+ */
+#define TSENS_WAKEUP_TH_HIGH    0x000000FFU
+#define TSENS_WAKEUP_TH_HIGH_M  (TSENS_WAKEUP_TH_HIGH_V << TSENS_WAKEUP_TH_HIGH_S)
+#define TSENS_WAKEUP_TH_HIGH_V  0x000000FFU
+#define TSENS_WAKEUP_TH_HIGH_S  14
+/** TSENS_WAKEUP_OVER_UPPER_TH : RO; bitpos: [29]; default: 0;
+ *  Indicates that this wakeup event arose from exceeding upper threshold.
+ */
+#define TSENS_WAKEUP_OVER_UPPER_TH    (BIT(29))
+#define TSENS_WAKEUP_OVER_UPPER_TH_M  (TSENS_WAKEUP_OVER_UPPER_TH_V << TSENS_WAKEUP_OVER_UPPER_TH_S)
+#define TSENS_WAKEUP_OVER_UPPER_TH_V  0x00000001U
+#define TSENS_WAKEUP_OVER_UPPER_TH_S  29
+/** TSENS_WAKEUP_EN : R/W; bitpos: [30]; default: 0;
+ *  Tsens wakeup enable.
+ */
+#define TSENS_WAKEUP_EN    (BIT(30))
+#define TSENS_WAKEUP_EN_M  (TSENS_WAKEUP_EN_V << TSENS_WAKEUP_EN_S)
+#define TSENS_WAKEUP_EN_V  0x00000001U
+#define TSENS_WAKEUP_EN_S  30
+/** TSENS_WAKEUP_MODE : R/W; bitpos: [31]; default: 0;
+ *  0:absolute value comparison mode. 1: relative value comparison mode.
+ */
+#define TSENS_WAKEUP_MODE    (BIT(31))
+#define TSENS_WAKEUP_MODE_M  (TSENS_WAKEUP_MODE_V << TSENS_WAKEUP_MODE_S)
+#define TSENS_WAKEUP_MODE_V  0x00000001U
+#define TSENS_WAKEUP_MODE_S  31
+
+/** TSENS_SAMPLE_RATE_REG register
+ *  Hardware automatic sampling control registers.
+ */
+#define TSENS_SAMPLE_RATE_REG (DR_REG_TSENS_BASE + 0x28)
+/** TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20;
+ *  Hardware automatic sampling rate.
+ */
+#define TSENS_SAMPLE_RATE    0x0000FFFFU
+#define TSENS_SAMPLE_RATE_M  (TSENS_SAMPLE_RATE_V << TSENS_SAMPLE_RATE_S)
+#define TSENS_SAMPLE_RATE_V  0x0000FFFFU
+#define TSENS_SAMPLE_RATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/tsens_struct.h

@@ -0,0 +1,233 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Tsens control registers. */
+/** Type of ctrl register
+ *  Tsens configuration.
+ */
+typedef union {
+    struct {
+        /** out : RO; bitpos: [7:0]; default: 0;
+         *  Temperature sensor data out.
+         */
+        uint32_t out:8;
+        /** ready : RO; bitpos: [8]; default: 0;
+         *  Indicate temperature sensor out ready.
+         */
+        uint32_t ready:1;
+        /** sample_en : R/W; bitpos: [9]; default: 0;
+         *  Enable sample signal for wakeup module.
+         */
+        uint32_t sample_en:1;
+        /** wakeup_mask : R/W; bitpos: [10]; default: 1;
+         *  Wake up signal  mask.
+         */
+        uint32_t wakeup_mask:1;
+        uint32_t reserved_11:1;
+        /** int_en : R/W; bitpos: [12]; default: 1;
+         *  Enable temperature sensor to send out interrupt.
+         */
+        uint32_t int_en:1;
+        /** in_inv : R/W; bitpos: [13]; default: 0;
+         *  Invert temperature sensor data.
+         */
+        uint32_t in_inv:1;
+        /** clk_div : R/W; bitpos: [21:14]; default: 6;
+         *  Temperature sensor clock divider.
+         */
+        uint32_t clk_div:8;
+        /** power_up : R/W; bitpos: [22]; default: 0;
+         *  Temperature sensor power up.
+         */
+        uint32_t power_up:1;
+        /** power_up_force : R/W; bitpos: [23]; default: 0;
+         *  1: dump out & power up controlled by SW,  0: by FSM.
+         */
+        uint32_t power_up_force:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} tsens_ctrl_reg_t;
+
+
+/** Group: Tsens interrupt registers. */
+/** Type of int_raw register
+ *  Tsens interrupt raw registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_tsens_wake_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Tsens wakeup interrupt raw.
+         */
+        uint32_t cocpu_tsens_wake_int_raw:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Tsens interrupt status registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_tsens_wake_int_st : RO; bitpos: [0]; default: 0;
+         *  Tsens wakeup interrupt status.
+         */
+        uint32_t cocpu_tsens_wake_int_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Tsens interrupt enable registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_tsens_wake_int_ena : R/WTC; bitpos: [0]; default: 0;
+         *  Tsens wakeup interrupt enable.
+         */
+        uint32_t cocpu_tsens_wake_int_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Tsens interrupt clear registers.
+ */
+typedef union {
+    struct {
+        /** cocpu_tsens_wake_int_clr : WT; bitpos: [0]; default: 0;
+         *  Tsens wakeup interrupt clear.
+         */
+        uint32_t cocpu_tsens_wake_int_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_int_clr_reg_t;
+
+/** Type of int_ena_w1ts register
+ *  Tsens wakeup interrupt enable assert.
+ */
+typedef union {
+    struct {
+        /** cocpu_tsens_wake_int_ena_w1ts : WT; bitpos: [0]; default: 0;
+         *  Write 1 to this field to assert interrupt enable.
+         */
+        uint32_t cocpu_tsens_wake_int_ena_w1ts:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_int_ena_w1ts_reg_t;
+
+/** Type of int_ena_w1tc register
+ *  Tsens wakeup interrupt enable deassert.
+ */
+typedef union {
+    struct {
+        /** cocpu_tsens_wake_int_ena_w1tc : WT; bitpos: [0]; default: 0;
+         *  Write 1 to this field to deassert interrupt enable.
+         */
+        uint32_t cocpu_tsens_wake_int_ena_w1tc:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_int_ena_w1tc_reg_t;
+
+
+/** Group: Tsens regbank clock control registers. */
+/** Type of clk_conf register
+ *  Tsens regbank configuration registers.
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Tsens regbank clock gating enable.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tsens_clk_conf_reg_t;
+
+
+/** Group: Tsens wakeup control registers. */
+/** Type of wakeup_ctrl register
+ *  Tsens wakeup control registers.
+ */
+typedef union {
+    struct {
+        /** wakeup_th_low : R/W; bitpos: [7:0]; default: 0;
+         *  Lower threshold.
+         */
+        uint32_t wakeup_th_low:8;
+        uint32_t reserved_8:6;
+        /** wakeup_th_high : R/W; bitpos: [21:14]; default: 255;
+         *  Upper threshold.
+         */
+        uint32_t wakeup_th_high:8;
+        uint32_t reserved_22:7;
+        /** wakeup_over_upper_th : RO; bitpos: [29]; default: 0;
+         *  Indicates that this wakeup event arose from exceeding upper threshold.
+         */
+        uint32_t wakeup_over_upper_th:1;
+        /** wakeup_en : R/W; bitpos: [30]; default: 0;
+         *  Tsens wakeup enable.
+         */
+        uint32_t wakeup_en:1;
+        /** wakeup_mode : R/W; bitpos: [31]; default: 0;
+         *  0:absolute value comparison mode. 1: relative value comparison mode.
+         */
+        uint32_t wakeup_mode:1;
+    };
+    uint32_t val;
+} tsens_wakeup_ctrl_reg_t;
+
+/** Type of sample_rate register
+ *  Hardware automatic sampling control registers.
+ */
+typedef union {
+    struct {
+        /** sample_rate : R/W; bitpos: [15:0]; default: 20;
+         *  Hardware automatic sampling rate.
+         */
+        uint32_t sample_rate:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} tsens_sample_rate_reg_t;
+
+
+typedef struct {
+    volatile tsens_ctrl_reg_t ctrl;
+    uint32_t reserved_004;
+    volatile tsens_int_raw_reg_t int_raw;
+    volatile tsens_int_st_reg_t int_st;
+    volatile tsens_int_ena_reg_t int_ena;
+    volatile tsens_int_clr_reg_t int_clr;
+    volatile tsens_clk_conf_reg_t clk_conf;
+    volatile tsens_int_ena_w1ts_reg_t int_ena_w1ts;
+    volatile tsens_int_ena_w1tc_reg_t int_ena_w1tc;
+    volatile tsens_wakeup_ctrl_reg_t wakeup_ctrl;
+    volatile tsens_sample_rate_reg_t sample_rate;
+} tsens_dev_t;
+
+extern tsens_dev_t LP_TSENS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(tsens_dev_t) == 0x2c, "Invalid size of tsens_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/twai_eco5_struct.h

@@ -0,0 +1,799 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of mode register
+ *  TWAI mode register.
+ */
+typedef union {
+    struct {
+        /** reset_mode : R/W; bitpos: [0]; default: 1;
+         *  1: reset, detection of a set reset mode bit results in aborting the current
+         *  transmission/reception of a message and entering the reset mode. 0: normal, on the
+         *  '1-to-0' transition of the reset mode bit, the TWAI controller returns to the
+         *  operating mode.
+         */
+        uint32_t reset_mode:1;
+        /** listen_only_mode : R/W; bitpos: [1]; default: 0;
+         *  1: listen only, in this mode the TWAI controller would give no acknowledge to the
+         *  TWAI-bus, even if a message is received successfully. The error counters are
+         *  stopped at the current value. 0: normal.
+         */
+        uint32_t listen_only_mode:1;
+        /** self_test_mode : R/W; bitpos: [2]; default: 0;
+         *  1: self test, in this mode a full node test is possible without any other active
+         *  node on the bus using the self reception request command. The TWAI controller will
+         *  perform a successful transmission, even if there is no acknowledge received. 0:
+         *  normal, an acknowledge is required for successful transmission.
+         */
+        uint32_t self_test_mode:1;
+        /** acceptance_filter_mode : R/W; bitpos: [3]; default: 0;
+         *  1:single, the single acceptance filter option is enabled (one filter with the
+         *  length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled
+         *  (two filters, each with the length of 16 bit are active).
+         */
+        uint32_t acceptance_filter_mode:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} twai_mode_reg_t;
+
+/** Type of cmd register
+ *  TWAI command register.
+ */
+typedef union {
+    struct {
+        /** tx_request : WO; bitpos: [0]; default: 0;
+         *  1: present, a message shall be transmitted. 0: absent
+         */
+        uint32_t tx_request:1;
+        /** abort_tx : WO; bitpos: [1]; default: 0;
+         *  1: present, if not already in progress, a pending transmission request is
+         *  cancelled. 0: absent
+         */
+        uint32_t abort_tx:1;
+        /** release_buffer : WO; bitpos: [2]; default: 0;
+         *  1: released, the receive buffer, representing the message memory space in the
+         *  RXFIFO is released. 0: no action
+         */
+        uint32_t release_buffer:1;
+        /** clear_data_overrun : WO; bitpos: [3]; default: 0;
+         *  1: clear, the data overrun status bit is cleared. 0: no action.
+         */
+        uint32_t clear_data_overrun:1;
+        /** self_rx_request : WO; bitpos: [4]; default: 0;
+         *  1: present, a message shall be transmitted and received simultaneously. 0: absent.
+         */
+        uint32_t self_rx_request:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} twai_cmd_reg_t;
+
+/** Type of bus_timing_0 register
+ *  Bit timing configuration register 0.
+ */
+typedef union {
+    struct {
+        /** baud_presc : R/W; bitpos: [13:0]; default: 0;
+         *  The period of the TWAI system clock is programmable and determines the individual
+         *  bit timing. Software has R/W permission in reset mode and RO permission in
+         *  operation mode.
+         */
+        uint32_t baud_presc:14;
+        /** sync_jump_width : R/W; bitpos: [15:14]; default: 0;
+         *  The synchronization jump width defines the maximum number of clock cycles a bit
+         *  period may be shortened or lengthened. Software has R/W permission in reset mode
+         *  and RO in operation mode.
+         */
+        uint32_t sync_jump_width:2;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} twai_bus_timing_0_reg_t;
+
+/** Type of bus_timing_1 register
+ *  Bit timing configuration register 1.
+ */
+typedef union {
+    struct {
+        /** time_segment1 : R/W; bitpos: [3:0]; default: 0;
+         *  The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in
+         *  reset mode and RO in operation mode.
+         */
+        uint32_t time_segment1:4;
+        /** time_segment2 : R/W; bitpos: [6:4]; default: 0;
+         *  The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in
+         *  reset mode and RO in operation mode.
+         */
+        uint32_t time_segment2:3;
+        /** time_sampling : R/W; bitpos: [7]; default: 0;
+         *  1: triple, the bus is sampled three times. 0: single, the bus is sampled once.
+         *  Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t time_sampling:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_bus_timing_1_reg_t;
+
+/** Type of err_warning_limit register
+ *  TWAI error threshold configuration register.
+ */
+typedef union {
+    struct {
+        /** err_warning_limit : R/W; bitpos: [7:0]; default: 96;
+         *  The threshold that trigger error warning interrupt when this interrupt is enabled.
+         *  Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t err_warning_limit:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_err_warning_limit_reg_t;
+
+/** Type of clock_divider register
+ *  Clock divider register.
+ */
+typedef union {
+    struct {
+        /** cd : R/W; bitpos: [7:0]; default: 0;
+         *  These bits are used to define the frequency at the external CLKOUT pin.
+         */
+        uint32_t cd:8;
+        /** clock_off : R/W; bitpos: [8]; default: 0;
+         *  1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has
+         *  R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t clock_off:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_clock_divider_reg_t;
+
+/** Type of sw_standby_cfg register
+ *  Software configure standby pin directly.
+ */
+typedef union {
+    struct {
+        /** sw_standby_en : R/W; bitpos: [0]; default: 0;
+         *  Enable standby pin.
+         */
+        uint32_t sw_standby_en:1;
+        /** sw_standby_clr : R/W; bitpos: [1]; default: 1;
+         *  Clear standby pin.
+         */
+        uint32_t sw_standby_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} twai_sw_standby_cfg_reg_t;
+
+/** Type of hw_cfg register
+ *  Hardware configure standby pin.
+ */
+typedef union {
+    struct {
+        /** hw_standby_en : R/W; bitpos: [0]; default: 0;
+         *  Enable function that hardware control standby pin.
+         */
+        uint32_t hw_standby_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} twai_hw_cfg_reg_t;
+
+/** Type of hw_standby_cnt register
+ *  Configure standby counter.
+ */
+typedef union {
+    struct {
+        /** standby_wait_cnt : R/W; bitpos: [31:0]; default: 1;
+         *  Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN
+         *  is enabled.
+         */
+        uint32_t standby_wait_cnt:32;
+    };
+    uint32_t val;
+} twai_hw_standby_cnt_reg_t;
+
+/** Type of idle_intr_cnt register
+ *  Configure idle interrupt counter.
+ */
+typedef union {
+    struct {
+        /** idle_intr_cnt : R/W; bitpos: [31:0]; default: 1;
+         *  Configure the number of cycles before triggering idle interrupt.
+         */
+        uint32_t idle_intr_cnt:32;
+    };
+    uint32_t val;
+} twai_idle_intr_cnt_reg_t;
+
+/** Type of eco_cfg register
+ *  ECO configuration register.
+ */
+typedef union {
+    struct {
+        /** rdn_ena : R/W; bitpos: [0]; default: 0;
+         *  Enable eco module.
+         */
+        uint32_t rdn_ena:1;
+        /** rdn_result : RO; bitpos: [1]; default: 1;
+         *  Output of eco module.
+         */
+        uint32_t rdn_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} twai_eco_cfg_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of status register
+ *  TWAI status register.
+ */
+typedef union {
+    struct {
+        /** status_receive_buffer : RO; bitpos: [0]; default: 0;
+         *  1: full, one or more complete messages are available in the RXFIFO. 0: empty, no
+         *  message is available
+         */
+        uint32_t status_receive_buffer:1;
+        /** status_overrun : RO; bitpos: [1]; default: 0;
+         *  1: overrun, a message was lost because there was not enough space for that message
+         *  in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data
+         *  overrun command was given
+         */
+        uint32_t status_overrun:1;
+        /** status_transmit_buffer : RO; bitpos: [2]; default: 0;
+         *  1: released, the CPU may write a message into the transmit buffer. 0: locked, the
+         *  CPU cannot access the transmit buffer, a message is either waiting for transmission
+         *  or is in the process of being transmitted
+         */
+        uint32_t status_transmit_buffer:1;
+        /** status_transmission_complete : RO; bitpos: [3]; default: 0;
+         *  1: complete, last requested transmission has been successfully completed. 0:
+         *  incomplete, previously requested transmission is not yet completed
+         */
+        uint32_t status_transmission_complete:1;
+        /** status_receive : RO; bitpos: [4]; default: 0;
+         *  1: receive, the TWAI controller is receiving a message. 0: idle
+         */
+        uint32_t status_receive:1;
+        /** status_transmit : RO; bitpos: [5]; default: 0;
+         *  1: transmit, the TWAI controller is transmitting a message. 0: idle
+         */
+        uint32_t status_transmit:1;
+        /** status_err : RO; bitpos: [6]; default: 0;
+         *  1: error, at least one of the error counters has reached or exceeded the CPU
+         *  warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error
+         *  counters are below the warning limit
+         */
+        uint32_t status_err:1;
+        /** status_node_bus_off : RO; bitpos: [7]; default: 0;
+         *  1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the
+         *  TWAI controller is involved in bus activities
+         */
+        uint32_t status_node_bus_off:1;
+        /** status_miss : RO; bitpos: [8]; default: 0;
+         *  1: current message is destroyed because of FIFO overflow.
+         */
+        uint32_t status_miss:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_status_reg_t;
+
+/** Type of arb_lost_cap register
+ *  TWAI arbiter lost capture register.
+ */
+typedef union {
+    struct {
+        /** arbitration_lost_capture : RO; bitpos: [4:0]; default: 0;
+         *  This register contains information about the bit position of losing arbitration.
+         */
+        uint32_t arbitration_lost_capture:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} twai_arb_lost_cap_reg_t;
+
+/** Type of err_code_cap register
+ *  TWAI error info capture register.
+ */
+typedef union {
+    struct {
+        /** err_capture_code_segment : RO; bitpos: [4:0]; default: 0;
+         *  This register contains information about the location of errors on the bus.
+         */
+        uint32_t err_capture_code_segment:5;
+        /** err_capture_code_direction : RO; bitpos: [5]; default: 0;
+         *  1: RX, error occurred during reception. 0: TX, error occurred during transmission.
+         */
+        uint32_t err_capture_code_direction:1;
+        /** err_capture_code_type : RO; bitpos: [7:6]; default: 0;
+         *  00: bit error. 01: form error. 10:stuff error. 11:other type of error.
+         */
+        uint32_t err_capture_code_type:2;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_err_code_cap_reg_t;
+
+/** Type of rx_err_cnt register
+ *  Rx error counter register.
+ */
+typedef union {
+    struct {
+        /** rx_err_cnt : R/W; bitpos: [7:0]; default: 0;
+         *  The RX error counter register reflects the current value of the transmit error
+         *  counter. Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t rx_err_cnt:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_rx_err_cnt_reg_t;
+
+/** Type of tx_err_cnt register
+ *  Tx error counter register.
+ */
+typedef union {
+    struct {
+        /** tx_err_cnt : R/W; bitpos: [7:0]; default: 0;
+         *  The TX error counter register reflects the current value of the transmit error
+         *  counter. Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t tx_err_cnt:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_tx_err_cnt_reg_t;
+
+/** Type of rx_message_counter register
+ *  Received message counter register.
+ */
+typedef union {
+    struct {
+        /** rx_message_counter : RO; bitpos: [6:0]; default: 0;
+         *  Reflects the number of messages available within the RXFIFO. The value is
+         *  incremented with each receive event and decremented by the release receive buffer
+         *  command.
+         */
+        uint32_t rx_message_counter:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} twai_rx_message_counter_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of interrupt register
+ *  Interrupt signals' register.
+ */
+typedef union {
+    struct {
+        /** receive_int_st : RO; bitpos: [0]; default: 0;
+         *  1: this bit is set while the receive FIFO is not empty and the RIE bit is set
+         *  within the interrupt enable register. 0: reset
+         */
+        uint32_t receive_int_st:1;
+        /** transmit_int_st : RO; bitpos: [1]; default: 0;
+         *  1: this bit is set whenever the transmit buffer status changes from '0-to-1'
+         *  (released) and the TIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t transmit_int_st:1;
+        /** err_warning_int_st : RO; bitpos: [2]; default: 0;
+         *  1: this bit is set on every change (set and clear) of either the error status or
+         *  bus status bits and the EIE bit is set within the interrupt enable register. 0:
+         *  reset
+         */
+        uint32_t err_warning_int_st:1;
+        /** data_overrun_int_st : RO; bitpos: [3]; default: 0;
+         *  1: this bit is set on a '0-to-1' transition of the data overrun status bit and the
+         *  DOIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t data_overrun_int_st:1;
+        /** ts_counter_ovfl_int_st : RO; bitpos: [4]; default: 0;
+         *  1: this bit is set then the timestamp counter reaches the maximum value and
+         *  overflow.
+         */
+        uint32_t ts_counter_ovfl_int_st:1;
+        /** err_passive_int_st : RO; bitpos: [5]; default: 0;
+         *  1: this bit is set whenever the TWAI controller has reached the error passive
+         *  status (at least one error counter exceeds the protocol-defined level of 127) or if
+         *  the TWAI controller is in the error passive status and enters the error active
+         *  status again and the EPIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t err_passive_int_st:1;
+        /** arbitration_lost_int_st : RO; bitpos: [6]; default: 0;
+         *  1: this bit is set when the TWAI controller lost the arbitration and becomes a
+         *  receiver and the ALIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t arbitration_lost_int_st:1;
+        /** bus_err_int_st : RO; bitpos: [7]; default: 0;
+         *  1: this bit is set when the TWAI controller detects an error on the TWAI-bus and
+         *  the BEIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t bus_err_int_st:1;
+        /** idle_int_st : RO; bitpos: [8]; default: 0;
+         *  1: this bit is set when the TWAI controller detects state of TWAI become IDLE and
+         *  this interrupt enable bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t idle_int_st:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_interrupt_reg_t;
+
+/** Type of interrupt_enable register
+ *  Interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** ext_receive_int_ena : R/W; bitpos: [0]; default: 0;
+         *  1: enabled, when the receive buffer status is 'full' the TWAI controller requests
+         *  the respective interrupt. 0: disable
+         */
+        uint32_t ext_receive_int_ena:1;
+        /** ext_transmit_int_ena : R/W; bitpos: [1]; default: 0;
+         *  1: enabled, when a message has been successfully transmitted or the transmit buffer
+         *  is accessible again (e.g. after an abort transmission command), the TWAI controller
+         *  requests the respective interrupt. 0: disable
+         */
+        uint32_t ext_transmit_int_ena:1;
+        /** ext_err_warning_int_ena : R/W; bitpos: [2]; default: 0;
+         *  1: enabled, if the error or bus status change (see status register. Table 14), the
+         *  TWAI controllerrequests the respective interrupt. 0: disable
+         */
+        uint32_t ext_err_warning_int_ena:1;
+        /** ext_data_overrun_int_ena : R/W; bitpos: [3]; default: 0;
+         *  1: enabled, if the data overrun status bit is set (see status register. Table 14),
+         *  the TWAI controllerrequests the respective interrupt. 0: disable
+         */
+        uint32_t ext_data_overrun_int_ena:1;
+        /** ts_counter_ovfl_int_ena : R/W; bitpos: [4]; default: 0;
+         *  enable the timestamp counter overflow interrupt request.
+         */
+        uint32_t ts_counter_ovfl_int_ena:1;
+        /** err_passive_int_ena : R/W; bitpos: [5]; default: 0;
+         *  1: enabled, if the error status of the TWAI controller changes from error active to
+         *  error passive or vice versa, the respective interrupt is requested. 0: disable
+         */
+        uint32_t err_passive_int_ena:1;
+        /** arbitration_lost_int_ena : R/W; bitpos: [6]; default: 0;
+         *  1: enabled, if the TWAI controller has lost arbitration, the respective interrupt
+         *  is requested. 0: disable
+         */
+        uint32_t arbitration_lost_int_ena:1;
+        /** bus_err_int_ena : R/W; bitpos: [7]; default: 0;
+         *  1: enabled, if an bus error has been detected, the TWAI controller requests the
+         *  respective interrupt. 0: disable
+         */
+        uint32_t bus_err_int_ena:1;
+        /** idle_int_ena : RO; bitpos: [8]; default: 0;
+         *  1: enabled, if state of TWAI become IDLE, the TWAI controller requests the
+         *  respective interrupt. 0: disable
+         */
+        uint32_t idle_int_ena:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_interrupt_enable_reg_t;
+
+
+/** Group: Data Registers */
+/** Type of data_0 register
+ *  Data register 0.
+ */
+typedef union {
+    struct {
+        /** data_0 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance code register 0 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 0 and when
+         *  software initiate read operation, it is rx data register 0.
+         */
+        uint32_t data_0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_0_reg_t;
+
+/** Type of data_1 register
+ *  Data register 1.
+ */
+typedef union {
+    struct {
+        /** data_1 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance code register 1 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 1 and when
+         *  software initiate read operation, it is rx data register 1.
+         */
+        uint32_t data_1:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_1_reg_t;
+
+/** Type of data_2 register
+ *  Data register 2.
+ */
+typedef union {
+    struct {
+        /** data_2 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance code register 2 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 2 and when
+         *  software initiate read operation, it is rx data register 2.
+         */
+        uint32_t data_2:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_2_reg_t;
+
+/** Type of data_3 register
+ *  Data register 3.
+ */
+typedef union {
+    struct {
+        /** data_3 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance code register 3 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 3 and when
+         *  software initiate read operation, it is rx data register 3.
+         */
+        uint32_t data_3:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_3_reg_t;
+
+/** Type of data_4 register
+ *  Data register 4.
+ */
+typedef union {
+    struct {
+        /** data_4 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance mask register 0 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 4 and when
+         *  software initiate read operation, it is rx data register 4.
+         */
+        uint32_t data_4:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_4_reg_t;
+
+/** Type of data_5 register
+ *  Data register 5.
+ */
+typedef union {
+    struct {
+        /** data_5 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance mask register 1 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 5 and when
+         *  software initiate read operation, it is rx data register 5.
+         */
+        uint32_t data_5:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_5_reg_t;
+
+/** Type of data_6 register
+ *  Data register 6.
+ */
+typedef union {
+    struct {
+        /** data_6 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance mask register 2 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 6 and when
+         *  software initiate read operation, it is rx data register 6.
+         */
+        uint32_t data_6:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_6_reg_t;
+
+/** Type of data_7 register
+ *  Data register 7.
+ */
+typedef union {
+    struct {
+        /** data_7 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance mask register 3 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 7 and when
+         *  software initiate read operation, it is rx data register 7.
+         */
+        uint32_t data_7:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_7_reg_t;
+
+/** Type of data_8 register
+ *  Data register 8.
+ */
+typedef union {
+    struct {
+        /** data_8 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, reserved with RO. In operation mode, when software initiate write
+         *  operation, it is tx data register 8 and when software initiate read operation, it
+         *  is rx data register 8.
+         */
+        uint32_t data_8:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_8_reg_t;
+
+/** Type of data_9 register
+ *  Data register 9.
+ */
+typedef union {
+    struct {
+        /** data_9 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, reserved with RO. In operation mode, when software initiate write
+         *  operation, it is tx data register 9 and when software initiate read operation, it
+         *  is rx data register 9.
+         */
+        uint32_t data_9:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_9_reg_t;
+
+/** Type of data_10 register
+ *  Data register 10.
+ */
+typedef union {
+    struct {
+        /** data_10 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, reserved with RO. In operation mode, when software initiate write
+         *  operation, it is tx data register 10 and when software initiate read operation, it
+         *  is rx data register 10.
+         */
+        uint32_t data_10:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_10_reg_t;
+
+/** Type of data_11 register
+ *  Data register 11.
+ */
+typedef union {
+    struct {
+        /** data_11 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, reserved with RO. In operation mode, when software initiate write
+         *  operation, it is tx data register 11 and when software initiate read operation, it
+         *  is rx data register 11.
+         */
+        uint32_t data_11:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_11_reg_t;
+
+/** Type of data_12 register
+ *  Data register 12.
+ */
+typedef union {
+    struct {
+        /** data_12 : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, reserved with RO. In operation mode, when software initiate write
+         *  operation, it is tx data register 12 and when software initiate read operation, it
+         *  is rx data register 12.
+         */
+        uint32_t data_12:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_data_12_reg_t;
+
+
+/** Group: Timestamp Register */
+/** Type of timestamp_data register
+ *  Timestamp data register
+ */
+typedef union {
+    struct {
+        /** timestamp_data : RO; bitpos: [31:0]; default: 0;
+         *  Data of timestamp of a CAN frame.
+         */
+        uint32_t timestamp_data:32;
+    };
+    uint32_t val;
+} twai_timestamp_data_reg_t;
+
+/** Type of timestamp_prescaler register
+ *  Timestamp configuration register
+ */
+typedef union {
+    struct {
+        /** ts_div_num : R/W; bitpos: [15:0]; default: 31;
+         *  Configures the clock division number of timestamp counter.
+         */
+        uint32_t ts_div_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} twai_timestamp_prescaler_reg_t;
+
+/** Type of timestamp_cfg register
+ *  Timestamp configuration register
+ */
+typedef union {
+    struct {
+        /** ts_enable : R/W; bitpos: [0]; default: 0;
+         *  enable the timestamp collection function.
+         */
+        uint32_t ts_enable:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} twai_timestamp_cfg_reg_t;
+
+
+typedef struct {
+    volatile twai_mode_reg_t mode;
+    volatile twai_cmd_reg_t cmd;
+    volatile twai_status_reg_t status;
+    volatile twai_interrupt_reg_t interrupt;
+    volatile twai_interrupt_enable_reg_t interrupt_enable;
+    uint32_t reserved_014;
+    volatile twai_bus_timing_0_reg_t bus_timing_0;
+    volatile twai_bus_timing_1_reg_t bus_timing_1;
+    uint32_t reserved_020[3];
+    volatile twai_arb_lost_cap_reg_t arb_lost_cap;
+    volatile twai_err_code_cap_reg_t err_code_cap;
+    volatile twai_err_warning_limit_reg_t err_warning_limit;
+    volatile twai_rx_err_cnt_reg_t rx_err_cnt;
+    volatile twai_tx_err_cnt_reg_t tx_err_cnt;
+    volatile twai_data_0_reg_t data_0;
+    volatile twai_data_1_reg_t data_1;
+    volatile twai_data_2_reg_t data_2;
+    volatile twai_data_3_reg_t data_3;
+    volatile twai_data_4_reg_t data_4;
+    volatile twai_data_5_reg_t data_5;
+    volatile twai_data_6_reg_t data_6;
+    volatile twai_data_7_reg_t data_7;
+    volatile twai_data_8_reg_t data_8;
+    volatile twai_data_9_reg_t data_9;
+    volatile twai_data_10_reg_t data_10;
+    volatile twai_data_11_reg_t data_11;
+    volatile twai_data_12_reg_t data_12;
+    volatile twai_rx_message_counter_reg_t rx_message_counter;
+    uint32_t reserved_078;
+    volatile twai_clock_divider_reg_t clock_divider;
+    volatile twai_sw_standby_cfg_reg_t sw_standby_cfg;
+    volatile twai_hw_cfg_reg_t hw_cfg;
+    volatile twai_hw_standby_cnt_reg_t hw_standby_cnt;
+    volatile twai_idle_intr_cnt_reg_t idle_intr_cnt;
+    volatile twai_eco_cfg_reg_t eco_cfg;
+    volatile twai_timestamp_data_reg_t timestamp_data;
+    volatile twai_timestamp_prescaler_reg_t timestamp_prescaler;
+    volatile twai_timestamp_cfg_reg_t timestamp_cfg;
+} twai_dev_t;
+
+extern twai_dev_t TWAI0;
+extern twai_dev_t TWAI1;
+extern twai_dev_t TWAI2;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(twai_dev_t) == 0xa0, "Invalid size of twai_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/twai_reg.h

@@ -0,0 +1,791 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TWAI_MODE_REG register
+ *  TWAI mode register.
+ */
+#define TWAI_MODE_REG(i) (DR_REG_TWAI_BASE(i) + 0x0)
+/** TWAI_RESET_MODE : R/W; bitpos: [0]; default: 1;
+ *  1: reset, detection of a set reset mode bit results in aborting the current
+ *  transmission/reception of a message and entering the reset mode. 0: normal, on the
+ *  '1-to-0' transition of the reset mode bit, the TWAI controller returns to the
+ *  operating mode.
+ */
+#define TWAI_RESET_MODE    (BIT(0))
+#define TWAI_RESET_MODE_M  (TWAI_RESET_MODE_V << TWAI_RESET_MODE_S)
+#define TWAI_RESET_MODE_V  0x00000001U
+#define TWAI_RESET_MODE_S  0
+/** TWAI_LISTEN_ONLY_MODE : R/W; bitpos: [1]; default: 0;
+ *  1: listen only, in this mode the TWAI controller would give no acknowledge to the
+ *  TWAI-bus, even if a message is received successfully. The error counters are
+ *  stopped at the current value. 0: normal.
+ */
+#define TWAI_LISTEN_ONLY_MODE    (BIT(1))
+#define TWAI_LISTEN_ONLY_MODE_M  (TWAI_LISTEN_ONLY_MODE_V << TWAI_LISTEN_ONLY_MODE_S)
+#define TWAI_LISTEN_ONLY_MODE_V  0x00000001U
+#define TWAI_LISTEN_ONLY_MODE_S  1
+/** TWAI_SELF_TEST_MODE : R/W; bitpos: [2]; default: 0;
+ *  1: self test, in this mode a full node test is possible without any other active
+ *  node on the bus using the self reception request command. The TWAI controller will
+ *  perform a successful transmission, even if there is no acknowledge received. 0:
+ *  normal, an acknowledge is required for successful transmission.
+ */
+#define TWAI_SELF_TEST_MODE    (BIT(2))
+#define TWAI_SELF_TEST_MODE_M  (TWAI_SELF_TEST_MODE_V << TWAI_SELF_TEST_MODE_S)
+#define TWAI_SELF_TEST_MODE_V  0x00000001U
+#define TWAI_SELF_TEST_MODE_S  2
+/** TWAI_ACCEPTANCE_FILTER_MODE : R/W; bitpos: [3]; default: 0;
+ *  1:single, the single acceptance filter option is enabled (one filter with the
+ *  length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled
+ *  (two filters, each with the length of 16 bit are active).
+ */
+#define TWAI_ACCEPTANCE_FILTER_MODE    (BIT(3))
+#define TWAI_ACCEPTANCE_FILTER_MODE_M  (TWAI_ACCEPTANCE_FILTER_MODE_V << TWAI_ACCEPTANCE_FILTER_MODE_S)
+#define TWAI_ACCEPTANCE_FILTER_MODE_V  0x00000001U
+#define TWAI_ACCEPTANCE_FILTER_MODE_S  3
+
+/** TWAI_CMD_REG register
+ *  TWAI command register.
+ */
+#define TWAI_CMD_REG(i) (DR_REG_TWAI_BASE(i) + 0x4)
+/** TWAI_TX_REQUEST : WO; bitpos: [0]; default: 0;
+ *  1: present, a message shall be transmitted. 0: absent
+ */
+#define TWAI_TX_REQUEST    (BIT(0))
+#define TWAI_TX_REQUEST_M  (TWAI_TX_REQUEST_V << TWAI_TX_REQUEST_S)
+#define TWAI_TX_REQUEST_V  0x00000001U
+#define TWAI_TX_REQUEST_S  0
+/** TWAI_ABORT_TX : WO; bitpos: [1]; default: 0;
+ *  1: present, if not already in progress, a pending transmission request is
+ *  cancelled. 0: absent
+ */
+#define TWAI_ABORT_TX    (BIT(1))
+#define TWAI_ABORT_TX_M  (TWAI_ABORT_TX_V << TWAI_ABORT_TX_S)
+#define TWAI_ABORT_TX_V  0x00000001U
+#define TWAI_ABORT_TX_S  1
+/** TWAI_RELEASE_BUFFER : WO; bitpos: [2]; default: 0;
+ *  1: released, the receive buffer, representing the message memory space in the
+ *  RXFIFO is released. 0: no action
+ */
+#define TWAI_RELEASE_BUFFER    (BIT(2))
+#define TWAI_RELEASE_BUFFER_M  (TWAI_RELEASE_BUFFER_V << TWAI_RELEASE_BUFFER_S)
+#define TWAI_RELEASE_BUFFER_V  0x00000001U
+#define TWAI_RELEASE_BUFFER_S  2
+/** TWAI_CLEAR_DATA_OVERRUN : WO; bitpos: [3]; default: 0;
+ *  1: clear, the data overrun status bit is cleared. 0: no action.
+ */
+#define TWAI_CLEAR_DATA_OVERRUN    (BIT(3))
+#define TWAI_CLEAR_DATA_OVERRUN_M  (TWAI_CLEAR_DATA_OVERRUN_V << TWAI_CLEAR_DATA_OVERRUN_S)
+#define TWAI_CLEAR_DATA_OVERRUN_V  0x00000001U
+#define TWAI_CLEAR_DATA_OVERRUN_S  3
+/** TWAI_SELF_RX_REQUEST : WO; bitpos: [4]; default: 0;
+ *  1: present, a message shall be transmitted and received simultaneously. 0: absent.
+ */
+#define TWAI_SELF_RX_REQUEST    (BIT(4))
+#define TWAI_SELF_RX_REQUEST_M  (TWAI_SELF_RX_REQUEST_V << TWAI_SELF_RX_REQUEST_S)
+#define TWAI_SELF_RX_REQUEST_V  0x00000001U
+#define TWAI_SELF_RX_REQUEST_S  4
+
+/** TWAI_STATUS_REG register
+ *  TWAI status register.
+ */
+#define TWAI_STATUS_REG(i) (DR_REG_TWAI_BASE(i) + 0x8)
+/** TWAI_STATUS_RECEIVE_BUFFER : RO; bitpos: [0]; default: 0;
+ *  1: full, one or more complete messages are available in the RXFIFO. 0: empty, no
+ *  message is available
+ */
+#define TWAI_STATUS_RECEIVE_BUFFER    (BIT(0))
+#define TWAI_STATUS_RECEIVE_BUFFER_M  (TWAI_STATUS_RECEIVE_BUFFER_V << TWAI_STATUS_RECEIVE_BUFFER_S)
+#define TWAI_STATUS_RECEIVE_BUFFER_V  0x00000001U
+#define TWAI_STATUS_RECEIVE_BUFFER_S  0
+/** TWAI_STATUS_OVERRUN : RO; bitpos: [1]; default: 0;
+ *  1: overrun, a message was lost because there was not enough space for that message
+ *  in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data
+ *  overrun command was given
+ */
+#define TWAI_STATUS_OVERRUN    (BIT(1))
+#define TWAI_STATUS_OVERRUN_M  (TWAI_STATUS_OVERRUN_V << TWAI_STATUS_OVERRUN_S)
+#define TWAI_STATUS_OVERRUN_V  0x00000001U
+#define TWAI_STATUS_OVERRUN_S  1
+/** TWAI_STATUS_TRANSMIT_BUFFER : RO; bitpos: [2]; default: 0;
+ *  1: released, the CPU may write a message into the transmit buffer. 0: locked, the
+ *  CPU cannot access the transmit buffer, a message is either waiting for transmission
+ *  or is in the process of being transmitted
+ */
+#define TWAI_STATUS_TRANSMIT_BUFFER    (BIT(2))
+#define TWAI_STATUS_TRANSMIT_BUFFER_M  (TWAI_STATUS_TRANSMIT_BUFFER_V << TWAI_STATUS_TRANSMIT_BUFFER_S)
+#define TWAI_STATUS_TRANSMIT_BUFFER_V  0x00000001U
+#define TWAI_STATUS_TRANSMIT_BUFFER_S  2
+/** TWAI_STATUS_TRANSMISSION_COMPLETE : RO; bitpos: [3]; default: 0;
+ *  1: complete, last requested transmission has been successfully completed. 0:
+ *  incomplete, previously requested transmission is not yet completed
+ */
+#define TWAI_STATUS_TRANSMISSION_COMPLETE    (BIT(3))
+#define TWAI_STATUS_TRANSMISSION_COMPLETE_M  (TWAI_STATUS_TRANSMISSION_COMPLETE_V << TWAI_STATUS_TRANSMISSION_COMPLETE_S)
+#define TWAI_STATUS_TRANSMISSION_COMPLETE_V  0x00000001U
+#define TWAI_STATUS_TRANSMISSION_COMPLETE_S  3
+/** TWAI_STATUS_RECEIVE : RO; bitpos: [4]; default: 0;
+ *  1: receive, the TWAI controller is receiving a message. 0: idle
+ */
+#define TWAI_STATUS_RECEIVE    (BIT(4))
+#define TWAI_STATUS_RECEIVE_M  (TWAI_STATUS_RECEIVE_V << TWAI_STATUS_RECEIVE_S)
+#define TWAI_STATUS_RECEIVE_V  0x00000001U
+#define TWAI_STATUS_RECEIVE_S  4
+/** TWAI_STATUS_TRANSMIT : RO; bitpos: [5]; default: 0;
+ *  1: transmit, the TWAI controller is transmitting a message. 0: idle
+ */
+#define TWAI_STATUS_TRANSMIT    (BIT(5))
+#define TWAI_STATUS_TRANSMIT_M  (TWAI_STATUS_TRANSMIT_V << TWAI_STATUS_TRANSMIT_S)
+#define TWAI_STATUS_TRANSMIT_V  0x00000001U
+#define TWAI_STATUS_TRANSMIT_S  5
+/** TWAI_STATUS_ERR : RO; bitpos: [6]; default: 0;
+ *  1: error, at least one of the error counters has reached or exceeded the CPU
+ *  warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error
+ *  counters are below the warning limit
+ */
+#define TWAI_STATUS_ERR    (BIT(6))
+#define TWAI_STATUS_ERR_M  (TWAI_STATUS_ERR_V << TWAI_STATUS_ERR_S)
+#define TWAI_STATUS_ERR_V  0x00000001U
+#define TWAI_STATUS_ERR_S  6
+/** TWAI_STATUS_NODE_BUS_OFF : RO; bitpos: [7]; default: 0;
+ *  1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the
+ *  TWAI controller is involved in bus activities
+ */
+#define TWAI_STATUS_NODE_BUS_OFF    (BIT(7))
+#define TWAI_STATUS_NODE_BUS_OFF_M  (TWAI_STATUS_NODE_BUS_OFF_V << TWAI_STATUS_NODE_BUS_OFF_S)
+#define TWAI_STATUS_NODE_BUS_OFF_V  0x00000001U
+#define TWAI_STATUS_NODE_BUS_OFF_S  7
+/** TWAI_STATUS_MISS : RO; bitpos: [8]; default: 0;
+ *  1: current message is destroyed because of FIFO overflow.
+ */
+#define TWAI_STATUS_MISS    (BIT(8))
+#define TWAI_STATUS_MISS_M  (TWAI_STATUS_MISS_V << TWAI_STATUS_MISS_S)
+#define TWAI_STATUS_MISS_V  0x00000001U
+#define TWAI_STATUS_MISS_S  8
+
+/** TWAI_INTERRUPT_REG register
+ *  Interrupt signals' register.
+ */
+#define TWAI_INTERRUPT_REG(i) (DR_REG_TWAI_BASE(i) + 0xc)
+/** TWAI_RECEIVE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  1: this bit is set while the receive FIFO is not empty and the RIE bit is set
+ *  within the interrupt enable register. 0: reset
+ */
+#define TWAI_RECEIVE_INT_ST    (BIT(0))
+#define TWAI_RECEIVE_INT_ST_M  (TWAI_RECEIVE_INT_ST_V << TWAI_RECEIVE_INT_ST_S)
+#define TWAI_RECEIVE_INT_ST_V  0x00000001U
+#define TWAI_RECEIVE_INT_ST_S  0
+/** TWAI_TRANSMIT_INT_ST : RO; bitpos: [1]; default: 0;
+ *  1: this bit is set whenever the transmit buffer status changes from '0-to-1'
+ *  (released) and the TIE bit is set within the interrupt enable register. 0: reset
+ */
+#define TWAI_TRANSMIT_INT_ST    (BIT(1))
+#define TWAI_TRANSMIT_INT_ST_M  (TWAI_TRANSMIT_INT_ST_V << TWAI_TRANSMIT_INT_ST_S)
+#define TWAI_TRANSMIT_INT_ST_V  0x00000001U
+#define TWAI_TRANSMIT_INT_ST_S  1
+/** TWAI_ERR_WARNING_INT_ST : RO; bitpos: [2]; default: 0;
+ *  1: this bit is set on every change (set and clear) of either the error status or
+ *  bus status bits and the EIE bit is set within the interrupt enable register. 0:
+ *  reset
+ */
+#define TWAI_ERR_WARNING_INT_ST    (BIT(2))
+#define TWAI_ERR_WARNING_INT_ST_M  (TWAI_ERR_WARNING_INT_ST_V << TWAI_ERR_WARNING_INT_ST_S)
+#define TWAI_ERR_WARNING_INT_ST_V  0x00000001U
+#define TWAI_ERR_WARNING_INT_ST_S  2
+/** TWAI_DATA_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0;
+ *  1: this bit is set on a '0-to-1' transition of the data overrun status bit and the
+ *  DOIE bit is set within the interrupt enable register. 0: reset
+ */
+#define TWAI_DATA_OVERRUN_INT_ST    (BIT(3))
+#define TWAI_DATA_OVERRUN_INT_ST_M  (TWAI_DATA_OVERRUN_INT_ST_V << TWAI_DATA_OVERRUN_INT_ST_S)
+#define TWAI_DATA_OVERRUN_INT_ST_V  0x00000001U
+#define TWAI_DATA_OVERRUN_INT_ST_S  3
+/** TWAI_TS_COUNTER_OVFL_INT_ST : RO; bitpos: [4]; default: 0;
+ *  1: this bit is set then the timestamp counter reaches the maximum value and
+ *  overflow.
+ */
+#define TWAI_TS_COUNTER_OVFL_INT_ST    (BIT(4))
+#define TWAI_TS_COUNTER_OVFL_INT_ST_M  (TWAI_TS_COUNTER_OVFL_INT_ST_V << TWAI_TS_COUNTER_OVFL_INT_ST_S)
+#define TWAI_TS_COUNTER_OVFL_INT_ST_V  0x00000001U
+#define TWAI_TS_COUNTER_OVFL_INT_ST_S  4
+/** TWAI_ERR_PASSIVE_INT_ST : RO; bitpos: [5]; default: 0;
+ *  1: this bit is set whenever the TWAI controller has reached the error passive
+ *  status (at least one error counter exceeds the protocol-defined level of 127) or if
+ *  the TWAI controller is in the error passive status and enters the error active
+ *  status again and the EPIE bit is set within the interrupt enable register. 0: reset
+ */
+#define TWAI_ERR_PASSIVE_INT_ST    (BIT(5))
+#define TWAI_ERR_PASSIVE_INT_ST_M  (TWAI_ERR_PASSIVE_INT_ST_V << TWAI_ERR_PASSIVE_INT_ST_S)
+#define TWAI_ERR_PASSIVE_INT_ST_V  0x00000001U
+#define TWAI_ERR_PASSIVE_INT_ST_S  5
+/** TWAI_ARBITRATION_LOST_INT_ST : RO; bitpos: [6]; default: 0;
+ *  1: this bit is set when the TWAI controller lost the arbitration and becomes a
+ *  receiver and the ALIE bit is set within the interrupt enable register. 0: reset
+ */
+#define TWAI_ARBITRATION_LOST_INT_ST    (BIT(6))
+#define TWAI_ARBITRATION_LOST_INT_ST_M  (TWAI_ARBITRATION_LOST_INT_ST_V << TWAI_ARBITRATION_LOST_INT_ST_S)
+#define TWAI_ARBITRATION_LOST_INT_ST_V  0x00000001U
+#define TWAI_ARBITRATION_LOST_INT_ST_S  6
+/** TWAI_BUS_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  1: this bit is set when the TWAI controller detects an error on the TWAI-bus and
+ *  the BEIE bit is set within the interrupt enable register. 0: reset
+ */
+#define TWAI_BUS_ERR_INT_ST    (BIT(7))
+#define TWAI_BUS_ERR_INT_ST_M  (TWAI_BUS_ERR_INT_ST_V << TWAI_BUS_ERR_INT_ST_S)
+#define TWAI_BUS_ERR_INT_ST_V  0x00000001U
+#define TWAI_BUS_ERR_INT_ST_S  7
+/** TWAI_IDLE_INT_ST : RO; bitpos: [8]; default: 0;
+ *  1: this bit is set when the TWAI controller detects state of TWAI become IDLE and
+ *  this interrupt enable bit is set within the interrupt enable register. 0: reset
+ */
+#define TWAI_IDLE_INT_ST    (BIT(8))
+#define TWAI_IDLE_INT_ST_M  (TWAI_IDLE_INT_ST_V << TWAI_IDLE_INT_ST_S)
+#define TWAI_IDLE_INT_ST_V  0x00000001U
+#define TWAI_IDLE_INT_ST_S  8
+
+/** TWAI_INTERRUPT_ENABLE_REG register
+ *  Interrupt enable register.
+ */
+#define TWAI_INTERRUPT_ENABLE_REG(i) (DR_REG_TWAI_BASE(i) + 0x10)
+/** TWAI_EXT_RECEIVE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  1: enabled, when the receive buffer status is 'full' the TWAI controller requests
+ *  the respective interrupt. 0: disable
+ */
+#define TWAI_EXT_RECEIVE_INT_ENA    (BIT(0))
+#define TWAI_EXT_RECEIVE_INT_ENA_M  (TWAI_EXT_RECEIVE_INT_ENA_V << TWAI_EXT_RECEIVE_INT_ENA_S)
+#define TWAI_EXT_RECEIVE_INT_ENA_V  0x00000001U
+#define TWAI_EXT_RECEIVE_INT_ENA_S  0
+/** TWAI_EXT_TRANSMIT_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  1: enabled, when a message has been successfully transmitted or the transmit buffer
+ *  is accessible again (e.g. after an abort transmission command), the TWAI controller
+ *  requests the respective interrupt. 0: disable
+ */
+#define TWAI_EXT_TRANSMIT_INT_ENA    (BIT(1))
+#define TWAI_EXT_TRANSMIT_INT_ENA_M  (TWAI_EXT_TRANSMIT_INT_ENA_V << TWAI_EXT_TRANSMIT_INT_ENA_S)
+#define TWAI_EXT_TRANSMIT_INT_ENA_V  0x00000001U
+#define TWAI_EXT_TRANSMIT_INT_ENA_S  1
+/** TWAI_EXT_ERR_WARNING_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  1: enabled, if the error or bus status change (see status register. Table 14), the
+ *  TWAI controllerrequests the respective interrupt. 0: disable
+ */
+#define TWAI_EXT_ERR_WARNING_INT_ENA    (BIT(2))
+#define TWAI_EXT_ERR_WARNING_INT_ENA_M  (TWAI_EXT_ERR_WARNING_INT_ENA_V << TWAI_EXT_ERR_WARNING_INT_ENA_S)
+#define TWAI_EXT_ERR_WARNING_INT_ENA_V  0x00000001U
+#define TWAI_EXT_ERR_WARNING_INT_ENA_S  2
+/** TWAI_EXT_DATA_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  1: enabled, if the data overrun status bit is set (see status register. Table 14),
+ *  the TWAI controllerrequests the respective interrupt. 0: disable
+ */
+#define TWAI_EXT_DATA_OVERRUN_INT_ENA    (BIT(3))
+#define TWAI_EXT_DATA_OVERRUN_INT_ENA_M  (TWAI_EXT_DATA_OVERRUN_INT_ENA_V << TWAI_EXT_DATA_OVERRUN_INT_ENA_S)
+#define TWAI_EXT_DATA_OVERRUN_INT_ENA_V  0x00000001U
+#define TWAI_EXT_DATA_OVERRUN_INT_ENA_S  3
+/** TWAI_TS_COUNTER_OVFL_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  enable the timestamp counter overflow interrupt request.
+ */
+#define TWAI_TS_COUNTER_OVFL_INT_ENA    (BIT(4))
+#define TWAI_TS_COUNTER_OVFL_INT_ENA_M  (TWAI_TS_COUNTER_OVFL_INT_ENA_V << TWAI_TS_COUNTER_OVFL_INT_ENA_S)
+#define TWAI_TS_COUNTER_OVFL_INT_ENA_V  0x00000001U
+#define TWAI_TS_COUNTER_OVFL_INT_ENA_S  4
+/** TWAI_ERR_PASSIVE_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  1: enabled, if the error status of the TWAI controller changes from error active to
+ *  error passive or vice versa, the respective interrupt is requested. 0: disable
+ */
+#define TWAI_ERR_PASSIVE_INT_ENA    (BIT(5))
+#define TWAI_ERR_PASSIVE_INT_ENA_M  (TWAI_ERR_PASSIVE_INT_ENA_V << TWAI_ERR_PASSIVE_INT_ENA_S)
+#define TWAI_ERR_PASSIVE_INT_ENA_V  0x00000001U
+#define TWAI_ERR_PASSIVE_INT_ENA_S  5
+/** TWAI_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  1: enabled, if the TWAI controller has lost arbitration, the respective interrupt
+ *  is requested. 0: disable
+ */
+#define TWAI_ARBITRATION_LOST_INT_ENA    (BIT(6))
+#define TWAI_ARBITRATION_LOST_INT_ENA_M  (TWAI_ARBITRATION_LOST_INT_ENA_V << TWAI_ARBITRATION_LOST_INT_ENA_S)
+#define TWAI_ARBITRATION_LOST_INT_ENA_V  0x00000001U
+#define TWAI_ARBITRATION_LOST_INT_ENA_S  6
+/** TWAI_BUS_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  1: enabled, if an bus error has been detected, the TWAI controller requests the
+ *  respective interrupt. 0: disable
+ */
+#define TWAI_BUS_ERR_INT_ENA    (BIT(7))
+#define TWAI_BUS_ERR_INT_ENA_M  (TWAI_BUS_ERR_INT_ENA_V << TWAI_BUS_ERR_INT_ENA_S)
+#define TWAI_BUS_ERR_INT_ENA_V  0x00000001U
+#define TWAI_BUS_ERR_INT_ENA_S  7
+/** TWAI_IDLE_INT_ENA : RO; bitpos: [8]; default: 0;
+ *  1: enabled, if state of TWAI become IDLE, the TWAI controller requests the
+ *  respective interrupt. 0: disable
+ */
+#define TWAI_IDLE_INT_ENA    (BIT(8))
+#define TWAI_IDLE_INT_ENA_M  (TWAI_IDLE_INT_ENA_V << TWAI_IDLE_INT_ENA_S)
+#define TWAI_IDLE_INT_ENA_V  0x00000001U
+#define TWAI_IDLE_INT_ENA_S  8
+
+/** TWAI_BUS_TIMING_0_REG register
+ *  Bit timing configuration register 0.
+ */
+#define TWAI_BUS_TIMING_0_REG(i) (DR_REG_TWAI_BASE(i) + 0x18)
+/** TWAI_BAUD_PRESC : R/W; bitpos: [13:0]; default: 0;
+ *  The period of the TWAI system clock is programmable and determines the individual
+ *  bit timing. Software has R/W permission in reset mode and RO permission in
+ *  operation mode.
+ */
+#define TWAI_BAUD_PRESC    0x00003FFFU
+#define TWAI_BAUD_PRESC_M  (TWAI_BAUD_PRESC_V << TWAI_BAUD_PRESC_S)
+#define TWAI_BAUD_PRESC_V  0x00003FFFU
+#define TWAI_BAUD_PRESC_S  0
+/** TWAI_SYNC_JUMP_WIDTH : R/W; bitpos: [15:14]; default: 0;
+ *  The synchronization jump width defines the maximum number of clock cycles a bit
+ *  period may be shortened or lengthened. Software has R/W permission in reset mode
+ *  and RO in operation mode.
+ */
+#define TWAI_SYNC_JUMP_WIDTH    0x00000003U
+#define TWAI_SYNC_JUMP_WIDTH_M  (TWAI_SYNC_JUMP_WIDTH_V << TWAI_SYNC_JUMP_WIDTH_S)
+#define TWAI_SYNC_JUMP_WIDTH_V  0x00000003U
+#define TWAI_SYNC_JUMP_WIDTH_S  14
+
+/** TWAI_BUS_TIMING_1_REG register
+ *  Bit timing configuration register 1.
+ */
+#define TWAI_BUS_TIMING_1_REG(i) (DR_REG_TWAI_BASE(i) + 0x1c)
+/** TWAI_TIME_SEGMENT1 : R/W; bitpos: [3:0]; default: 0;
+ *  The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in
+ *  reset mode and RO in operation mode.
+ */
+#define TWAI_TIME_SEGMENT1    0x0000000FU
+#define TWAI_TIME_SEGMENT1_M  (TWAI_TIME_SEGMENT1_V << TWAI_TIME_SEGMENT1_S)
+#define TWAI_TIME_SEGMENT1_V  0x0000000FU
+#define TWAI_TIME_SEGMENT1_S  0
+/** TWAI_TIME_SEGMENT2 : R/W; bitpos: [6:4]; default: 0;
+ *  The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in
+ *  reset mode and RO in operation mode.
+ */
+#define TWAI_TIME_SEGMENT2    0x00000007U
+#define TWAI_TIME_SEGMENT2_M  (TWAI_TIME_SEGMENT2_V << TWAI_TIME_SEGMENT2_S)
+#define TWAI_TIME_SEGMENT2_V  0x00000007U
+#define TWAI_TIME_SEGMENT2_S  4
+/** TWAI_TIME_SAMPLING : R/W; bitpos: [7]; default: 0;
+ *  1: triple, the bus is sampled three times. 0: single, the bus is sampled once.
+ *  Software has R/W permission in reset mode and RO in operation mode.
+ */
+#define TWAI_TIME_SAMPLING    (BIT(7))
+#define TWAI_TIME_SAMPLING_M  (TWAI_TIME_SAMPLING_V << TWAI_TIME_SAMPLING_S)
+#define TWAI_TIME_SAMPLING_V  0x00000001U
+#define TWAI_TIME_SAMPLING_S  7
+
+/** TWAI_ARB_LOST_CAP_REG register
+ *  TWAI arbiter lost capture register.
+ */
+#define TWAI_ARB_LOST_CAP_REG(i) (DR_REG_TWAI_BASE(i) + 0x2c)
+/** TWAI_ARBITRATION_LOST_CAPTURE : RO; bitpos: [4:0]; default: 0;
+ *  This register contains information about the bit position of losing arbitration.
+ */
+#define TWAI_ARBITRATION_LOST_CAPTURE    0x0000001FU
+#define TWAI_ARBITRATION_LOST_CAPTURE_M  (TWAI_ARBITRATION_LOST_CAPTURE_V << TWAI_ARBITRATION_LOST_CAPTURE_S)
+#define TWAI_ARBITRATION_LOST_CAPTURE_V  0x0000001FU
+#define TWAI_ARBITRATION_LOST_CAPTURE_S  0
+
+/** TWAI_ERR_CODE_CAP_REG register
+ *  TWAI error info capture register.
+ */
+#define TWAI_ERR_CODE_CAP_REG(i) (DR_REG_TWAI_BASE(i) + 0x30)
+/** TWAI_ERR_CAPTURE_CODE_SEGMENT : RO; bitpos: [4:0]; default: 0;
+ *  This register contains information about the location of errors on the bus.
+ */
+#define TWAI_ERR_CAPTURE_CODE_SEGMENT    0x0000001FU
+#define TWAI_ERR_CAPTURE_CODE_SEGMENT_M  (TWAI_ERR_CAPTURE_CODE_SEGMENT_V << TWAI_ERR_CAPTURE_CODE_SEGMENT_S)
+#define TWAI_ERR_CAPTURE_CODE_SEGMENT_V  0x0000001FU
+#define TWAI_ERR_CAPTURE_CODE_SEGMENT_S  0
+/** TWAI_ERR_CAPTURE_CODE_DIRECTION : RO; bitpos: [5]; default: 0;
+ *  1: RX, error occurred during reception. 0: TX, error occurred during transmission.
+ */
+#define TWAI_ERR_CAPTURE_CODE_DIRECTION    (BIT(5))
+#define TWAI_ERR_CAPTURE_CODE_DIRECTION_M  (TWAI_ERR_CAPTURE_CODE_DIRECTION_V << TWAI_ERR_CAPTURE_CODE_DIRECTION_S)
+#define TWAI_ERR_CAPTURE_CODE_DIRECTION_V  0x00000001U
+#define TWAI_ERR_CAPTURE_CODE_DIRECTION_S  5
+/** TWAI_ERR_CAPTURE_CODE_TYPE : RO; bitpos: [7:6]; default: 0;
+ *  00: bit error. 01: form error. 10:stuff error. 11:other type of error.
+ */
+#define TWAI_ERR_CAPTURE_CODE_TYPE    0x00000003U
+#define TWAI_ERR_CAPTURE_CODE_TYPE_M  (TWAI_ERR_CAPTURE_CODE_TYPE_V << TWAI_ERR_CAPTURE_CODE_TYPE_S)
+#define TWAI_ERR_CAPTURE_CODE_TYPE_V  0x00000003U
+#define TWAI_ERR_CAPTURE_CODE_TYPE_S  6
+
+/** TWAI_ERR_WARNING_LIMIT_REG register
+ *  TWAI error threshold configuration register.
+ */
+#define TWAI_ERR_WARNING_LIMIT_REG(i) (DR_REG_TWAI_BASE(i) + 0x34)
+/** TWAI_ERR_WARNING_LIMIT : R/W; bitpos: [7:0]; default: 96;
+ *  The threshold that trigger error warning interrupt when this interrupt is enabled.
+ *  Software has R/W permission in reset mode and RO in operation mode.
+ */
+#define TWAI_ERR_WARNING_LIMIT    0x000000FFU
+#define TWAI_ERR_WARNING_LIMIT_M  (TWAI_ERR_WARNING_LIMIT_V << TWAI_ERR_WARNING_LIMIT_S)
+#define TWAI_ERR_WARNING_LIMIT_V  0x000000FFU
+#define TWAI_ERR_WARNING_LIMIT_S  0
+
+/** TWAI_RX_ERR_CNT_REG register
+ *  Rx error counter register.
+ */
+#define TWAI_RX_ERR_CNT_REG(i) (DR_REG_TWAI_BASE(i) + 0x38)
+/** TWAI_RX_ERR_CNT : R/W; bitpos: [7:0]; default: 0;
+ *  The RX error counter register reflects the current value of the transmit error
+ *  counter. Software has R/W permission in reset mode and RO in operation mode.
+ */
+#define TWAI_RX_ERR_CNT    0x000000FFU
+#define TWAI_RX_ERR_CNT_M  (TWAI_RX_ERR_CNT_V << TWAI_RX_ERR_CNT_S)
+#define TWAI_RX_ERR_CNT_V  0x000000FFU
+#define TWAI_RX_ERR_CNT_S  0
+
+/** TWAI_TX_ERR_CNT_REG register
+ *  Tx error counter register.
+ */
+#define TWAI_TX_ERR_CNT_REG(i) (DR_REG_TWAI_BASE(i) + 0x3c)
+/** TWAI_TX_ERR_CNT : R/W; bitpos: [7:0]; default: 0;
+ *  The TX error counter register reflects the current value of the transmit error
+ *  counter. Software has R/W permission in reset mode and RO in operation mode.
+ */
+#define TWAI_TX_ERR_CNT    0x000000FFU
+#define TWAI_TX_ERR_CNT_M  (TWAI_TX_ERR_CNT_V << TWAI_TX_ERR_CNT_S)
+#define TWAI_TX_ERR_CNT_V  0x000000FFU
+#define TWAI_TX_ERR_CNT_S  0
+
+/** TWAI_DATA_0_REG register
+ *  Data register 0.
+ */
+#define TWAI_DATA_0_REG(i) (DR_REG_TWAI_BASE(i) + 0x40)
+/** TWAI_DATA_0 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance code register 0 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 0 and when
+ *  software initiate read operation, it is rx data register 0.
+ */
+#define TWAI_DATA_0    0x000000FFU
+#define TWAI_DATA_0_M  (TWAI_DATA_0_V << TWAI_DATA_0_S)
+#define TWAI_DATA_0_V  0x000000FFU
+#define TWAI_DATA_0_S  0
+
+/** TWAI_DATA_1_REG register
+ *  Data register 1.
+ */
+#define TWAI_DATA_1_REG(i) (DR_REG_TWAI_BASE(i) + 0x44)
+/** TWAI_DATA_1 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance code register 1 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 1 and when
+ *  software initiate read operation, it is rx data register 1.
+ */
+#define TWAI_DATA_1    0x000000FFU
+#define TWAI_DATA_1_M  (TWAI_DATA_1_V << TWAI_DATA_1_S)
+#define TWAI_DATA_1_V  0x000000FFU
+#define TWAI_DATA_1_S  0
+
+/** TWAI_DATA_2_REG register
+ *  Data register 2.
+ */
+#define TWAI_DATA_2_REG(i) (DR_REG_TWAI_BASE(i) + 0x48)
+/** TWAI_DATA_2 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance code register 2 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 2 and when
+ *  software initiate read operation, it is rx data register 2.
+ */
+#define TWAI_DATA_2    0x000000FFU
+#define TWAI_DATA_2_M  (TWAI_DATA_2_V << TWAI_DATA_2_S)
+#define TWAI_DATA_2_V  0x000000FFU
+#define TWAI_DATA_2_S  0
+
+/** TWAI_DATA_3_REG register
+ *  Data register 3.
+ */
+#define TWAI_DATA_3_REG(i) (DR_REG_TWAI_BASE(i) + 0x4c)
+/** TWAI_DATA_3 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance code register 3 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 3 and when
+ *  software initiate read operation, it is rx data register 3.
+ */
+#define TWAI_DATA_3    0x000000FFU
+#define TWAI_DATA_3_M  (TWAI_DATA_3_V << TWAI_DATA_3_S)
+#define TWAI_DATA_3_V  0x000000FFU
+#define TWAI_DATA_3_S  0
+
+/** TWAI_DATA_4_REG register
+ *  Data register 4.
+ */
+#define TWAI_DATA_4_REG(i) (DR_REG_TWAI_BASE(i) + 0x50)
+/** TWAI_DATA_4 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance mask register 0 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 4 and when
+ *  software initiate read operation, it is rx data register 4.
+ */
+#define TWAI_DATA_4    0x000000FFU
+#define TWAI_DATA_4_M  (TWAI_DATA_4_V << TWAI_DATA_4_S)
+#define TWAI_DATA_4_V  0x000000FFU
+#define TWAI_DATA_4_S  0
+
+/** TWAI_DATA_5_REG register
+ *  Data register 5.
+ */
+#define TWAI_DATA_5_REG(i) (DR_REG_TWAI_BASE(i) + 0x54)
+/** TWAI_DATA_5 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance mask register 1 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 5 and when
+ *  software initiate read operation, it is rx data register 5.
+ */
+#define TWAI_DATA_5    0x000000FFU
+#define TWAI_DATA_5_M  (TWAI_DATA_5_V << TWAI_DATA_5_S)
+#define TWAI_DATA_5_V  0x000000FFU
+#define TWAI_DATA_5_S  0
+
+/** TWAI_DATA_6_REG register
+ *  Data register 6.
+ */
+#define TWAI_DATA_6_REG(i) (DR_REG_TWAI_BASE(i) + 0x58)
+/** TWAI_DATA_6 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance mask register 2 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 6 and when
+ *  software initiate read operation, it is rx data register 6.
+ */
+#define TWAI_DATA_6    0x000000FFU
+#define TWAI_DATA_6_M  (TWAI_DATA_6_V << TWAI_DATA_6_S)
+#define TWAI_DATA_6_V  0x000000FFU
+#define TWAI_DATA_6_S  0
+
+/** TWAI_DATA_7_REG register
+ *  Data register 7.
+ */
+#define TWAI_DATA_7_REG(i) (DR_REG_TWAI_BASE(i) + 0x5c)
+/** TWAI_DATA_7 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance mask register 3 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 7 and when
+ *  software initiate read operation, it is rx data register 7.
+ */
+#define TWAI_DATA_7    0x000000FFU
+#define TWAI_DATA_7_M  (TWAI_DATA_7_V << TWAI_DATA_7_S)
+#define TWAI_DATA_7_V  0x000000FFU
+#define TWAI_DATA_7_S  0
+
+/** TWAI_DATA_8_REG register
+ *  Data register 8.
+ */
+#define TWAI_DATA_8_REG(i) (DR_REG_TWAI_BASE(i) + 0x60)
+/** TWAI_DATA_8 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, reserved with RO. In operation mode, when software initiate write
+ *  operation, it is tx data register 8 and when software initiate read operation, it
+ *  is rx data register 8.
+ */
+#define TWAI_DATA_8    0x000000FFU
+#define TWAI_DATA_8_M  (TWAI_DATA_8_V << TWAI_DATA_8_S)
+#define TWAI_DATA_8_V  0x000000FFU
+#define TWAI_DATA_8_S  0
+
+/** TWAI_DATA_9_REG register
+ *  Data register 9.
+ */
+#define TWAI_DATA_9_REG(i) (DR_REG_TWAI_BASE(i) + 0x64)
+/** TWAI_DATA_9 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, reserved with RO. In operation mode, when software initiate write
+ *  operation, it is tx data register 9 and when software initiate read operation, it
+ *  is rx data register 9.
+ */
+#define TWAI_DATA_9    0x000000FFU
+#define TWAI_DATA_9_M  (TWAI_DATA_9_V << TWAI_DATA_9_S)
+#define TWAI_DATA_9_V  0x000000FFU
+#define TWAI_DATA_9_S  0
+
+/** TWAI_DATA_10_REG register
+ *  Data register 10.
+ */
+#define TWAI_DATA_10_REG(i) (DR_REG_TWAI_BASE(i) + 0x68)
+/** TWAI_DATA_10 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, reserved with RO. In operation mode, when software initiate write
+ *  operation, it is tx data register 10 and when software initiate read operation, it
+ *  is rx data register 10.
+ */
+#define TWAI_DATA_10    0x000000FFU
+#define TWAI_DATA_10_M  (TWAI_DATA_10_V << TWAI_DATA_10_S)
+#define TWAI_DATA_10_V  0x000000FFU
+#define TWAI_DATA_10_S  0
+
+/** TWAI_DATA_11_REG register
+ *  Data register 11.
+ */
+#define TWAI_DATA_11_REG(i) (DR_REG_TWAI_BASE(i) + 0x6c)
+/** TWAI_DATA_11 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, reserved with RO. In operation mode, when software initiate write
+ *  operation, it is tx data register 11 and when software initiate read operation, it
+ *  is rx data register 11.
+ */
+#define TWAI_DATA_11    0x000000FFU
+#define TWAI_DATA_11_M  (TWAI_DATA_11_V << TWAI_DATA_11_S)
+#define TWAI_DATA_11_V  0x000000FFU
+#define TWAI_DATA_11_S  0
+
+/** TWAI_DATA_12_REG register
+ *  Data register 12.
+ */
+#define TWAI_DATA_12_REG(i) (DR_REG_TWAI_BASE(i) + 0x70)
+/** TWAI_DATA_12 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, reserved with RO. In operation mode, when software initiate write
+ *  operation, it is tx data register 12 and when software initiate read operation, it
+ *  is rx data register 12.
+ */
+#define TWAI_DATA_12    0x000000FFU
+#define TWAI_DATA_12_M  (TWAI_DATA_12_V << TWAI_DATA_12_S)
+#define TWAI_DATA_12_V  0x000000FFU
+#define TWAI_DATA_12_S  0
+
+/** TWAI_RX_MESSAGE_COUNTER_REG register
+ *  Received message counter register.
+ */
+#define TWAI_RX_MESSAGE_COUNTER_REG(i) (DR_REG_TWAI_BASE(i) + 0x74)
+/** TWAI_RX_MESSAGE_COUNTER : RO; bitpos: [6:0]; default: 0;
+ *  Reflects the number of messages available within the RXFIFO. The value is
+ *  incremented with each receive event and decremented by the release receive buffer
+ *  command.
+ */
+#define TWAI_RX_MESSAGE_COUNTER    0x0000007FU
+#define TWAI_RX_MESSAGE_COUNTER_M  (TWAI_RX_MESSAGE_COUNTER_V << TWAI_RX_MESSAGE_COUNTER_S)
+#define TWAI_RX_MESSAGE_COUNTER_V  0x0000007FU
+#define TWAI_RX_MESSAGE_COUNTER_S  0
+
+/** TWAI_CLOCK_DIVIDER_REG register
+ *  Clock divider register.
+ */
+#define TWAI_CLOCK_DIVIDER_REG(i) (DR_REG_TWAI_BASE(i) + 0x7c)
+/** TWAI_CD : R/W; bitpos: [7:0]; default: 0;
+ *  These bits are used to define the frequency at the external CLKOUT pin.
+ */
+#define TWAI_CD    0x000000FFU
+#define TWAI_CD_M  (TWAI_CD_V << TWAI_CD_S)
+#define TWAI_CD_V  0x000000FFU
+#define TWAI_CD_S  0
+/** TWAI_CLOCK_OFF : R/W; bitpos: [8]; default: 0;
+ *  1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has
+ *  R/W permission in reset mode and RO in operation mode.
+ */
+#define TWAI_CLOCK_OFF    (BIT(8))
+#define TWAI_CLOCK_OFF_M  (TWAI_CLOCK_OFF_V << TWAI_CLOCK_OFF_S)
+#define TWAI_CLOCK_OFF_V  0x00000001U
+#define TWAI_CLOCK_OFF_S  8
+
+/** TWAI_SW_STANDBY_CFG_REG register
+ *  Software configure standby pin directly.
+ */
+#define TWAI_SW_STANDBY_CFG_REG(i) (DR_REG_TWAI_BASE(i) + 0x80)
+/** TWAI_SW_STANDBY_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable standby pin.
+ */
+#define TWAI_SW_STANDBY_EN    (BIT(0))
+#define TWAI_SW_STANDBY_EN_M  (TWAI_SW_STANDBY_EN_V << TWAI_SW_STANDBY_EN_S)
+#define TWAI_SW_STANDBY_EN_V  0x00000001U
+#define TWAI_SW_STANDBY_EN_S  0
+/** TWAI_SW_STANDBY_CLR : R/W; bitpos: [1]; default: 1;
+ *  Clear standby pin.
+ */
+#define TWAI_SW_STANDBY_CLR    (BIT(1))
+#define TWAI_SW_STANDBY_CLR_M  (TWAI_SW_STANDBY_CLR_V << TWAI_SW_STANDBY_CLR_S)
+#define TWAI_SW_STANDBY_CLR_V  0x00000001U
+#define TWAI_SW_STANDBY_CLR_S  1
+
+/** TWAI_HW_CFG_REG register
+ *  Hardware configure standby pin.
+ */
+#define TWAI_HW_CFG_REG(i) (DR_REG_TWAI_BASE(i) + 0x84)
+/** TWAI_HW_STANDBY_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable function that hardware control standby pin.
+ */
+#define TWAI_HW_STANDBY_EN    (BIT(0))
+#define TWAI_HW_STANDBY_EN_M  (TWAI_HW_STANDBY_EN_V << TWAI_HW_STANDBY_EN_S)
+#define TWAI_HW_STANDBY_EN_V  0x00000001U
+#define TWAI_HW_STANDBY_EN_S  0
+
+/** TWAI_HW_STANDBY_CNT_REG register
+ *  Configure standby counter.
+ */
+#define TWAI_HW_STANDBY_CNT_REG(i) (DR_REG_TWAI_BASE(i) + 0x88)
+/** TWAI_STANDBY_WAIT_CNT : R/W; bitpos: [31:0]; default: 1;
+ *  Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN
+ *  is enabled.
+ */
+#define TWAI_STANDBY_WAIT_CNT    0xFFFFFFFFU
+#define TWAI_STANDBY_WAIT_CNT_M  (TWAI_STANDBY_WAIT_CNT_V << TWAI_STANDBY_WAIT_CNT_S)
+#define TWAI_STANDBY_WAIT_CNT_V  0xFFFFFFFFU
+#define TWAI_STANDBY_WAIT_CNT_S  0
+
+/** TWAI_IDLE_INTR_CNT_REG register
+ *  Configure idle interrupt counter.
+ */
+#define TWAI_IDLE_INTR_CNT_REG(i) (DR_REG_TWAI_BASE(i) + 0x8c)
+/** TWAI_IDLE_INTR_CNT : R/W; bitpos: [31:0]; default: 1;
+ *  Configure the number of cycles before triggering idle interrupt.
+ */
+#define TWAI_IDLE_INTR_CNT    0xFFFFFFFFU
+#define TWAI_IDLE_INTR_CNT_M  (TWAI_IDLE_INTR_CNT_V << TWAI_IDLE_INTR_CNT_S)
+#define TWAI_IDLE_INTR_CNT_V  0xFFFFFFFFU
+#define TWAI_IDLE_INTR_CNT_S  0
+
+/** TWAI_ECO_CFG_REG register
+ *  ECO configuration register.
+ */
+#define TWAI_ECO_CFG_REG(i) (DR_REG_TWAI_BASE(i) + 0x90)
+/** TWAI_RDN_ENA : R/W; bitpos: [0]; default: 0;
+ *  Enable eco module.
+ */
+#define TWAI_RDN_ENA    (BIT(0))
+#define TWAI_RDN_ENA_M  (TWAI_RDN_ENA_V << TWAI_RDN_ENA_S)
+#define TWAI_RDN_ENA_V  0x00000001U
+#define TWAI_RDN_ENA_S  0
+/** TWAI_RDN_RESULT : RO; bitpos: [1]; default: 1;
+ *  Output of eco module.
+ */
+#define TWAI_RDN_RESULT    (BIT(1))
+#define TWAI_RDN_RESULT_M  (TWAI_RDN_RESULT_V << TWAI_RDN_RESULT_S)
+#define TWAI_RDN_RESULT_V  0x00000001U
+#define TWAI_RDN_RESULT_S  1
+
+/** TWAI_TIMESTAMP_DATA_REG register
+ *  Timestamp data register
+ */
+#define TWAI_TIMESTAMP_DATA_REG(i) (DR_REG_TWAI_BASE(i) + 0x94)
+/** TWAI_TIMESTAMP_DATA : RO; bitpos: [31:0]; default: 0;
+ *  Data of timestamp of a CAN frame.
+ */
+#define TWAI_TIMESTAMP_DATA    0xFFFFFFFFU
+#define TWAI_TIMESTAMP_DATA_M  (TWAI_TIMESTAMP_DATA_V << TWAI_TIMESTAMP_DATA_S)
+#define TWAI_TIMESTAMP_DATA_V  0xFFFFFFFFU
+#define TWAI_TIMESTAMP_DATA_S  0
+
+/** TWAI_TIMESTAMP_PRESCALER_REG register
+ *  Timestamp configuration register
+ */
+#define TWAI_TIMESTAMP_PRESCALER_REG(i) (DR_REG_TWAI_BASE(i) + 0x98)
+/** TWAI_TS_DIV_NUM : R/W; bitpos: [15:0]; default: 31;
+ *  Configures the clock division number of timestamp counter.
+ */
+#define TWAI_TS_DIV_NUM    0x0000FFFFU
+#define TWAI_TS_DIV_NUM_M  (TWAI_TS_DIV_NUM_V << TWAI_TS_DIV_NUM_S)
+#define TWAI_TS_DIV_NUM_V  0x0000FFFFU
+#define TWAI_TS_DIV_NUM_S  0
+
+/** TWAI_TIMESTAMP_CFG_REG register
+ *  Timestamp configuration register
+ */
+#define TWAI_TIMESTAMP_CFG_REG(i) (DR_REG_TWAI_BASE(i) + 0x9c)
+/** TWAI_TS_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  enable the timestamp collection function.
+ */
+#define TWAI_TS_ENABLE    (BIT(0))
+#define TWAI_TS_ENABLE_M  (TWAI_TS_ENABLE_V << TWAI_TS_ENABLE_S)
+#define TWAI_TS_ENABLE_V  0x00000001U
+#define TWAI_TS_ENABLE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/twai_struct.h

@@ -0,0 +1,619 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of mode register
+ *  TWAI mode register.
+ */
+typedef union {
+    struct {
+        /** reset_mode : R/W; bitpos: [0]; default: 1;
+         *  1: reset, detection of a set reset mode bit results in aborting the current
+         *  transmission/reception of a message and entering the reset mode. 0: normal, on the
+         *  '1-to-0' transition of the reset mode bit, the TWAI controller returns to the
+         *  operating mode.
+         */
+        uint32_t reset_mode:1;
+        /** listen_only_mode : R/W; bitpos: [1]; default: 0;
+         *  1: listen only, in this mode the TWAI controller would give no acknowledge to the
+         *  TWAI-bus, even if a message is received successfully. The error counters are
+         *  stopped at the current value. 0: normal.
+         */
+        uint32_t listen_only_mode:1;
+        /** self_test_mode : R/W; bitpos: [2]; default: 0;
+         *  1: self test, in this mode a full node test is possible without any other active
+         *  node on the bus using the self reception request command. The TWAI controller will
+         *  perform a successful transmission, even if there is no acknowledge received. 0:
+         *  normal, an acknowledge is required for successful transmission.
+         */
+        uint32_t self_test_mode:1;
+        /** acceptance_filter_mode : R/W; bitpos: [3]; default: 0;
+         *  1:single, the single acceptance filter option is enabled (one filter with the
+         *  length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled
+         *  (two filters, each with the length of 16 bit are active).
+         */
+        uint32_t acceptance_filter_mode:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} twai_mode_reg_t;
+
+/** Type of cmd register
+ *  TWAI command register.
+ */
+typedef union {
+    struct {
+        /** tx_request : WO; bitpos: [0]; default: 0;
+         *  1: present, a message shall be transmitted. 0: absent
+         */
+        uint32_t tx_request:1;
+        /** abort_tx : WO; bitpos: [1]; default: 0;
+         *  1: present, if not already in progress, a pending transmission request is
+         *  cancelled. 0: absent
+         */
+        uint32_t abort_tx:1;
+        /** release_buffer : WO; bitpos: [2]; default: 0;
+         *  1: released, the receive buffer, representing the message memory space in the
+         *  RXFIFO is released. 0: no action
+         */
+        uint32_t release_buffer:1;
+        /** clear_data_overrun : WO; bitpos: [3]; default: 0;
+         *  1: clear, the data overrun status bit is cleared. 0: no action.
+         */
+        uint32_t clear_data_overrun:1;
+        /** self_rx_request : WO; bitpos: [4]; default: 0;
+         *  1: present, a message shall be transmitted and received simultaneously. 0: absent.
+         */
+        uint32_t self_rx_request:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} twai_cmd_reg_t;
+
+/** Type of bus_timing_0 register
+ *  Bit timing configuration register 0.
+ */
+typedef union {
+    struct {
+        /** baud_presc : R/W; bitpos: [13:0]; default: 0;
+         *  The period of the TWAI system clock is programmable and determines the individual
+         *  bit timing. Software has R/W permission in reset mode and RO permission in
+         *  operation mode.
+         */
+        uint32_t baud_presc:14;
+        /** sync_jump_width : R/W; bitpos: [15:14]; default: 0;
+         *  The synchronization jump width defines the maximum number of clock cycles a bit
+         *  period may be shortened or lengthened. Software has R/W permission in reset mode
+         *  and RO in operation mode.
+         */
+        uint32_t sync_jump_width:2;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} twai_bus_timing_0_reg_t;
+
+/** Type of bus_timing_1 register
+ *  Bit timing configuration register 1.
+ */
+typedef union {
+    struct {
+        /** time_segment1 : R/W; bitpos: [3:0]; default: 0;
+         *  The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in
+         *  reset mode and RO in operation mode.
+         */
+        uint32_t time_segment1:4;
+        /** time_segment2 : R/W; bitpos: [6:4]; default: 0;
+         *  The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in
+         *  reset mode and RO in operation mode.
+         */
+        uint32_t time_segment2:3;
+        /** time_sampling : R/W; bitpos: [7]; default: 0;
+         *  1: triple, the bus is sampled three times. 0: single, the bus is sampled once.
+         *  Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t time_sampling:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_bus_timing_1_reg_t;
+
+/** Type of err_warning_limit register
+ *  TWAI error threshold configuration register.
+ */
+typedef union {
+    struct {
+        /** err_warning_limit : R/W; bitpos: [7:0]; default: 96;
+         *  The threshold that trigger error warning interrupt when this interrupt is enabled.
+         *  Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t err_warning_limit:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_err_warning_limit_reg_t;
+
+/** Type of clock_divider register
+ *  Clock divider register.
+ */
+typedef union {
+    struct {
+        /** cd : R/W; bitpos: [7:0]; default: 0;
+         *  These bits are used to define the frequency at the external CLKOUT pin.
+         */
+        uint32_t cd:8;
+        /** clock_off : R/W; bitpos: [8]; default: 0;
+         *  1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has
+         *  R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t clock_off:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_clock_divider_reg_t;
+
+/** Type of sw_standby_cfg register
+ *  Software configure standby pin directly.
+ */
+typedef union {
+    struct {
+        /** sw_standby_en : R/W; bitpos: [0]; default: 0;
+         *  Enable standby pin.
+         */
+        uint32_t sw_standby_en:1;
+        /** sw_standby_clr : R/W; bitpos: [1]; default: 1;
+         *  Clear standby pin.
+         */
+        uint32_t sw_standby_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} twai_sw_standby_cfg_reg_t;
+
+/** Type of hw_cfg register
+ *  Hardware configure standby pin.
+ */
+typedef union {
+    struct {
+        /** hw_standby_en : R/W; bitpos: [0]; default: 0;
+         *  Enable function that hardware control standby pin.
+         */
+        uint32_t hw_standby_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} twai_hw_cfg_reg_t;
+
+/** Type of hw_standby_cnt register
+ *  Configure standby counter.
+ */
+typedef union {
+    struct {
+        /** standby_wait_cnt : R/W; bitpos: [31:0]; default: 1;
+         *  Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN
+         *  is enabled.
+         */
+        uint32_t standby_wait_cnt:32;
+    };
+    uint32_t val;
+} twai_hw_standby_cnt_reg_t;
+
+/** Type of idle_intr_cnt register
+ *  Configure idle interrupt counter.
+ */
+typedef union {
+    struct {
+        /** idle_intr_cnt : R/W; bitpos: [31:0]; default: 1;
+         *  Configure the number of cycles before triggering idle interrupt.
+         */
+        uint32_t idle_intr_cnt:32;
+    };
+    uint32_t val;
+} twai_idle_intr_cnt_reg_t;
+
+/** Type of eco_cfg register
+ *  ECO configuration register.
+ */
+typedef union {
+    struct {
+        /** rdn_ena : R/W; bitpos: [0]; default: 0;
+         *  Enable eco module.
+         */
+        uint32_t rdn_ena:1;
+        /** rdn_result : RO; bitpos: [1]; default: 1;
+         *  Output of eco module.
+         */
+        uint32_t rdn_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} twai_eco_cfg_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of status register
+ *  TWAI status register.
+ */
+typedef union {
+    struct {
+        /** status_receive_buffer : RO; bitpos: [0]; default: 0;
+         *  1: full, one or more complete messages are available in the RXFIFO. 0: empty, no
+         *  message is available
+         */
+        uint32_t status_receive_buffer:1;
+        /** status_overrun : RO; bitpos: [1]; default: 0;
+         *  1: overrun, a message was lost because there was not enough space for that message
+         *  in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data
+         *  overrun command was given
+         */
+        uint32_t status_overrun:1;
+        /** status_transmit_buffer : RO; bitpos: [2]; default: 0;
+         *  1: released, the CPU may write a message into the transmit buffer. 0: locked, the
+         *  CPU cannot access the transmit buffer, a message is either waiting for transmission
+         *  or is in the process of being transmitted
+         */
+        uint32_t status_transmit_buffer:1;
+        /** status_transmission_complete : RO; bitpos: [3]; default: 0;
+         *  1: complete, last requested transmission has been successfully completed. 0:
+         *  incomplete, previously requested transmission is not yet completed
+         */
+        uint32_t status_transmission_complete:1;
+        /** status_receive : RO; bitpos: [4]; default: 0;
+         *  1: receive, the TWAI controller is receiving a message. 0: idle
+         */
+        uint32_t status_receive:1;
+        /** status_transmit : RO; bitpos: [5]; default: 0;
+         *  1: transmit, the TWAI controller is transmitting a message. 0: idle
+         */
+        uint32_t status_transmit:1;
+        /** status_err : RO; bitpos: [6]; default: 0;
+         *  1: error, at least one of the error counters has reached or exceeded the CPU
+         *  warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error
+         *  counters are below the warning limit
+         */
+        uint32_t status_err:1;
+        /** status_node_bus_off : RO; bitpos: [7]; default: 0;
+         *  1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the
+         *  TWAI controller is involved in bus activities
+         */
+        uint32_t status_node_bus_off:1;
+        /** status_miss : RO; bitpos: [8]; default: 0;
+         *  1: current message is destroyed because of FIFO overflow.
+         */
+        uint32_t status_miss:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_status_reg_t;
+
+/** Type of arb_lost_cap register
+ *  TWAI arbiter lost capture register.
+ */
+typedef union {
+    struct {
+        /** arbitration_lost_capture : RO; bitpos: [4:0]; default: 0;
+         *  This register contains information about the bit position of losing arbitration.
+         */
+        uint32_t arbitration_lost_capture:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} twai_arb_lost_cap_reg_t;
+
+/** Type of err_code_cap register
+ *  TWAI error info capture register.
+ */
+typedef union {
+    struct {
+        /** err_capture_code_segment : RO; bitpos: [4:0]; default: 0;
+         *  This register contains information about the location of errors on the bus.
+         */
+        uint32_t err_capture_code_segment:5;
+        /** err_capture_code_direction : RO; bitpos: [5]; default: 0;
+         *  1: RX, error occurred during reception. 0: TX, error occurred during transmission.
+         */
+        uint32_t err_capture_code_direction:1;
+        /** err_capture_code_type : RO; bitpos: [7:6]; default: 0;
+         *  00: bit error. 01: form error. 10:stuff error. 11:other type of error.
+         */
+        uint32_t err_capture_code_type:2;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_err_code_cap_reg_t;
+
+/** Type of rx_err_cnt register
+ *  Rx error counter register.
+ */
+typedef union {
+    struct {
+        /** rx_err_cnt : R/W; bitpos: [7:0]; default: 0;
+         *  The RX error counter register reflects the current value of the transmit error
+         *  counter. Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t rx_err_cnt:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_rx_err_cnt_reg_t;
+
+/** Type of tx_err_cnt register
+ *  Tx error counter register.
+ */
+typedef union {
+    struct {
+        /** tx_err_cnt : R/W; bitpos: [7:0]; default: 0;
+         *  The TX error counter register reflects the current value of the transmit error
+         *  counter. Software has R/W permission in reset mode and RO in operation mode.
+         */
+        uint32_t tx_err_cnt:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_tx_err_cnt_reg_t;
+
+/** Type of rx_message_counter register
+ *  Received message counter register.
+ */
+typedef union {
+    struct {
+        /** rx_message_counter : RO; bitpos: [6:0]; default: 0;
+         *  Reflects the number of messages available within the RXFIFO. The value is
+         *  incremented with each receive event and decremented by the release receive buffer
+         *  command.
+         */
+        uint32_t rx_message_counter:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} twai_rx_message_counter_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of interrupt register
+ *  Interrupt signals' register.
+ */
+typedef union {
+    struct {
+        /** receive_int_st : RO; bitpos: [0]; default: 0;
+         *  1: this bit is set while the receive FIFO is not empty and the RIE bit is set
+         *  within the interrupt enable register. 0: reset
+         */
+        uint32_t receive_int_st:1;
+        /** transmit_int_st : RO; bitpos: [1]; default: 0;
+         *  1: this bit is set whenever the transmit buffer status changes from '0-to-1'
+         *  (released) and the TIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t transmit_int_st:1;
+        /** err_warning_int_st : RO; bitpos: [2]; default: 0;
+         *  1: this bit is set on every change (set and clear) of either the error status or
+         *  bus status bits and the EIE bit is set within the interrupt enable register. 0:
+         *  reset
+         */
+        uint32_t err_warning_int_st:1;
+        /** data_overrun_int_st : RO; bitpos: [3]; default: 0;
+         *  1: this bit is set on a '0-to-1' transition of the data overrun status bit and the
+         *  DOIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t data_overrun_int_st:1;
+        /** ts_counter_ovfl_int_st : RO; bitpos: [4]; default: 0;
+         *  1: this bit is set then the timestamp counter reaches the maximum value and
+         *  overflow.
+         */
+        uint32_t ts_counter_ovfl_int_st:1;
+        /** err_passive_int_st : RO; bitpos: [5]; default: 0;
+         *  1: this bit is set whenever the TWAI controller has reached the error passive
+         *  status (at least one error counter exceeds the protocol-defined level of 127) or if
+         *  the TWAI controller is in the error passive status and enters the error active
+         *  status again and the EPIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t err_passive_int_st:1;
+        /** arbitration_lost_int_st : RO; bitpos: [6]; default: 0;
+         *  1: this bit is set when the TWAI controller lost the arbitration and becomes a
+         *  receiver and the ALIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t arbitration_lost_int_st:1;
+        /** bus_err_int_st : RO; bitpos: [7]; default: 0;
+         *  1: this bit is set when the TWAI controller detects an error on the TWAI-bus and
+         *  the BEIE bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t bus_err_int_st:1;
+        /** idle_int_st : RO; bitpos: [8]; default: 0;
+         *  1: this bit is set when the TWAI controller detects state of TWAI become IDLE and
+         *  this interrupt enable bit is set within the interrupt enable register. 0: reset
+         */
+        uint32_t idle_int_st:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_interrupt_status_reg_t;
+
+/** Type of interrupt_enable register
+ *  Interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** ext_receive_int_ena : R/W; bitpos: [0]; default: 0;
+         *  1: enabled, when the receive buffer status is 'full' the TWAI controller requests
+         *  the respective interrupt. 0: disable
+         */
+        uint32_t ext_receive_int_ena:1;
+        /** ext_transmit_int_ena : R/W; bitpos: [1]; default: 0;
+         *  1: enabled, when a message has been successfully transmitted or the transmit buffer
+         *  is accessible again (e.g. after an abort transmission command), the TWAI controller
+         *  requests the respective interrupt. 0: disable
+         */
+        uint32_t ext_transmit_int_ena:1;
+        /** ext_err_warning_int_ena : R/W; bitpos: [2]; default: 0;
+         *  1: enabled, if the error or bus status change (see status register. Table 14), the
+         *  TWAI controllerrequests the respective interrupt. 0: disable
+         */
+        uint32_t ext_err_warning_int_ena:1;
+        /** ext_data_overrun_int_ena : R/W; bitpos: [3]; default: 0;
+         *  1: enabled, if the data overrun status bit is set (see status register. Table 14),
+         *  the TWAI controllerrequests the respective interrupt. 0: disable
+         */
+        uint32_t ext_data_overrun_int_ena:1;
+        /** ts_counter_ovfl_int_ena : R/W; bitpos: [4]; default: 0;
+         *  enable the timestamp counter overflow interrupt request.
+         */
+        uint32_t ts_counter_ovfl_int_ena:1;
+        /** err_passive_int_ena : R/W; bitpos: [5]; default: 0;
+         *  1: enabled, if the error status of the TWAI controller changes from error active to
+         *  error passive or vice versa, the respective interrupt is requested. 0: disable
+         */
+        uint32_t err_passive_int_ena:1;
+        /** arbitration_lost_int_ena : R/W; bitpos: [6]; default: 0;
+         *  1: enabled, if the TWAI controller has lost arbitration, the respective interrupt
+         *  is requested. 0: disable
+         */
+        uint32_t arbitration_lost_int_ena:1;
+        /** bus_err_int_ena : R/W; bitpos: [7]; default: 0;
+         *  1: enabled, if an bus error has been detected, the TWAI controller requests the
+         *  respective interrupt. 0: disable
+         */
+        uint32_t bus_err_int_ena:1;
+        /** idle_int_ena : RO; bitpos: [8]; default: 0;
+         *  1: enabled, if state of TWAI become IDLE, the TWAI controller requests the
+         *  respective interrupt. 0: disable
+         */
+        uint32_t idle_int_ena:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} twai_interrupt_enable_reg_t;
+
+
+/** Group: Data Registers */
+/** Type of buffer register
+ *  TX RX Buffer.
+ */
+typedef union {
+    struct {
+        /** byte : R/W; bitpos: [7:0]; default: 0;
+         *  In reset mode, it is acceptance code register 0 with R/W Permission. In operation
+         *  mode, when software initiate write operation, it is tx data register 0 and when
+         *  software initiate read operation, it is rx data register 0.
+         */
+        uint32_t byte:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} twai_tx_rx_buffer_reg_t;
+
+typedef struct {
+    union {
+        struct {
+            uint32_t byte: 8;           /* ACRx[7:0] Acceptance Code */
+            uint32_t reserved8: 24;     /* Internal Reserved */
+        };
+        uint32_t val;
+    } acr[4];
+    union {
+        struct {
+            uint32_t byte: 8;           /* AMRx[7:0] Acceptance Mask */
+            uint32_t reserved8: 24;     /* Internal Reserved */
+        };
+        uint32_t val;
+    } amr[4];
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+} acceptance_filter_reg_t;
+
+/** Group: Timestamp Register */
+/** Type of timestamp_data register
+ *  Timestamp data register
+ */
+typedef union {
+    struct {
+        /** timestamp_data : RO; bitpos: [31:0]; default: 0;
+         *  Data of timestamp of a CAN frame.
+         */
+        uint32_t timestamp_data:32;
+    };
+    uint32_t val;
+} twai_timestamp_data_reg_t;
+
+/** Type of timestamp_prescaler register
+ *  Timestamp configuration register
+ */
+typedef union {
+    struct {
+        /** ts_div_num : R/W; bitpos: [15:0]; default: 31;
+         *  Configures the clock division number of timestamp counter.
+         */
+        uint32_t ts_div_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} twai_timestamp_prescaler_reg_t;
+
+/** Type of timestamp_cfg register
+ *  Timestamp configuration register
+ */
+typedef union {
+    struct {
+        /** ts_enable : R/W; bitpos: [0]; default: 0;
+         *  enable the timestamp collection function.
+         */
+        uint32_t ts_enable:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} twai_timestamp_cfg_reg_t;
+
+
+typedef struct twai_dev_t {
+    volatile twai_mode_reg_t mode;
+    volatile twai_cmd_reg_t cmd;
+    volatile twai_status_reg_t status;
+    volatile twai_interrupt_status_reg_t interrupt_st;
+    volatile twai_interrupt_enable_reg_t interrupt_ena;
+    uint32_t reserved_014;
+    volatile twai_bus_timing_0_reg_t bus_timing_0;
+    volatile twai_bus_timing_1_reg_t bus_timing_1;
+    uint32_t reserved_020[3];
+    volatile twai_arb_lost_cap_reg_t arb_lost_cap;
+    volatile twai_err_code_cap_reg_t err_code_cap;
+    volatile twai_err_warning_limit_reg_t err_warning_limit;
+    volatile twai_rx_err_cnt_reg_t rx_err_cnt;
+    volatile twai_tx_err_cnt_reg_t tx_err_cnt;
+    volatile union {
+        acceptance_filter_reg_t acceptance_filter;
+        twai_tx_rx_buffer_reg_t tx_rx_buffer[13];
+    };
+    volatile twai_rx_message_counter_reg_t rx_message_counter;
+    uint32_t reserved_078;
+    volatile twai_clock_divider_reg_t clock_divider;
+    volatile twai_sw_standby_cfg_reg_t sw_standby_cfg;
+    volatile twai_hw_cfg_reg_t hw_cfg;
+    volatile twai_hw_standby_cnt_reg_t hw_standby_cnt;
+    volatile twai_idle_intr_cnt_reg_t idle_intr_cnt;
+    volatile twai_eco_cfg_reg_t eco_cfg;
+    volatile twai_timestamp_data_reg_t timestamp_data;
+    volatile twai_timestamp_prescaler_reg_t timestamp_prescaler;
+    volatile twai_timestamp_cfg_reg_t timestamp_cfg;
+} twai_dev_t;
+
+extern twai_dev_t TWAI0;
+extern twai_dev_t TWAI1;
+extern twai_dev_t TWAI2;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(twai_dev_t) == 0xa0, "Invalid size of twai_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/uhci_reg.h

@@ -0,0 +1,966 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** UHCI_CONF0_REG register
+ *  UHCI Configuration Register0
+ */
+#define UHCI_CONF0_REG (DR_REG_UHCI_BASE + 0x0)
+/** UHCI_TX_RST : R/W; bitpos: [0]; default: 0;
+ *  Write 1 then write 0 to this bit to reset decode state machine.
+ */
+#define UHCI_TX_RST    (BIT(0))
+#define UHCI_TX_RST_M  (UHCI_TX_RST_V << UHCI_TX_RST_S)
+#define UHCI_TX_RST_V  0x00000001U
+#define UHCI_TX_RST_S  0
+/** UHCI_RX_RST : R/W; bitpos: [1]; default: 0;
+ *  Write 1 then write 0 to this bit to reset encode state machine.
+ */
+#define UHCI_RX_RST    (BIT(1))
+#define UHCI_RX_RST_M  (UHCI_RX_RST_V << UHCI_RX_RST_S)
+#define UHCI_RX_RST_V  0x00000001U
+#define UHCI_RX_RST_S  1
+/** UHCI_UART_SEL : R/W; bitpos: [4:2]; default: 7;
+ *  Select which uart to connect with GDMA.
+ */
+#define UHCI_UART_SEL    0x00000007U
+#define UHCI_UART_SEL_M  (UHCI_UART_SEL_V << UHCI_UART_SEL_S)
+#define UHCI_UART_SEL_V  0x00000007U
+#define UHCI_UART_SEL_S  2
+/** UHCI_SEPER_EN : R/W; bitpos: [5]; default: 1;
+ *  Set this bit to separate the data frame using a special char.
+ */
+#define UHCI_SEPER_EN    (BIT(5))
+#define UHCI_SEPER_EN_M  (UHCI_SEPER_EN_V << UHCI_SEPER_EN_S)
+#define UHCI_SEPER_EN_V  0x00000001U
+#define UHCI_SEPER_EN_S  5
+/** UHCI_HEAD_EN : R/W; bitpos: [6]; default: 1;
+ *  Set this bit to encode the data packet with a formatting header.
+ */
+#define UHCI_HEAD_EN    (BIT(6))
+#define UHCI_HEAD_EN_M  (UHCI_HEAD_EN_V << UHCI_HEAD_EN_S)
+#define UHCI_HEAD_EN_V  0x00000001U
+#define UHCI_HEAD_EN_S  6
+/** UHCI_CRC_REC_EN : R/W; bitpos: [7]; default: 1;
+ *  Set this bit to enable UHCI to receive the 16 bit CRC.
+ */
+#define UHCI_CRC_REC_EN    (BIT(7))
+#define UHCI_CRC_REC_EN_M  (UHCI_CRC_REC_EN_V << UHCI_CRC_REC_EN_S)
+#define UHCI_CRC_REC_EN_V  0x00000001U
+#define UHCI_CRC_REC_EN_S  7
+/** UHCI_UART_IDLE_EOF_EN : R/W; bitpos: [8]; default: 0;
+ *  If this bit is set to 1 UHCI will end the payload receiving process when UART has
+ *  been in idle state.
+ */
+#define UHCI_UART_IDLE_EOF_EN    (BIT(8))
+#define UHCI_UART_IDLE_EOF_EN_M  (UHCI_UART_IDLE_EOF_EN_V << UHCI_UART_IDLE_EOF_EN_S)
+#define UHCI_UART_IDLE_EOF_EN_V  0x00000001U
+#define UHCI_UART_IDLE_EOF_EN_S  8
+/** UHCI_LEN_EOF_EN : R/W; bitpos: [9]; default: 1;
+ *  If this bit is set to 1 UHCI decoder receiving payload data is end when the
+ *  receiving byte count has reached the specified value. The value is payload length
+ *  indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
+ *  configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder
+ *  receiving payload data is end when 0xc0 is received.
+ */
+#define UHCI_LEN_EOF_EN    (BIT(9))
+#define UHCI_LEN_EOF_EN_M  (UHCI_LEN_EOF_EN_V << UHCI_LEN_EOF_EN_S)
+#define UHCI_LEN_EOF_EN_V  0x00000001U
+#define UHCI_LEN_EOF_EN_S  9
+/** UHCI_ENCODE_CRC_EN : R/W; bitpos: [10]; default: 1;
+ *  Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to
+ *  end of the payload.
+ */
+#define UHCI_ENCODE_CRC_EN    (BIT(10))
+#define UHCI_ENCODE_CRC_EN_M  (UHCI_ENCODE_CRC_EN_V << UHCI_ENCODE_CRC_EN_S)
+#define UHCI_ENCODE_CRC_EN_V  0x00000001U
+#define UHCI_ENCODE_CRC_EN_S  10
+/** UHCI_CLK_EN : R/W; bitpos: [11]; default: 0;
+ *  1'b1: Force clock on for register. 1'b0: Support clock only when application writes
+ *  registers.
+ */
+#define UHCI_CLK_EN    (BIT(11))
+#define UHCI_CLK_EN_M  (UHCI_CLK_EN_V << UHCI_CLK_EN_S)
+#define UHCI_CLK_EN_V  0x00000001U
+#define UHCI_CLK_EN_S  11
+/** UHCI_UART_RX_BRK_EOF_EN : R/W; bitpos: [12]; default: 0;
+ *  If this bit is set to 1 UHCI will end payload receive process when NULL frame is
+ *  received by UART.
+ */
+#define UHCI_UART_RX_BRK_EOF_EN    (BIT(12))
+#define UHCI_UART_RX_BRK_EOF_EN_M  (UHCI_UART_RX_BRK_EOF_EN_V << UHCI_UART_RX_BRK_EOF_EN_S)
+#define UHCI_UART_RX_BRK_EOF_EN_V  0x00000001U
+#define UHCI_UART_RX_BRK_EOF_EN_S  12
+
+/** UHCI_INT_RAW_REG register
+ *  UHCI Interrupt Raw Register
+ */
+#define UHCI_INT_RAW_REG (DR_REG_UHCI_BASE + 0x4)
+/** UHCI_RX_START_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when
+ *  delimiter is sent successfully.
+ */
+#define UHCI_RX_START_INT_RAW    (BIT(0))
+#define UHCI_RX_START_INT_RAW_M  (UHCI_RX_START_INT_RAW_V << UHCI_RX_START_INT_RAW_S)
+#define UHCI_RX_START_INT_RAW_V  0x00000001U
+#define UHCI_RX_START_INT_RAW_S  0
+/** UHCI_TX_START_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when
+ *  DMA detects delimiter.
+ */
+#define UHCI_TX_START_INT_RAW    (BIT(1))
+#define UHCI_TX_START_INT_RAW_M  (UHCI_TX_START_INT_RAW_V << UHCI_TX_START_INT_RAW_S)
+#define UHCI_TX_START_INT_RAW_V  0x00000001U
+#define UHCI_TX_START_INT_RAW_S  1
+/** UHCI_RX_HUNG_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when
+ *  the required time of DMA receiving data  exceeds the configuration value.
+ */
+#define UHCI_RX_HUNG_INT_RAW    (BIT(2))
+#define UHCI_RX_HUNG_INT_RAW_M  (UHCI_RX_HUNG_INT_RAW_V << UHCI_RX_HUNG_INT_RAW_S)
+#define UHCI_RX_HUNG_INT_RAW_V  0x00000001U
+#define UHCI_RX_HUNG_INT_RAW_S  2
+/** UHCI_TX_HUNG_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when
+ *  the required time of DMA reading RAM data  exceeds the configuration value.
+ */
+#define UHCI_TX_HUNG_INT_RAW    (BIT(3))
+#define UHCI_TX_HUNG_INT_RAW_M  (UHCI_TX_HUNG_INT_RAW_V << UHCI_TX_HUNG_INT_RAW_S)
+#define UHCI_TX_HUNG_INT_RAW_V  0x00000001U
+#define UHCI_TX_HUNG_INT_RAW_S  3
+/** UHCI_SEND_S_REG_Q_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered
+ *  when UHCI sends short packet successfully with single_send mode.
+ */
+#define UHCI_SEND_S_REG_Q_INT_RAW    (BIT(4))
+#define UHCI_SEND_S_REG_Q_INT_RAW_M  (UHCI_SEND_S_REG_Q_INT_RAW_V << UHCI_SEND_S_REG_Q_INT_RAW_S)
+#define UHCI_SEND_S_REG_Q_INT_RAW_V  0x00000001U
+#define UHCI_SEND_S_REG_Q_INT_RAW_S  4
+/** UHCI_SEND_A_REG_Q_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered
+ *  when UHCI sends short packet successfully with always_send mode.
+ */
+#define UHCI_SEND_A_REG_Q_INT_RAW    (BIT(5))
+#define UHCI_SEND_A_REG_Q_INT_RAW_M  (UHCI_SEND_A_REG_Q_INT_RAW_V << UHCI_SEND_A_REG_Q_INT_RAW_S)
+#define UHCI_SEND_A_REG_Q_INT_RAW_V  0x00000001U
+#define UHCI_SEND_A_REG_Q_INT_RAW_S  5
+/** UHCI_OUT_EOF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when
+ *  there are errors in EOF.
+ */
+#define UHCI_OUT_EOF_INT_RAW    (BIT(6))
+#define UHCI_OUT_EOF_INT_RAW_M  (UHCI_OUT_EOF_INT_RAW_V << UHCI_OUT_EOF_INT_RAW_S)
+#define UHCI_OUT_EOF_INT_RAW_V  0x00000001U
+#define UHCI_OUT_EOF_INT_RAW_S  6
+/** UHCI_APP_CTRL0_INT_RAW : R/W; bitpos: [7]; default: 0;
+ *  Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when
+ *  UHCI_APP_CTRL0_IN_SET is set to 1.
+ */
+#define UHCI_APP_CTRL0_INT_RAW    (BIT(7))
+#define UHCI_APP_CTRL0_INT_RAW_M  (UHCI_APP_CTRL0_INT_RAW_V << UHCI_APP_CTRL0_INT_RAW_S)
+#define UHCI_APP_CTRL0_INT_RAW_V  0x00000001U
+#define UHCI_APP_CTRL0_INT_RAW_S  7
+/** UHCI_APP_CTRL1_INT_RAW : R/W; bitpos: [8]; default: 0;
+ *  Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when
+ *  UHCI_APP_CTRL1_IN_SET is set to 1.
+ */
+#define UHCI_APP_CTRL1_INT_RAW    (BIT(8))
+#define UHCI_APP_CTRL1_INT_RAW_M  (UHCI_APP_CTRL1_INT_RAW_V << UHCI_APP_CTRL1_INT_RAW_S)
+#define UHCI_APP_CTRL1_INT_RAW_V  0x00000001U
+#define UHCI_APP_CTRL1_INT_RAW_S  8
+
+/** UHCI_INT_ST_REG register
+ *  UHCI Interrupt Status Register
+ */
+#define UHCI_INT_ST_REG (DR_REG_UHCI_BASE + 0x8)
+/** UHCI_RX_START_INT_ST : RO; bitpos: [0]; default: 0;
+ *  Indicates the interrupt status of UHCI_RX_START_INT.
+ */
+#define UHCI_RX_START_INT_ST    (BIT(0))
+#define UHCI_RX_START_INT_ST_M  (UHCI_RX_START_INT_ST_V << UHCI_RX_START_INT_ST_S)
+#define UHCI_RX_START_INT_ST_V  0x00000001U
+#define UHCI_RX_START_INT_ST_S  0
+/** UHCI_TX_START_INT_ST : RO; bitpos: [1]; default: 0;
+ *  Indicates the interrupt status of UHCI_TX_START_INT.
+ */
+#define UHCI_TX_START_INT_ST    (BIT(1))
+#define UHCI_TX_START_INT_ST_M  (UHCI_TX_START_INT_ST_V << UHCI_TX_START_INT_ST_S)
+#define UHCI_TX_START_INT_ST_V  0x00000001U
+#define UHCI_TX_START_INT_ST_S  1
+/** UHCI_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Indicates the interrupt status of UHCI_RX_HUNG_INT.
+ */
+#define UHCI_RX_HUNG_INT_ST    (BIT(2))
+#define UHCI_RX_HUNG_INT_ST_M  (UHCI_RX_HUNG_INT_ST_V << UHCI_RX_HUNG_INT_ST_S)
+#define UHCI_RX_HUNG_INT_ST_V  0x00000001U
+#define UHCI_RX_HUNG_INT_ST_S  2
+/** UHCI_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0;
+ *  Indicates the interrupt status of UHCI_TX_HUNG_INT.
+ */
+#define UHCI_TX_HUNG_INT_ST    (BIT(3))
+#define UHCI_TX_HUNG_INT_ST_M  (UHCI_TX_HUNG_INT_ST_V << UHCI_TX_HUNG_INT_ST_S)
+#define UHCI_TX_HUNG_INT_ST_V  0x00000001U
+#define UHCI_TX_HUNG_INT_ST_S  3
+/** UHCI_SEND_S_REG_Q_INT_ST : RO; bitpos: [4]; default: 0;
+ *  Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT.
+ */
+#define UHCI_SEND_S_REG_Q_INT_ST    (BIT(4))
+#define UHCI_SEND_S_REG_Q_INT_ST_M  (UHCI_SEND_S_REG_Q_INT_ST_V << UHCI_SEND_S_REG_Q_INT_ST_S)
+#define UHCI_SEND_S_REG_Q_INT_ST_V  0x00000001U
+#define UHCI_SEND_S_REG_Q_INT_ST_S  4
+/** UHCI_SEND_A_REG_Q_INT_ST : RO; bitpos: [5]; default: 0;
+ *  Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT.
+ */
+#define UHCI_SEND_A_REG_Q_INT_ST    (BIT(5))
+#define UHCI_SEND_A_REG_Q_INT_ST_M  (UHCI_SEND_A_REG_Q_INT_ST_V << UHCI_SEND_A_REG_Q_INT_ST_S)
+#define UHCI_SEND_A_REG_Q_INT_ST_V  0x00000001U
+#define UHCI_SEND_A_REG_Q_INT_ST_S  5
+/** UHCI_OUTLINK_EOF_ERR_INT_ST : RO; bitpos: [6]; default: 0;
+ *  Indicates the interrupt status of UHCI_OUT_EOF_INT.
+ */
+#define UHCI_OUTLINK_EOF_ERR_INT_ST    (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_M  (UHCI_OUTLINK_EOF_ERR_INT_ST_V << UHCI_OUTLINK_EOF_ERR_INT_ST_S)
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_V  0x00000001U
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_S  6
+/** UHCI_APP_CTRL0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  Indicates the interrupt status of UHCI_APP_CTRL0_INT.
+ */
+#define UHCI_APP_CTRL0_INT_ST    (BIT(7))
+#define UHCI_APP_CTRL0_INT_ST_M  (UHCI_APP_CTRL0_INT_ST_V << UHCI_APP_CTRL0_INT_ST_S)
+#define UHCI_APP_CTRL0_INT_ST_V  0x00000001U
+#define UHCI_APP_CTRL0_INT_ST_S  7
+/** UHCI_APP_CTRL1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  Indicates the interrupt status of UHCI_APP_CTRL1_INT.
+ */
+#define UHCI_APP_CTRL1_INT_ST    (BIT(8))
+#define UHCI_APP_CTRL1_INT_ST_M  (UHCI_APP_CTRL1_INT_ST_V << UHCI_APP_CTRL1_INT_ST_S)
+#define UHCI_APP_CTRL1_INT_ST_V  0x00000001U
+#define UHCI_APP_CTRL1_INT_ST_S  8
+
+/** UHCI_INT_ENA_REG register
+ *  UHCI Interrupt Enable Register
+ */
+#define UHCI_INT_ENA_REG (DR_REG_UHCI_BASE + 0xc)
+/** UHCI_RX_START_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_RX_START_INT.
+ */
+#define UHCI_RX_START_INT_ENA    (BIT(0))
+#define UHCI_RX_START_INT_ENA_M  (UHCI_RX_START_INT_ENA_V << UHCI_RX_START_INT_ENA_S)
+#define UHCI_RX_START_INT_ENA_V  0x00000001U
+#define UHCI_RX_START_INT_ENA_S  0
+/** UHCI_TX_START_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_TX_START_INT.
+ */
+#define UHCI_TX_START_INT_ENA    (BIT(1))
+#define UHCI_TX_START_INT_ENA_M  (UHCI_TX_START_INT_ENA_V << UHCI_TX_START_INT_ENA_S)
+#define UHCI_TX_START_INT_ENA_V  0x00000001U
+#define UHCI_TX_START_INT_ENA_S  1
+/** UHCI_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_RX_HUNG_INT.
+ */
+#define UHCI_RX_HUNG_INT_ENA    (BIT(2))
+#define UHCI_RX_HUNG_INT_ENA_M  (UHCI_RX_HUNG_INT_ENA_V << UHCI_RX_HUNG_INT_ENA_S)
+#define UHCI_RX_HUNG_INT_ENA_V  0x00000001U
+#define UHCI_RX_HUNG_INT_ENA_S  2
+/** UHCI_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_TX_HUNG_INT.
+ */
+#define UHCI_TX_HUNG_INT_ENA    (BIT(3))
+#define UHCI_TX_HUNG_INT_ENA_M  (UHCI_TX_HUNG_INT_ENA_V << UHCI_TX_HUNG_INT_ENA_S)
+#define UHCI_TX_HUNG_INT_ENA_V  0x00000001U
+#define UHCI_TX_HUNG_INT_ENA_S  3
+/** UHCI_SEND_S_REG_Q_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT.
+ */
+#define UHCI_SEND_S_REG_Q_INT_ENA    (BIT(4))
+#define UHCI_SEND_S_REG_Q_INT_ENA_M  (UHCI_SEND_S_REG_Q_INT_ENA_V << UHCI_SEND_S_REG_Q_INT_ENA_S)
+#define UHCI_SEND_S_REG_Q_INT_ENA_V  0x00000001U
+#define UHCI_SEND_S_REG_Q_INT_ENA_S  4
+/** UHCI_SEND_A_REG_Q_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT.
+ */
+#define UHCI_SEND_A_REG_Q_INT_ENA    (BIT(5))
+#define UHCI_SEND_A_REG_Q_INT_ENA_M  (UHCI_SEND_A_REG_Q_INT_ENA_V << UHCI_SEND_A_REG_Q_INT_ENA_S)
+#define UHCI_SEND_A_REG_Q_INT_ENA_V  0x00000001U
+#define UHCI_SEND_A_REG_Q_INT_ENA_S  5
+/** UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_OUT_EOF_INT.
+ */
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA    (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M  (UHCI_OUTLINK_EOF_ERR_INT_ENA_V << UHCI_OUTLINK_EOF_ERR_INT_ENA_S)
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V  0x00000001U
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S  6
+/** UHCI_APP_CTRL0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT.
+ */
+#define UHCI_APP_CTRL0_INT_ENA    (BIT(7))
+#define UHCI_APP_CTRL0_INT_ENA_M  (UHCI_APP_CTRL0_INT_ENA_V << UHCI_APP_CTRL0_INT_ENA_S)
+#define UHCI_APP_CTRL0_INT_ENA_V  0x00000001U
+#define UHCI_APP_CTRL0_INT_ENA_S  7
+/** UHCI_APP_CTRL1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT.
+ */
+#define UHCI_APP_CTRL1_INT_ENA    (BIT(8))
+#define UHCI_APP_CTRL1_INT_ENA_M  (UHCI_APP_CTRL1_INT_ENA_V << UHCI_APP_CTRL1_INT_ENA_S)
+#define UHCI_APP_CTRL1_INT_ENA_V  0x00000001U
+#define UHCI_APP_CTRL1_INT_ENA_S  8
+
+/** UHCI_INT_CLR_REG register
+ *  UHCI Interrupt Clear Register
+ */
+#define UHCI_INT_CLR_REG (DR_REG_UHCI_BASE + 0x10)
+/** UHCI_RX_START_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_RX_START_INT.
+ */
+#define UHCI_RX_START_INT_CLR    (BIT(0))
+#define UHCI_RX_START_INT_CLR_M  (UHCI_RX_START_INT_CLR_V << UHCI_RX_START_INT_CLR_S)
+#define UHCI_RX_START_INT_CLR_V  0x00000001U
+#define UHCI_RX_START_INT_CLR_S  0
+/** UHCI_TX_START_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_TX_START_INT.
+ */
+#define UHCI_TX_START_INT_CLR    (BIT(1))
+#define UHCI_TX_START_INT_CLR_M  (UHCI_TX_START_INT_CLR_V << UHCI_TX_START_INT_CLR_S)
+#define UHCI_TX_START_INT_CLR_V  0x00000001U
+#define UHCI_TX_START_INT_CLR_S  1
+/** UHCI_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT.
+ */
+#define UHCI_RX_HUNG_INT_CLR    (BIT(2))
+#define UHCI_RX_HUNG_INT_CLR_M  (UHCI_RX_HUNG_INT_CLR_V << UHCI_RX_HUNG_INT_CLR_S)
+#define UHCI_RX_HUNG_INT_CLR_V  0x00000001U
+#define UHCI_RX_HUNG_INT_CLR_S  2
+/** UHCI_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT.
+ */
+#define UHCI_TX_HUNG_INT_CLR    (BIT(3))
+#define UHCI_TX_HUNG_INT_CLR_M  (UHCI_TX_HUNG_INT_CLR_V << UHCI_TX_HUNG_INT_CLR_S)
+#define UHCI_TX_HUNG_INT_CLR_V  0x00000001U
+#define UHCI_TX_HUNG_INT_CLR_S  3
+/** UHCI_SEND_S_REG_Q_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT.
+ */
+#define UHCI_SEND_S_REG_Q_INT_CLR    (BIT(4))
+#define UHCI_SEND_S_REG_Q_INT_CLR_M  (UHCI_SEND_S_REG_Q_INT_CLR_V << UHCI_SEND_S_REG_Q_INT_CLR_S)
+#define UHCI_SEND_S_REG_Q_INT_CLR_V  0x00000001U
+#define UHCI_SEND_S_REG_Q_INT_CLR_S  4
+/** UHCI_SEND_A_REG_Q_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT.
+ */
+#define UHCI_SEND_A_REG_Q_INT_CLR    (BIT(5))
+#define UHCI_SEND_A_REG_Q_INT_CLR_M  (UHCI_SEND_A_REG_Q_INT_CLR_V << UHCI_SEND_A_REG_Q_INT_CLR_S)
+#define UHCI_SEND_A_REG_Q_INT_CLR_V  0x00000001U
+#define UHCI_SEND_A_REG_Q_INT_CLR_S  5
+/** UHCI_OUTLINK_EOF_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT.
+ */
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR    (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M  (UHCI_OUTLINK_EOF_ERR_INT_CLR_V << UHCI_OUTLINK_EOF_ERR_INT_CLR_S)
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V  0x00000001U
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S  6
+/** UHCI_APP_CTRL0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT.
+ */
+#define UHCI_APP_CTRL0_INT_CLR    (BIT(7))
+#define UHCI_APP_CTRL0_INT_CLR_M  (UHCI_APP_CTRL0_INT_CLR_V << UHCI_APP_CTRL0_INT_CLR_S)
+#define UHCI_APP_CTRL0_INT_CLR_V  0x00000001U
+#define UHCI_APP_CTRL0_INT_CLR_S  7
+/** UHCI_APP_CTRL1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT.
+ */
+#define UHCI_APP_CTRL1_INT_CLR    (BIT(8))
+#define UHCI_APP_CTRL1_INT_CLR_M  (UHCI_APP_CTRL1_INT_CLR_V << UHCI_APP_CTRL1_INT_CLR_S)
+#define UHCI_APP_CTRL1_INT_CLR_V  0x00000001U
+#define UHCI_APP_CTRL1_INT_CLR_S  8
+
+/** UHCI_CONF1_REG register
+ *  UHCI Configuration Register1
+ */
+#define UHCI_CONF1_REG (DR_REG_UHCI_BASE + 0x14)
+/** UHCI_CHECK_SUM_EN : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to enable head checksum check when receiving.
+ */
+#define UHCI_CHECK_SUM_EN    (BIT(0))
+#define UHCI_CHECK_SUM_EN_M  (UHCI_CHECK_SUM_EN_V << UHCI_CHECK_SUM_EN_S)
+#define UHCI_CHECK_SUM_EN_V  0x00000001U
+#define UHCI_CHECK_SUM_EN_S  0
+/** UHCI_CHECK_SEQ_EN : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to  enable sequence number check when receiving.
+ */
+#define UHCI_CHECK_SEQ_EN    (BIT(1))
+#define UHCI_CHECK_SEQ_EN_M  (UHCI_CHECK_SEQ_EN_V << UHCI_CHECK_SEQ_EN_S)
+#define UHCI_CHECK_SEQ_EN_V  0x00000001U
+#define UHCI_CHECK_SEQ_EN_S  1
+/** UHCI_CRC_DISABLE : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to support CRC calculation, and data integrity check bit should 1.
+ */
+#define UHCI_CRC_DISABLE    (BIT(2))
+#define UHCI_CRC_DISABLE_M  (UHCI_CRC_DISABLE_V << UHCI_CRC_DISABLE_S)
+#define UHCI_CRC_DISABLE_V  0x00000001U
+#define UHCI_CRC_DISABLE_S  2
+/** UHCI_SAVE_HEAD : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to save data packet head when UHCI receive data.
+ */
+#define UHCI_SAVE_HEAD    (BIT(3))
+#define UHCI_SAVE_HEAD_M  (UHCI_SAVE_HEAD_V << UHCI_SAVE_HEAD_S)
+#define UHCI_SAVE_HEAD_V  0x00000001U
+#define UHCI_SAVE_HEAD_S  3
+/** UHCI_TX_CHECK_SUM_RE : R/W; bitpos: [4]; default: 1;
+ *  Set this bit to encode data packet with checksum.
+ */
+#define UHCI_TX_CHECK_SUM_RE    (BIT(4))
+#define UHCI_TX_CHECK_SUM_RE_M  (UHCI_TX_CHECK_SUM_RE_V << UHCI_TX_CHECK_SUM_RE_S)
+#define UHCI_TX_CHECK_SUM_RE_V  0x00000001U
+#define UHCI_TX_CHECK_SUM_RE_S  4
+/** UHCI_TX_ACK_NUM_RE : R/W; bitpos: [5]; default: 1;
+ *  Set this bit to encode data packet with ACK when reliable data packet is ready.
+ */
+#define UHCI_TX_ACK_NUM_RE    (BIT(5))
+#define UHCI_TX_ACK_NUM_RE_M  (UHCI_TX_ACK_NUM_RE_V << UHCI_TX_ACK_NUM_RE_S)
+#define UHCI_TX_ACK_NUM_RE_V  0x00000001U
+#define UHCI_TX_ACK_NUM_RE_S  5
+/** UHCI_WAIT_SW_START : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status.
+ */
+#define UHCI_WAIT_SW_START    (BIT(7))
+#define UHCI_WAIT_SW_START_M  (UHCI_WAIT_SW_START_V << UHCI_WAIT_SW_START_S)
+#define UHCI_WAIT_SW_START_V  0x00000001U
+#define UHCI_WAIT_SW_START_S  7
+/** UHCI_SW_START : WT; bitpos: [8]; default: 0;
+ *  Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT.
+ */
+#define UHCI_SW_START    (BIT(8))
+#define UHCI_SW_START_M  (UHCI_SW_START_V << UHCI_SW_START_S)
+#define UHCI_SW_START_V  0x00000001U
+#define UHCI_SW_START_S  8
+
+/** UHCI_STATE0_REG register
+ *  UHCI Receive Status Register
+ */
+#define UHCI_STATE0_REG (DR_REG_UHCI_BASE + 0x18)
+/** UHCI_RX_ERR_CAUSE : RO; bitpos: [2:0]; default: 0;
+ *  Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet
+ *  checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC
+ *  bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is
+ *  not found, but received packet is completed. 3'b110: CRC check error.
+ */
+#define UHCI_RX_ERR_CAUSE    0x00000007U
+#define UHCI_RX_ERR_CAUSE_M  (UHCI_RX_ERR_CAUSE_V << UHCI_RX_ERR_CAUSE_S)
+#define UHCI_RX_ERR_CAUSE_V  0x00000007U
+#define UHCI_RX_ERR_CAUSE_S  0
+/** UHCI_DECODE_STATE : RO; bitpos: [5:3]; default: 0;
+ *  Indicates UHCI decoder status.
+ */
+#define UHCI_DECODE_STATE    0x00000007U
+#define UHCI_DECODE_STATE_M  (UHCI_DECODE_STATE_V << UHCI_DECODE_STATE_S)
+#define UHCI_DECODE_STATE_V  0x00000007U
+#define UHCI_DECODE_STATE_S  3
+
+/** UHCI_STATE1_REG register
+ *  UHCI Transmit Status Register
+ */
+#define UHCI_STATE1_REG (DR_REG_UHCI_BASE + 0x1c)
+/** UHCI_ENCODE_STATE : RO; bitpos: [2:0]; default: 0;
+ *  Indicates UHCI encoder status.
+ */
+#define UHCI_ENCODE_STATE    0x00000007U
+#define UHCI_ENCODE_STATE_M  (UHCI_ENCODE_STATE_V << UHCI_ENCODE_STATE_S)
+#define UHCI_ENCODE_STATE_V  0x00000007U
+#define UHCI_ENCODE_STATE_S  0
+
+/** UHCI_ESCAPE_CONF_REG register
+ *  UHCI Escapes Configuration Register0
+ */
+#define UHCI_ESCAPE_CONF_REG (DR_REG_UHCI_BASE + 0x20)
+/** UHCI_TX_C0_ESC_EN : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to enable resolve char 0xC0 when DMA receiving data.
+ */
+#define UHCI_TX_C0_ESC_EN    (BIT(0))
+#define UHCI_TX_C0_ESC_EN_M  (UHCI_TX_C0_ESC_EN_V << UHCI_TX_C0_ESC_EN_S)
+#define UHCI_TX_C0_ESC_EN_V  0x00000001U
+#define UHCI_TX_C0_ESC_EN_S  0
+/** UHCI_TX_DB_ESC_EN : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to enable resolve char 0xDB when DMA receiving data.
+ */
+#define UHCI_TX_DB_ESC_EN    (BIT(1))
+#define UHCI_TX_DB_ESC_EN_M  (UHCI_TX_DB_ESC_EN_V << UHCI_TX_DB_ESC_EN_S)
+#define UHCI_TX_DB_ESC_EN_V  0x00000001U
+#define UHCI_TX_DB_ESC_EN_S  1
+/** UHCI_TX_11_ESC_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable resolve flow control char 0x11 when DMA receiving data.
+ */
+#define UHCI_TX_11_ESC_EN    (BIT(2))
+#define UHCI_TX_11_ESC_EN_M  (UHCI_TX_11_ESC_EN_V << UHCI_TX_11_ESC_EN_S)
+#define UHCI_TX_11_ESC_EN_V  0x00000001U
+#define UHCI_TX_11_ESC_EN_S  2
+/** UHCI_TX_13_ESC_EN : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable resolve flow control char 0x13 when DMA receiving data.
+ */
+#define UHCI_TX_13_ESC_EN    (BIT(3))
+#define UHCI_TX_13_ESC_EN_M  (UHCI_TX_13_ESC_EN_V << UHCI_TX_13_ESC_EN_S)
+#define UHCI_TX_13_ESC_EN_V  0x00000001U
+#define UHCI_TX_13_ESC_EN_S  3
+/** UHCI_RX_C0_ESC_EN : R/W; bitpos: [4]; default: 1;
+ *  Set this bit to enable replacing 0xC0 with special char when DMA receiving data.
+ */
+#define UHCI_RX_C0_ESC_EN    (BIT(4))
+#define UHCI_RX_C0_ESC_EN_M  (UHCI_RX_C0_ESC_EN_V << UHCI_RX_C0_ESC_EN_S)
+#define UHCI_RX_C0_ESC_EN_V  0x00000001U
+#define UHCI_RX_C0_ESC_EN_S  4
+/** UHCI_RX_DB_ESC_EN : R/W; bitpos: [5]; default: 1;
+ *  Set this bit to enable replacing 0xDB with special char when DMA receiving data.
+ */
+#define UHCI_RX_DB_ESC_EN    (BIT(5))
+#define UHCI_RX_DB_ESC_EN_M  (UHCI_RX_DB_ESC_EN_V << UHCI_RX_DB_ESC_EN_S)
+#define UHCI_RX_DB_ESC_EN_V  0x00000001U
+#define UHCI_RX_DB_ESC_EN_S  5
+/** UHCI_RX_11_ESC_EN : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable replacing 0x11 with special char when DMA receiving data.
+ */
+#define UHCI_RX_11_ESC_EN    (BIT(6))
+#define UHCI_RX_11_ESC_EN_M  (UHCI_RX_11_ESC_EN_V << UHCI_RX_11_ESC_EN_S)
+#define UHCI_RX_11_ESC_EN_V  0x00000001U
+#define UHCI_RX_11_ESC_EN_S  6
+/** UHCI_RX_13_ESC_EN : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to enable replacing 0x13 with special char when DMA receiving data.
+ */
+#define UHCI_RX_13_ESC_EN    (BIT(7))
+#define UHCI_RX_13_ESC_EN_M  (UHCI_RX_13_ESC_EN_V << UHCI_RX_13_ESC_EN_S)
+#define UHCI_RX_13_ESC_EN_V  0x00000001U
+#define UHCI_RX_13_ESC_EN_S  7
+
+/** UHCI_HUNG_CONF_REG register
+ *  UHCI Hung Configuration Register0
+ */
+#define UHCI_HUNG_CONF_REG (DR_REG_UHCI_BASE + 0x24)
+/** UHCI_TXFIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
+ *  Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving
+ *  data.
+ */
+#define UHCI_TXFIFO_TIMEOUT    0x000000FFU
+#define UHCI_TXFIFO_TIMEOUT_M  (UHCI_TXFIFO_TIMEOUT_V << UHCI_TXFIFO_TIMEOUT_S)
+#define UHCI_TXFIFO_TIMEOUT_V  0x000000FFU
+#define UHCI_TXFIFO_TIMEOUT_S  0
+/** UHCI_TXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0;
+ *  Configures the maximum counter value.
+ */
+#define UHCI_TXFIFO_TIMEOUT_SHIFT    0x00000007U
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_M  (UHCI_TXFIFO_TIMEOUT_SHIFT_V << UHCI_TXFIFO_TIMEOUT_SHIFT_S)
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_V  0x00000007U
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_S  8
+/** UHCI_TXFIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
+ *  Set this bit to enable TX FIFO timeout when receiving.
+ */
+#define UHCI_TXFIFO_TIMEOUT_ENA    (BIT(11))
+#define UHCI_TXFIFO_TIMEOUT_ENA_M  (UHCI_TXFIFO_TIMEOUT_ENA_V << UHCI_TXFIFO_TIMEOUT_ENA_S)
+#define UHCI_TXFIFO_TIMEOUT_ENA_V  0x00000001U
+#define UHCI_TXFIFO_TIMEOUT_ENA_S  11
+/** UHCI_RXFIFO_TIMEOUT : R/W; bitpos: [19:12]; default: 16;
+ *  Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading
+ *  RAM data.
+ */
+#define UHCI_RXFIFO_TIMEOUT    0x000000FFU
+#define UHCI_RXFIFO_TIMEOUT_M  (UHCI_RXFIFO_TIMEOUT_V << UHCI_RXFIFO_TIMEOUT_S)
+#define UHCI_RXFIFO_TIMEOUT_V  0x000000FFU
+#define UHCI_RXFIFO_TIMEOUT_S  12
+/** UHCI_RXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [22:20]; default: 0;
+ *  Configures the maximum counter value.
+ */
+#define UHCI_RXFIFO_TIMEOUT_SHIFT    0x00000007U
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_M  (UHCI_RXFIFO_TIMEOUT_SHIFT_V << UHCI_RXFIFO_TIMEOUT_SHIFT_S)
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_V  0x00000007U
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_S  20
+/** UHCI_RXFIFO_TIMEOUT_ENA : R/W; bitpos: [23]; default: 1;
+ *  Set this bit to enable TX FIFO timeout when DMA sending data.
+ */
+#define UHCI_RXFIFO_TIMEOUT_ENA    (BIT(23))
+#define UHCI_RXFIFO_TIMEOUT_ENA_M  (UHCI_RXFIFO_TIMEOUT_ENA_V << UHCI_RXFIFO_TIMEOUT_ENA_S)
+#define UHCI_RXFIFO_TIMEOUT_ENA_V  0x00000001U
+#define UHCI_RXFIFO_TIMEOUT_ENA_S  23
+
+/** UHCI_ACK_NUM_REG register
+ *  UHCI Ack Value Configuration Register0
+ */
+#define UHCI_ACK_NUM_REG (DR_REG_UHCI_BASE + 0x28)
+/** UHCI_ACK_NUM : R/W; bitpos: [2:0]; default: 0;
+ *  Indicates the ACK number during software flow control.
+ */
+#define UHCI_ACK_NUM    0x00000007U
+#define UHCI_ACK_NUM_M  (UHCI_ACK_NUM_V << UHCI_ACK_NUM_S)
+#define UHCI_ACK_NUM_V  0x00000007U
+#define UHCI_ACK_NUM_S  0
+/** UHCI_ACK_NUM_LOAD : WT; bitpos: [3]; default: 0;
+ *  Set this bit to load the ACK value of UHCI_ACK_NUM.
+ */
+#define UHCI_ACK_NUM_LOAD    (BIT(3))
+#define UHCI_ACK_NUM_LOAD_M  (UHCI_ACK_NUM_LOAD_V << UHCI_ACK_NUM_LOAD_S)
+#define UHCI_ACK_NUM_LOAD_V  0x00000001U
+#define UHCI_ACK_NUM_LOAD_S  3
+
+/** UHCI_RX_HEAD_REG register
+ *  UHCI Head Register
+ */
+#define UHCI_RX_HEAD_REG (DR_REG_UHCI_BASE + 0x2c)
+/** UHCI_RX_HEAD : RO; bitpos: [31:0]; default: 0;
+ *  Stores the head of received packet.
+ */
+#define UHCI_RX_HEAD    0xFFFFFFFFU
+#define UHCI_RX_HEAD_M  (UHCI_RX_HEAD_V << UHCI_RX_HEAD_S)
+#define UHCI_RX_HEAD_V  0xFFFFFFFFU
+#define UHCI_RX_HEAD_S  0
+
+/** UHCI_QUICK_SENT_REG register
+ *  UCHI Quick send Register
+ */
+#define UHCI_QUICK_SENT_REG (DR_REG_UHCI_BASE + 0x30)
+/** UHCI_SINGLE_SEND_NUM : R/W; bitpos: [2:0]; default: 0;
+ *  Configures single_send mode.
+ */
+#define UHCI_SINGLE_SEND_NUM    0x00000007U
+#define UHCI_SINGLE_SEND_NUM_M  (UHCI_SINGLE_SEND_NUM_V << UHCI_SINGLE_SEND_NUM_S)
+#define UHCI_SINGLE_SEND_NUM_V  0x00000007U
+#define UHCI_SINGLE_SEND_NUM_S  0
+/** UHCI_SINGLE_SEND_EN : WT; bitpos: [3]; default: 0;
+ *  Set this bit to enable sending short packet with single_send mode.
+ */
+#define UHCI_SINGLE_SEND_EN    (BIT(3))
+#define UHCI_SINGLE_SEND_EN_M  (UHCI_SINGLE_SEND_EN_V << UHCI_SINGLE_SEND_EN_S)
+#define UHCI_SINGLE_SEND_EN_V  0x00000001U
+#define UHCI_SINGLE_SEND_EN_S  3
+/** UHCI_ALWAYS_SEND_NUM : R/W; bitpos: [6:4]; default: 0;
+ *  Configures always_send mode.
+ */
+#define UHCI_ALWAYS_SEND_NUM    0x00000007U
+#define UHCI_ALWAYS_SEND_NUM_M  (UHCI_ALWAYS_SEND_NUM_V << UHCI_ALWAYS_SEND_NUM_S)
+#define UHCI_ALWAYS_SEND_NUM_V  0x00000007U
+#define UHCI_ALWAYS_SEND_NUM_S  4
+/** UHCI_ALWAYS_SEND_EN : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to enable sending short packet with always_send mode.
+ */
+#define UHCI_ALWAYS_SEND_EN    (BIT(7))
+#define UHCI_ALWAYS_SEND_EN_M  (UHCI_ALWAYS_SEND_EN_V << UHCI_ALWAYS_SEND_EN_S)
+#define UHCI_ALWAYS_SEND_EN_V  0x00000001U
+#define UHCI_ALWAYS_SEND_EN_S  7
+
+/** UHCI_REG_Q0_WORD0_REG register
+ *  UHCI Q0_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q0_WORD0_REG (DR_REG_UHCI_BASE + 0x34)
+/** UHCI_SEND_Q0_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q0_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q0_WORD0_M  (UHCI_SEND_Q0_WORD0_V << UHCI_SEND_Q0_WORD0_S)
+#define UHCI_SEND_Q0_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q0_WORD0_S  0
+
+/** UHCI_REG_Q0_WORD1_REG register
+ *  UHCI Q0_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q0_WORD1_REG (DR_REG_UHCI_BASE + 0x38)
+/** UHCI_SEND_Q0_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q0_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q0_WORD1_M  (UHCI_SEND_Q0_WORD1_V << UHCI_SEND_Q0_WORD1_S)
+#define UHCI_SEND_Q0_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q0_WORD1_S  0
+
+/** UHCI_REG_Q1_WORD0_REG register
+ *  UHCI Q1_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q1_WORD0_REG (DR_REG_UHCI_BASE + 0x3c)
+/** UHCI_SEND_Q1_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q1_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q1_WORD0_M  (UHCI_SEND_Q1_WORD0_V << UHCI_SEND_Q1_WORD0_S)
+#define UHCI_SEND_Q1_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q1_WORD0_S  0
+
+/** UHCI_REG_Q1_WORD1_REG register
+ *  UHCI Q1_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q1_WORD1_REG (DR_REG_UHCI_BASE + 0x40)
+/** UHCI_SEND_Q1_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q1_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q1_WORD1_M  (UHCI_SEND_Q1_WORD1_V << UHCI_SEND_Q1_WORD1_S)
+#define UHCI_SEND_Q1_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q1_WORD1_S  0
+
+/** UHCI_REG_Q2_WORD0_REG register
+ *  UHCI Q2_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q2_WORD0_REG (DR_REG_UHCI_BASE + 0x44)
+/** UHCI_SEND_Q2_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q2_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q2_WORD0_M  (UHCI_SEND_Q2_WORD0_V << UHCI_SEND_Q2_WORD0_S)
+#define UHCI_SEND_Q2_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q2_WORD0_S  0
+
+/** UHCI_REG_Q2_WORD1_REG register
+ *  UHCI Q2_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q2_WORD1_REG (DR_REG_UHCI_BASE + 0x48)
+/** UHCI_SEND_Q2_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q2_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q2_WORD1_M  (UHCI_SEND_Q2_WORD1_V << UHCI_SEND_Q2_WORD1_S)
+#define UHCI_SEND_Q2_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q2_WORD1_S  0
+
+/** UHCI_REG_Q3_WORD0_REG register
+ *  UHCI Q3_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q3_WORD0_REG (DR_REG_UHCI_BASE + 0x4c)
+/** UHCI_SEND_Q3_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q3_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q3_WORD0_M  (UHCI_SEND_Q3_WORD0_V << UHCI_SEND_Q3_WORD0_S)
+#define UHCI_SEND_Q3_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q3_WORD0_S  0
+
+/** UHCI_REG_Q3_WORD1_REG register
+ *  UHCI Q3_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q3_WORD1_REG (DR_REG_UHCI_BASE + 0x50)
+/** UHCI_SEND_Q3_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q3_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q3_WORD1_M  (UHCI_SEND_Q3_WORD1_V << UHCI_SEND_Q3_WORD1_S)
+#define UHCI_SEND_Q3_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q3_WORD1_S  0
+
+/** UHCI_REG_Q4_WORD0_REG register
+ *  UHCI Q4_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q4_WORD0_REG (DR_REG_UHCI_BASE + 0x54)
+/** UHCI_SEND_Q4_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q4_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q4_WORD0_M  (UHCI_SEND_Q4_WORD0_V << UHCI_SEND_Q4_WORD0_S)
+#define UHCI_SEND_Q4_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q4_WORD0_S  0
+
+/** UHCI_REG_Q4_WORD1_REG register
+ *  UHCI Q4_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q4_WORD1_REG (DR_REG_UHCI_BASE + 0x58)
+/** UHCI_SEND_Q4_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q4_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q4_WORD1_M  (UHCI_SEND_Q4_WORD1_V << UHCI_SEND_Q4_WORD1_S)
+#define UHCI_SEND_Q4_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q4_WORD1_S  0
+
+/** UHCI_REG_Q5_WORD0_REG register
+ *  UHCI Q5_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q5_WORD0_REG (DR_REG_UHCI_BASE + 0x5c)
+/** UHCI_SEND_Q5_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q5_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q5_WORD0_M  (UHCI_SEND_Q5_WORD0_V << UHCI_SEND_Q5_WORD0_S)
+#define UHCI_SEND_Q5_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q5_WORD0_S  0
+
+/** UHCI_REG_Q5_WORD1_REG register
+ *  UHCI Q5_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q5_WORD1_REG (DR_REG_UHCI_BASE + 0x60)
+/** UHCI_SEND_Q5_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q5_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q5_WORD1_M  (UHCI_SEND_Q5_WORD1_V << UHCI_SEND_Q5_WORD1_S)
+#define UHCI_SEND_Q5_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q5_WORD1_S  0
+
+/** UHCI_REG_Q6_WORD0_REG register
+ *  UHCI Q6_WORD0 Quick Send Register
+ */
+#define UHCI_REG_Q6_WORD0_REG (DR_REG_UHCI_BASE + 0x64)
+/** UHCI_SEND_Q6_WORD0 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q6_WORD0    0xFFFFFFFFU
+#define UHCI_SEND_Q6_WORD0_M  (UHCI_SEND_Q6_WORD0_V << UHCI_SEND_Q6_WORD0_S)
+#define UHCI_SEND_Q6_WORD0_V  0xFFFFFFFFU
+#define UHCI_SEND_Q6_WORD0_S  0
+
+/** UHCI_REG_Q6_WORD1_REG register
+ *  UHCI Q6_WORD1 Quick Send Register
+ */
+#define UHCI_REG_Q6_WORD1_REG (DR_REG_UHCI_BASE + 0x68)
+/** UHCI_SEND_Q6_WORD1 : R/W; bitpos: [31:0]; default: 0;
+ *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+ *  UHCI_SINGLE_SEND_NUM.
+ */
+#define UHCI_SEND_Q6_WORD1    0xFFFFFFFFU
+#define UHCI_SEND_Q6_WORD1_M  (UHCI_SEND_Q6_WORD1_V << UHCI_SEND_Q6_WORD1_S)
+#define UHCI_SEND_Q6_WORD1_V  0xFFFFFFFFU
+#define UHCI_SEND_Q6_WORD1_S  0
+
+/** UHCI_ESC_CONF0_REG register
+ *  UHCI Escapes Sequence Configuration Register0
+ */
+#define UHCI_ESC_CONF0_REG (DR_REG_UHCI_BASE + 0x6c)
+/** UHCI_SEPER_CHAR : R/W; bitpos: [7:0]; default: 192;
+ *  Configures the delimiter for encoding, default value is 0xC0.
+ */
+#define UHCI_SEPER_CHAR    0x000000FFU
+#define UHCI_SEPER_CHAR_M  (UHCI_SEPER_CHAR_V << UHCI_SEPER_CHAR_S)
+#define UHCI_SEPER_CHAR_V  0x000000FFU
+#define UHCI_SEPER_CHAR_S  0
+/** UHCI_SEPER_ESC_CHAR0 : R/W; bitpos: [15:8]; default: 219;
+ *  Configures the first char of SLIP escape character, default value is 0xDB.
+ */
+#define UHCI_SEPER_ESC_CHAR0    0x000000FFU
+#define UHCI_SEPER_ESC_CHAR0_M  (UHCI_SEPER_ESC_CHAR0_V << UHCI_SEPER_ESC_CHAR0_S)
+#define UHCI_SEPER_ESC_CHAR0_V  0x000000FFU
+#define UHCI_SEPER_ESC_CHAR0_S  8
+/** UHCI_SEPER_ESC_CHAR1 : R/W; bitpos: [23:16]; default: 220;
+ *  Configures the second char of SLIP escape character, default value is 0xDC.
+ */
+#define UHCI_SEPER_ESC_CHAR1    0x000000FFU
+#define UHCI_SEPER_ESC_CHAR1_M  (UHCI_SEPER_ESC_CHAR1_V << UHCI_SEPER_ESC_CHAR1_S)
+#define UHCI_SEPER_ESC_CHAR1_V  0x000000FFU
+#define UHCI_SEPER_ESC_CHAR1_S  16
+
+/** UHCI_ESC_CONF1_REG register
+ *  UHCI Escapes Sequence Configuration Register1
+ */
+#define UHCI_ESC_CONF1_REG (DR_REG_UHCI_BASE + 0x70)
+/** UHCI_ESC_SEQ0 : R/W; bitpos: [7:0]; default: 219;
+ *  Configures the char needing encoding, which is 0xDB as flow control char by default.
+ */
+#define UHCI_ESC_SEQ0    0x000000FFU
+#define UHCI_ESC_SEQ0_M  (UHCI_ESC_SEQ0_V << UHCI_ESC_SEQ0_S)
+#define UHCI_ESC_SEQ0_V  0x000000FFU
+#define UHCI_ESC_SEQ0_S  0
+/** UHCI_ESC_SEQ0_CHAR0 : R/W; bitpos: [15:8]; default: 219;
+ *  Configures the first char of SLIP escape character, default value is 0xDB.
+ */
+#define UHCI_ESC_SEQ0_CHAR0    0x000000FFU
+#define UHCI_ESC_SEQ0_CHAR0_M  (UHCI_ESC_SEQ0_CHAR0_V << UHCI_ESC_SEQ0_CHAR0_S)
+#define UHCI_ESC_SEQ0_CHAR0_V  0x000000FFU
+#define UHCI_ESC_SEQ0_CHAR0_S  8
+/** UHCI_ESC_SEQ0_CHAR1 : R/W; bitpos: [23:16]; default: 221;
+ *  Configures the second char of SLIP escape character, default value is 0xDD.
+ */
+#define UHCI_ESC_SEQ0_CHAR1    0x000000FFU
+#define UHCI_ESC_SEQ0_CHAR1_M  (UHCI_ESC_SEQ0_CHAR1_V << UHCI_ESC_SEQ0_CHAR1_S)
+#define UHCI_ESC_SEQ0_CHAR1_V  0x000000FFU
+#define UHCI_ESC_SEQ0_CHAR1_S  16
+
+/** UHCI_ESC_CONF2_REG register
+ *  UHCI Escapes Sequence Configuration Register2
+ */
+#define UHCI_ESC_CONF2_REG (DR_REG_UHCI_BASE + 0x74)
+/** UHCI_ESC_SEQ1 : R/W; bitpos: [7:0]; default: 17;
+ *  Configures the char needing encoding, which is 0x11 as flow control char by default.
+ */
+#define UHCI_ESC_SEQ1    0x000000FFU
+#define UHCI_ESC_SEQ1_M  (UHCI_ESC_SEQ1_V << UHCI_ESC_SEQ1_S)
+#define UHCI_ESC_SEQ1_V  0x000000FFU
+#define UHCI_ESC_SEQ1_S  0
+/** UHCI_ESC_SEQ1_CHAR0 : R/W; bitpos: [15:8]; default: 219;
+ *  Configures the first char of SLIP escape character, default value is 0xDB.
+ */
+#define UHCI_ESC_SEQ1_CHAR0    0x000000FFU
+#define UHCI_ESC_SEQ1_CHAR0_M  (UHCI_ESC_SEQ1_CHAR0_V << UHCI_ESC_SEQ1_CHAR0_S)
+#define UHCI_ESC_SEQ1_CHAR0_V  0x000000FFU
+#define UHCI_ESC_SEQ1_CHAR0_S  8
+/** UHCI_ESC_SEQ1_CHAR1 : R/W; bitpos: [23:16]; default: 222;
+ *  Configures the second char of SLIP escape character, default value is 0xDE.
+ */
+#define UHCI_ESC_SEQ1_CHAR1    0x000000FFU
+#define UHCI_ESC_SEQ1_CHAR1_M  (UHCI_ESC_SEQ1_CHAR1_V << UHCI_ESC_SEQ1_CHAR1_S)
+#define UHCI_ESC_SEQ1_CHAR1_V  0x000000FFU
+#define UHCI_ESC_SEQ1_CHAR1_S  16
+
+/** UHCI_ESC_CONF3_REG register
+ *  UHCI Escapes Sequence Configuration Register3
+ */
+#define UHCI_ESC_CONF3_REG (DR_REG_UHCI_BASE + 0x78)
+/** UHCI_ESC_SEQ2 : R/W; bitpos: [7:0]; default: 19;
+ *  Configures the char needing encoding, which is 0x13 as flow control char by default.
+ */
+#define UHCI_ESC_SEQ2    0x000000FFU
+#define UHCI_ESC_SEQ2_M  (UHCI_ESC_SEQ2_V << UHCI_ESC_SEQ2_S)
+#define UHCI_ESC_SEQ2_V  0x000000FFU
+#define UHCI_ESC_SEQ2_S  0
+/** UHCI_ESC_SEQ2_CHAR0 : R/W; bitpos: [15:8]; default: 219;
+ *  Configures the first char of SLIP escape character, default value is 0xDB.
+ */
+#define UHCI_ESC_SEQ2_CHAR0    0x000000FFU
+#define UHCI_ESC_SEQ2_CHAR0_M  (UHCI_ESC_SEQ2_CHAR0_V << UHCI_ESC_SEQ2_CHAR0_S)
+#define UHCI_ESC_SEQ2_CHAR0_V  0x000000FFU
+#define UHCI_ESC_SEQ2_CHAR0_S  8
+/** UHCI_ESC_SEQ2_CHAR1 : R/W; bitpos: [23:16]; default: 223;
+ *  Configures the second char of SLIP escape character, default value is 0xDF.
+ */
+#define UHCI_ESC_SEQ2_CHAR1    0x000000FFU
+#define UHCI_ESC_SEQ2_CHAR1_M  (UHCI_ESC_SEQ2_CHAR1_V << UHCI_ESC_SEQ2_CHAR1_S)
+#define UHCI_ESC_SEQ2_CHAR1_V  0x000000FFU
+#define UHCI_ESC_SEQ2_CHAR1_S  16
+
+/** UHCI_PKT_THRES_REG register
+ *  UCHI Packet Length Configuration Register
+ */
+#define UHCI_PKT_THRES_REG (DR_REG_UHCI_BASE + 0x7c)
+/** UHCI_PKT_THRS : R/W; bitpos: [12:0]; default: 128;
+ *  Configures the data packet's maximum length when UHCI_HEAD_EN is 0.
+ */
+#define UHCI_PKT_THRS    0x00001FFFU
+#define UHCI_PKT_THRS_M  (UHCI_PKT_THRS_V << UHCI_PKT_THRS_S)
+#define UHCI_PKT_THRS_V  0x00001FFFU
+#define UHCI_PKT_THRS_S  0
+
+/** UHCI_DATE_REG register
+ *  UHCI Version Register
+ */
+#define UHCI_DATE_REG (DR_REG_UHCI_BASE + 0x80)
+/** UHCI_DATE : R/W; bitpos: [31:0]; default: 35655936;
+ *  Configures version.
+ */
+#define UHCI_DATE    0xFFFFFFFFU
+#define UHCI_DATE_M  (UHCI_DATE_V << UHCI_DATE_S)
+#define UHCI_DATE_V  0xFFFFFFFFU
+#define UHCI_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/uhci_struct.h

@@ -0,0 +1,844 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Register */
+/** Type of conf0 register
+ *  UHCI Configuration Register0
+ */
+typedef union {
+    struct {
+        /** tx_rst : R/W; bitpos: [0]; default: 0;
+         *  Write 1 then write 0 to this bit to reset decode state machine.
+         */
+        uint32_t tx_rst:1;
+        /** rx_rst : R/W; bitpos: [1]; default: 0;
+         *  Write 1 then write 0 to this bit to reset encode state machine.
+         */
+        uint32_t rx_rst:1;
+        /** uart_sel : R/W; bitpos: [4:2]; default: 7;
+         *  Select which uart to connect with GDMA.
+         */
+        uint32_t uart_sel:3;
+        /** seper_en : R/W; bitpos: [5]; default: 1;
+         *  Set this bit to separate the data frame using a special char.
+         */
+        uint32_t seper_en:1;
+        /** head_en : R/W; bitpos: [6]; default: 1;
+         *  Set this bit to encode the data packet with a formatting header.
+         */
+        uint32_t head_en:1;
+        /** crc_rec_en : R/W; bitpos: [7]; default: 1;
+         *  Set this bit to enable UHCI to receive the 16 bit CRC.
+         */
+        uint32_t crc_rec_en:1;
+        /** uart_idle_eof_en : R/W; bitpos: [8]; default: 0;
+         *  If this bit is set to 1 UHCI will end the payload receiving process when UART has
+         *  been in idle state.
+         */
+        uint32_t uart_idle_eof_en:1;
+        /** len_eof_en : R/W; bitpos: [9]; default: 1;
+         *  If this bit is set to 1 UHCI decoder receiving payload data is end when the
+         *  receiving byte count has reached the specified value. The value is payload length
+         *  indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
+         *  configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder
+         *  receiving payload data is end when 0xc0 is received.
+         */
+        uint32_t len_eof_en:1;
+        /** encode_crc_en : R/W; bitpos: [10]; default: 1;
+         *  Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to
+         *  end of the payload.
+         */
+        uint32_t encode_crc_en:1;
+        /** clk_en : R/W; bitpos: [11]; default: 0;
+         *  1'b1: Force clock on for register. 1'b0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        /** uart_rx_brk_eof_en : R/W; bitpos: [12]; default: 0;
+         *  If this bit is set to 1 UHCI will end payload receive process when NULL frame is
+         *  received by UART.
+         */
+        uint32_t uart_rx_brk_eof_en:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} uhci_conf0_reg_t;
+
+/** Type of conf1 register
+ *  UHCI Configuration Register1
+ */
+typedef union {
+    struct {
+        /** check_sum_en : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to enable head checksum check when receiving.
+         */
+        uint32_t check_sum_en:1;
+        /** check_seq_en : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to  enable sequence number check when receiving.
+         */
+        uint32_t check_seq_en:1;
+        /** crc_disable : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to support CRC calculation, and data integrity check bit should 1.
+         */
+        uint32_t crc_disable:1;
+        /** save_head : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to save data packet head when UHCI receive data.
+         */
+        uint32_t save_head:1;
+        /** tx_check_sum_re : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to encode data packet with checksum.
+         */
+        uint32_t tx_check_sum_re:1;
+        /** tx_ack_num_re : R/W; bitpos: [5]; default: 1;
+         *  Set this bit to encode data packet with ACK when reliable data packet is ready.
+         */
+        uint32_t tx_ack_num_re:1;
+        uint32_t reserved_6:1;
+        /** wait_sw_start : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status.
+         */
+        uint32_t wait_sw_start:1;
+        /** sw_start : WT; bitpos: [8]; default: 0;
+         *  Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT.
+         */
+        uint32_t sw_start:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uhci_conf1_reg_t;
+
+/** Type of escape_conf register
+ *  UHCI Escapes Configuration Register0
+ */
+typedef union {
+    struct {
+        /** tx_c0_esc_en : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to enable resolve char 0xC0 when DMA receiving data.
+         */
+        uint32_t tx_c0_esc_en:1;
+        /** tx_db_esc_en : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to enable resolve char 0xDB when DMA receiving data.
+         */
+        uint32_t tx_db_esc_en:1;
+        /** tx_11_esc_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable resolve flow control char 0x11 when DMA receiving data.
+         */
+        uint32_t tx_11_esc_en:1;
+        /** tx_13_esc_en : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable resolve flow control char 0x13 when DMA receiving data.
+         */
+        uint32_t tx_13_esc_en:1;
+        /** rx_c0_esc_en : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to enable replacing 0xC0 with special char when DMA receiving data.
+         */
+        uint32_t rx_c0_esc_en:1;
+        /** rx_db_esc_en : R/W; bitpos: [5]; default: 1;
+         *  Set this bit to enable replacing 0xDB with special char when DMA receiving data.
+         */
+        uint32_t rx_db_esc_en:1;
+        /** rx_11_esc_en : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable replacing 0x11 with special char when DMA receiving data.
+         */
+        uint32_t rx_11_esc_en:1;
+        /** rx_13_esc_en : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to enable replacing 0x13 with special char when DMA receiving data.
+         */
+        uint32_t rx_13_esc_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uhci_escape_conf_reg_t;
+
+/** Type of hung_conf register
+ *  UHCI Hung Configuration Register0
+ */
+typedef union {
+    struct {
+        /** txfifo_timeout : R/W; bitpos: [7:0]; default: 16;
+         *  Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving
+         *  data.
+         */
+        uint32_t txfifo_timeout:8;
+        /** txfifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
+         *  Configures the maximum counter value.
+         */
+        uint32_t txfifo_timeout_shift:3;
+        /** txfifo_timeout_ena : R/W; bitpos: [11]; default: 1;
+         *  Set this bit to enable TX FIFO timeout when receiving.
+         */
+        uint32_t txfifo_timeout_ena:1;
+        /** rxfifo_timeout : R/W; bitpos: [19:12]; default: 16;
+         *  Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading
+         *  RAM data.
+         */
+        uint32_t rxfifo_timeout:8;
+        /** rxfifo_timeout_shift : R/W; bitpos: [22:20]; default: 0;
+         *  Configures the maximum counter value.
+         */
+        uint32_t rxfifo_timeout_shift:3;
+        /** rxfifo_timeout_ena : R/W; bitpos: [23]; default: 1;
+         *  Set this bit to enable TX FIFO timeout when DMA sending data.
+         */
+        uint32_t rxfifo_timeout_ena:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uhci_hung_conf_reg_t;
+
+/** Type of ack_num register
+ *  UHCI Ack Value Configuration Register0
+ */
+typedef union {
+    struct {
+        /** ack_num : R/W; bitpos: [2:0]; default: 0;
+         *  Indicates the ACK number during software flow control.
+         */
+        uint32_t ack_num:3;
+        /** ack_num_load : WT; bitpos: [3]; default: 0;
+         *  Set this bit to load the ACK value of UHCI_ACK_NUM.
+         */
+        uint32_t ack_num_load:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} uhci_ack_num_reg_t;
+
+/** Type of quick_sent register
+ *  UCHI Quick send Register
+ */
+typedef union {
+    struct {
+        /** single_send_num : R/W; bitpos: [2:0]; default: 0;
+         *  Configures single_send mode.
+         */
+        uint32_t single_send_num:3;
+        /** single_send_en : WT; bitpos: [3]; default: 0;
+         *  Set this bit to enable sending short packet with single_send mode.
+         */
+        uint32_t single_send_en:1;
+        /** always_send_num : R/W; bitpos: [6:4]; default: 0;
+         *  Configures always_send mode.
+         */
+        uint32_t always_send_num:3;
+        /** always_send_en : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to enable sending short packet with always_send mode.
+         */
+        uint32_t always_send_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uhci_quick_sent_reg_t;
+
+/** Type of reg_q0_word0 register
+ *  UHCI Q0_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q0_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q0_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q0_word0_reg_t;
+
+/** Type of reg_q0_word1 register
+ *  UHCI Q0_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q0_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q0_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q0_word1_reg_t;
+
+/** Type of reg_q1_word0 register
+ *  UHCI Q1_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q1_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q1_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q1_word0_reg_t;
+
+/** Type of reg_q1_word1 register
+ *  UHCI Q1_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q1_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q1_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q1_word1_reg_t;
+
+/** Type of reg_q2_word0 register
+ *  UHCI Q2_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q2_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q2_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q2_word0_reg_t;
+
+/** Type of reg_q2_word1 register
+ *  UHCI Q2_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q2_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q2_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q2_word1_reg_t;
+
+/** Type of reg_q3_word0 register
+ *  UHCI Q3_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q3_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q3_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q3_word0_reg_t;
+
+/** Type of reg_q3_word1 register
+ *  UHCI Q3_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q3_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q3_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q3_word1_reg_t;
+
+/** Type of reg_q4_word0 register
+ *  UHCI Q4_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q4_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q4_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q4_word0_reg_t;
+
+/** Type of reg_q4_word1 register
+ *  UHCI Q4_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q4_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q4_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q4_word1_reg_t;
+
+/** Type of reg_q5_word0 register
+ *  UHCI Q5_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q5_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q5_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q5_word0_reg_t;
+
+/** Type of reg_q5_word1 register
+ *  UHCI Q5_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q5_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q5_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q5_word1_reg_t;
+
+/** Type of reg_q6_word0 register
+ *  UHCI Q6_WORD0 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q6_word0 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q6_word0:32;
+    };
+    uint32_t val;
+} uhci_reg_q6_word0_reg_t;
+
+/** Type of reg_q6_word1 register
+ *  UHCI Q6_WORD1 Quick Send Register
+ */
+typedef union {
+    struct {
+        /** send_q6_word1 : R/W; bitpos: [31:0]; default: 0;
+         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
+         *  UHCI_SINGLE_SEND_NUM.
+         */
+        uint32_t send_q6_word1:32;
+    };
+    uint32_t val;
+} uhci_reg_q6_word1_reg_t;
+
+/** Type of esc_conf0 register
+ *  UHCI Escapes Sequence Configuration Register0
+ */
+typedef union {
+    struct {
+        /** seper_char : R/W; bitpos: [7:0]; default: 192;
+         *  Configures the delimiter for encoding, default value is 0xC0.
+         */
+        uint32_t seper_char:8;
+        /** seper_esc_char0 : R/W; bitpos: [15:8]; default: 219;
+         *  Configures the first char of SLIP escape character, default value is 0xDB.
+         */
+        uint32_t seper_esc_char0:8;
+        /** seper_esc_char1 : R/W; bitpos: [23:16]; default: 220;
+         *  Configures the second char of SLIP escape character, default value is 0xDC.
+         */
+        uint32_t seper_esc_char1:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uhci_esc_conf0_reg_t;
+
+/** Type of esc_conf1 register
+ *  UHCI Escapes Sequence Configuration Register1
+ */
+typedef union {
+    struct {
+        /** esc_seq0 : R/W; bitpos: [7:0]; default: 219;
+         *  Configures the char needing encoding, which is 0xDB as flow control char by default.
+         */
+        uint32_t esc_seq0:8;
+        /** esc_seq0_char0 : R/W; bitpos: [15:8]; default: 219;
+         *  Configures the first char of SLIP escape character, default value is 0xDB.
+         */
+        uint32_t esc_seq0_char0:8;
+        /** esc_seq0_char1 : R/W; bitpos: [23:16]; default: 221;
+         *  Configures the second char of SLIP escape character, default value is 0xDD.
+         */
+        uint32_t esc_seq0_char1:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uhci_esc_conf1_reg_t;
+
+/** Type of esc_conf2 register
+ *  UHCI Escapes Sequence Configuration Register2
+ */
+typedef union {
+    struct {
+        /** esc_seq1 : R/W; bitpos: [7:0]; default: 17;
+         *  Configures the char needing encoding, which is 0x11 as flow control char by default.
+         */
+        uint32_t esc_seq1:8;
+        /** esc_seq1_char0 : R/W; bitpos: [15:8]; default: 219;
+         *  Configures the first char of SLIP escape character, default value is 0xDB.
+         */
+        uint32_t esc_seq1_char0:8;
+        /** esc_seq1_char1 : R/W; bitpos: [23:16]; default: 222;
+         *  Configures the second char of SLIP escape character, default value is 0xDE.
+         */
+        uint32_t esc_seq1_char1:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uhci_esc_conf2_reg_t;
+
+/** Type of esc_conf3 register
+ *  UHCI Escapes Sequence Configuration Register3
+ */
+typedef union {
+    struct {
+        /** esc_seq2 : R/W; bitpos: [7:0]; default: 19;
+         *  Configures the char needing encoding, which is 0x13 as flow control char by default.
+         */
+        uint32_t esc_seq2:8;
+        /** esc_seq2_char0 : R/W; bitpos: [15:8]; default: 219;
+         *  Configures the first char of SLIP escape character, default value is 0xDB.
+         */
+        uint32_t esc_seq2_char0:8;
+        /** esc_seq2_char1 : R/W; bitpos: [23:16]; default: 223;
+         *  Configures the second char of SLIP escape character, default value is 0xDF.
+         */
+        uint32_t esc_seq2_char1:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uhci_esc_conf3_reg_t;
+
+/** Type of pkt_thres register
+ *  UCHI Packet Length Configuration Register
+ */
+typedef union {
+    struct {
+        /** pkt_thrs : R/W; bitpos: [12:0]; default: 128;
+         *  Configures the data packet's maximum length when UHCI_HEAD_EN is 0.
+         */
+        uint32_t pkt_thrs:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} uhci_pkt_thres_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  UHCI Interrupt Raw Register
+ */
+typedef union {
+    struct {
+        /** rx_start_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when
+         *  delimiter is sent successfully.
+         */
+        uint32_t rx_start_int_raw:1;
+        /** tx_start_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when
+         *  DMA detects delimiter.
+         */
+        uint32_t tx_start_int_raw:1;
+        /** rx_hung_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when
+         *  the required time of DMA receiving data  exceeds the configuration value.
+         */
+        uint32_t rx_hung_int_raw:1;
+        /** tx_hung_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when
+         *  the required time of DMA reading RAM data  exceeds the configuration value.
+         */
+        uint32_t tx_hung_int_raw:1;
+        /** send_s_reg_q_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered
+         *  when UHCI sends short packet successfully with single_send mode.
+         */
+        uint32_t send_s_reg_q_int_raw:1;
+        /** send_a_reg_q_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered
+         *  when UHCI sends short packet successfully with always_send mode.
+         */
+        uint32_t send_a_reg_q_int_raw:1;
+        /** out_eof_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when
+         *  there are errors in EOF.
+         */
+        uint32_t out_eof_int_raw:1;
+        /** app_ctrl0_int_raw : R/W; bitpos: [7]; default: 0;
+         *  Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when
+         *  UHCI_APP_CTRL0_IN_SET is set to 1.
+         */
+        uint32_t app_ctrl0_int_raw:1;
+        /** app_ctrl1_int_raw : R/W; bitpos: [8]; default: 0;
+         *  Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when
+         *  UHCI_APP_CTRL1_IN_SET is set to 1.
+         */
+        uint32_t app_ctrl1_int_raw:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uhci_int_raw_reg_t;
+
+/** Type of int_st register
+ *  UHCI Interrupt Status Register
+ */
+typedef union {
+    struct {
+        /** rx_start_int_st : RO; bitpos: [0]; default: 0;
+         *  Indicates the interrupt status of UHCI_RX_START_INT.
+         */
+        uint32_t rx_start_int_st:1;
+        /** tx_start_int_st : RO; bitpos: [1]; default: 0;
+         *  Indicates the interrupt status of UHCI_TX_START_INT.
+         */
+        uint32_t tx_start_int_st:1;
+        /** rx_hung_int_st : RO; bitpos: [2]; default: 0;
+         *  Indicates the interrupt status of UHCI_RX_HUNG_INT.
+         */
+        uint32_t rx_hung_int_st:1;
+        /** tx_hung_int_st : RO; bitpos: [3]; default: 0;
+         *  Indicates the interrupt status of UHCI_TX_HUNG_INT.
+         */
+        uint32_t tx_hung_int_st:1;
+        /** send_s_reg_q_int_st : RO; bitpos: [4]; default: 0;
+         *  Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT.
+         */
+        uint32_t send_s_reg_q_int_st:1;
+        /** send_a_reg_q_int_st : RO; bitpos: [5]; default: 0;
+         *  Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT.
+         */
+        uint32_t send_a_reg_q_int_st:1;
+        /** outlink_eof_err_int_st : RO; bitpos: [6]; default: 0;
+         *  Indicates the interrupt status of UHCI_OUT_EOF_INT.
+         */
+        uint32_t outlink_eof_err_int_st:1;
+        /** app_ctrl0_int_st : RO; bitpos: [7]; default: 0;
+         *  Indicates the interrupt status of UHCI_APP_CTRL0_INT.
+         */
+        uint32_t app_ctrl0_int_st:1;
+        /** app_ctrl1_int_st : RO; bitpos: [8]; default: 0;
+         *  Indicates the interrupt status of UHCI_APP_CTRL1_INT.
+         */
+        uint32_t app_ctrl1_int_st:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uhci_int_st_reg_t;
+
+/** Type of int_ena register
+ *  UHCI Interrupt Enable Register
+ */
+typedef union {
+    struct {
+        /** rx_start_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_RX_START_INT.
+         */
+        uint32_t rx_start_int_ena:1;
+        /** tx_start_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_TX_START_INT.
+         */
+        uint32_t tx_start_int_ena:1;
+        /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_RX_HUNG_INT.
+         */
+        uint32_t rx_hung_int_ena:1;
+        /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_TX_HUNG_INT.
+         */
+        uint32_t tx_hung_int_ena:1;
+        /** send_s_reg_q_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT.
+         */
+        uint32_t send_s_reg_q_int_ena:1;
+        /** send_a_reg_q_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT.
+         */
+        uint32_t send_a_reg_q_int_ena:1;
+        /** outlink_eof_err_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_OUT_EOF_INT.
+         */
+        uint32_t outlink_eof_err_int_ena:1;
+        /** app_ctrl0_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT.
+         */
+        uint32_t app_ctrl0_int_ena:1;
+        /** app_ctrl1_int_ena : R/W; bitpos: [8]; default: 0;
+         *  Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT.
+         */
+        uint32_t app_ctrl1_int_ena:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uhci_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  UHCI Interrupt Clear Register
+ */
+typedef union {
+    struct {
+        /** rx_start_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_RX_START_INT.
+         */
+        uint32_t rx_start_int_clr:1;
+        /** tx_start_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_TX_START_INT.
+         */
+        uint32_t tx_start_int_clr:1;
+        /** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT.
+         */
+        uint32_t rx_hung_int_clr:1;
+        /** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT.
+         */
+        uint32_t tx_hung_int_clr:1;
+        /** send_s_reg_q_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT.
+         */
+        uint32_t send_s_reg_q_int_clr:1;
+        /** send_a_reg_q_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT.
+         */
+        uint32_t send_a_reg_q_int_clr:1;
+        /** outlink_eof_err_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT.
+         */
+        uint32_t outlink_eof_err_int_clr:1;
+        /** app_ctrl0_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT.
+         */
+        uint32_t app_ctrl0_int_clr:1;
+        /** app_ctrl1_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT.
+         */
+        uint32_t app_ctrl1_int_clr:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uhci_int_clr_reg_t;
+
+
+/** Group: UHCI Status Register */
+/** Type of state0 register
+ *  UHCI Receive Status Register
+ */
+typedef union {
+    struct {
+        /** rx_err_cause : RO; bitpos: [2:0]; default: 0;
+         *  Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet
+         *  checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC
+         *  bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is
+         *  not found, but received packet is completed. 3'b110: CRC check error.
+         */
+        uint32_t rx_err_cause:3;
+        /** decode_state : RO; bitpos: [5:3]; default: 0;
+         *  Indicates UHCI decoder status.
+         */
+        uint32_t decode_state:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} uhci_state0_reg_t;
+
+/** Type of state1 register
+ *  UHCI Transmit Status Register
+ */
+typedef union {
+    struct {
+        /** encode_state : RO; bitpos: [2:0]; default: 0;
+         *  Indicates UHCI encoder status.
+         */
+        uint32_t encode_state:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} uhci_state1_reg_t;
+
+/** Type of rx_head register
+ *  UHCI Head Register
+ */
+typedef union {
+    struct {
+        /** rx_head : RO; bitpos: [31:0]; default: 0;
+         *  Stores the head of received packet.
+         */
+        uint32_t rx_head:32;
+    };
+    uint32_t val;
+} uhci_rx_head_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  UHCI Version Register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 35655936;
+         *  Configures version.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} uhci_date_reg_t;
+
+
+typedef struct uhci_dev_t {
+    volatile uhci_conf0_reg_t conf0;
+    volatile uhci_int_raw_reg_t int_raw;
+    volatile uhci_int_st_reg_t int_st;
+    volatile uhci_int_ena_reg_t int_ena;
+    volatile uhci_int_clr_reg_t int_clr;
+    volatile uhci_conf1_reg_t conf1;
+    volatile uhci_state0_reg_t state0;
+    volatile uhci_state1_reg_t state1;
+    volatile uhci_escape_conf_reg_t escape_conf;
+    volatile uhci_hung_conf_reg_t hung_conf;
+    volatile uhci_ack_num_reg_t ack_num;
+    volatile uhci_rx_head_reg_t rx_head;
+    volatile uhci_quick_sent_reg_t quick_sent;
+    volatile uhci_reg_q0_word0_reg_t reg_q0_word0;
+    volatile uhci_reg_q0_word1_reg_t reg_q0_word1;
+    volatile uhci_reg_q1_word0_reg_t reg_q1_word0;
+    volatile uhci_reg_q1_word1_reg_t reg_q1_word1;
+    volatile uhci_reg_q2_word0_reg_t reg_q2_word0;
+    volatile uhci_reg_q2_word1_reg_t reg_q2_word1;
+    volatile uhci_reg_q3_word0_reg_t reg_q3_word0;
+    volatile uhci_reg_q3_word1_reg_t reg_q3_word1;
+    volatile uhci_reg_q4_word0_reg_t reg_q4_word0;
+    volatile uhci_reg_q4_word1_reg_t reg_q4_word1;
+    volatile uhci_reg_q5_word0_reg_t reg_q5_word0;
+    volatile uhci_reg_q5_word1_reg_t reg_q5_word1;
+    volatile uhci_reg_q6_word0_reg_t reg_q6_word0;
+    volatile uhci_reg_q6_word1_reg_t reg_q6_word1;
+    volatile uhci_esc_conf0_reg_t esc_conf0;
+    volatile uhci_esc_conf1_reg_t esc_conf1;
+    volatile uhci_esc_conf2_reg_t esc_conf2;
+    volatile uhci_esc_conf3_reg_t esc_conf3;
+    volatile uhci_pkt_thres_reg_t pkt_thres;
+    volatile uhci_date_reg_t date;
+} uhci_dev_t;
+
+extern uhci_dev_t UHCI0;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(uhci_dev_t) == 0x84, "Invalid size of uhci_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/usb_utmi_struct.h

@@ -0,0 +1,231 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13430
+
+/**
+ * Following register description is taken from
+ * U2OPHYT40LL USB 2.0 OTG PHY specification v2.0
+ */
+
+typedef union {
+    struct {
+        /** clk_gate_rx : R/W; bitpos: [0]; default 2'b0;
+          * Clock Gating Control Signal for Rx.
+          * 2'b0 Lower power consumption
+          * 2'b1 Lowest power consumption mode
+          * 2'b2 Normal power consumption mode
+          */
+        uint32_t clk_gate_rx: 2;
+        /** clk_gate_tx : R/W; bitpos: [2]; default: 1'b0;
+          * Clock Gating Control Signal for Rx.
+          * 1'b0 Low power consumption mode
+          * 1'b1 Normal power consumption mode
+          */
+        uint32_t clk_gate_tx: 1;
+        /** adj_res_fs : Reserved; bitpos: [3]; default: 0;
+          * Fine tune the 45ohm termination resistor (FS)
+          * Reserved
+          */
+        uint32_t adj_res_fs: 2;
+        /** adj_res_hs : R/W; bitpos: [5]; default: 3'b100;
+          * Fine tune the 45ohm termination resistor (HS)
+          * 3'b000 40 Ohm
+          * 3'b100 45 Ohm
+          * 3'b110 50 Ohm
+          */
+        uint32_t adj_res_hs: 3;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} usb_utmi_fc_00_reg_t;
+
+typedef union {
+    struct {
+        /** adj_vref_sq : R/W; bitpos: [0]; default: 4'b0010;
+          * Squelch detection threshold voltage control bits
+          * 4'b0000  92 mV
+          * 4'b0010 124 mV
+          * 4'b0011 152 mV
+          */
+        uint32_t adj_vref_sq: 4;
+        /** adj_pw_hs : R/W; bitpos: [4]; default: 4'b1111;
+          * Super power saving with reduced output swing mode control bits (for HS mode only)
+          * 4'b0001 100 mV output swing
+          * 4'b0011 200 mV output swing
+          * 4'b0111 300 mV output swing
+          * 4'b1111 400 mV output swing
+          */
+        uint32_t adj_pw_hs: 4;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} usb_utmi_fc_01_reg_t;
+
+typedef union {
+    struct {
+        /** adj_iref_res : R/W; bitpos: [0]; default: 4'b0111
+          * Internal bias current adjustment control bits
+          * 4'b0000 125 uA
+          * 4'b0111 100 uA
+          * 4'b1111  78 uA
+          */
+        uint32_t adj_iref_res: 4;
+        /** adj_vsw_hs : R/W; bitpos: [4]; default: 3'b100
+          * Output eye shape adjustment control bits
+          * 3'b000 320 mV
+          * 3'b100 400 mV
+          * 3'b111 460 mV
+          */
+        uint32_t adj_vsw_hs: 3;
+        uint32_t reserved_7: 25;
+    };
+    uint32_t val;
+} usb_utmi_fc_02_reg_t;
+
+typedef union {
+    struct {
+        /** adj_pll : R/W; bitpos: [0]; default: 4'b0101
+          * PLL adjustment signal
+          */
+        uint32_t adj_pll: 4;
+        /** adj_osc : R/W; bitpos: [4]; default: 3'b000
+          * TX Clock phase adjust signal
+          */
+        uint32_t adj_txclk_phase: 3;
+        uint32_t reserved_7: 25;
+    };
+    uint32_t val;
+} usb_utmi_fc_03_reg_t;
+
+typedef union {
+    struct {
+        /** test_sel : R/W; bitpos: [0]; default: 8'b0
+          * The PHY has test_sel register here, which normally drives DTO (Digital Test Output) signal.
+          * In our implementation output of this register is left floating and DTO is driven from Probe module.
+          * Thus writing to this register has no effect and is renamed to 'reserved'
+          */
+        uint32_t reserved: 8;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} usb_utmi_fc_04_reg_t;
+
+typedef union {
+    struct {
+        /** rxgap_fix_en : R/W; bitpos: [0]; default: 1'b1
+          * RXGAP fix enable
+          */
+        uint32_t rxgap_fix_en: 1;
+        /** counter_sel : R/W; bitpos: [1]; default: 1'b0
+          * SIE_input sample enable
+          */
+        uint32_t counter_sel: 1;
+        /** clk_sel : R/W; bitpos: [2]; default: 1'b0
+          * CLK60_30 source select
+          */
+        uint32_t clk_sel: 1;
+        /** phy_mode_sel : R/W; bitpos: [3]; default: 1'b0
+          * PHY MODE select
+          */
+        uint32_t phy_mode_sel: 1;
+        /** uni_bidi_i : R/W; bitpos: [4]; default: 1'b0
+          * UNI_BIDI signal
+          */
+        uint32_t uni_bidi_i: 1;
+        /** short_5v : R/W; bitpos: [5]; default: 1'b0
+          * SHORT_5V signal
+          */
+        uint32_t short_5v: 1;
+        /** short_5v_enable : R/W; bitpos: [6]; default: 1'b1
+          * SHORT_5V_ENABLE signal
+          */
+        uint32_t short_5v_enable: 1;
+        /** usable_en : R/W; bitpos: [7]; default: 1'b1
+          * compare_begin delay time select
+          */
+        uint32_t usable_en: 1;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} usb_utmi_fc_05_reg_t;
+
+typedef union {
+    struct {
+        /** ls_par_en : R/W; bitpos: [0]; default: 1'b0
+          * LS mode with parallel enable
+          */
+        uint32_t ls_par_en: 1;
+        /** det_fseop_en : R/W; bitpos: [1]; default: 1'b0
+          * FS EOP detect enable
+          */
+        uint32_t det_fseop_en: 1;
+        /** pre_hphy_lsie : R/W; bitpos: [2]; default: 1'b0
+          * Dis_preamble enable
+          */
+        uint32_t pre_hphy_lsie: 1;
+        /** ls_kpalv_en : R/W; bitpos: [3]; default: 1'b0
+          * LS mode keep alive enable
+          */
+        uint32_t ls_kpalv_en: 1;
+        /** hs_tx2rx_dly_cnt_sel : R/W; bitpos: [4]; default: 3'b100
+          * PHY High-SPeed bus turn-around time select
+          */
+        uint32_t hs_tx2rx_dly_cnt_sel: 3;
+        uint32_t reserved_7: 25;
+    };
+    uint32_t val;
+} usb_utmi_fc_06_reg_t;
+
+typedef union {
+    struct {
+        /** cnt_num : R/W; bitpos: [1:0]; default: 2'b00
+          * 3 ms counter select
+          * 00: 392us (Default)
+          * 01: 682us
+          * 10: 1.36ms
+          * 11: 2.72ms
+          */
+        uint32_t cnt_num: 2;
+        /** clk480_sel : R/W; bitpos: [2]; default: 1'b0
+          * CLK_480 output time select
+          * 0: CLK_480 is valid after a delay time when PLL is locked
+          * 1: CLK_480 is valid immediately after PLL is locked
+          */
+        uint32_t clk480_sel: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} usb_utmi_fc_07_reg_t;
+
+typedef struct usb_utmi_dev_t {
+    volatile usb_utmi_fc_00_reg_t fc_00;
+    volatile usb_utmi_fc_01_reg_t fc_01;
+    volatile usb_utmi_fc_02_reg_t fc_02;
+    volatile usb_utmi_fc_03_reg_t fc_03;
+    volatile usb_utmi_fc_04_reg_t fc_04;
+    volatile usb_utmi_fc_05_reg_t fc_05;
+    volatile usb_utmi_fc_06_reg_t fc_06;
+    volatile usb_utmi_fc_07_reg_t fc_07;
+} usb_utmi_dev_t;
+
+extern usb_utmi_dev_t USB_UTMI;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(usb_utmi_dev_t) == 0x20, "Invalid size of usb_utmi_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/usb_wrap_eco5_struct.h

@@ -0,0 +1,139 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: USB wrapper registers. */
+/** Type of otg_conf register
+ *  USB wrapper configuration registers.
+ */
+typedef union {
+    struct {
+        /** srp_sessend_override : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to enable the software over-ride of srp session end signal. 1'b0:
+         *  the signal is controlled by the chip input, 1'b1: the signal is controlled by the
+         *  software.
+         */
+        uint32_t srp_sessend_override:1;
+        /** srp_sessend_value : R/W; bitpos: [1]; default: 0;
+         *  Software over-ride value of srp session end signal.
+         */
+        uint32_t srp_sessend_value:1;
+        /** phy_sel : R/W; bitpos: [2]; default: 0;
+         *  Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY.
+         */
+        uint32_t phy_sel:1;
+        /** dfifo_force_pd : R/W; bitpos: [3]; default: 0;
+         *  Force the dfifo to go into low power mode. The data in dfifo will not lost.
+         */
+        uint32_t dfifo_force_pd:1;
+        /** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0;
+         *  Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals
+         */
+        uint32_t dbnce_fltr_bypass:1;
+        /** exchg_pins_override : R/W; bitpos: [5]; default: 0;
+         *  Enable software controlle USB D+ D- exchange
+         */
+        uint32_t exchg_pins_override:1;
+        /** exchg_pins : R/W; bitpos: [6]; default: 0;
+         *  USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-.
+         */
+        uint32_t exchg_pins:1;
+        /** vrefh : R/W; bitpos: [8:7]; default: 0;
+         *  Control single-end input high threshold,1.76V to 2V, step 80mV.
+         */
+        uint32_t vrefh:2;
+        /** vrefl : R/W; bitpos: [10:9]; default: 0;
+         *  Control single-end input low threshold,0.8V to 1.04V, step 80mV.
+         */
+        uint32_t vrefl:2;
+        /** vref_override : R/W; bitpos: [11]; default: 0;
+         *  Enable software controlle input  threshold.
+         */
+        uint32_t vref_override:1;
+        /** pad_pull_override : R/W; bitpos: [12]; default: 0;
+         *  Enable software controlle USB D+ D- pullup pulldown.
+         */
+        uint32_t pad_pull_override:1;
+        /** dp_pullup : R/W; bitpos: [13]; default: 0;
+         *  Controlle USB D+ pullup.
+         */
+        uint32_t dp_pullup:1;
+        /** dp_pulldown : R/W; bitpos: [14]; default: 0;
+         *  Controlle USB D+ pulldown.
+         */
+        uint32_t dp_pulldown:1;
+        /** dm_pullup : R/W; bitpos: [15]; default: 0;
+         *  Controlle USB D+ pullup.
+         */
+        uint32_t dm_pullup:1;
+        /** dm_pulldown : R/W; bitpos: [16]; default: 0;
+         *  Controlle USB D+ pulldown.
+         */
+        uint32_t dm_pulldown:1;
+        /** pullup_value : R/W; bitpos: [17]; default: 0;
+         *  Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K.
+         */
+        uint32_t pullup_value:1;
+        /** usb_pad_enable : R/W; bitpos: [18]; default: 0;
+         *  Enable USB pad function.
+         */
+        uint32_t usb_pad_enable:1;
+        /** ahb_clk_force_on : R/W; bitpos: [19]; default: 0;
+         *  Force ahb clock always on.
+         */
+        uint32_t ahb_clk_force_on:1;
+        /** phy_clk_force_on : R/W; bitpos: [20]; default: 1;
+         *  Force phy clock always on.
+         */
+        uint32_t phy_clk_force_on:1;
+        uint32_t reserved_21:1;
+        /** dfifo_force_pu : R/W; bitpos: [22]; default: 0;
+         *  Disable the dfifo to go into low power mode. The data in dfifo will not lost.
+         */
+        uint32_t dfifo_force_pu:1;
+        uint32_t reserved_23:8;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Disable auto clock gating of CSR registers.
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} usb_wrap_otg_conf_reg_t;
+
+/** Type of date register
+ *  Date register.
+ */
+typedef union {
+    struct {
+        /** usb_wrap_date : HRO; bitpos: [31:0]; default: 587400452;
+         *  Date register.
+         */
+        uint32_t usb_wrap_date:32;
+    };
+    uint32_t val;
+} usb_wrap_date_reg_t;
+
+
+typedef struct {
+    volatile usb_wrap_otg_conf_reg_t otg_conf;
+    uint32_t reserved_004[254];
+    volatile usb_wrap_date_reg_t date;
+} usb_wrap_dev_t;
+
+extern usb_wrap_dev_t USB_WRAP;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(usb_wrap_dev_t) == 0x400, "Invalid size of usb_wrap_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/usb_wrap_reg.h

@@ -0,0 +1,182 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** USB_WRAP_OTG_CONF_REG register
+ *  USB wrapper configuration registers.
+ */
+#define USB_WRAP_OTG_CONF_REG (DR_REG_USB_WRAP_BASE + 0x0)
+/** USB_WRAP_SRP_SESSEND_OVERRIDE : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to enable the software over-ride of srp session end signal. 1'b0:
+ *  the signal is controlled by the chip input, 1'b1: the signal is controlled by the
+ *  software.
+ */
+#define USB_WRAP_SRP_SESSEND_OVERRIDE    (BIT(0))
+#define USB_WRAP_SRP_SESSEND_OVERRIDE_M  (USB_WRAP_SRP_SESSEND_OVERRIDE_V << USB_WRAP_SRP_SESSEND_OVERRIDE_S)
+#define USB_WRAP_SRP_SESSEND_OVERRIDE_V  0x00000001U
+#define USB_WRAP_SRP_SESSEND_OVERRIDE_S  0
+/** USB_WRAP_SRP_SESSEND_VALUE : R/W; bitpos: [1]; default: 0;
+ *  Software over-ride value of srp session end signal.
+ */
+#define USB_WRAP_SRP_SESSEND_VALUE    (BIT(1))
+#define USB_WRAP_SRP_SESSEND_VALUE_M  (USB_WRAP_SRP_SESSEND_VALUE_V << USB_WRAP_SRP_SESSEND_VALUE_S)
+#define USB_WRAP_SRP_SESSEND_VALUE_V  0x00000001U
+#define USB_WRAP_SRP_SESSEND_VALUE_S  1
+/** USB_WRAP_PHY_SEL : R/W; bitpos: [2]; default: 0;
+ *  Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY.
+ */
+#define USB_WRAP_PHY_SEL    (BIT(2))
+#define USB_WRAP_PHY_SEL_M  (USB_WRAP_PHY_SEL_V << USB_WRAP_PHY_SEL_S)
+#define USB_WRAP_PHY_SEL_V  0x00000001U
+#define USB_WRAP_PHY_SEL_S  2
+/** USB_WRAP_DFIFO_FORCE_PD : R/W; bitpos: [3]; default: 0;
+ *  Force the dfifo to go into low power mode. The data in dfifo will not lost.
+ */
+#define USB_WRAP_DFIFO_FORCE_PD    (BIT(3))
+#define USB_WRAP_DFIFO_FORCE_PD_M  (USB_WRAP_DFIFO_FORCE_PD_V << USB_WRAP_DFIFO_FORCE_PD_S)
+#define USB_WRAP_DFIFO_FORCE_PD_V  0x00000001U
+#define USB_WRAP_DFIFO_FORCE_PD_S  3
+/** USB_WRAP_DBNCE_FLTR_BYPASS : R/W; bitpos: [4]; default: 0;
+ *  Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals
+ */
+#define USB_WRAP_DBNCE_FLTR_BYPASS    (BIT(4))
+#define USB_WRAP_DBNCE_FLTR_BYPASS_M  (USB_WRAP_DBNCE_FLTR_BYPASS_V << USB_WRAP_DBNCE_FLTR_BYPASS_S)
+#define USB_WRAP_DBNCE_FLTR_BYPASS_V  0x00000001U
+#define USB_WRAP_DBNCE_FLTR_BYPASS_S  4
+/** USB_WRAP_EXCHG_PINS_OVERRIDE : R/W; bitpos: [5]; default: 0;
+ *  Enable software controlle USB D+ D- exchange
+ */
+#define USB_WRAP_EXCHG_PINS_OVERRIDE    (BIT(5))
+#define USB_WRAP_EXCHG_PINS_OVERRIDE_M  (USB_WRAP_EXCHG_PINS_OVERRIDE_V << USB_WRAP_EXCHG_PINS_OVERRIDE_S)
+#define USB_WRAP_EXCHG_PINS_OVERRIDE_V  0x00000001U
+#define USB_WRAP_EXCHG_PINS_OVERRIDE_S  5
+/** USB_WRAP_EXCHG_PINS : R/W; bitpos: [6]; default: 0;
+ *  USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-.
+ */
+#define USB_WRAP_EXCHG_PINS    (BIT(6))
+#define USB_WRAP_EXCHG_PINS_M  (USB_WRAP_EXCHG_PINS_V << USB_WRAP_EXCHG_PINS_S)
+#define USB_WRAP_EXCHG_PINS_V  0x00000001U
+#define USB_WRAP_EXCHG_PINS_S  6
+/** USB_WRAP_VREFH : R/W; bitpos: [8:7]; default: 0;
+ *  Control single-end input high threshold,1.76V to 2V, step 80mV.
+ */
+#define USB_WRAP_VREFH    0x00000003U
+#define USB_WRAP_VREFH_M  (USB_WRAP_VREFH_V << USB_WRAP_VREFH_S)
+#define USB_WRAP_VREFH_V  0x00000003U
+#define USB_WRAP_VREFH_S  7
+/** USB_WRAP_VREFL : R/W; bitpos: [10:9]; default: 0;
+ *  Control single-end input low threshold,0.8V to 1.04V, step 80mV.
+ */
+#define USB_WRAP_VREFL    0x00000003U
+#define USB_WRAP_VREFL_M  (USB_WRAP_VREFL_V << USB_WRAP_VREFL_S)
+#define USB_WRAP_VREFL_V  0x00000003U
+#define USB_WRAP_VREFL_S  9
+/** USB_WRAP_VREF_OVERRIDE : R/W; bitpos: [11]; default: 0;
+ *  Enable software controlle input  threshold.
+ */
+#define USB_WRAP_VREF_OVERRIDE    (BIT(11))
+#define USB_WRAP_VREF_OVERRIDE_M  (USB_WRAP_VREF_OVERRIDE_V << USB_WRAP_VREF_OVERRIDE_S)
+#define USB_WRAP_VREF_OVERRIDE_V  0x00000001U
+#define USB_WRAP_VREF_OVERRIDE_S  11
+/** USB_WRAP_PAD_PULL_OVERRIDE : R/W; bitpos: [12]; default: 0;
+ *  Enable software controlle USB D+ D- pullup pulldown.
+ */
+#define USB_WRAP_PAD_PULL_OVERRIDE    (BIT(12))
+#define USB_WRAP_PAD_PULL_OVERRIDE_M  (USB_WRAP_PAD_PULL_OVERRIDE_V << USB_WRAP_PAD_PULL_OVERRIDE_S)
+#define USB_WRAP_PAD_PULL_OVERRIDE_V  0x00000001U
+#define USB_WRAP_PAD_PULL_OVERRIDE_S  12
+/** USB_WRAP_DP_PULLUP : R/W; bitpos: [13]; default: 0;
+ *  Controlle USB D+ pullup.
+ */
+#define USB_WRAP_DP_PULLUP    (BIT(13))
+#define USB_WRAP_DP_PULLUP_M  (USB_WRAP_DP_PULLUP_V << USB_WRAP_DP_PULLUP_S)
+#define USB_WRAP_DP_PULLUP_V  0x00000001U
+#define USB_WRAP_DP_PULLUP_S  13
+/** USB_WRAP_DP_PULLDOWN : R/W; bitpos: [14]; default: 0;
+ *  Controlle USB D+ pulldown.
+ */
+#define USB_WRAP_DP_PULLDOWN    (BIT(14))
+#define USB_WRAP_DP_PULLDOWN_M  (USB_WRAP_DP_PULLDOWN_V << USB_WRAP_DP_PULLDOWN_S)
+#define USB_WRAP_DP_PULLDOWN_V  0x00000001U
+#define USB_WRAP_DP_PULLDOWN_S  14
+/** USB_WRAP_DM_PULLUP : R/W; bitpos: [15]; default: 0;
+ *  Controlle USB D+ pullup.
+ */
+#define USB_WRAP_DM_PULLUP    (BIT(15))
+#define USB_WRAP_DM_PULLUP_M  (USB_WRAP_DM_PULLUP_V << USB_WRAP_DM_PULLUP_S)
+#define USB_WRAP_DM_PULLUP_V  0x00000001U
+#define USB_WRAP_DM_PULLUP_S  15
+/** USB_WRAP_DM_PULLDOWN : R/W; bitpos: [16]; default: 0;
+ *  Controlle USB D+ pulldown.
+ */
+#define USB_WRAP_DM_PULLDOWN    (BIT(16))
+#define USB_WRAP_DM_PULLDOWN_M  (USB_WRAP_DM_PULLDOWN_V << USB_WRAP_DM_PULLDOWN_S)
+#define USB_WRAP_DM_PULLDOWN_V  0x00000001U
+#define USB_WRAP_DM_PULLDOWN_S  16
+/** USB_WRAP_PULLUP_VALUE : R/W; bitpos: [17]; default: 0;
+ *  Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K.
+ */
+#define USB_WRAP_PULLUP_VALUE    (BIT(17))
+#define USB_WRAP_PULLUP_VALUE_M  (USB_WRAP_PULLUP_VALUE_V << USB_WRAP_PULLUP_VALUE_S)
+#define USB_WRAP_PULLUP_VALUE_V  0x00000001U
+#define USB_WRAP_PULLUP_VALUE_S  17
+/** USB_WRAP_USB_PAD_ENABLE : R/W; bitpos: [18]; default: 0;
+ *  Enable USB pad function.
+ */
+#define USB_WRAP_USB_PAD_ENABLE    (BIT(18))
+#define USB_WRAP_USB_PAD_ENABLE_M  (USB_WRAP_USB_PAD_ENABLE_V << USB_WRAP_USB_PAD_ENABLE_S)
+#define USB_WRAP_USB_PAD_ENABLE_V  0x00000001U
+#define USB_WRAP_USB_PAD_ENABLE_S  18
+/** USB_WRAP_AHB_CLK_FORCE_ON : R/W; bitpos: [19]; default: 0;
+ *  Force ahb clock always on.
+ */
+#define USB_WRAP_AHB_CLK_FORCE_ON    (BIT(19))
+#define USB_WRAP_AHB_CLK_FORCE_ON_M  (USB_WRAP_AHB_CLK_FORCE_ON_V << USB_WRAP_AHB_CLK_FORCE_ON_S)
+#define USB_WRAP_AHB_CLK_FORCE_ON_V  0x00000001U
+#define USB_WRAP_AHB_CLK_FORCE_ON_S  19
+/** USB_WRAP_PHY_CLK_FORCE_ON : R/W; bitpos: [20]; default: 1;
+ *  Force phy clock always on.
+ */
+#define USB_WRAP_PHY_CLK_FORCE_ON    (BIT(20))
+#define USB_WRAP_PHY_CLK_FORCE_ON_M  (USB_WRAP_PHY_CLK_FORCE_ON_V << USB_WRAP_PHY_CLK_FORCE_ON_S)
+#define USB_WRAP_PHY_CLK_FORCE_ON_V  0x00000001U
+#define USB_WRAP_PHY_CLK_FORCE_ON_S  20
+/** USB_WRAP_DFIFO_FORCE_PU : R/W; bitpos: [22]; default: 0;
+ *  Disable the dfifo to go into low power mode. The data in dfifo will not lost.
+ */
+#define USB_WRAP_DFIFO_FORCE_PU    (BIT(22))
+#define USB_WRAP_DFIFO_FORCE_PU_M  (USB_WRAP_DFIFO_FORCE_PU_V << USB_WRAP_DFIFO_FORCE_PU_S)
+#define USB_WRAP_DFIFO_FORCE_PU_V  0x00000001U
+#define USB_WRAP_DFIFO_FORCE_PU_S  22
+/** USB_WRAP_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Disable auto clock gating of CSR registers.
+ */
+#define USB_WRAP_CLK_EN    (BIT(31))
+#define USB_WRAP_CLK_EN_M  (USB_WRAP_CLK_EN_V << USB_WRAP_CLK_EN_S)
+#define USB_WRAP_CLK_EN_V  0x00000001U
+#define USB_WRAP_CLK_EN_S  31
+
+/** USB_WRAP_DATE_REG register
+ *  Date register.
+ */
+#define USB_WRAP_DATE_REG (DR_REG_USB_WRAP_BASE + 0x3fc)
+/** USB_WRAP_USB_WRAP_DATE : HRO; bitpos: [31:0]; default: 587400452;
+ *  Date register.
+ */
+#define USB_WRAP_USB_WRAP_DATE    0xFFFFFFFFU
+#define USB_WRAP_USB_WRAP_DATE_M  (USB_WRAP_USB_WRAP_DATE_V << USB_WRAP_USB_WRAP_DATE_S)
+#define USB_WRAP_USB_WRAP_DATE_V  0xFFFFFFFFU
+#define USB_WRAP_USB_WRAP_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/register/hw_ver2/soc/usb_wrap_struct.h

@@ -0,0 +1,181 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: USB wrapper registers. */
+/** Type of otg_conf register
+ *  USB wrapper configuration registers.
+ */
+typedef union {
+    struct {
+        /** srp_sessend_override : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to enable the software over-ride of srp session end signal. 1'b0:
+         *  the signal is controlled by the chip input, 1'b1: the signal is controlled by the
+         *  software.
+         */
+        uint32_t srp_sessend_override:1;
+        /** srp_sessend_value : R/W; bitpos: [1]; default: 0;
+         *  Software over-ride value of srp session end signal.
+         */
+        uint32_t srp_sessend_value:1;
+        /** phy_sel : R/W; bitpos: [2]; default: 0;
+         *  Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY.
+         */
+        uint32_t phy_sel:1;
+        /** dfifo_force_pd : R/W; bitpos: [3]; default: 0;
+         *  Force the dfifo to go into low power mode. The data in dfifo will not lost.
+         */
+        uint32_t dfifo_force_pd:1;
+        /** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0;
+         *  Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals
+         */
+        uint32_t dbnce_fltr_bypass:1;
+        /** exchg_pins_override : R/W; bitpos: [5]; default: 0;
+         *  Enable software controlle USB D+ D- exchange
+         */
+        uint32_t exchg_pins_override:1;
+        /** exchg_pins : R/W; bitpos: [6]; default: 0;
+         *  USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-.
+         */
+        uint32_t exchg_pins:1;
+        /** vrefh : R/W; bitpos: [8:7]; default: 0;
+         *  Control single-end input high threshold,1.76V to 2V, step 80mV.
+         */
+        uint32_t vrefh:2;
+        /** vrefl : R/W; bitpos: [10:9]; default: 0;
+         *  Control single-end input low threshold,0.8V to 1.04V, step 80mV.
+         */
+        uint32_t vrefl:2;
+        /** vref_override : R/W; bitpos: [11]; default: 0;
+         *  Enable software controlle input  threshold.
+         */
+        uint32_t vref_override:1;
+        /** pad_pull_override : R/W; bitpos: [12]; default: 0;
+         *  Enable software controlle USB D+ D- pullup pulldown.
+         */
+        uint32_t pad_pull_override:1;
+        /** dp_pullup : R/W; bitpos: [13]; default: 0;
+         *  Controlle USB D+ pullup.
+         */
+        uint32_t dp_pullup:1;
+        /** dp_pulldown : R/W; bitpos: [14]; default: 0;
+         *  Controlle USB D+ pulldown.
+         */
+        uint32_t dp_pulldown:1;
+        /** dm_pullup : R/W; bitpos: [15]; default: 0;
+         *  Controlle USB D+ pullup.
+         */
+        uint32_t dm_pullup:1;
+        /** dm_pulldown : R/W; bitpos: [16]; default: 0;
+         *  Controlle USB D+ pulldown.
+         */
+        uint32_t dm_pulldown:1;
+        /** pullup_value : R/W; bitpos: [17]; default: 0;
+         *  Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K.
+         */
+        uint32_t pullup_value:1;
+        /** usb_pad_enable : R/W; bitpos: [18]; default: 0;
+         *  Enable USB pad function.
+         */
+        uint32_t usb_pad_enable:1;
+        /** ahb_clk_force_on : R/W; bitpos: [19]; default: 0;
+         *  Force ahb clock always on.
+         */
+        uint32_t ahb_clk_force_on:1;
+        /** phy_clk_force_on : R/W; bitpos: [20]; default: 1;
+         *  Force phy clock always on.
+         */
+        uint32_t phy_clk_force_on:1;
+        /** phy_tx_edge_sel : R/W; bitpos: [21]; default: 0;
+         *  Select PHY tx signal output clock edge.1'b0: negedge;1'b1: posedge.
+         */
+        uint32_t phy_tx_edge_sel:1;
+        /** dfifo_force_pu : R/W; bitpos: [22]; default: 0;
+         *  Disable the dfifo to go into low power mode. The data in dfifo will not lost.
+         */
+        uint32_t dfifo_force_pu:1;
+        uint32_t reserved_23:8;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Disable auto clock gating of CSR registers.
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} usb_wrap_otg_conf_reg_t;
+
+/** Type of test_conf register
+ *  TEST relative configuration registers.
+ */
+typedef union {
+    struct {
+        /** test_enable : R/W; bitpos: [0]; default: 0;
+         *  Enable to test the USB pad.
+         */
+        uint32_t test_enable:1;
+        /** test_usb_wrap_oe : R/W; bitpos: [1]; default: 0;
+         *  USB pad oen in test.
+         */
+        uint32_t test_usb_wrap_oe:1;
+        /** test_tx_dp : R/W; bitpos: [2]; default: 0;
+         *  USB D+ tx value in test.
+         */
+        uint32_t test_tx_dp:1;
+        /** test_tx_dm : R/W; bitpos: [3]; default: 0;
+         *  USB D- tx value in test.
+         */
+        uint32_t test_tx_dm:1;
+        /** test_rx_rcv : RO; bitpos: [4]; default: 0;
+         *  USB differential rx value in test.
+         */
+        uint32_t test_rx_rcv:1;
+        /** test_rx_dp : RO; bitpos: [5]; default: 0;
+         *  USB D+ rx value in test.
+         */
+        uint32_t test_rx_dp:1;
+        /** test_rx_dm : RO; bitpos: [6]; default: 0;
+         *  USB D- rx value in test.
+         */
+        uint32_t test_rx_dm:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} usb_wrap_test_conf_reg_t;
+
+/** Type of date register
+ *  Date register.
+ */
+typedef union {
+    struct {
+        /** usb_wrap_date : HRO; bitpos: [31:0]; default: 587400452;
+         *  Date register.
+         */
+        uint32_t usb_wrap_date:32;
+    };
+    uint32_t val;
+} usb_wrap_date_reg_t;
+
+
+typedef struct usb_wrap_dev_t {
+    volatile usb_wrap_otg_conf_reg_t otg_conf;
+    volatile usb_wrap_test_conf_reg_t test_conf;
+    uint32_t reserved_008[253];
+    volatile usb_wrap_date_reg_t date;
+} usb_wrap_dev_t;
+
+extern usb_wrap_dev_t USB_WRAP;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(usb_wrap_dev_t) == 0x400, "Invalid size of usb_wrap_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif