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fix(driver_spi): fixed c5/c61/h21 eco spi master rx and slave rx issue

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wanckl
2025-06-13 21:53:48 +08:00
parent 7f325d47bf
commit a48afb4711
5 changed files with 30 additions and 13 deletions
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9
components/esp_driver_spi/test_apps/master/main/test_spi_master.c
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@@ -150,7 +150,9 @@ TEST_CASE("SPI Master clk_source and divider accuracy", "[spi]")
spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
devcfg.clock_source = spi_clk_sour[sour_idx];
devcfg.clock_speed_hz = MIN(IDF_TARGET_MAX_SPI_CLK_FREQ, clock_source_hz) >> test_time;
#if CONFIG_IDF_TARGET_ESP32
devcfg.flags |= SPI_DEVICE_HALFDUPLEX; //esp32 half duplex to work on high freq
#endif
#if SOC_SPI_SUPPORT_CLK_RC_FAST
if (devcfg.clock_source == SPI_CLK_SRC_RC_FAST) {
devcfg.clock_speed_hz /= 2; //rc_fast have bad accuracy, test at low speed
@@ -160,6 +162,13 @@ TEST_CASE("SPI Master clk_source and divider accuracy", "[spi]")
// one trans first to trigger lazy load
TEST_ESP_OK(spi_device_polling_transmit(handle, &trans));
// test single tx/rx under full duplex mode, refer to `TEST_CASE_MULTIPLE_DEVICES("SPI Master: FD, DMA, Master Single Direction Test"...`
if (!(devcfg.flags && SPI_DEVICE_HALFDUPLEX)) {
trans.tx_buffer = NULL;
trans.rxlength = trans.length;
trans.rx_buffer = sendbuf;
}
// calculate theoretical transaction time by actual freq and trans length
int real_freq_khz;
spi_device_get_actual_freq(handle, &real_freq_khz);

10
components/hal/esp32c5/include/hal/spi_ll.h
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@@ -6,12 +6,10 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* The LL layer for ESP32C5 SPI register operations
* It is NOT public api, don't use in application code.
******************************************************************************/
// The LL layer for SPI register operations
#pragma once
#include <stdlib.h> //for abs()
@@ -198,6 +196,10 @@ static inline void spi_ll_master_init(spi_dev_t *hw)
hw->user.usr_miso_highpart = 0;
hw->user.usr_mosi_highpart = 0;
//Disable unused error_end condition
hw->user1.mst_wfull_err_end_en = 0;
hw->user2.mst_rempty_err_end_en = 0;
//Disable unneeded ints
hw->slave.val = 0;
hw->user.val = 0;

12
components/hal/esp32c61/include/hal/spi_ll.h
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@@ -1,17 +1,15 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* The LL layer for ESP32C61 SPI register operations
* It is NOT public api, don't use in application code.
******************************************************************************/
// The LL layer for SPI register operations
#pragma once
#include <stdlib.h> //for abs()
@@ -199,6 +197,10 @@ static inline void spi_ll_master_init(spi_dev_t *hw)
hw->user.usr_miso_highpart = 0;
hw->user.usr_mosi_highpart = 0;
//Disable unused error_end condition
hw->user1.mst_wfull_err_end_en = 0;
hw->user2.mst_rempty_err_end_en = 0;
//Disable unneeded ints
hw->slave.val = 0;
hw->user.val = 0;

8
components/hal/esp32h21/include/hal/spi_ll.h
View File

@@ -6,8 +6,8 @@
/*******************************************************************************
* NOTICE
* The LL layer for SPI register operations
* Not public api, don't use in application code.
* The LL layer for ESP32H21 SPI register operations
* It is NOT public api, don't use in application code.
******************************************************************************/
#pragma once
@@ -162,6 +162,10 @@ static inline void spi_ll_master_init(spi_dev_t *hw)
hw->user.usr_miso_highpart = 0;
hw->user.usr_mosi_highpart = 0;
//Disable unused error_end condition
hw->user1.mst_wfull_err_end_en = 0;
hw->user2.mst_rempty_err_end_en = 0;
//Disable unneeded ints
hw->slave.val = 0;
hw->user.val = 0;

4
components/soc/esp32c61/include/soc/gpio_pins.h
View File

@@ -10,8 +10,8 @@
extern "C" {
#endif
#define GPIO_MATRIX_CONST_ONE_INPUT (0x20)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x30)
#define GPIO_MATRIX_CONST_ONE_INPUT (0x40)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x60)
#ifdef __cplusplus
}