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feat(ble): support ble sleep using 136 kHz RC on ESP32-C2

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(cherry picked from commit 73f1084bf8)

Co-authored-by: cjin <jinchen@espressif.com>
This commit is contained in:
Jin Chen
2025-04-22 19:05:27 +08:00
parent 5d9623dbcc
commit a6c8a080f4
4 changed files with 82 additions and 19 deletions
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17
components/bt/controller/esp32c2/Kconfig.in
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@ -445,6 +445,23 @@ config BT_LE_LL_SCA
help
Sleep clock accuracy of our device (in ppm)
config BT_LE_LL_PEER_SCA_SET_ENABLE
bool "Enable to set constant peer SCA"
default n
help
Enable setting of constant peer SCA, use this if peer device has SCA larger than 500 PPM.
Enable this option, the controller will always use BT_LE_LL_PEER_SCA as the peer SCA value
to calculate the window widening instead of the value received from peer device.
config BT_LE_LL_PEER_SCA
int "Constant peer sleep clock accuracy value"
range 0 10000
depends on BT_LE_LL_PEER_SCA_SET_ENABLE
default 0
help
Set the sleep clock accuracy of peer device
config BT_LE_MAX_CONNECTIONS
int "Maximum number of concurrent connections"
depends on !BT_NIMBLE_ENABLED

77
components/bt/controller/esp32c2/bt.c
View File

@ -43,6 +43,7 @@
#include "soc/syscon_reg.h"
#include "soc/modem_clkrst_reg.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_clk_tree_common.h"
#include "bt_osi_mem.h"
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
@ -149,6 +150,9 @@ extern void r_ble_rtc_wake_up_state_clr(void);
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
extern void esp_ble_set_wakeup_overhead(uint32_t overhead);
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
#if CONFIG_BT_LE_LL_PEER_SCA_SET_ENABLE
extern void r_ble_ll_customize_peer_sca_set(uint16_t peer_sca);
#endif // CONFIG_BT_LE_LL_PEER_SCA_SET_ENABLE
extern int os_msys_init(void);
extern void os_msys_buf_free(void);
extern int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x,
@ -466,7 +470,13 @@ static bool s_ble_active = false;
static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
#define BTDM_MIN_TIMER_UNCERTAINTY_US (200)
#endif // CONFIG_PM_ENABLE
#ifdef CONFIG_XTAL_FREQ_26
#define MAIN_XTAL_FREQ_HZ (26000000)
#else
#define MAIN_XTAL_FREQ_HZ (40000000)
#endif
static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID;
static DRAM_ATTR uint32_t s_bt_lpclk_freq = 100000;
#define BLE_RTC_DELAY_US (1800)
@ -597,6 +607,10 @@ modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void)
void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src)
{
if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) {
return;
}
if (clk_src >= MODEM_CLOCK_LPCLK_SRC_MAX) {
return;
}
@ -604,6 +618,27 @@ void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src)
s_bt_lpclk_src = clk_src;
}
uint32_t esp_bt_get_lpclk_freq(void)
{
return s_bt_lpclk_freq;
}
void esp_bt_set_lpclk_freq(uint32_t clk_freq)
{
if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) {
return;
}
if (!clk_freq) {
return;
}
if (MAIN_XTAL_FREQ_HZ % clk_freq) {
return;
}
s_bt_lpclk_freq = clk_freq;
}
void controller_sleep_cb(uint32_t enable_tick, void *arg)
{
if (!s_ble_active) {
@ -622,11 +657,18 @@ void controller_wakeup_cb(void *arg)
if (s_ble_active) {
return;
}
esp_phy_enable(PHY_MODEM_BT);
// need to check if need to call pm lock here
#ifdef CONFIG_PM_ENABLE
esp_pm_config_t pm_config;
esp_pm_lock_acquire(s_pm_lock);
esp_pm_get_configuration(&pm_config);
assert(esp_rom_get_cpu_ticks_per_us() == pm_config.max_freq_mhz);
#endif //CONFIG_PM_ENABLE
esp_phy_enable(PHY_MODEM_BT);
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC_SLOW) {
uint32_t *clk_freq = (uint32_t *)arg;
*clk_freq = esp_clk_tree_lp_slow_get_freq_hz(ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED) / 5;
}
// need to check if need to call pm lock here
s_ble_active = true;
}
@ -703,11 +745,7 @@ static void esp_bt_rtc_slow_clk_select(modem_clock_lpclk_src_t slow_clk_src)
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_8M_S);
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S);
#ifdef CONFIG_XTAL_FREQ_26
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 129, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
#else
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 249, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
#endif // CONFIG_XTAL_FREQ_26
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, (MAIN_XTAL_FREQ_HZ/(5 * s_bt_lpclk_freq) - 1), MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
break;
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using external 32.768 kHz XTAL as clock source");
@ -717,6 +755,14 @@ static void esp_bt_rtc_slow_clk_select(modem_clock_lpclk_src_t slow_clk_src)
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S);
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 0, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
break;
case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "Using 136 kHz RC as clock source, use with caution as it may not maintain ACL or Sync process due to low clock accuracy!");
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_8M_S);
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S);
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 0, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
break;
default:
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported slow clock");
assert(0);
@ -732,23 +778,26 @@ static modem_clock_lpclk_src_t ble_rtc_clk_init(esp_bt_controller_config_t *cfg)
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
#else
#if CONFIG_RTC_CLK_SRC_INT_RC
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC_SLOW;
#elif CONFIG_RTC_CLK_SRC_EXT_OSC
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_EXT32K;
} else {
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
}
#endif // CONFIG_RTC_CLK_SRC_INT_RC
#endif // CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
}
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_EXT32K) {
cfg->rtc_freq = 32768;
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
#ifdef CONFIG_XTAL_FREQ_26
cfg->rtc_freq = 40000;
#else
cfg->rtc_freq = 32000;
#endif // CONFIG_XTAL_FREQ_26
cfg->rtc_freq = s_bt_lpclk_freq;
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC_SLOW) {
cfg->rtc_freq = esp_clk_tree_lp_slow_get_freq_hz(ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED) / 5;
cfg->ble_ll_sca = 3000;
}
esp_bt_rtc_slow_clk_select(s_bt_lpclk_src);
return s_bt_lpclk_src;
@ -851,6 +900,10 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
goto modem_deint;
}
#if CONFIG_BT_LE_LL_PEER_SCA_SET_ENABLE
r_ble_ll_customize_peer_sca_set(CONFIG_BT_LE_LL_PEER_SCA);
#endif // CONFIG_BT_LE_LL_PEER_SCA_SET_ENABLE
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version());
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble rom commit:[%s]", r_ble_controller_get_rom_compile_version());

5
components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld
View File

@ -236,7 +236,6 @@ r_ble_ll_conn_master_init = 0x40000df8;
r_ble_ll_conn_module_deinit = 0x40000dfc;
r_ble_ll_conn_module_init = 0x40000e00;
r_ble_ll_conn_module_reset = 0x40000e04;
r_ble_ll_conn_next_event = 0x40000e08;
r_ble_ll_conn_num_comp_pkts_event_send = 0x40000e0c;
r_ble_ll_conn_prepare_tx_pdu = 0x40000e10;
r_ble_ll_conn_process_conn_params = 0x40000e14;
@ -438,7 +437,6 @@ r_ble_ll_read_rf_path_compensation = 0x40001120;
r_ble_ll_read_supp_features = 0x40001124;
r_ble_ll_read_supp_states = 0x40001128;
r_ble_ll_read_tx_power = 0x4000112c;
r_ble_ll_reset = 0x40001130;
r_ble_ll_resolv_clear_all_pl_bit = 0x40001134;
r_ble_ll_resolv_clear_all_wl_bit = 0x40001138;
r_ble_ll_resolv_deinit = 0x4000113c;
@ -598,7 +596,6 @@ r_ble_ll_usecs_to_ticks_round_up = 0x400013a0;
r_ble_ll_utils_calc_access_addr = 0x400013a4;
r_ble_ll_utils_calc_dci_csa2 = 0x400013a8;
r_ble_ll_utils_calc_num_used_chans = 0x400013ac;
r_ble_ll_utils_calc_window_widening = 0x400013b0;
r_ble_ll_utils_csa2_perm = 0x400013b4;
r_ble_ll_utils_csa2_prng = 0x400013b8;
r_ble_ll_utils_remapped_channel = 0x400013bc;
@ -911,11 +908,9 @@ r_ble_phy_sequence_update_conn_ind_params = 0x40001884;
r_ble_phy_set_adv_mode = 0x40001888;
r_ble_phy_set_coex_pti = 0x4000188c;
r_ble_phy_set_conn_ind_pdu = 0x40001890;
r_ble_phy_set_conn_mode = 0x40001894;
r_ble_phy_set_dev_address = 0x40001898;
r_ble_phy_set_rx_pwr_compensation = 0x4000189c;
r_ble_phy_set_rxhdr = 0x400018a0;
r_ble_phy_set_scan_mode = 0x400018a4;
r_ble_phy_set_sequence_mode = 0x400018a8;
r_ble_phy_set_single_packet_rx_sequence = 0x400018ac;
r_ble_phy_set_single_packet_tx_sequence = 0x400018b0;

2
components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld
View File

@ -480,7 +480,6 @@ r_ble_ll_usecs_to_ticks_round_up = 0x400013a0;
r_ble_ll_utils_calc_access_addr = 0x400013a4;
r_ble_ll_utils_calc_dci_csa2 = 0x400013a8;
r_ble_ll_utils_calc_num_used_chans = 0x400013ac;
r_ble_ll_utils_calc_window_widening = 0x400013b0;
r_ble_ll_utils_csa2_perm = 0x400013b4;
r_ble_ll_utils_csa2_prng = 0x400013b8;
r_ble_ll_utils_remapped_channel = 0x400013bc;
@ -719,7 +718,6 @@ r_ble_phy_sequence_tx_end_invoke = 0x40001880;
r_ble_phy_sequence_update_conn_ind_params = 0x40001884;
r_ble_phy_set_coex_pti = 0x4000188c;
r_ble_phy_set_conn_ind_pdu = 0x40001890;
r_ble_phy_set_conn_mode = 0x40001894;
r_ble_phy_set_dev_address = 0x40001898;
r_ble_phy_set_rx_pwr_compensation = 0x4000189c;
r_ble_phy_set_single_packet_rx_sequence = 0x400018ac;