mirror of
https://github.com/espressif/esp-idf.git
synced 2025-08-04 21:24:32 +02:00
feat(soc): Update ESP32-C5's key manager reg and struct files to ECO2
- Also added a new soc_cap to denote if key manager key deployment is available
This commit is contained in:
harshal.patil
@@ -14,16 +14,16 @@
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#include "esp_err.h"
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#include "hal/efuse_hal.h"
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#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY || SOC_KEY_MANAGER_FE_KEY_DEPLOY
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#if SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
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#include "hal/key_mgr_ll.h"
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#endif
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#endif /* SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT */
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__attribute__((unused)) static const char *TAG = "esp_security";
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static void esp_key_mgr_init(void)
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{
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// The following code initializes the key manager.
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#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY || SOC_KEY_MANAGER_FE_KEY_DEPLOY
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#if SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
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// Enable key manager clock
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// Using ll APIs which do not require critical section
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_key_mgr_ll_enable_bus_clock(true);
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@@ -31,7 +31,7 @@ static void esp_key_mgr_init(void)
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_key_mgr_ll_reset_register();
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while (key_mgr_ll_get_state() != ESP_KEY_MGR_STATE_IDLE) {
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};
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#endif /* SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY || SOC_KEY_MANAGER_FE_KEY_DEPLOY */
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#endif /* SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT */
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}
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ESP_SYSTEM_INIT_FN(esp_security_init, SECONDARY, BIT(0), 103)
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@@ -1407,6 +1407,10 @@ config SOC_EFUSE_ECDSA_KEY_P384
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bool
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default y
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config SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
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bool
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default y
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config SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
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bool
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default y
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@@ -541,8 +541,9 @@
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#define SOC_EFUSE_ECDSA_KEY_P384 1
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/*-------------------------- Key Manager CAPS----------------------------*/
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#define SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY 1 /*!< Key manager responsible to deploy ECDSA key */
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#define SOC_KEY_MANAGER_FE_KEY_DEPLOY 1 /*!< Key manager responsible to deploy Flash Encryption key */
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#define SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT 1 /*!< Key manager supports key deployment */
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#define SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY 1 /*!< Key manager responsible to deploy ECDSA key */
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#define SOC_KEY_MANAGER_FE_KEY_DEPLOY 1 /*!< Key manager responsible to deploy Flash Encryption key */
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/*-------------------------- Secure Boot CAPS----------------------------*/
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#define SOC_SECURE_BOOT_V2_RSA 1
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@@ -148,44 +148,46 @@ extern "C" {
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#define KEYMNG_USE_EFUSE_KEY_V 0x0000001FU
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#define KEYMNG_USE_EFUSE_KEY_S 0
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/* KEYMNG_USE_EFUSE_KEY_ECDSA : R/W ;bitpos:[0] ;default: 1'd0 ; */
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/*description: Set this bit to choose efuse key instead of key manager deployed key for ecdsa.*/
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/** KEYMNG_USE_EFUSE_KEY_ECDSA : R/W; bitpos:[0]; default: 0;
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* Set this bit to choose efuse key instead of key manager deployed key for ecdsa.
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*/
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#define KEYMNG_USE_EFUSE_KEY_ECDSA (BIT(0))
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#define KEYMNG_USE_EFUSE_KEY_ECDSA_M ((KEYMNG_USE_EFUSE_KEY_ECDSA_V)<<(KEYMNG_USE_EFUSE_KEY_ECDSA_S))
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#define KEYMNG_USE_EFUSE_KEY_ECDSA_V 0x1
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#define KEYMNG_USE_EFUSE_KEY_ECDSA_M (KEYMNG_USE_EFUSE_KEY_ECDSA_V << KEYMNG_USE_EFUSE_KEY_ECDSA_S)
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#define KEYMNG_USE_EFUSE_KEY_ECDSA_V 0x00000001U
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#define KEYMNG_USE_EFUSE_KEY_ECDSA_S 0
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/* KEYMNG_USE_EFUSE_KEY_FLASH : R/W ;bitpos:[1] ;default: 1'd0 ; */
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/*description: Set this bit to choose efuse key instead of key manager deployed key for flash.*/
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/** KEYMNG_USE_EFUSE_KEY_FLASH : R/W; bitpos:[1]; default: 0;
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* Set this bit to choose efuse key instead of key manager deployed key for flash.
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*/
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#define KEYMNG_USE_EFUSE_KEY_FLASH (BIT(1))
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#define KEYMNG_USE_EFUSE_KEY_FLASH_M ((KEYMNG_USE_EFUSE_KEY_FLASH_V)<<(KEYMNG_USE_EFUSE_KEY_FLASH_S))
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#define KEYMNG_USE_EFUSE_KEY_FLASH_V 0x1
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#define KEYMNG_USE_EFUSE_KEY_FLASH_M (KEYMNG_USE_EFUSE_KEY_FLASH_V << KEYMNG_USE_EFUSE_KEY_FLASH_S)
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#define KEYMNG_USE_EFUSE_KEY_FLASH_V 0x00000001U
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#define KEYMNG_USE_EFUSE_KEY_FLASH_S 1
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/* KEYMNG_USE_EFUSE_KEY_HMAC : R/W ;bitpos:[0] ;default: 1'd0 ; */
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/*description: Set this bit to choose efuse key instead of key manager deployed key for hmac.*/
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/** KEYMNG_USE_EFUSE_KEY_HMAC : R/W; bitpos:[0]; default: 0;
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* Set this bit to choose efuse key instead of key manager deployed key for hmac.
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*/
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#define KEYMNG_USE_EFUSE_KEY_HMAC (BIT(2))
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#define KEYMNG_USE_EFUSE_KEY_HMAC_M ((KEYMNG_USE_EFUSE_KEY_HMAC_V)<<(KEYMNG_USE_EFUSE_KEY_HMAC_S))
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#define KEYMNG_USE_EFUSE_KEY_HMAC_V 0x1
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#define KEYMNG_USE_EFUSE_KEY_HMAC_M (KEYMNG_USE_EFUSE_KEY_HMAC_V << KEYMNG_USE_EFUSE_KEY_HMAC_S)
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#define KEYMNG_USE_EFUSE_KEY_HMAC_V 0x00000001U
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#define KEYMNG_USE_EFUSE_KEY_HMAC_S 2
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/* KEYMNG_USE_EFUSE_KEY_DS : R/W ;bitpos:[1] ;default: 1'd0 ; */
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/*description: Set this bit to choose efuse key instead of key manager deployed key for ds.*/
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/** KEYMNG_USE_EFUSE_KEY_DS : R/W; bitpos:[1]; default: 0;
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* Set this bit to choose efuse key instead of key manager deployed key for ds.
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*/
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#define KEYMNG_USE_EFUSE_KEY_DS (BIT(3))
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#define KEYMNG_USE_EFUSE_KEY_DS_M ((KEYMNG_USE_EFUSE_KEY_DS_V)<<(KEYMNG_USE_EFUSE_KEY_DS_S))
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#define KEYMNG_USE_EFUSE_KEY_DS_V 0x1
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#define KEYMNG_USE_EFUSE_KEY_DS_M (KEYMNG_USE_EFUSE_KEY_DS_V << KEYMNG_USE_EFUSE_KEY_DS_S)
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#define KEYMNG_USE_EFUSE_KEY_DS_V 0x00000001U
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#define KEYMNG_USE_EFUSE_KEY_DS_S 3
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/* KEYMNG_USE_EFUSE_KEY_PSRAM : R/W ;bitpos:[1] ;default: 1'd0 ; */
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/*description: Set this bit to choose efuse key instead of key manager deployed key for psram.*/
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/** KEYMNG_USE_EFUSE_KEY_PSRAM : R/W; bitpos:[1]; default: 0;
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* Set this bit to choose efuse key instead of key manager deployed key for psram.
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*/
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#define KEYMNG_USE_EFUSE_KEY_PSRAM (BIT(4))
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#define KEYMNG_USE_EFUSE_KEY_PSRAM_M ((KEYMNG_USE_EFUSE_KEY_PSRAM_V)<<(KEYMNG_USE_EFUSE_KEY_PSRAM_S))
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#define KEYMNG_USE_EFUSE_KEY_PSRAM_V 0x1
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#define KEYMNG_USE_EFUSE_KEY_PSRAM_M (KEYMNG_USE_EFUSE_KEY_PSRAM_V << KEYMNG_USE_EFUSE_KEY_PSRAM_S)
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#define KEYMNG_USE_EFUSE_KEY_PSRAM_V 0x00000001U
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#define KEYMNG_USE_EFUSE_KEY_PSRAM_S 4
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/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [9:5]; default: 15;
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* The core clock cycle number to sample one rng input data. Please set it bigger than
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* the clock cycle ratio: T_rng/T_km
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@@ -231,70 +233,42 @@ extern "C" {
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#define KEYMNG_USE_EFUSE_KEY_LOCK_V 0x0000001FU
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#define KEYMNG_USE_EFUSE_KEY_LOCK_S 0
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/* KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA : R/W1 ;bitpos:[0] ;default: 1'd0 ; */
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/*description: Write 1 to lock reg_use_efuse_key for esdsa*/
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/** KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA : R/W1 ;bitpos:[0]; default: 0;
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* Write 1 to lock reg_use_efuse_key for esdsa
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*/
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#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA (BIT(0))
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#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_M ((KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S))
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#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V 0x1
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#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_M (KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V << KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S)
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#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V 0x00000001U
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#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S 0
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/* KEYMNG_USE_EFUSE_KEY_LOCK_FLASH : R/W1 ;bitpos:[1] ;default: 1'd0 ; */
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/*description: Write 1 to lock reg_use_efuse_key for FLASH*/
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/** KEYMNG_USE_EFUSE_KEY_LOCK_FLASH : R/W1 ;bitpos:[1]; default: 0;
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* Write 1 to lock reg_use_efuse_key for FLASH
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*/
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#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH (BIT(1))
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#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_M ((KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_S))
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#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_V 0x1
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#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_M (KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_V << KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_S)
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#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_V 0x00000001U
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#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_S 1
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/* KEYMNG_USE_EFUSE_KEY_LOCK_HMAC : R/W1 ;bitpos:[0] ;default: 1'd0 ; */
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/*description: Write 1 to lock reg_use_efuse_key for hmac*/
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/** KEYMNG_USE_EFUSE_KEY_LOCK_HMAC : R/W1 ;bitpos:[0]; default: 0;
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* Write 1 to lock reg_use_efuse_key for hmac
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*/
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#define KEYMNG_USE_EFUSE_KEY_LOCK_HMAC (BIT(2))
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#define KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_M ((KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_S))
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#define KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_V 0x1
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#define KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_M (KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_V << KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_S)
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#define KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_V 0x00000001U
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#define KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_S 2
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/* KEYMNG_USE_EFUSE_KEY_LOCK_DS : R/W1 ;bitpos:[1] ;default: 1'd0 ; */
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/*description: Write 1 to lock reg_use_efuse_key for ds*/
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/** KEYMNG_USE_EFUSE_KEY_LOCK_DS : R/W1 ;bitpos:[1]; default: 0;
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* Write 1 to lock reg_use_efuse_key for ds
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*/
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#define KEYMNG_USE_EFUSE_KEY_LOCK_DS (BIT(3))
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#define KEYMNG_USE_EFUSE_KEY_LOCK_DS_M ((KEYMNG_USE_EFUSE_KEY_LOCK_DS_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_DS_S))
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#define KEYMNG_USE_EFUSE_KEY_LOCK_DS_V 0x1
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#define KEYMNG_USE_EFUSE_KEY_LOCK_DS_M (KEYMNG_USE_EFUSE_KEY_LOCK_DS_V << KEYMNG_USE_EFUSE_KEY_LOCK_DS_S)
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#define KEYMNG_USE_EFUSE_KEY_LOCK_DS_V 0x00000001U
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#define KEYMNG_USE_EFUSE_KEY_LOCK_DS_S 3
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/* KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM : R/W1 ;bitpos:[1] ;default: 1'd0 ; */
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/*description: Write 1 to lock reg_use_efuse_key for PSRAM*/
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/** KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM : R/W1 ;bitpos:[1]; default: 0;
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* Write 1 to lock reg_use_efuse_key for PSRAM
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*/
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#define KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM (BIT(4))
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#define KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_M ((KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_S))
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#define KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_V 0x1
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#define KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_M (KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_V << KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_S)
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#define KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_V 0x00000001U
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#define KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_S 4
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/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [5]; default: 0;
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* Write 1 to lock reg_rnd_switch_cycle.
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*/
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@@ -1,395 +0,0 @@
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/**
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** KEYMNG_CLK_REG register
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* Key Manager clock gate control register
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*/
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#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4)
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/** KEYMNG_REG_CG_FORCE_ON : R/W; bitpos: [0]; default: 1;
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* Write 1 to force on register clock gate.
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*/
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#define KEYMNG_REG_CG_FORCE_ON (BIT(0))
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#define KEYMNG_REG_CG_FORCE_ON_M (KEYMNG_REG_CG_FORCE_ON_V << KEYMNG_REG_CG_FORCE_ON_S)
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#define KEYMNG_REG_CG_FORCE_ON_V 0x00000001U
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#define KEYMNG_REG_CG_FORCE_ON_S 0
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/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
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* Write 1 to force on memory clock gate.
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*/
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#define KEYMNG_MEM_CG_FORCE_ON (BIT(1))
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#define KEYMNG_MEM_CG_FORCE_ON_M (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S)
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#define KEYMNG_MEM_CG_FORCE_ON_V 0x00000001U
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#define KEYMNG_MEM_CG_FORCE_ON_S 1
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/** KEYMNG_INT_RAW_REG register
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* Key Manager interrupt raw register, valid in level.
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*/
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#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8)
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/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
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* The raw interrupt status bit for the km_prep_done_int interrupt
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*/
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#define KEYMNG_PREP_DONE_INT_RAW (BIT(0))
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#define KEYMNG_PREP_DONE_INT_RAW_M (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S)
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#define KEYMNG_PREP_DONE_INT_RAW_V 0x00000001U
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#define KEYMNG_PREP_DONE_INT_RAW_S 0
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/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
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* The raw interrupt status bit for the km_proc_done_int interrupt
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*/
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#define KEYMNG_PROC_DONE_INT_RAW (BIT(1))
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#define KEYMNG_PROC_DONE_INT_RAW_M (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S)
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#define KEYMNG_PROC_DONE_INT_RAW_V 0x00000001U
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#define KEYMNG_PROC_DONE_INT_RAW_S 1
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/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
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* The raw interrupt status bit for the km_post_done_int interrupt
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*/
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#define KEYMNG_POST_DONE_INT_RAW (BIT(2))
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#define KEYMNG_POST_DONE_INT_RAW_M (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S)
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#define KEYMNG_POST_DONE_INT_RAW_V 0x00000001U
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#define KEYMNG_POST_DONE_INT_RAW_S 2
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/** KEYMNG_INT_ST_REG register
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* Key Manager interrupt status register.
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*/
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#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc)
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/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
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* The masked interrupt status bit for the km_prep_done_int interrupt
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*/
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#define KEYMNG_PREP_DONE_INT_ST (BIT(0))
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#define KEYMNG_PREP_DONE_INT_ST_M (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S)
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#define KEYMNG_PREP_DONE_INT_ST_V 0x00000001U
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#define KEYMNG_PREP_DONE_INT_ST_S 0
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/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
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* The masked interrupt status bit for the km_proc_done_int interrupt
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*/
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#define KEYMNG_PROC_DONE_INT_ST (BIT(1))
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#define KEYMNG_PROC_DONE_INT_ST_M (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S)
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#define KEYMNG_PROC_DONE_INT_ST_V 0x00000001U
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#define KEYMNG_PROC_DONE_INT_ST_S 1
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/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
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* The masked interrupt status bit for the km_post_done_int interrupt
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*/
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#define KEYMNG_POST_DONE_INT_ST (BIT(2))
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#define KEYMNG_POST_DONE_INT_ST_M (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S)
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#define KEYMNG_POST_DONE_INT_ST_V 0x00000001U
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#define KEYMNG_POST_DONE_INT_ST_S 2
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/** KEYMNG_INT_ENA_REG register
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* Key Manager interrupt enable register.
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*/
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#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10)
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/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
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* The interrupt enable bit for the km_prep_done_int interrupt
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*/
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#define KEYMNG_PREP_DONE_INT_ENA (BIT(0))
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#define KEYMNG_PREP_DONE_INT_ENA_M (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S)
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#define KEYMNG_PREP_DONE_INT_ENA_V 0x00000001U
|
||||
#define KEYMNG_PREP_DONE_INT_ENA_S 0
|
||||
/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the km_proc_done_int interrupt
|
||||
*/
|
||||
#define KEYMNG_PROC_DONE_INT_ENA (BIT(1))
|
||||
#define KEYMNG_PROC_DONE_INT_ENA_M (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S)
|
||||
#define KEYMNG_PROC_DONE_INT_ENA_V 0x00000001U
|
||||
#define KEYMNG_PROC_DONE_INT_ENA_S 1
|
||||
/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* The interrupt enable bit for the km_post_done_int interrupt
|
||||
*/
|
||||
#define KEYMNG_POST_DONE_INT_ENA (BIT(2))
|
||||
#define KEYMNG_POST_DONE_INT_ENA_M (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S)
|
||||
#define KEYMNG_POST_DONE_INT_ENA_V 0x00000001U
|
||||
#define KEYMNG_POST_DONE_INT_ENA_S 2
|
||||
|
||||
/** KEYMNG_INT_CLR_REG register
|
||||
* Key Manager interrupt clear register.
|
||||
*/
|
||||
#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14)
|
||||
/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the km_prep_done_int interrupt
|
||||
*/
|
||||
#define KEYMNG_PREP_DONE_INT_CLR (BIT(0))
|
||||
#define KEYMNG_PREP_DONE_INT_CLR_M (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S)
|
||||
#define KEYMNG_PREP_DONE_INT_CLR_V 0x00000001U
|
||||
#define KEYMNG_PREP_DONE_INT_CLR_S 0
|
||||
/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the km_proc_done_int interrupt
|
||||
*/
|
||||
#define KEYMNG_PROC_DONE_INT_CLR (BIT(1))
|
||||
#define KEYMNG_PROC_DONE_INT_CLR_M (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S)
|
||||
#define KEYMNG_PROC_DONE_INT_CLR_V 0x00000001U
|
||||
#define KEYMNG_PROC_DONE_INT_CLR_S 1
|
||||
/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the km_post_done_int interrupt
|
||||
*/
|
||||
#define KEYMNG_POST_DONE_INT_CLR (BIT(2))
|
||||
#define KEYMNG_POST_DONE_INT_CLR_M (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S)
|
||||
#define KEYMNG_POST_DONE_INT_CLR_V 0x00000001U
|
||||
#define KEYMNG_POST_DONE_INT_CLR_S 2
|
||||
|
||||
/** KEYMNG_STATIC_REG register
|
||||
* Key Manager static configuration register
|
||||
*/
|
||||
#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18)
|
||||
/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [4:0]; default: 0;
|
||||
* Set each bit to choose efuse key instead of key manager deployed key. Each bit
|
||||
* stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key;
|
||||
* bit 1 for flash_key; bit 0 for ecdsa_key
|
||||
*/
|
||||
#define KEYMNG_USE_EFUSE_KEY 0x0000001FU
|
||||
#define KEYMNG_USE_EFUSE_KEY_M (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S)
|
||||
#define KEYMNG_USE_EFUSE_KEY_V 0x0000001FU
|
||||
#define KEYMNG_USE_EFUSE_KEY_S 0
|
||||
/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [9:5]; default: 15;
|
||||
* The core clock cycle number to sample one rng input data. Please set it bigger than
|
||||
* the clock cycle ratio: T_rng/T_km
|
||||
*/
|
||||
#define KEYMNG_RND_SWITCH_CYCLE 0x0000001FU
|
||||
#define KEYMNG_RND_SWITCH_CYCLE_M (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S)
|
||||
#define KEYMNG_RND_SWITCH_CYCLE_V 0x0000001FU
|
||||
#define KEYMNG_RND_SWITCH_CYCLE_S 5
|
||||
/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [10]; default: 0;
|
||||
* Set this bit to use software written init key instead of efuse_init_key.
|
||||
*/
|
||||
#define KEYMNG_USE_SW_INIT_KEY (BIT(10))
|
||||
#define KEYMNG_USE_SW_INIT_KEY_M (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S)
|
||||
#define KEYMNG_USE_SW_INIT_KEY_V 0x00000001U
|
||||
#define KEYMNG_USE_SW_INIT_KEY_S 10
|
||||
/** KEYMNG_FLASH_KEY_LEN : R/W; bitpos: [11]; default: 0;
|
||||
* Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use
|
||||
* xts-aes-256. 0: use xts-aes-128.
|
||||
*/
|
||||
#define KEYMNG_FLASH_KEY_LEN (BIT(11))
|
||||
#define KEYMNG_FLASH_KEY_LEN_M (KEYMNG_FLASH_KEY_LEN_V << KEYMNG_FLASH_KEY_LEN_S)
|
||||
#define KEYMNG_FLASH_KEY_LEN_V 0x00000001U
|
||||
#define KEYMNG_FLASH_KEY_LEN_S 11
|
||||
/** KEYMNG_PSRAM_KEY_LEN : R/W; bitpos: [12]; default: 0;
|
||||
* Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use
|
||||
* xts-aes-256. 0: use xts-aes-128.
|
||||
*/
|
||||
#define KEYMNG_PSRAM_KEY_LEN (BIT(12))
|
||||
#define KEYMNG_PSRAM_KEY_LEN_M (KEYMNG_PSRAM_KEY_LEN_V << KEYMNG_PSRAM_KEY_LEN_S)
|
||||
#define KEYMNG_PSRAM_KEY_LEN_V 0x00000001U
|
||||
#define KEYMNG_PSRAM_KEY_LEN_S 12
|
||||
|
||||
/** KEYMNG_LOCK_REG register
|
||||
* Key Manager static configuration locker register
|
||||
*/
|
||||
#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c)
|
||||
/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [4:0]; default: 0;
|
||||
* Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
|
||||
* reg_use_efuse_key.
|
||||
*/
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK 0x0000001FU
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_M (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S)
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_V 0x0000001FU
|
||||
#define KEYMNG_USE_EFUSE_KEY_LOCK_S 0
|
||||
/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [5]; default: 0;
|
||||
* Write 1 to lock reg_rnd_switch_cycle.
|
||||
*/
|
||||
#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(5))
|
||||
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S)
|
||||
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V 0x00000001U
|
||||
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 5
|
||||
/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [6]; default: 0;
|
||||
* Write 1 to lock reg_use_sw_init_key.
|
||||
*/
|
||||
#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(6))
|
||||
#define KEYMNG_USE_SW_INIT_KEY_LOCK_M (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S)
|
||||
#define KEYMNG_USE_SW_INIT_KEY_LOCK_V 0x00000001U
|
||||
#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 6
|
||||
/** KEYMNG_FLASH_KEY_LEN_LOCK : R/W1; bitpos: [7]; default: 0;
|
||||
* Write 1 to lock reg_flash_key_len.
|
||||
*/
|
||||
#define KEYMNG_FLASH_KEY_LEN_LOCK (BIT(7))
|
||||
#define KEYMNG_FLASH_KEY_LEN_LOCK_M (KEYMNG_FLASH_KEY_LEN_LOCK_V << KEYMNG_FLASH_KEY_LEN_LOCK_S)
|
||||
#define KEYMNG_FLASH_KEY_LEN_LOCK_V 0x00000001U
|
||||
#define KEYMNG_FLASH_KEY_LEN_LOCK_S 7
|
||||
/** KEYMNG_PSRAM_KEY_LEN_LOCK : R/W1; bitpos: [8]; default: 0;
|
||||
* Write 1 to lock reg_psram_key_len.
|
||||
*/
|
||||
#define KEYMNG_PSRAM_KEY_LEN_LOCK (BIT(8))
|
||||
#define KEYMNG_PSRAM_KEY_LEN_LOCK_M (KEYMNG_PSRAM_KEY_LEN_LOCK_V << KEYMNG_PSRAM_KEY_LEN_LOCK_S)
|
||||
#define KEYMNG_PSRAM_KEY_LEN_LOCK_V 0x00000001U
|
||||
#define KEYMNG_PSRAM_KEY_LEN_LOCK_S 8
|
||||
|
||||
/** KEYMNG_CONF_REG register
|
||||
* Key Manager configuration register
|
||||
*/
|
||||
#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20)
|
||||
/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0;
|
||||
* Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
|
||||
* mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
|
||||
*/
|
||||
#define KEYMNG_KGEN_MODE 0x00000007U
|
||||
#define KEYMNG_KGEN_MODE_M (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S)
|
||||
#define KEYMNG_KGEN_MODE_V 0x00000007U
|
||||
#define KEYMNG_KGEN_MODE_S 0
|
||||
/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0;
|
||||
* Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3:
|
||||
* flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8:
|
||||
* psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12:
|
||||
* ecdsa_key_384_h. Others: reserved.
|
||||
*/
|
||||
#define KEYMNG_KEY_PURPOSE 0x0000000FU
|
||||
#define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S)
|
||||
#define KEYMNG_KEY_PURPOSE_V 0x0000000FU
|
||||
#define KEYMNG_KEY_PURPOSE_S 3
|
||||
|
||||
/** KEYMNG_START_REG register
|
||||
* Key Manager control register
|
||||
*/
|
||||
#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24)
|
||||
/** KEYMNG_START : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to continue Key Manager operation at LOAD/GAIN state.
|
||||
*/
|
||||
#define KEYMNG_START (BIT(0))
|
||||
#define KEYMNG_START_M (KEYMNG_START_V << KEYMNG_START_S)
|
||||
#define KEYMNG_START_V 0x00000001U
|
||||
#define KEYMNG_START_S 0
|
||||
/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0;
|
||||
* Write 1 to start Key Manager at IDLE state.
|
||||
*/
|
||||
#define KEYMNG_CONTINUE (BIT(1))
|
||||
#define KEYMNG_CONTINUE_M (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S)
|
||||
#define KEYMNG_CONTINUE_V 0x00000001U
|
||||
#define KEYMNG_CONTINUE_S 1
|
||||
|
||||
/** KEYMNG_STATE_REG register
|
||||
* Key Manager state register
|
||||
*/
|
||||
#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28)
|
||||
/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0;
|
||||
* The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
|
||||
*/
|
||||
#define KEYMNG_STATE 0x00000003U
|
||||
#define KEYMNG_STATE_M (KEYMNG_STATE_V << KEYMNG_STATE_S)
|
||||
#define KEYMNG_STATE_V 0x00000003U
|
||||
#define KEYMNG_STATE_S 0
|
||||
|
||||
/** KEYMNG_RESULT_REG register
|
||||
* Key Manager operation result register
|
||||
*/
|
||||
#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c)
|
||||
/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0;
|
||||
* The procedure result bit of Key Manager, only valid when Key Manager procedure is
|
||||
* done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
|
||||
*/
|
||||
#define KEYMNG_PROC_RESULT (BIT(0))
|
||||
#define KEYMNG_PROC_RESULT_M (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S)
|
||||
#define KEYMNG_PROC_RESULT_V 0x00000001U
|
||||
#define KEYMNG_PROC_RESULT_S 0
|
||||
|
||||
/** KEYMNG_KEY_VLD_REG register
|
||||
* Key Manager key status register
|
||||
*/
|
||||
#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30)
|
||||
/** KEYMNG_KEY_ECDSA_192_VLD : RO; bitpos: [0]; default: 0;
|
||||
* The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_ECDSA_192_VLD (BIT(0))
|
||||
#define KEYMNG_KEY_ECDSA_192_VLD_M (KEYMNG_KEY_ECDSA_192_VLD_V << KEYMNG_KEY_ECDSA_192_VLD_S)
|
||||
#define KEYMNG_KEY_ECDSA_192_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_ECDSA_192_VLD_S 0
|
||||
/** KEYMNG_KEY_ECDSA_256_VLD : RO; bitpos: [1]; default: 0;
|
||||
* The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_ECDSA_256_VLD (BIT(1))
|
||||
#define KEYMNG_KEY_ECDSA_256_VLD_M (KEYMNG_KEY_ECDSA_256_VLD_V << KEYMNG_KEY_ECDSA_256_VLD_S)
|
||||
#define KEYMNG_KEY_ECDSA_256_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_ECDSA_256_VLD_S 1
|
||||
/** KEYMNG_KEY_FLASH_VLD : RO; bitpos: [2]; default: 0;
|
||||
* The status bit for key_flash. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_FLASH_VLD (BIT(2))
|
||||
#define KEYMNG_KEY_FLASH_VLD_M (KEYMNG_KEY_FLASH_VLD_V << KEYMNG_KEY_FLASH_VLD_S)
|
||||
#define KEYMNG_KEY_FLASH_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_FLASH_VLD_S 2
|
||||
/** KEYMNG_KEY_HMAC_VLD : RO; bitpos: [3]; default: 0;
|
||||
* The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key
|
||||
* has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_HMAC_VLD (BIT(3))
|
||||
#define KEYMNG_KEY_HMAC_VLD_M (KEYMNG_KEY_HMAC_VLD_V << KEYMNG_KEY_HMAC_VLD_S)
|
||||
#define KEYMNG_KEY_HMAC_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_HMAC_VLD_S 3
|
||||
/** KEYMNG_KEY_DS_VLD : RO; bitpos: [4]; default: 0;
|
||||
* The status bit for key_ds. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_DS_VLD (BIT(4))
|
||||
#define KEYMNG_KEY_DS_VLD_M (KEYMNG_KEY_DS_VLD_V << KEYMNG_KEY_DS_VLD_S)
|
||||
#define KEYMNG_KEY_DS_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_DS_VLD_S 4
|
||||
/** KEYMNG_KEY_PSRAM_VLD : RO; bitpos: [5]; default: 0;
|
||||
* The status bit for key_psram. 1: The key has been deployed correctly. 0: The key
|
||||
* has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_PSRAM_VLD (BIT(5))
|
||||
#define KEYMNG_KEY_PSRAM_VLD_M (KEYMNG_KEY_PSRAM_VLD_V << KEYMNG_KEY_PSRAM_VLD_S)
|
||||
#define KEYMNG_KEY_PSRAM_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_PSRAM_VLD_S 5
|
||||
/** KEYMNG_KEY_ECDSA_384_VLD : RO; bitpos: [6]; default: 0;
|
||||
* The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
#define KEYMNG_KEY_ECDSA_384_VLD (BIT(6))
|
||||
#define KEYMNG_KEY_ECDSA_384_VLD_M (KEYMNG_KEY_ECDSA_384_VLD_V << KEYMNG_KEY_ECDSA_384_VLD_S)
|
||||
#define KEYMNG_KEY_ECDSA_384_VLD_V 0x00000001U
|
||||
#define KEYMNG_KEY_ECDSA_384_VLD_S 6
|
||||
|
||||
/** KEYMNG_HUK_VLD_REG register
|
||||
* Key Manager HUK status register
|
||||
*/
|
||||
#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34)
|
||||
/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0;
|
||||
* The HUK status. 0: HUK is not valid. 1: HUK is valid.
|
||||
*/
|
||||
#define KEYMNG_HUK_VALID (BIT(0))
|
||||
#define KEYMNG_HUK_VALID_M (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S)
|
||||
#define KEYMNG_HUK_VALID_V 0x00000001U
|
||||
#define KEYMNG_HUK_VALID_S 0
|
||||
|
||||
/** KEYMNG_DATE_REG register
|
||||
* Version control register
|
||||
*/
|
||||
#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc)
|
||||
/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 37781824;
|
||||
* Key Manager version control register.
|
||||
*/
|
||||
#define KEYMNG_DATE 0x0FFFFFFFU
|
||||
#define KEYMNG_DATE_M (KEYMNG_DATE_V << KEYMNG_DATE_S)
|
||||
#define KEYMNG_DATE_V 0x0FFFFFFFU
|
||||
#define KEYMNG_DATE_S 0
|
||||
|
||||
/** KEYMNG_ASSIST_INFO_MEM register
|
||||
* The memory that stores assist key info.
|
||||
*/
|
||||
#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100)
|
||||
#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64
|
||||
|
||||
/** KEYMNG_PUBLIC_INFO_MEM register
|
||||
* The memory that stores public key info.
|
||||
*/
|
||||
#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140)
|
||||
#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64
|
||||
|
||||
/** KEYMNG_SW_INIT_KEY_MEM register
|
||||
* The memory that stores software written init key.
|
||||
*/
|
||||
#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180)
|
||||
#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,5 +1,5 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -202,9 +202,10 @@ typedef union {
|
||||
*/
|
||||
uint32_t kgen_mode:3;
|
||||
/** key_purpose : R/W; bitpos: [6:3]; default: 0;
|
||||
* Set this field to choose the key purpose. 1: ecdsa_key 2: flash_256_1_key. 3:
|
||||
* flash_256_2_key. 4: flash_128_key. 6: hmac_key. 7: ds_key. 8: psram_256_1_key. 9:
|
||||
* psram_256_2_key. 10: psram_128_key. Others: reserved.
|
||||
* Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3:
|
||||
* flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8:
|
||||
* psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12:
|
||||
* ecdsa_key_384_h. Others: reserved.
|
||||
*/
|
||||
uint32_t key_purpose:4;
|
||||
uint32_t reserved_7:25;
|
||||
@@ -270,32 +271,42 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** key_ecdsa_vld : RO; bitpos: [0]; default: 0;
|
||||
* The status bit for key_ecdsa. 1: The key has been deployed correctly. 0: The key
|
||||
* has not been deployed yet.
|
||||
/** key_ecdsa_192_vld : RO; bitpos: [0]; default: 0;
|
||||
* The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
uint32_t key_ecdsa_vld:1;
|
||||
/** key_flash_vld : RO; bitpos: [1]; default: 0;
|
||||
uint32_t key_ecdsa_192_vld:1;
|
||||
/** key_ecdsa_256_vld : RO; bitpos: [1]; default: 0;
|
||||
* The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
uint32_t key_ecdsa_256_vld:1;
|
||||
/** key_flash_vld : RO; bitpos: [2]; default: 0;
|
||||
* The status bit for key_flash. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
uint32_t key_flash_vld:1;
|
||||
/** key_hmac_vld : RO; bitpos: [2]; default: 0;
|
||||
/** key_hmac_vld : RO; bitpos: [3]; default: 0;
|
||||
* The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key
|
||||
* has not been deployed yet.
|
||||
*/
|
||||
uint32_t key_hmac_vld:1;
|
||||
/** key_ds_vld : RO; bitpos: [3]; default: 0;
|
||||
/** key_ds_vld : RO; bitpos: [4]; default: 0;
|
||||
* The status bit for key_ds. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
uint32_t key_ds_vld:1;
|
||||
/** key_psram_vld : RO; bitpos: [4]; default: 0;
|
||||
/** key_psram_vld : RO; bitpos: [5]; default: 0;
|
||||
* The status bit for key_psram. 1: The key has been deployed correctly. 0: The key
|
||||
* has not been deployed yet.
|
||||
*/
|
||||
uint32_t key_psram_vld:1;
|
||||
uint32_t reserved_5:27;
|
||||
/** key_ecdsa_384_vld : RO; bitpos: [6]; default: 0;
|
||||
* The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
uint32_t key_ecdsa_384_vld:1;
|
||||
uint32_t reserved_7:25;
|
||||
};
|
||||
uint32_t val;
|
||||
} keymng_key_vld_reg_t;
|
||||
@@ -321,7 +332,7 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [27:0]; default: 36774224;
|
||||
/** date : R/W; bitpos: [27:0]; default: 37781824;
|
||||
* Key Manager version control register.
|
||||
*/
|
||||
uint32_t date:28;
|
||||
@@ -338,7 +349,7 @@ typedef struct {
|
||||
volatile keymng_int_st_reg_t int_st;
|
||||
volatile keymng_int_ena_reg_t int_ena;
|
||||
volatile keymng_int_clr_reg_t int_clr;
|
||||
volatile keymng_static_reg_t static_cfg;
|
||||
volatile keymng_static_reg_t static_conf;
|
||||
volatile keymng_lock_reg_t lock;
|
||||
volatile keymng_conf_reg_t conf;
|
||||
volatile keymng_start_reg_t start;
|
||||
|
||||
@@ -1,375 +0,0 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Memory data */
|
||||
|
||||
/** Group: Clock gate register */
|
||||
/** Type of clk register
|
||||
* Key Manager clock gate control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** reg_cg_force_on : R/W; bitpos: [0]; default: 1;
|
||||
* Write 1 to force on register clock gate.
|
||||
*/
|
||||
uint32_t reg_cg_force_on:1;
|
||||
/** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
|
||||
* Write 1 to force on memory clock gate.
|
||||
*/
|
||||
uint32_t mem_cg_force_on:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} keymng_clk_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt registers */
|
||||
/** Type of int_raw register
|
||||
* Key Manager interrupt raw register, valid in level.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the km_prep_done_int interrupt
|
||||
*/
|
||||
uint32_t prep_done_int_raw:1;
|
||||
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the km_proc_done_int interrupt
|
||||
*/
|
||||
uint32_t proc_done_int_raw:1;
|
||||
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status bit for the km_post_done_int interrupt
|
||||
*/
|
||||
uint32_t post_done_int_raw:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} keymng_int_raw_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* Key Manager interrupt status register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the km_prep_done_int interrupt
|
||||
*/
|
||||
uint32_t prep_done_int_st:1;
|
||||
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for the km_proc_done_int interrupt
|
||||
*/
|
||||
uint32_t proc_done_int_st:1;
|
||||
/** post_done_int_st : RO; bitpos: [2]; default: 0;
|
||||
* The masked interrupt status bit for the km_post_done_int interrupt
|
||||
*/
|
||||
uint32_t post_done_int_st:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} keymng_int_st_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* Key Manager interrupt enable register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the km_prep_done_int interrupt
|
||||
*/
|
||||
uint32_t prep_done_int_ena:1;
|
||||
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the km_proc_done_int interrupt
|
||||
*/
|
||||
uint32_t proc_done_int_ena:1;
|
||||
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
|
||||
* The interrupt enable bit for the km_post_done_int interrupt
|
||||
*/
|
||||
uint32_t post_done_int_ena:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} keymng_int_ena_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* Key Manager interrupt clear register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the km_prep_done_int interrupt
|
||||
*/
|
||||
uint32_t prep_done_int_clr:1;
|
||||
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the km_proc_done_int interrupt
|
||||
*/
|
||||
uint32_t proc_done_int_clr:1;
|
||||
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the km_post_done_int interrupt
|
||||
*/
|
||||
uint32_t post_done_int_clr:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} keymng_int_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: Static configuration registers */
|
||||
/** Type of static register
|
||||
* Key Manager static configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** use_efuse_key : R/W; bitpos: [4:0]; default: 0;
|
||||
* Set each bit to choose efuse key instead of key manager deployed key. Each bit
|
||||
* stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key;
|
||||
* bit 1 for flash_key; bit 0 for ecdsa_key
|
||||
*/
|
||||
uint32_t use_efuse_key:5;
|
||||
/** rnd_switch_cycle : R/W; bitpos: [9:5]; default: 15;
|
||||
* The core clock cycle number to sample one rng input data. Please set it bigger than
|
||||
* the clock cycle ratio: T_rng/T_km
|
||||
*/
|
||||
uint32_t rnd_switch_cycle:5;
|
||||
/** use_sw_init_key : R/W; bitpos: [10]; default: 0;
|
||||
* Set this bit to use software written init key instead of efuse_init_key.
|
||||
*/
|
||||
uint32_t use_sw_init_key:1;
|
||||
/** flash_key_len : R/W; bitpos: [11]; default: 0;
|
||||
* Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use
|
||||
* xts-aes-256. 0: use xts-aes-128.
|
||||
*/
|
||||
uint32_t flash_key_len:1;
|
||||
/** psram_key_len : R/W; bitpos: [12]; default: 0;
|
||||
* Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use
|
||||
* xts-aes-256. 0: use xts-aes-128.
|
||||
*/
|
||||
uint32_t psram_key_len:1;
|
||||
uint32_t reserved_13:19;
|
||||
};
|
||||
uint32_t val;
|
||||
} keymng_static_reg_t;
|
||||
|
||||
/** Type of lock register
|
||||
* Key Manager static configuration locker register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** use_efuse_key_lock : R/W1; bitpos: [4:0]; default: 0;
|
||||
* Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
|
||||
* reg_use_efuse_key.
|
||||
*/
|
||||
uint32_t use_efuse_key_lock:5;
|
||||
/** rnd_switch_cycle_lock : R/W1; bitpos: [5]; default: 0;
|
||||
* Write 1 to lock reg_rnd_switch_cycle.
|
||||
*/
|
||||
uint32_t rnd_switch_cycle_lock:1;
|
||||
/** use_sw_init_key_lock : R/W1; bitpos: [6]; default: 0;
|
||||
* Write 1 to lock reg_use_sw_init_key.
|
||||
*/
|
||||
uint32_t use_sw_init_key_lock:1;
|
||||
/** flash_key_len_lock : R/W1; bitpos: [7]; default: 0;
|
||||
* Write 1 to lock reg_flash_key_len.
|
||||
*/
|
||||
uint32_t flash_key_len_lock:1;
|
||||
/** psram_key_len_lock : R/W1; bitpos: [8]; default: 0;
|
||||
* Write 1 to lock reg_psram_key_len.
|
||||
*/
|
||||
uint32_t psram_key_len_lock:1;
|
||||
uint32_t reserved_9:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} keymng_lock_reg_t;
|
||||
|
||||
|
||||
/** Group: Configuration registers */
|
||||
/** Type of conf register
|
||||
* Key Manager configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** kgen_mode : R/W; bitpos: [2:0]; default: 0;
|
||||
* Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
|
||||
* mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
|
||||
*/
|
||||
uint32_t kgen_mode:3;
|
||||
/** key_purpose : R/W; bitpos: [6:3]; default: 0;
|
||||
* Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3:
|
||||
* flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8:
|
||||
* psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12:
|
||||
* ecdsa_key_384_h. Others: reserved.
|
||||
*/
|
||||
uint32_t key_purpose:4;
|
||||
uint32_t reserved_7:25;
|
||||
};
|
||||
uint32_t val;
|
||||
} keymng_conf_reg_t;
|
||||
|
||||
|
||||
/** Group: Control registers */
|
||||
/** Type of start register
|
||||
* Key Manager control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** start : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to conti Key Manager operation at LOAD/GAIN state.
|
||||
*/
|
||||
uint32_t start:1;
|
||||
/** conti : WT; bitpos: [1]; default: 0;
|
||||
* Write 1 to start Key Manager at IDLE state.
|
||||
*/
|
||||
uint32_t conti:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} keymng_start_reg_t;
|
||||
|
||||
|
||||
/** Group: State registers */
|
||||
/** Type of state register
|
||||
* Key Manager state register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** state : RO; bitpos: [1:0]; default: 0;
|
||||
* The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
|
||||
*/
|
||||
uint32_t state:2;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} keymng_state_reg_t;
|
||||
|
||||
|
||||
/** Group: Result registers */
|
||||
/** Type of result register
|
||||
* Key Manager operation result register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** proc_result : RO/SS; bitpos: [0]; default: 0;
|
||||
* The procedure result bit of Key Manager, only valid when Key Manager procedure is
|
||||
* done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
|
||||
*/
|
||||
uint32_t proc_result:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} keymng_result_reg_t;
|
||||
|
||||
/** Type of key_vld register
|
||||
* Key Manager key status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** key_ecdsa_192_vld : RO; bitpos: [0]; default: 0;
|
||||
* The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
uint32_t key_ecdsa_192_vld:1;
|
||||
/** key_ecdsa_256_vld : RO; bitpos: [1]; default: 0;
|
||||
* The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
uint32_t key_ecdsa_256_vld:1;
|
||||
/** key_flash_vld : RO; bitpos: [2]; default: 0;
|
||||
* The status bit for key_flash. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
uint32_t key_flash_vld:1;
|
||||
/** key_hmac_vld : RO; bitpos: [3]; default: 0;
|
||||
* The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key
|
||||
* has not been deployed yet.
|
||||
*/
|
||||
uint32_t key_hmac_vld:1;
|
||||
/** key_ds_vld : RO; bitpos: [4]; default: 0;
|
||||
* The status bit for key_ds. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
uint32_t key_ds_vld:1;
|
||||
/** key_psram_vld : RO; bitpos: [5]; default: 0;
|
||||
* The status bit for key_psram. 1: The key has been deployed correctly. 0: The key
|
||||
* has not been deployed yet.
|
||||
*/
|
||||
uint32_t key_psram_vld:1;
|
||||
/** key_ecdsa_384_vld : RO; bitpos: [6]; default: 0;
|
||||
* The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The
|
||||
* key has not been deployed yet.
|
||||
*/
|
||||
uint32_t key_ecdsa_384_vld:1;
|
||||
uint32_t reserved_7:25;
|
||||
};
|
||||
uint32_t val;
|
||||
} keymng_key_vld_reg_t;
|
||||
|
||||
/** Type of huk_vld register
|
||||
* Key Manager HUK status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** huk_valid : RO; bitpos: [0]; default: 0;
|
||||
* The HUK status. 0: HUK is not valid. 1: HUK is valid.
|
||||
*/
|
||||
uint32_t huk_valid:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} keymng_huk_vld_reg_t;
|
||||
|
||||
|
||||
/** Group: Version register */
|
||||
/** Type of date register
|
||||
* Version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [27:0]; default: 37781824;
|
||||
* Key Manager version control register.
|
||||
*/
|
||||
uint32_t date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} keymng_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint32_t reserved_000;
|
||||
volatile keymng_clk_reg_t clk;
|
||||
volatile keymng_int_raw_reg_t int_raw;
|
||||
volatile keymng_int_st_reg_t int_st;
|
||||
volatile keymng_int_ena_reg_t int_ena;
|
||||
volatile keymng_int_clr_reg_t int_clr;
|
||||
volatile keymng_static_reg_t static_conf;
|
||||
volatile keymng_lock_reg_t lock;
|
||||
volatile keymng_conf_reg_t conf;
|
||||
volatile keymng_start_reg_t start;
|
||||
volatile keymng_state_reg_t state;
|
||||
volatile keymng_result_reg_t result;
|
||||
volatile keymng_key_vld_reg_t key_vld;
|
||||
volatile keymng_huk_vld_reg_t huk_vld;
|
||||
uint32_t reserved_038[49];
|
||||
volatile keymng_date_reg_t date;
|
||||
volatile uint32_t assist_info[16];
|
||||
volatile uint32_t public_info[16];
|
||||
volatile uint32_t sw_init_key[8];
|
||||
} keymng_dev_t;
|
||||
|
||||
extern keymng_dev_t KEYMNG;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(keymng_dev_t) == 0x1a0, "Invalid size of keymng_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1839,6 +1839,10 @@ config SOC_EFUSE_ECDSA_KEY
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -673,8 +673,10 @@
|
||||
#define SOC_EFUSE_ECDSA_KEY 1
|
||||
|
||||
/*-------------------------- Key Manager CAPS----------------------------*/
|
||||
#define SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY 1 /*!< Key manager responsible to deploy ECDSA key */
|
||||
#define SOC_KEY_MANAGER_FE_KEY_DEPLOY 1 /*!< Key manager responsible to deploy Flash Encryption key */
|
||||
#define SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT 1 /*!< Key manager supports key deployment */
|
||||
#define SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY 1 /*!< Key manager responsible to deploy ECDSA key */
|
||||
#define SOC_KEY_MANAGER_FE_KEY_DEPLOY 1 /*!< Key manager responsible to deploy Flash Encryption key */
|
||||
|
||||
/*-------------------------- Secure Boot CAPS----------------------------*/
|
||||
#define SOC_SECURE_BOOT_V2_RSA 1
|
||||
#define SOC_SECURE_BOOT_V2_ECC 1
|
||||
|
||||
Reference in New Issue
Block a user