Merge branch 'refactor/split_esp32h2_soc_include_folder' into 'master'

refactor(soc): sort esp32h2 soc headers

See merge request espressif/esp-idf!33318

components/soc/esp32c5/include/soc/usb_serial_jtag_reg.h

@@ -653,7 +653,7 @@ extern "C" {
 #define USB_SERIAL_JTAG_TEST_ENABLE_V  0x00000001U
 #define USB_SERIAL_JTAG_TEST_ENABLE_S  0
 /** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
- *  USB pad one in test
+ *  USB pad oen in test
  */
 #define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
 #define USB_SERIAL_JTAG_TEST_USB_OE_M  (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)

components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h

@@ -130,7 +130,7 @@ typedef union {
          */
         uint32_t test_enable:1;
         /** test_usb_oe : R/W; bitpos: [1]; default: 0;
-         *  USB pad one in test
+         *  USB pad oen in test
          */
         uint32_t test_usb_oe:1;
         /** test_tx_dp : R/W; bitpos: [2]; default: 0;

components/soc/esp32h2/include/soc/dport_access.h

@@ -7,8 +7,7 @@
 #pragma once
 
 #include <stdint.h>
-#include "soc.h"
-#include "uart_reg.h"
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {

components/soc/esp32h2/include/soc/interrupt_reg.h

@@ -5,8 +5,8 @@
  */
 #pragma once
 
-#include "interrupt_matrix_reg.h"
-#include "plic_reg.h"
+#include "soc/interrupt_matrix_reg.h"
+#include "soc/plic_reg.h"
 #include "soc/soc_caps.h"
 
 #define INTERRUPT_PRIO_REG(n)                   (PLIC_MXINT0_PRI_REG + (n)*4)

components/soc/esp32h2/include/soc/soc.h

@@ -12,7 +12,7 @@
 #endif
 
 #include "esp_bit_defs.h"
-#include "reg_base.h"
+#include "soc/reg_base.h"
 
 #define PRO_CPU_NUM (0)
 

components/soc/esp32h2/include/soc/system_reg.h

@@ -5,7 +5,7 @@
  */
 
 #include "soc/hp_system_reg.h"
-#include "intpri_reg.h"
+#include "soc/intpri_reg.h"
 
 // ESP32H2-TODO : TODO: IDF-5720
 #define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG

components/soc/esp32h2/register/soc/assist_debug_reg.h

@@ -92,7 +92,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S  10
 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0;
- *  DBUS busy monitor enbale
+ *  DBUS busy monitor enable
  */
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA    (BIT(11))
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S)
@@ -270,7 +270,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S  10
 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [11]; default: 0;
- *  DBUS busy monitor interrupt enbale
+ *  DBUS busy monitor interrupt enable
  */
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS    (BIT(11))
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S)
@@ -491,7 +491,7 @@ extern "C" {
  */
 #define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
 /** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
- *  core0 sp region configuration regsiter
+ *  core0 sp region configuration register
  */
 #define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_SP_MIN_M  (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
@@ -515,7 +515,7 @@ extern "C" {
  */
 #define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
 /** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
- *  This regsiter stores the PC when trigger stack monitor.
+ *  This register stores the PC when trigger stack monitor.
  */
 #define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_SP_PC_M  (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
@@ -542,7 +542,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
 
 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
- *  record status regsiter
+ *  record status register
  */
 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
@@ -554,7 +554,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
 
 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
- *  record status regsiter
+ *  record status register
  */
 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;

components/soc/esp32h2/register/soc/assist_debug_struct.h

@@ -61,7 +61,7 @@ typedef union {
          */
         uint32_t core_0_iram0_exception_monitor_ena:1;
         /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0;
-         *  DBUS busy monitor enbale
+         *  DBUS busy monitor enable
          */
         uint32_t core_0_dram0_exception_monitor_ena:1;
         uint32_t reserved_12:20;
@@ -205,7 +205,7 @@ typedef union {
 typedef union {
     struct {
         /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
-         *  core0 sp region configuration regsiter
+         *  core0 sp region configuration register
          */
         uint32_t core_0_sp_min:32;
     };
@@ -231,7 +231,7 @@ typedef union {
 typedef union {
     struct {
         /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
-         *  This regsiter stores the PC when trigger stack monitor.
+         *  This register stores the PC when trigger stack monitor.
          */
         uint32_t core_0_sp_pc:32;
     };
@@ -348,7 +348,7 @@ typedef union {
          */
         uint32_t core_0_iram0_exception_monitor_rls:1;
         /** core_0_dram0_exception_monitor_rls : R/W; bitpos: [11]; default: 0;
-         *  DBUS busy monitor interrupt enbale
+         *  DBUS busy monitor interrupt enable
          */
         uint32_t core_0_dram0_exception_monitor_rls:1;
         uint32_t reserved_12:20;
@@ -415,7 +415,7 @@ typedef union {
 } assist_debug_core_0_intr_clr_reg_t;
 
 
-/** Group: pc reording configuration register */
+/** Group: pc recording configuration register */
 /** Type of core_0_rcd_en register
  *  record enable configuration register
  */
@@ -435,9 +435,9 @@ typedef union {
 } assist_debug_core_0_rcd_en_reg_t;
 
 
-/** Group: pc reording status register */
+/** Group: pc recording status register */
 /** Type of core_0_rcd_pdebugpc register
- *  record status regsiter
+ *  record status register
  */
 typedef union {
     struct {
@@ -450,7 +450,7 @@ typedef union {
 } assist_debug_core_0_rcd_pdebugpc_reg_t;
 
 /** Type of core_0_rcd_pdebugsp register
- *  record status regsiter
+ *  record status register
  */
 typedef union {
     struct {
@@ -463,7 +463,7 @@ typedef union {
 } assist_debug_core_0_rcd_pdebugsp_reg_t;
 
 
-/** Group: exception monitor regsiter */
+/** Group: exception monitor register */
 /** Type of core_0_iram0_exception_monitor_0 register
  *  exception monitor status register0
  */

components/soc/esp32h2/register/soc/cache_reg.h

@@ -4185,7 +4185,7 @@ extern "C" {
 #define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x244)
 /** CACHE_L1_ICACHE0_UNALLOC_CLR : HRO; bitpos: [0]; default: 0;
  *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
- *  unallocate request is responsed but not completed.
+ *  unallocate request is responded but not completed.
  */
 #define CACHE_L1_ICACHE0_UNALLOC_CLR    (BIT(0))
 #define CACHE_L1_ICACHE0_UNALLOC_CLR_M  (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S)
@@ -4193,7 +4193,7 @@ extern "C" {
 #define CACHE_L1_ICACHE0_UNALLOC_CLR_S  0
 /** CACHE_L1_ICACHE1_UNALLOC_CLR : HRO; bitpos: [1]; default: 0;
  *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
- *  unallocate request is responsed but not completed.
+ *  unallocate request is responded but not completed.
  */
 #define CACHE_L1_ICACHE1_UNALLOC_CLR    (BIT(1))
 #define CACHE_L1_ICACHE1_UNALLOC_CLR_M  (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S)
@@ -4215,7 +4215,7 @@ extern "C" {
 #define CACHE_L1_ICACHE3_UNALLOC_CLR_S  3
 /** CACHE_L1_CACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0;
  *  The bit is used to clear the unallocate request buffer of l1 cache where the
- *  unallocate request is responsed but not completed.
+ *  unallocate request is responded but not completed.
  */
 #define CACHE_L1_CACHE_UNALLOC_CLR    (BIT(4))
 #define CACHE_L1_CACHE_UNALLOC_CLR_M  (CACHE_L1_CACHE_UNALLOC_CLR_V << CACHE_L1_CACHE_UNALLOC_CLR_S)
@@ -6025,7 +6025,7 @@ extern "C" {
 #define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x390)
 /** CACHE_L2_CACHE_UNALLOC_CLR : HRO; bitpos: [5]; default: 0;
  *  The bit is used to clear the unallocate request buffer of l2 icache where the
- *  unallocate request is responsed but not completed.
+ *  unallocate request is responded but not completed.
  */
 #define CACHE_L2_CACHE_UNALLOC_CLR    (BIT(5))
 #define CACHE_L2_CACHE_UNALLOC_CLR_M  (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S)

components/soc/esp32h2/register/soc/cache_struct.h

@@ -5115,12 +5115,12 @@ typedef union {
     struct {
         /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l1_icache0_unalloc_clr:1;
         /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l1_icache1_unalloc_clr:1;
         /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0;
@@ -5133,7 +5133,7 @@ typedef union {
         uint32_t l1_icache3_unalloc_clr:1;
         /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l1 cache where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l1_cache_unalloc_clr:1;
         uint32_t reserved_5:27;
@@ -5149,7 +5149,7 @@ typedef union {
         uint32_t reserved_0:5;
         /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l2 icache where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l2_cache_unalloc_clr:1;
         uint32_t reserved_6:26;

components/soc/esp32h2/register/soc/ecc_mult_reg.h

@@ -64,7 +64,7 @@ extern "C" {
  */
 #define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
 /** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
- *  Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
+ *  Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after
  *  the caculatrion is done.
  */
 #define ECC_MULT_START    (BIT(0))
@@ -97,7 +97,7 @@ extern "C" {
  *  The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
  *  verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
  *  Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
- *  8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division.
+ *  8: mod addition. 9. mod subtraction. 10: mod multiplication. 11: mod division.
  */
 #define ECC_MULT_WORK_MODE    0x0000000FU
 #define ECC_MULT_WORK_MODE_M  (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)

components/soc/esp32h2/register/soc/ecc_mult_struct.h

@@ -79,7 +79,7 @@ typedef union {
 typedef union {
     struct {
         /** start : R/W/SC; bitpos: [0]; default: 0;
-         *  Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
+         *  Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after
          *  the caculatrion is done.
          */
         uint32_t start:1;
@@ -100,7 +100,7 @@ typedef union {
          *  The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
          *  verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
          *  Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
-         *  8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division.
+         *  8: mod addition. 9. mod subtraction. 10: mod multiplication. 11: mod division.
          */
         uint32_t work_mode:4;
         /** security_mode : R/W; bitpos: [8]; default: 0;

components/soc/esp32h2/register/soc/ecdsa_reg.h

@@ -140,7 +140,7 @@ extern "C" {
  */
 #define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
 /** ECDSA_START : WT; bitpos: [0]; default: 0;
- *  Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
+ *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
  *  after configuration.
  */
 #define ECDSA_START    (BIT(0))
@@ -220,7 +220,7 @@ extern "C" {
  */
 #define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
 /** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
- *  Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
+ *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
  *  bit will be self-cleared after configuration.
  */
 #define ECDSA_SHA_START    (BIT(0))
@@ -233,7 +233,7 @@ extern "C" {
  */
 #define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
 /** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
- *  Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
+ *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
  *  bit will be self-cleared after configuration.
  */
 #define ECDSA_SHA_CONTINUE    (BIT(0))

components/soc/esp32h2/register/soc/ecdsa_struct.h

@@ -48,7 +48,7 @@ typedef union {
 typedef union {
     struct {
         /** start : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
+         *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
          *  after configuration.
          */
         uint32_t start:1;
@@ -214,7 +214,7 @@ typedef union {
 typedef union {
     struct {
         /** sha_start : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
+         *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
          *  bit will be self-cleared after configuration.
          */
         uint32_t sha_start:1;
@@ -229,7 +229,7 @@ typedef union {
 typedef union {
     struct {
         /** sha_continue : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
+         *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
          *  bit will be self-cleared after configuration.
          */
         uint32_t sha_continue:1;

components/soc/esp32h2/register/soc/efuse_reg.h

@@ -7,7 +7,7 @@
 
 #include <stdint.h>
 #include "soc/soc.h"
-#include "efuse_defs.h"
+#include "soc/efuse_defs.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -261,14 +261,14 @@ extern "C" {
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
 /** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0;
- *  Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
+ *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
  */
 #define EFUSE_USB_DREFH    0x00000003U
 #define EFUSE_USB_DREFH_M  (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
 #define EFUSE_USB_DREFH_V  0x00000003U
 #define EFUSE_USB_DREFH_S  21
 /** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0;
- *  Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
+ *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
  */
 #define EFUSE_USB_DREFL    0x00000003U
 #define EFUSE_USB_DREFL_M  (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
@@ -2355,7 +2355,7 @@ extern "C" {
 #define EFUSE_CLK_EN_S  16
 
 /** EFUSE_CONF_REG register
- *  eFuse operation mode configuraiton register
+ *  eFuse operation mode configuration register
  */
 #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
 /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;

components/soc/esp32h2/register/soc/efuse_struct.h

@@ -236,11 +236,11 @@ typedef union {
          */
         uint32_t dis_download_manual_encrypt:1;
         /** usb_drefh : RO; bitpos: [22:21]; default: 0;
-         *  Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
+         *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
          */
         uint32_t usb_drefh:2;
         /** usb_drefl : RO; bitpos: [24:23]; default: 0;
-         *  Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
+         *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
          */
         uint32_t usb_drefl:2;
         /** usb_exchg_pins : RO; bitpos: [25]; default: 0;
@@ -2007,7 +2007,7 @@ typedef union {
 } efuse_clk_reg_t;
 
 /** Type of conf register
- *  eFuse operation mode configuraiton register
+ *  eFuse operation mode configuration register
  */
 typedef union {
     struct {

components/soc/esp32h2/register/soc/extmem_reg.h

@@ -10,7 +10,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 
 #define CACHE_L1_CACHE_CTRL_REG          (DR_REG_CACHE_BASE + 0x4)
 /* CACHE_L1_CACHE_SHUT_BUS1 : R/W ;bitpos:[1] ;default: 1'h0 ; */
@@ -250,8 +250,8 @@ ould be used together with CACHE_LOCK_ADDR_REG.*/
 #define CACHE_SYNC_DONE_S  4
 /* CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */
 /*description: The bit is used to enable writeback-invalidate operation. It will be cleared by
-hardware after writeback-invalidate operation done. Note that this bit and the o
-ther sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive
+hardware after writeback-invalidate operation done. Note that this bit and the
+other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive
 , that is, those bits can not be set to 1 at the same time..*/
 #define CACHE_WRITEBACK_INVALIDATE_ENA    (BIT(3))
 #define CACHE_WRITEBACK_INVALIDATE_ENA_M  (BIT(3))
@@ -269,16 +269,16 @@ those bits can not be set to 1 at the same time..*/
 /* CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */
 /*description: The bit is used to enable clean operation. It will be cleared by hardware after
 clean operation done. Note that this bit and the other sync-bits (invalidate_ena
-, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, thos
-e bits can not be set to 1 at the same time..*/
+, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
+bits can not be set to 1 at the same time..*/
 #define CACHE_CLEAN_ENA    (BIT(1))
 #define CACHE_CLEAN_ENA_M  (BIT(1))
 #define CACHE_CLEAN_ENA_V  0x1
 #define CACHE_CLEAN_ENA_S  1
 /* CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */
 /*description: The bit is used to enable invalidate operation. It will be cleared by hardware a
-fter invalidate operation done. Note that this bit and the other sync-bits (clea
-n_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is,
+after invalidate operation done. Note that this bit and the other sync-bits (clean_ena,
+writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is,
  those bits can not be set to 1 at the same time..*/
 #define CACHE_INVALIDATE_ENA    (BIT(0))
 #define CACHE_INVALIDATE_ENA_M  (BIT(0))
@@ -499,15 +499,15 @@ SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA..*/
 
 #define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG          (DR_REG_CACHE_BASE + 0x15C)
 /* CACHE_L1_BUS1_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d
-ue to bus1 accesses L1-DCache..*/
+/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache
+due to bus1 accesses L1-DCache..*/
 #define CACHE_L1_BUS1_OVF_INT_CLR    (BIT(5))
 #define CACHE_L1_BUS1_OVF_INT_CLR_M  (BIT(5))
 #define CACHE_L1_BUS1_OVF_INT_CLR_V  0x1
 #define CACHE_L1_BUS1_OVF_INT_CLR_S  5
 /* CACHE_L1_BUS0_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d
-ue to bus0 accesses L1-DCache..*/
+/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache
+due to bus0 accesses L1-DCache..*/
 #define CACHE_L1_BUS0_OVF_INT_CLR    (BIT(4))
 #define CACHE_L1_BUS0_OVF_INT_CLR_M  (BIT(4))
 #define CACHE_L1_BUS0_OVF_INT_CLR_V  0x1
@@ -573,8 +573,8 @@ o cpu accesses L1-DCache..*/
 
 #define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG          (DR_REG_CACHE_BASE + 0x174)
 /* CACHE_L1_CACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache d
-ue to cpu accesses L1-DCache..*/
+/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache
+due to cpu accesses L1-DCache..*/
 #define CACHE_L1_CACHE_FAIL_INT_ST    (BIT(4))
 #define CACHE_L1_CACHE_FAIL_INT_ST_M  (BIT(4))
 #define CACHE_L1_CACHE_FAIL_INT_ST_V  0x1
@@ -787,7 +787,7 @@ ror occurs..*/
 #define CACHE_SYNC_ERR_INT_ST_V  0x1
 #define CACHE_SYNC_ERR_INT_ST_S  13
 /* CACHE_L1_CACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation erro
+/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation error
 r..*/
 #define CACHE_L1_CACHE_PLD_ERR_INT_ST    (BIT(11))
 #define CACHE_L1_CACHE_PLD_ERR_INT_ST_M  (BIT(11))
@@ -825,7 +825,7 @@ load-operation is done..*/
 
 #define CACHE_L1_CACHE_SYNC_RST_CTRL_REG          (DR_REG_CACHE_BASE + 0x238)
 /* CACHE_L1_CACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should onl
+/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
 y be used to initialize sync-logic when some fatal error of sync-logic occurs..*/
 #define CACHE_L1_CACHE_SYNC_RST    (BIT(4))
 #define CACHE_L1_CACHE_SYNC_RST_M  (BIT(4))
@@ -855,7 +855,7 @@ rks in L1-Cache..*/
 #define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG          (DR_REG_CACHE_BASE + 0x244)
 /* CACHE_L1_CACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
 /*description: The bit is used to clear the unallocate request buffer of l1 cache where the una
-llocate request is responsed but not completed..*/
+llocate request is responded but not completed..*/
 #define CACHE_L1_CACHE_UNALLOC_CLR    (BIT(4))
 #define CACHE_L1_CACHE_UNALLOC_CLR_M  (BIT(4))
 #define CACHE_L1_CACHE_UNALLOC_CLR_V  0x1
@@ -870,7 +870,7 @@ th the others fields inside this register..*/
 #define CACHE_L1_CACHE_MEM_OBJECT_V  0x1
 #define CACHE_L1_CACHE_MEM_OBJECT_S  10
 /* CACHE_L1_CACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot wit
+/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
 h the others fields inside this register..*/
 #define CACHE_L1_CACHE_TAG_OBJECT    (BIT(4))
 #define CACHE_L1_CACHE_TAG_OBJECT_M  (BIT(4))
@@ -888,8 +888,8 @@ h the others fields inside this register..*/
 
 #define CACHE_L1_CACHE_VADDR_REG          (DR_REG_CACHE_BASE + 0x250)
 /* CACHE_L1_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */
-/*description: Those bits stores the virtual address which will decide where inside the specifi
-ed tag memory object will be accessed..*/
+/*description: Those bits stores the virtual address which will decide where inside the specified
+tag memory object will be accessed..*/
 #define CACHE_L1_CACHE_VADDR    0xFFFFFFFF
 #define CACHE_L1_CACHE_VADDR_M  ((CACHE_L1_CACHE_VADDR_V)<<(CACHE_L1_CACHE_VADDR_S))
 #define CACHE_L1_CACHE_VADDR_V  0xFFFFFFFF

components/soc/esp32h2/register/soc/extmem_struct.h

@@ -5115,12 +5115,12 @@ typedef union {
     struct {
         /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l1_icache0_unalloc_clr:1;
         /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l1_icache1_unalloc_clr:1;
         /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0;
@@ -5133,7 +5133,7 @@ typedef union {
         uint32_t l1_icache3_unalloc_clr:1;
         /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l1 cache where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l1_cache_unalloc_clr:1;
         uint32_t reserved_5:27;
@@ -5149,7 +5149,7 @@ typedef union {
         uint32_t reserved_0:5;
         /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l2 icache where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l2_cache_unalloc_clr:1;
         uint32_t reserved_6:26;

components/soc/esp32h2/register/soc/hp_system_reg.h

@@ -78,7 +78,7 @@ extern "C" {
  *  0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
  *  the number, the stronger the ability to resist DPA attacks and the higher the
  *  security level, but it will increase the computational overhead of the hardware
- *  crypto-accelerators. Only avaliable if HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
+ *  crypto-accelerators. Only available if HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
  */
 #define HP_SYSTEM_SEC_DPA_LEVEL    0x00000003U
 #define HP_SYSTEM_SEC_DPA_LEVEL_M  (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S)

components/soc/esp32h2/register/soc/hp_system_struct.h

@@ -70,7 +70,7 @@ typedef union {
          *  0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
          *  the number, the stronger the ability to resist DPA attacks and the higher the
          *  security level, but it will increase the computational overhead of the hardware
-         *  crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0.
+         *  crypto-accelerators. Only available if HP_SYS_SEC_DPA_CFG_SEL is 0.
          */
         uint32_t sec_dpa_level:2;
         /** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;

components/soc/esp32h2/register/soc/i2s_reg.h

@@ -320,7 +320,7 @@ extern "C" {
 #define I2S_TX_SLAVE_MOD_V  0x00000001U
 #define I2S_TX_SLAVE_MOD_S  3
 /** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1;
- *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
+ *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
  */
 #define I2S_TX_STOP_EN    (BIT(4))
 #define I2S_TX_STOP_EN_M  (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S)

components/soc/esp32h2/register/soc/i2s_struct.h

@@ -459,7 +459,7 @@ typedef union {
          */
         uint32_t tx_slave_mod:1;
         /** tx_stop_en : R/W; bitpos: [4]; default: 1;
-         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
+         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
          */
         uint32_t tx_stop_en:1;
         /** tx_chan_equal : R/W; bitpos: [5]; default: 0;

components/soc/esp32h2/register/soc/io_mux_reg.h

@@ -5,7 +5,7 @@
  */
 
 #pragma once
-#include "soc.h"
+#include "soc/soc.h"
 
 /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
 /* Output enable in sleep mode */
@@ -79,7 +79,7 @@
 #define HYS_EN_S  16
 /* HYS_SEL : R/W; bitpos: [17]; default: 0;
  * Select enabling signals of the pad from software and efuse hardware.
- * 1: Select enabling siganl from software.
+ * 1: Select enabling signal from software.
  * 0: Select enabling signal from efuse hardware.
  */
 #define HYS_SEL    (BIT(17))

components/soc/esp32h2/register/soc/mcpwm_reg.h

@@ -894,7 +894,7 @@ extern "C" {
 #define MCPWM_DB0_RED_S  0
 
 /** MCPWM_CARRIER0_CFG_REG register
- *  Carrier enable and configuratoin
+ *  Carrier enable and configuration
  */
 #define MCPWM_CARRIER0_CFG_REG (DR_REG_MCPWM_BASE + 0x64)
 /** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0;
@@ -1575,7 +1575,7 @@ extern "C" {
 #define MCPWM_DB1_RED_S  0
 
 /** MCPWM_CARRIER1_CFG_REG register
- *  Carrier enable and configuratoin
+ *  Carrier enable and configuration
  */
 #define MCPWM_CARRIER1_CFG_REG (DR_REG_MCPWM_BASE + 0x9c)
 /** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0;
@@ -2256,7 +2256,7 @@ extern "C" {
 #define MCPWM_DB2_RED_S  0
 
 /** MCPWM_CARRIER2_CFG_REG register
- *  Carrier enable and configuratoin
+ *  Carrier enable and configuration
  */
 #define MCPWM_CARRIER2_CFG_REG (DR_REG_MCPWM_BASE + 0xd4)
 /** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0;
@@ -2621,7 +2621,7 @@ extern "C" {
 #define MCPWM_CAP0_MODE_V  0x00000003U
 #define MCPWM_CAP0_MODE_S  1
 /** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE +
+ *  Value of prescaling on positive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE +
  *  1
  */
 #define MCPWM_CAP0_PRESCALE    0x000000FFU
@@ -2664,7 +2664,7 @@ extern "C" {
 #define MCPWM_CAP1_MODE_V  0x00000003U
 #define MCPWM_CAP1_MODE_S  1
 /** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE +
+ *  Value of prescaling on positive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE +
  *  1
  */
 #define MCPWM_CAP1_PRESCALE    0x000000FFU
@@ -2707,7 +2707,7 @@ extern "C" {
 #define MCPWM_CAP2_MODE_V  0x00000003U
 #define MCPWM_CAP2_MODE_S  1
 /** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE +
+ *  Value of prescaling on positive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE +
  *  1
  */
 #define MCPWM_CAP2_PRESCALE    0x000000FFU

components/soc/esp32h2/register/soc/mcpwm_struct.h

@@ -462,7 +462,7 @@ typedef union {
 } mcpwm_dt_red_cfg_reg_t;
 
 /** Type of carrier_cfg register
- *  Carrier enable and configuratoin
+ *  Carrier enable and configuration
  */
 typedef union {
     struct {
@@ -734,7 +734,7 @@ typedef union {
          */
         uint32_t capn_mode:2;
         /** capn_prescale : R/W; bitpos: [10:3]; default: 0;
-         *  Value of prescaling on possitive edge of CAPn. Prescale value = PWM_CAP0_PRESCALE +
+         *  Value of prescaling on positive edge of CAPn. Prescale value = PWM_CAP0_PRESCALE +
          *  1
          */
         uint32_t capn_prescale:8;

components/soc/esp32h2/register/soc/mem_monitor_reg.h

@@ -12,7 +12,7 @@ extern "C" {
 #endif
 
 /** MEM_MONITOR_LOG_SETTING_REG register
- *  log config regsiter
+ *  log config register
  */
 #define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
 /** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0;
@@ -39,7 +39,7 @@ extern "C" {
 #define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S  7
 
 /** MEM_MONITOR_LOG_CHECK_DATA_REG register
- *  check data regsiter
+ *  check data register
  */
 #define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
 /** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
@@ -64,7 +64,7 @@ extern "C" {
 #define MEM_MONITOR_LOG_DATA_MASK_S  0
 
 /** MEM_MONITOR_LOG_MIN_REG register
- *  log boundary regsiter
+ *  log boundary register
  */
 #define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
 /** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
@@ -76,7 +76,7 @@ extern "C" {
 #define MEM_MONITOR_LOG_MIN_S  0
 
 /** MEM_MONITOR_LOG_MAX_REG register
- *  log boundary regsiter
+ *  log boundary register
  */
 #define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
 /** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;

components/soc/esp32h2/register/soc/mem_monitor_struct.h

@@ -12,7 +12,7 @@ extern "C" {
 
 /** Group: configuration registers */
 /** Type of log_setting register
- *  log config regsiter
+ *  log config register
  */
 typedef union {
     struct {
@@ -35,7 +35,7 @@ typedef union {
 } mem_monitor_log_setting_reg_t;
 
 /** Type of log_check_data register
- *  check data regsiter
+ *  check data register
  */
 typedef union {
     struct {
@@ -63,7 +63,7 @@ typedef union {
 } mem_monitor_log_data_mask_reg_t;
 
 /** Type of log_min register
- *  log boundary regsiter
+ *  log boundary register
  */
 typedef union {
     struct {
@@ -76,7 +76,7 @@ typedef union {
 } mem_monitor_log_min_reg_t;
 
 /** Type of log_max register
- *  log boundary regsiter
+ *  log boundary register
  */
 typedef union {
     struct {

components/soc/esp32h2/register/soc/parl_io_reg.h

@@ -252,7 +252,7 @@ extern "C" {
 #define PARL_IO_TX_READY_S  31
 
 /** PARL_IO_INT_ENA_REG register
- *  Parallel IO interrupt enable singal configuration register.
+ *  Parallel IO interrupt enable signal configuration register.
  */
 #define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28)
 /** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
@@ -278,7 +278,7 @@ extern "C" {
 #define PARL_IO_TX_EOF_INT_ENA_S  2
 
 /** PARL_IO_INT_RAW_REG register
- *  Parallel IO interrupt raw singal status register.
+ *  Parallel IO interrupt raw signal status register.
  */
 #define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c)
 /** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
@@ -304,7 +304,7 @@ extern "C" {
 #define PARL_IO_TX_EOF_INT_RAW_S  2
 
 /** PARL_IO_INT_ST_REG register
- *  Parallel IO interrupt singal status register.
+ *  Parallel IO interrupt signal status register.
  */
 #define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30)
 /** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
@@ -330,7 +330,7 @@ extern "C" {
 #define PARL_IO_TX_EOF_INT_ST_S  2
 
 /** PARL_IO_INT_CLR_REG register
- *  Parallel IO interrupt  clear singal configuration register.
+ *  Parallel IO interrupt  clear signal configuration register.
  */
 #define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34)
 /** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;

components/soc/esp32h2/register/soc/parl_io_struct.h

@@ -251,7 +251,7 @@ typedef union {
 
 /** Group: PARL_IO Interrupt Configuration and Status */
 /** Type of int_ena register
- *  Parallel IO interrupt enable singal configuration register.
+ *  Parallel IO interrupt enable signal configuration register.
  */
 typedef union {
     struct {
@@ -273,7 +273,7 @@ typedef union {
 } parl_io_int_ena_reg_t;
 
 /** Type of int_raw register
- *  Parallel IO interrupt raw singal status register.
+ *  Parallel IO interrupt raw signal status register.
  */
 typedef union {
     struct {
@@ -295,7 +295,7 @@ typedef union {
 } parl_io_int_raw_reg_t;
 
 /** Type of int_st register
- *  Parallel IO interrupt singal status register.
+ *  Parallel IO interrupt signal status register.
  */
 typedef union {
     struct {
@@ -317,7 +317,7 @@ typedef union {
 } parl_io_int_st_reg_t;
 
 /** Type of int_clr register
- *  Parallel IO interrupt  clear singal configuration register.
+ *  Parallel IO interrupt  clear signal configuration register.
  */
 typedef union {
     struct {

components/soc/esp32h2/register/soc/pcr_reg.h

@@ -229,7 +229,7 @@ extern "C" {
 #define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c)
 /** PCR_MSPI_FAST_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
  *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
- *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
+ *  clock-source to drive clk_mspi_fast. Only available when the clck-source is a
  *  low-speed clock-source such as XTAL/FOSC.
  */
 #define PCR_MSPI_FAST_DIV_NUM    0x000000FFU
@@ -1331,7 +1331,7 @@ extern "C" {
 #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V  0x0000000FU
 #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S  0
 /** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL
+ *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz driven by SPLL
  *  divided by 3.
  */
 #define PCR_PVT_MONITOR_FUNC_CLK_SEL    (BIT(20))
@@ -1904,8 +1904,8 @@ extern "C" {
  */
 #define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x114)
 /** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is
- *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed
+ *  Set this field to generate clk_cpu driven by clk_hproot. The clk_cpu is
+ *  div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed
  *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM.
  */
 #define PCR_CPU_DIV_NUM    0x000000FFU
@@ -1918,8 +1918,8 @@ extern "C" {
  */
 #define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118)
 /** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is
- *  div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for
+ *  Set this field to generate clk_ahb driven by clk_hproot. The clk_ahb is
+ *  div1(default)/div2/div4/div8 of clk_hproot. This field is only available for
  *  low-speed clock-source such as XTAL/FOSC, and should be used together with
  *  PCR_CPU_DIV_NUM.
  */
@@ -1946,7 +1946,7 @@ extern "C" {
 #define PCR_APB_DECREASE_DIV_NUM_V  0x000000FFU
 #define PCR_APB_DECREASE_DIV_NUM_S  0
 /** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
- *  Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is
+ *  Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is
  *  div1(default)/div2/div4 of clk_ahb.
  */
 #define PCR_APB_DIV_NUM    0x000000FFU
@@ -1978,48 +1978,48 @@ extern "C" {
  */
 #define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x124)
 /** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  This field is used to open 96 MHz clock (SPLL) drived from SPLL. 0: close, 1:
- *  open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 96 MHz clock (SPLL) driven from SPLL. 0: close, 1:
+ *  open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_240M_CLK_EN    (BIT(0))
 #define PCR_PLL_240M_CLK_EN_M  (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S)
 #define PCR_PLL_240M_CLK_EN_V  0x00000001U
 #define PCR_PLL_240M_CLK_EN_S  0
 /** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  This field is used to open 64 MHz clock (div3 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 64 MHz clock (div3 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_160M_CLK_EN    (BIT(1))
 #define PCR_PLL_160M_CLK_EN_M  (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S)
 #define PCR_PLL_160M_CLK_EN_V  0x00000001U
 #define PCR_PLL_160M_CLK_EN_S  1
 /** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  This field is used to open 48 MHz clock (div4 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 48 MHz clock (div4 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_120M_CLK_EN    (BIT(2))
 #define PCR_PLL_120M_CLK_EN_M  (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S)
 #define PCR_PLL_120M_CLK_EN_V  0x00000001U
 #define PCR_PLL_120M_CLK_EN_S  2
 /** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1;
- *  This field is used to open 32 MHz clock (div6  of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 32 MHz clock (div6  of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_80M_CLK_EN    (BIT(3))
 #define PCR_PLL_80M_CLK_EN_M  (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S)
 #define PCR_PLL_80M_CLK_EN_V  0x00000001U
 #define PCR_PLL_80M_CLK_EN_S  3
 /** PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1;
- *  This field is used to open 16 MHz clock (div10 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 16 MHz clock (div10 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_48M_CLK_EN    (BIT(4))
 #define PCR_PLL_48M_CLK_EN_M  (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S)
 #define PCR_PLL_48M_CLK_EN_V  0x00000001U
 #define PCR_PLL_48M_CLK_EN_S  4
 /** PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1;
- *  This field is used to open 8 MHz clock (div12 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 8 MHz clock (div12 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_40M_CLK_EN    (BIT(5))
 #define PCR_PLL_40M_CLK_EN_M  (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S)

components/soc/esp32h2/register/soc/pcr_struct.h

@@ -192,7 +192,7 @@ typedef union {
     struct {
         /** mspi_fast_div_num : R/W; bitpos: [7:0]; default: 0;
          *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
-         *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
+         *  clock-source to drive clk_mspi_fast. Only available when the clck-source is a
          *  low-speed clock-source such as XTAL/FOSC.
          */
         uint32_t mspi_fast_div_num:8;
@@ -1067,7 +1067,7 @@ typedef union {
         uint32_t pvt_monitor_func_clk_div_num:4;
         uint32_t reserved_4:16;
         /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL
+         *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz driven by SPLL
          *  divided by 3.
          */
         uint32_t pvt_monitor_func_clk_sel:1;
@@ -1573,8 +1573,8 @@ typedef union {
 typedef union {
     struct {
         /** cpu_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is
-         *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed
+         *  Set this field to generate clk_cpu driven by clk_hproot. The clk_cpu is
+         *  div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed
          *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM.
          */
         uint32_t cpu_div_num:8;
@@ -1589,8 +1589,8 @@ typedef union {
 typedef union {
     struct {
         /** ahb_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is
-         *  div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for
+         *  Set this field to generate clk_ahb driven by clk_hproot. The clk_ahb is
+         *  div1(default)/div2/div4/div8 of clk_hproot. This field is only available for
          *  low-speed clock-source such as XTAL/FOSC, and should be used together with
          *  PCR_CPU_DIV_NUM.
          */
@@ -1616,7 +1616,7 @@ typedef union {
          */
         uint32_t apb_decrease_div_num:8;
         /** apb_div_num : R/W; bitpos: [15:8]; default: 0;
-         *  Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is
+         *  Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is
          *  div1(default)/div2/div4 of clk_ahb.
          */
         uint32_t apb_div_num:8;
@@ -1631,33 +1631,33 @@ typedef union {
 typedef union {
     struct {
         /** pll_240m_clk_en : R/W; bitpos: [0]; default: 1;
-         *  This field is used to open 96 MHz clock (SPLL) drived from SPLL. 0: close, 1:
-         *  open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 96 MHz clock (SPLL) driven from SPLL. 0: close, 1:
+         *  open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_240m_clk_en:1;
         /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1;
-         *  This field is used to open 64 MHz clock (div3 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 64 MHz clock (div3 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_160m_clk_en:1;
         /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1;
-         *  This field is used to open 48 MHz clock (div4 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 48 MHz clock (div4 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_120m_clk_en:1;
         /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1;
-         *  This field is used to open 32 MHz clock (div6  of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 32 MHz clock (div6  of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_80m_clk_en:1;
         /** pll_48m_clk_en : R/W; bitpos: [4]; default: 1;
-         *  This field is used to open 16 MHz clock (div10 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 16 MHz clock (div10 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_48m_clk_en:1;
         /** pll_40m_clk_en : R/W; bitpos: [5]; default: 1;
-         *  This field is used to open 8 MHz clock (div12 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 8 MHz clock (div12 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_40m_clk_en:1;
         uint32_t reserved_6:26;

components/soc/esp32h2/register/soc/sha_reg.h

@@ -156,7 +156,7 @@ extern "C" {
 #define SHA_DATE_S  0
 
 /** SHA_H_MEM register
- *  Sha H memory which contains intermediate hash or finial hash.
+ *  Sha H memory which contains intermediate hash or final hash.
  */
 #define SHA_H_MEM_REG (DR_REG_SHA_BASE + 0x40)
 #define SHA_H_MEM_SIZE_BYTES 64

components/soc/esp32h2/register/soc/spi_mem_reg.h

@@ -5,7 +5,7 @@
  */
 #pragma once
 
-#include "soc.h"
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -93,23 +93,23 @@ he bit will be cleared once the operation done.1: enable 0: disable..*/
 #define SPI_MEM_FLASH_DP_S  21
 /* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
 /*description: This bit combined with reg_resandres bit releases Flash from the power-down stat
-e or high performance mode and obtains the devices ID. The bit will be cleared o
-nce the operation done.1: enable 0: disable..*/
+e or high performance mode and obtains the devices ID. The bit will be cleared once
+the operation done.1: enable 0: disable..*/
 #define SPI_MEM_FLASH_RES    (BIT(20))
 #define SPI_MEM_FLASH_RES_M  (BIT(20))
 #define SPI_MEM_FLASH_RES_V  0x1
 #define SPI_MEM_FLASH_RES_S  20
 /* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Drive Flash into high performance mode.  The bit will be cleared once the operat
-ion done.1: enable 0: disable..*/
+/*description: Drive Flash into high performance mode.  The bit will be cleared once the operation
+done.1: enable 0: disable..*/
 #define SPI_MEM_FLASH_HPM    (BIT(19))
 #define SPI_MEM_FLASH_HPM_M  (BIT(19))
 #define SPI_MEM_FLASH_HPM_V  0x1
 #define SPI_MEM_FLASH_HPM_S  19
 /* SPI_MEM_USR : HRO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operat
-ion will be triggered when the bit is set. The bit will be cleared once the oper
-ation done.1: enable 0: disable..*/
+/*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operation
+will be triggered when the bit is set. The bit will be cleared once the operation
+done.1: enable 0: disable..*/
 #define SPI_MEM_USR    (BIT(18))
 #define SPI_MEM_USR_M  (BIT(18))
 #define SPI_MEM_USR_V  0x1
@@ -123,9 +123,9 @@ peration done.1: enable 0: disable..*/
 #define SPI_MEM_FLASH_PE_V  0x1
 #define SPI_MEM_FLASH_PE_S  17
 /* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
-/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation sta
-te, 2: send command state, 3: send address state, 4: wait state, 5: read data st
-ate, 6:write data state, 7: done state, 8: read data end state..*/
+/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation
+state, 2: send command state, 3: send address state, 4: wait state, 5: read data state
+, 6:write data state, 7: done state, 8: read data end state..*/
 #define SPI_MEM_SLV_ST    0x0000000F
 #define SPI_MEM_SLV_ST_M  ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S))
 #define SPI_MEM_SLV_ST_V  0xF
@@ -157,7 +157,7 @@ lways 1. 0: Others..*/
 #define SPI_MEM_DATA_IE_ALWAYS_ON_V  0x1
 #define SPI_MEM_DATA_IE_ALWAYS_ON_S  31
 /* SPI_MEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are alway
+/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always
 s 1. 0: Others..*/
 #define SPI_MEM_DQS_IE_ALWAYS_ON    (BIT(30))
 #define SPI_MEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
@@ -229,14 +229,14 @@ UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/
 #define SPI_MEM_FASTRD_MODE_V  0x1
 #define SPI_MEM_FASTRD_MODE_S  13
 /* SPI_MEM_TX_CRC_EN : HRO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disabl
+/*description: For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable
 e.*/
 #define SPI_MEM_TX_CRC_EN    (BIT(11))
 #define SPI_MEM_TX_CRC_EN_M  (BIT(11))
 #define SPI_MEM_TX_CRC_EN_V  0x1
 #define SPI_MEM_TX_CRC_EN_S  11
 /* SPI_MEM_FCS_CRC_EN : HRO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: For SPI1,  initialize crc32 module before writing encrypted data to flash. Activ
+/*description: For SPI1,  initialize crc32 module before writing encrypted data to flash. Active
 e low..*/
 #define SPI_MEM_FCS_CRC_EN    (BIT(10))
 #define SPI_MEM_FCS_CRC_EN_M  (BIT(10))
@@ -392,7 +392,7 @@ y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/
 /* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
 /*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
 d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
-ve 3: SPI clock is alwasy on..*/
+ve 3: SPI clock is always on..*/
 #define SPI_MEM_CLK_MODE    0x00000003
 #define SPI_MEM_CLK_MODE_M  ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
 #define SPI_MEM_CLK_MODE_V  0x3
@@ -422,8 +422,8 @@ whether there is an ECC region or not..*/
 #define SPI_MEM_SPLIT_TRANS_EN_V  0x1
 #define SPI_MEM_SPLIT_TRANS_EN_S  24
 /* SPI_MEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
-n accesses flash..*/
+/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
+accesses flash..*/
 #define SPI_MEM_ECC_16TO18_BYTE_EN    (BIT(14))
 #define SPI_MEM_ECC_16TO18_BYTE_EN_M  (BIT(14))
 #define SPI_MEM_ECC_16TO18_BYTE_EN_V  0x1
@@ -803,8 +803,8 @@ he register value shall be (bit_num-1)..*/
 #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V  0x3F
 #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S  6
 /* SPI_MEM_CACHE_SRAM_USR_RCMD : HRO ;bitpos:[5] ;default: 1'b1 ; */
-/*description: For SPI0, In the external RAM mode cache read external RAM for user define comma
-nd..*/
+/*description: For SPI0, In the external RAM mode cache read external RAM for user define command
+..*/
 #define SPI_MEM_CACHE_SRAM_USR_RCMD    (BIT(5))
 #define SPI_MEM_CACHE_SRAM_USR_RCMD_M  (BIT(5))
 #define SPI_MEM_CACHE_SRAM_USR_RCMD_V  0x1
@@ -1011,7 +1011,7 @@ e for sram..*/
 
 #define SPI_MEM_SRAM_CLK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x50)
 /* SPI_MEM_SCLK_EQU_SYSCLK : HRO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_c
+/*description: For SPI0 external RAM  interface, 1: spi_mem_clk is equal to system 0: spi_mem_c
 lk is divided from system clock..*/
 #define SPI_MEM_SCLK_EQU_SYSCLK    (BIT(31))
 #define SPI_MEM_SCLK_EQU_SYSCLK_M  (BIT(31))
@@ -1269,7 +1269,7 @@ out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS
 #define SPI_MEM_FLASH_PES_EN_S  5
 /* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
 /*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a
-pplication should send PER after PES is done..*/
+application should send PER after PES is done..*/
 #define SPI_MEM_PES_PER_EN    (BIT(4))
 #define SPI_MEM_PES_PER_EN_M  (BIT(4))
 #define SPI_MEM_PES_PER_EN_V  0x1
@@ -1291,8 +1291,8 @@ resume command is sent..*/
 #define SPI_MEM_FLASH_PER_WAIT_EN_V  0x1
 #define SPI_MEM_FLASH_PER_WAIT_EN_S  2
 /* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
-/*description: program erase suspend bit, program erase suspend operation will be triggered whe
-n the bit is set. The bit will be cleared once the operation done.1: enable 0: d
+/*description: program erase suspend bit, program erase suspend operation will be triggered when
+the bit is set. The bit will be cleared once the operation done.1: enable 0: d
 isable..*/
 #define SPI_MEM_FLASH_PES    (BIT(1))
 #define SPI_MEM_FLASH_PES_M  (BIT(1))
@@ -1536,7 +1536,7 @@ mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
 #define SPI_MEM_INT_RAW_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC8)
 /* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
 /*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
-chip is loosing power and RTC module sends out brown out close flash request to
+chip is losing power and RTC module sends out brown out close flash request to
 SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
  and MSPI returns to idle state. 0: Others..*/
 #define SPI_MEM_BROWN_OUT_INT_RAW    (BIT(10))
@@ -1580,8 +1580,8 @@ his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq
 ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SP
 I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
 of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E
-RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleare
-d, this bit will not be triggered..*/
+RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are clearer,
+this bit will not be triggered..*/
 #define SPI_MEM_ECC_ERR_INT_RAW    (BIT(5))
 #define SPI_MEM_ECC_ERR_INT_RAW_M  (BIT(5))
 #define SPI_MEM_ECC_ERR_INT_RAW_V  0x1
@@ -2371,9 +2371,9 @@ and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/
 #define SPI_MEM_ALL_FIFO_EMPTY_V  0x1
 #define SPI_MEM_ALL_FIFO_EMPTY_S  26
 /* SPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits show the first AXI write/read invalid error or AXI write flash error a
-ddress. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS
-H_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/
+/*description: This bits show the first AXI write/read invalid error or AXI write flash error
+address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR
+or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/
 #define SPI_MEM_AXI_ERR_ADDR    0x03FFFFFF
 #define SPI_MEM_AXI_ERR_ADDR_M  ((SPI_MEM_AXI_ERR_ADDR_V)<<(SPI_MEM_AXI_ERR_ADDR_S))
 #define SPI_MEM_AXI_ERR_ADDR_V  0x3FFFFFF
@@ -2679,7 +2679,7 @@ ations..*/
 #define SPI_MEM_SMEM_TIMING_CALI_V  0x1
 #define SPI_MEM_SMEM_TIMING_CALI_S  1
 /* SPI_MEM_SMEM_TIMING_CLK_ENA : HRO ;bitpos:[0] ;default: 1'b1 ; */
-/*description: For sram, the bit is used to enable timing adjust clock for all reading operatio
+/*description: For sram, the bit is used to enable timing adjust clock for all reading operation
 ns..*/
 #define SPI_MEM_SMEM_TIMING_CLK_ENA    (BIT(0))
 #define SPI_MEM_SMEM_TIMING_CLK_ENA_M  (BIT(0))
@@ -2937,8 +2937,8 @@ SPI core clock cycles..*/
 #define SPI_MEM_SMEM_CS_HOLD_DELAY_V  0x3F
 #define SPI_MEM_SMEM_CS_HOLD_DELAY_S  25
 /* SPI_MEM_SMEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
-n accesses external RAM..*/
+/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
+accesses external RAM..*/
 #define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
 #define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_M  (BIT(16))
 #define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_V  0x1

components/soc/esp32h2/register/soc/spi_mem_struct.h

@@ -9,7 +9,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 
 typedef volatile struct spi_mem_dev_s {
     union {
@@ -70,7 +70,7 @@ typedef volatile struct spi_mem_dev_s {
     } ctrl;
     union {
         struct {
-            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
+            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
             uint32_t cs_hold_dly_res               :    10;  /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
             uint32_t reserved2                     :    9;  /*reserved*/
             uint32_t reg_ar_size0_1_support_en     :    1;  /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.*/
@@ -272,7 +272,7 @@ typedef volatile struct spi_mem_dev_s {
             uint32_t sclkcnt_h                     :    8;  /*For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
             uint32_t sclkcnt_n                     :    8;  /*For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
             uint32_t reserved24                    :    7;  /*reserved*/
-            uint32_t sclk_equ_sysclk               :    1;  /*For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/
+            uint32_t sclk_equ_sysclk               :    1;  /*For SPI0 external RAM  interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk is divided from system clock.*/
         };
         uint32_t val;
     } sram_clk;
@@ -389,7 +389,7 @@ typedef volatile struct spi_mem_dev_s {
             uint32_t axi_raddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.*/
             uint32_t axi_wr_flash_err              :    1;  /*The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.*/
             uint32_t axi_waddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.*/
-            uint32_t brown_out                     :    1;  /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
+            uint32_t brown_out                     :    1;  /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is losing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
             uint32_t reserved11                    :    21;  /*reserved*/
         };
         uint32_t val;
@@ -1026,7 +1026,7 @@ typedef volatile struct spi_mem_dev_s {
     } mmu_power_ctrl;
     union {
         struct {
-            uint32_t reg_crypt_security_level      :    3;  /*Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/
+            uint32_t reg_crypt_security_level      :    3;  /*Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/
             uint32_t reg_crypt_calc_d_dpa_en       :    1;  /*Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/
             uint32_t reg_crypt_dpa_selectister     :    1;  /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/
             uint32_t reserved5                     :    27;  /*reserved*/

components/soc/esp32h2/register/soc/spi_reg.h

@@ -221,7 +221,7 @@ extern "C" {
 #define SPI_CLKDIV_PRE_V  0x0000000FU
 #define SPI_CLKDIV_PRE_S  18
 /** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1;
- *  In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system
+ *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
  *  clock. Can be configured in CONF state.
  */
 #define SPI_CLK_EQU_SYSCLK    (BIT(31))
@@ -1950,7 +1950,7 @@ extern "C" {
 /** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
  *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
  *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
- *  SPI clock is alwasy on. Can be configured in CONF state.
+ *  SPI clock is always on. Can be configured in CONF state.
  */
 #define SPI_CLK_MODE    0x00000003U
 #define SPI_CLK_MODE_M  (SPI_CLK_MODE_V << SPI_CLK_MODE_S)

components/soc/esp32h2/register/soc/spi_struct.h

@@ -511,7 +511,7 @@ typedef union {
         /** clk_mode : R/W; bitpos: [1:0]; default: 0;
          *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
          *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
-         *  SPI clock is alwasy on. Can be configured in CONF state.
+         *  SPI clock is always on. Can be configured in CONF state.
          */
         uint32_t clk_mode:2;
         /** clk_mode_13 : R/W; bitpos: [2]; default: 0;
@@ -624,7 +624,7 @@ typedef union {
         uint32_t clkdiv_pre:4;
         uint32_t reserved_22:9;
         /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
-         *  In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system
+         *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
          *  clock. Can be configured in CONF state.
          */
         uint32_t clk_equ_sysclk:1;