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feat(cache): supported cache driver on h21

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This commit is contained in:
armando
2025-05-14 11:36:14 +08:00
parent 2189c52776
commit acda9a7a7e
3 changed files with 13 additions and 9 deletions
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2
components/esp_rom/esp32h21/include/esp32h21/rom/cache.h
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@ -13,8 +13,6 @@
extern "C" {
#endif
//TODO: [ESP32H21] IDF-11525
/** \defgroup cache_apis, cache operation related apis
* @brief cache apis
*/

11
components/esp_system/port/soc/esp32h21/Kconfig.cache Normal file
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@ -0,0 +1,11 @@
menu "Cache config"
config CACHE_L1_CACHE_SIZE
hex
default 0x4000
config CACHE_L1_CACHE_LINE_SIZE
int
default 32
endmenu # Cache config

9
components/hal/esp32h21/include/hal/cache_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,13 +10,12 @@
#include <stdbool.h>
#include "soc/cache_reg.h"
#include "soc/cache_struct.h"
#include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
#include "rom/cache.h"
//TODO: [ESP32H21] IDF-11525, inherit from h2
#ifdef __cplusplus
extern "C" {
#endif
@ -187,7 +186,6 @@ __attribute__((always_inline))
#endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{
//TODO: [ESP32H21] IDF-11525, inherit from h2
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
cache_bus_mask_t mask = (cache_bus_mask_t)0;
@ -213,7 +211,6 @@ __attribute__((always_inline))
#endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
//TODO: [ESP32H21] IDF-11525, inherit from h2
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32h21, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
@ -236,7 +233,6 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
__attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
//TODO: [ESP32H21] IDF-11525, inherit from h2
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32h21, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
@ -263,7 +259,6 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m
__attribute__((always_inline))
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
{
//TODO: [ESP32H21] IDF-11525, inherit from h2
bool valid = false;
uint32_t vaddr_end = vaddr_start + len - 1;