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bugfix: fix esp32s3 psram access failed when dfs is enabled

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This commit is contained in:
wuzhenghui
2023-06-09 17:19:24 +08:00
parent 4bc762621d
commit ad1605a464
3 changed files with 23 additions and 8 deletions
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4
components/esp_hw_support/mspi_timing_tuning.c
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@@ -561,8 +561,8 @@ void mspi_timing_enter_high_speed_mode(bool control_spi1)
void mspi_timing_change_speed_mode_cache_safe(bool switch_down) void mspi_timing_change_speed_mode_cache_safe(bool switch_down)
{ {
Cache_Freeze_ICache_Enable(1); Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
Cache_Freeze_DCache_Enable(1); Cache_Freeze_DCache_Enable(CACHE_FREEZE_ACK_BUSY);
if (switch_down) { if (switch_down) {
//enter MSPI low speed mode, extra delays should be removed //enter MSPI low speed mode, extra delays should be removed
mspi_timing_enter_low_speed_mode(false); mspi_timing_enter_low_speed_mode(false);

11
components/esp_hw_support/sleep_modes.c
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@@ -512,7 +512,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t mo
pd_flags &= ~RTC_SLEEP_PD_INT_8M; pd_flags &= ~RTC_SLEEP_PD_INT_8M;
} }
// Turn down mspi clock speed // Will switch to XTAL turn down MSPI speed
#if SOC_SPI_MEM_SUPPORT_TIME_TUNING #if SOC_SPI_MEM_SUPPORT_TIME_TUNING
mspi_timing_change_speed_mode_cache_safe(true); mspi_timing_change_speed_mode_cache_safe(true);
#endif #endif
@@ -704,14 +704,15 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t mo
} }
// Set mspi clock to ROM default one. // Set mspi clock to ROM default one.
if (cpu_freq_config.source == SOC_CPU_CLK_SRC_PLL) {
#if SOC_MEMSPI_CLOCK_IS_INDEPENDENT #if SOC_MEMSPI_CLOCK_IS_INDEPENDENT
spi_flash_set_clock_src(MSPI_CLK_SRC_DEFAULT); spi_flash_set_clock_src(MSPI_CLK_SRC_DEFAULT);
#endif #endif
// Speed up mspi clock freq
#if SOC_SPI_MEM_SUPPORT_TIME_TUNING #if SOC_SPI_MEM_SUPPORT_TIME_TUNING
mspi_timing_change_speed_mode_cache_safe(false); // Turn up MSPI speed if switch to PLL
mspi_timing_change_speed_mode_cache_safe(false);
#endif #endif
}
if (!deep_sleep) { if (!deep_sleep) {
s_config.ccount_ticks_record = esp_cpu_get_cycle_count(); s_config.ccount_ticks_record = esp_cpu_get_cycle_count();

16
components/esp_pm/pm_impl.c
View File

@@ -31,6 +31,10 @@
#include "xtensa/core-macros.h" #include "xtensa/core-macros.h"
#endif #endif
#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
#include "esp_private/mspi_timing_tuning.h"
#endif
#include "esp_private/pm_impl.h" #include "esp_private/pm_impl.h"
#include "esp_private/pm_trace.h" #include "esp_private/pm_trace.h"
#include "esp_private/esp_timer_private.h" #include "esp_private/esp_timer_private.h"
@@ -475,7 +479,17 @@ static void IRAM_ATTR do_switch(pm_mode_t new_mode)
if (switch_down) { if (switch_down) {
on_freq_update(old_ticks_per_us, new_ticks_per_us); on_freq_update(old_ticks_per_us, new_ticks_per_us);
} }
rtc_clk_cpu_freq_set_config_fast(&new_config); if (new_config.source == SOC_CPU_CLK_SRC_PLL) {
rtc_clk_cpu_freq_set_config_fast(&new_config);
#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
mspi_timing_change_speed_mode_cache_safe(false);
#endif
} else {
#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
mspi_timing_change_speed_mode_cache_safe(true);
#endif
rtc_clk_cpu_freq_set_config_fast(&new_config);
}
if (!switch_down) { if (!switch_down) {
on_freq_update(old_ticks_per_us, new_ticks_per_us); on_freq_update(old_ticks_per_us, new_ticks_per_us);
} }