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fix(psram): fixed psram cross page issue

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This commit is contained in:
armando
2025-08-15 12:13:24 +08:00
parent 23517c9317
commit ad4fe4c394
4 changed files with 36 additions and 6 deletions
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4
components/esp_psram/device/esp_psram_impl_ap_hex.c
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@@ -391,8 +391,6 @@ static void s_configure_psram_ecc(void)
{
psram_ctrlr_ll_enable_16to18_ecc(PSRAM_CTRLR_LL_MSPI_ID_2, true);
psram_ctrlr_ll_enable_skip_page_corner(PSRAM_CTRLR_LL_MSPI_ID_2, true);
psram_ctrlr_ll_enable_split_trans(PSRAM_CTRLR_LL_MSPI_ID_2, true);
psram_ctrlr_ll_set_page_size(PSRAM_CTRLR_LL_MSPI_ID_2, 2048);
psram_ctrlr_ll_enable_ecc_addr_conversion(PSRAM_CTRLR_LL_MSPI_ID_2, 2048);
/**
@@ -427,6 +425,8 @@ esp_err_t esp_psram_impl_enable(void)
mspi_timing_ll_enable_dqs(true);
s_set_psram_cs_timing();
psram_ctrlr_ll_enable_split_trans(PSRAM_CTRLR_LL_MSPI_ID_2, true);
psram_ctrlr_ll_set_page_size(PSRAM_CTRLR_LL_MSPI_ID_2, 2048);
#if CONFIG_SPIRAM_ECC_ENABLE
s_configure_psram_ecc();
#endif

11
components/esp_psram/device/esp_psram_impl_ap_quad.c
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@@ -233,8 +233,6 @@ static void s_configure_psram_ecc(void)
{
psram_ctrlr_ll_set_ecc_mode(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_LL_ECC_MODE_16TO18);
psram_ctrlr_ll_enable_skip_page_corner(PSRAM_CTRLR_LL_MSPI_ID_0, true);
psram_ctrlr_ll_enable_split_trans(PSRAM_CTRLR_LL_MSPI_ID_0, true);
psram_ctrlr_ll_set_page_size(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_PAGE_SIZE);
psram_ctrlr_ll_enable_ecc_addr_conversion(PSRAM_CTRLR_LL_MSPI_ID_0, true);
/**
@@ -399,6 +397,15 @@ esp_err_t esp_psram_impl_enable(void)
psram_reset_mode(PSRAM_CTRLR_LL_MSPI_ID_1);
//SPI1: send QPI enable command
psram_enable_qio_mode(PSRAM_CTRLR_LL_MSPI_ID_1);
//MSPI cross page configs
uint32_t page_size = 0;
if (s_psram_size == PSRAM_SIZE_2MB) {
page_size = 512;
} else {
page_size = 1024;
}
psram_ctrlr_ll_enable_split_trans(PSRAM_CTRLR_LL_MSPI_ID_1, true);
psram_ctrlr_ll_set_page_size(PSRAM_CTRLR_LL_MSPI_ID_1, page_size);
#if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
//Do PSRAM timing tuning, we use SPI1 to do the tuning, and set the SPI0 PSRAM timing related registers accordingly

1
components/esp_psram/device/esp_quad_psram_defs_ap.h
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@@ -78,7 +78,6 @@ extern "C" {
#define PSRAM_QUAD_CS_SETUP_VAL 1
#define PSRAM_QUAD_CS_ECC_HOLD_TIME_VAL 3
#define PSRAM_QUAD_PAGE_SIZE 512
#define PSRAM_QUAD_ECC_ENABLE_MASK BIT(8)
// QEMU has a simulated 16MB and 32MB Quad SPI PSRAM. Use a fake ID for these.

26
components/hal/esp32s3/include/hal/psram_ctrlr_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -226,6 +226,30 @@ static inline void psram_ctrlr_ll_enable_quad_command(uint32_t mspi_id, bool ena
SPIMEM1.ctrl.fcmd_quad = ena;
}
/**
* @brief Set page size
*
* @param mspi_id mspi_id
* @param size page size
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_page_size(uint32_t mspi_id, uint32_t size)
{
//for compatibility
}
/**
* @brief Enable splitting transactions
*
* @param mspi_id mspi_id
* @param en enable / disable
*/
__attribute__((always_inline))
static inline void psram_ctrlr_ll_enable_split_trans(uint32_t mspi_id, bool en)
{
//for compatibility
}
#ifdef __cplusplus
}
#endif