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feat(spi_flash): Add spi flash suspend support on esp32c5, esp32c61

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This commit is contained in:
C.S.M
2025-06-04 15:15:33 +08:00
committed by BOT
parent 4a80901841
commit b194636859
17 changed files with 300 additions and 7157 deletions
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15
components/hal/esp32c5/include/hal/spimem_flash_ll.h
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@@ -216,7 +216,7 @@ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint3
}
/**
* Configure the delay after Suspend/Resume
* Configure the delay after Suspend
*
* @param dev Beginning address of the peripheral registers.
* @param dly_val delay time
@@ -224,10 +224,21 @@ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint3
static inline void spimem_flash_ll_set_sus_delay(spi_mem_dev_t *dev, uint32_t dly_val)
{
dev->ctrl1.cs_hold_dly_res = dly_val;
dev->sus_status.flash_per_dly_128 = 1;
dev->sus_status.flash_pes_dly_128 = 1;
}
/**
* Configure the delay after Resume
*
* @param dev Beginning address of the peripheral registers.
* @param dly_val delay time
*/
static inline void spimem_flash_ll_set_rs_delay(spi_mem_dev_t *dev, uint32_t dly_val)
{
dev->ctrl1.cs_hold_dly_per = dly_val;
dev->sus_status.flash_per_dly_128 = 1;
}
/**
* Configure the cs hold delay time(used to set the minimum CS high time tSHSL)
*

15
components/hal/esp32c61/include/hal/spimem_flash_ll.h
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@@ -215,7 +215,7 @@ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint3
}
/**
* Configure the delay after Suspend/Resume
* Configure the delay after Suspend
*
* @param dev Beginning address of the peripheral registers.
* @param dly_val delay time
@@ -223,10 +223,21 @@ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint3
static inline void spimem_flash_ll_set_sus_delay(spi_mem_dev_t *dev, uint32_t dly_val)
{
dev->ctrl1.cs_hold_dly_res = dly_val;
dev->sus_status.flash_per_dly_128 = 1;
dev->sus_status.flash_pes_dly_128 = 1;
}
/**
* Configure the delay after Resume
*
* @param dev Beginning address of the peripheral registers.
* @param dly_val delay time
*/
static inline void spimem_flash_ll_set_rs_delay(spi_mem_dev_t *dev, uint32_t dly_val)
{
dev->ctrl1.cs_hold_dly_per = dly_val;
dev->sus_status.flash_per_dly_128 = 1;
}
/**
* Configure the cs hold delay time(used to set the minimum CS high time tSHSL)
*

2
components/hal/include/hal/spi_flash_hal.h
View File

@@ -57,6 +57,7 @@ typedef struct {
#define SPI_FLASH_HOST_CONTEXT_SLICER_FLAG_DTR BIT(0) ///< Slice data according to DTR mode, the address and length must be even (A0=0).
int freq_mhz; /// Flash clock frequency.
uint8_t tsus_val; ///< Tsus value of suspend (us)
uint8_t trs_val; ///< Trs value of suspend (us)
bool auto_waiti_pes; ///< True for auto-wait idle after suspend command. False for using time delay.
} spi_flash_hal_context_t;
ESP_STATIC_ASSERT(sizeof(spi_flash_hal_context_t) == 48, "size of spi_flash_hal_context_t incorrect. Please check data compatibility with the ROM");
@@ -94,6 +95,7 @@ typedef struct {
int freq_mhz; ///< SPI flash clock speed (MHZ).
int clock_src_freq; ///< SPI flash clock source (MHZ).
uint8_t tsus_val; ///< Tsus value of suspend (us).
uint8_t trs_val; ///< Trs value of suspend (us)
bool auto_waiti_pes; ///< True for auto-wait idle after suspend command. False for using time delay.
} spi_flash_hal_config_t;

1
components/hal/spi_flash_hal.c
View File

@@ -131,6 +131,7 @@ esp_err_t spi_flash_hal_init(spi_flash_hal_context_t *data_out, const spi_flash_
data_out->flags |= SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_SUSPEND;
data_out->flags |= SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_RESUME;
data_out->tsus_val = cfg->tsus_val;
data_out->trs_val = cfg->trs_val;
data_out->auto_waiti_pes = cfg->auto_waiti_pes;
}

7
components/hal/spi_flash_hal_iram.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -154,6 +154,11 @@ void spi_flash_hal_setup_auto_suspend_mode(spi_flash_host_inst_t *host)
// tsus = ceil(ctx->tsus_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles);
uint32_t tsus = (ctx->tsus_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles(dev)) + ((ctx->tsus_val * ctx->freq_mhz) % spimem_flash_ll_get_tsus_unit_in_cycles(dev) != 0);
spimem_flash_ll_set_sus_delay(dev, tsus);
#if SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
// trs = ceil(ctx->trs_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles);
uint32_t trs = (ctx->trs_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles(dev)) + ((ctx->trs_val * ctx->freq_mhz) % spimem_flash_ll_get_tsus_unit_in_cycles(dev) != 0);
spimem_flash_ll_set_rs_delay(dev, trs);
#endif // SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
// tshsl2 = ceil(SPI_FLASH_TSHSL2_SAFE_VAL_NS * spimem_flash_ll_get_source_freq_mhz() * 0.001);
uint32_t tshsl2 = (SPI_FLASH_TSHSL2_SAFE_VAL_NS * spimem_flash_ll_get_source_freq_mhz() / 1000) + ((SPI_FLASH_TSHSL2_SAFE_VAL_NS * spimem_flash_ll_get_source_freq_mhz()) % 1000 != 0);
spimem_flash_set_cs_hold_delay(dev, tshsl2);

4
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
View File

@@ -1207,6 +1207,10 @@ config SOC_SPI_MEM_SUPPORT_TIMING_TUNING
bool
default y
config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
bool
default y
config SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY
bool
default y

1
components/soc/esp32c5/include/soc/soc_caps.h
View File

@@ -475,6 +475,7 @@
#define SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL (1)
#define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1)
#define SOC_SPI_MEM_SUPPORT_TIMING_TUNING (1)
#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1)
#define SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY (1)
#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1

14
components/soc/esp32c5/register/soc/spi1_mem_reg.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -328,13 +328,21 @@ extern "C" {
#define SPI_MEM_CLK_MODE_V 0x00000003U
#define SPI_MEM_CLK_MODE_S 0
/** SPI_MEM_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023;
* After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512)
* SPI_CLK cycles.
* After RES/DP/HPM/PES command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] *
* 128) SPI_CLK cycles.
*/
#define SPI_MEM_CS_HOLD_DLY_RES 0x000003FFU
#define SPI_MEM_CS_HOLD_DLY_RES_M (SPI_MEM_CS_HOLD_DLY_RES_V << SPI_MEM_CS_HOLD_DLY_RES_S)
#define SPI_MEM_CS_HOLD_DLY_RES_V 0x000003FFU
#define SPI_MEM_CS_HOLD_DLY_RES_S 2
/** SPI_MEM_CS_HOLD_DLY_PER : R/W; bitpos: [21:12]; default: 1023;
* After PER command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DLY_PER[9:0] * 128) SPI_CLK
* cycles.
*/
#define SPI_MEM_CS_HOLD_DLY_PER 0x000003FFU
#define SPI_MEM_CS_HOLD_DLY_PER_M (SPI_MEM_CS_HOLD_DLY_PER_V << SPI_MEM_CS_HOLD_DLY_PER_S)
#define SPI_MEM_CS_HOLD_DLY_PER_V 0x000003FFU
#define SPI_MEM_CS_HOLD_DLY_PER_S 12
/** SPI_MEM_CTRL2_REG(i) register
* SPI1 control2 register.

21
components/soc/esp32c5/register/soc/spi1_mem_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -338,11 +338,16 @@ typedef union {
*/
uint32_t clk_mode:2;
/** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023;
* After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512)
* SPI_CLK cycles.
* After RES/DP/HPM/PES command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] *
* 128) SPI_CLK cycles.
*/
uint32_t cs_hold_dly_res:10;
uint32_t reserved_12:20;
/** cs_hold_dly_per : R/W; bitpos: [21:12]; default: 1023;
* After PER command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DLY_PER[9:0] * 128) SPI_CLK
* cycles.
*/
uint32_t cs_hold_dly_per:10;
uint32_t reserved_22:10;
};
uint32_t val;
} spi_mem_ctrl1_reg_t;
@@ -367,16 +372,16 @@ typedef union {
typedef union {
struct {
/** clkcnt_l : R/W; bitpos: [7:0]; default: 3;
* In the master mode it must be equal to spi_mem_clkcnt_N.
* In the master mode it must be equal to SPI_MEM_CLKCNT_N.
*/
uint32_t clkcnt_l:8;
/** clkcnt_h : R/W; bitpos: [15:8]; default: 1;
* In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
* In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1).
*/
uint32_t clkcnt_h:8;
/** clkcnt_n : R/W; bitpos: [23:16]; default: 3;
* In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
* system/(spi_mem_clkcnt_N+1)
* system/(SPI_MEM_CLKCNT_N+1)
*/
uint32_t clkcnt_n:8;
uint32_t reserved_24:7;
@@ -1222,7 +1227,7 @@ typedef union {
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36774400;
/** date : R/W; bitpos: [27:0]; default: 37786176;
* Version control register
*/
uint32_t date:28;

114
components/soc/esp32c5/register/soc/spi_mem_c_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -205,29 +205,21 @@ extern "C" {
#define SPI_MEM_CLK_MODE_M (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S)
#define SPI_MEM_CLK_MODE_V 0x00000003U
#define SPI_MEM_CLK_MODE_S 0
/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1;
/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1;
* 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply
* the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.
*/
#define SPI_AR_SIZE0_1_SUPPORT_EN (BIT(21))
#define SPI_AR_SIZE0_1_SUPPORT_EN (BIT(22))
#define SPI_AR_SIZE0_1_SUPPORT_EN_M (SPI_AR_SIZE0_1_SUPPORT_EN_V << SPI_AR_SIZE0_1_SUPPORT_EN_S)
#define SPI_AR_SIZE0_1_SUPPORT_EN_V 0x00000001U
#define SPI_AR_SIZE0_1_SUPPORT_EN_S 21
/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1;
#define SPI_AR_SIZE0_1_SUPPORT_EN_S 22
/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [23]; default: 1;
* 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.
*/
#define SPI_AW_SIZE0_1_SUPPORT_EN (BIT(22))
#define SPI_AW_SIZE0_1_SUPPORT_EN (BIT(23))
#define SPI_AW_SIZE0_1_SUPPORT_EN_M (SPI_AW_SIZE0_1_SUPPORT_EN_V << SPI_AW_SIZE0_1_SUPPORT_EN_S)
#define SPI_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U
#define SPI_AW_SIZE0_1_SUPPORT_EN_S 22
/** SPI_AXI_RDATA_BACK_FAST : R/W; bitpos: [23]; default: 1;
* 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0:
* Reply AXI read data to AXI bus when all the read data is available.
*/
#define SPI_AXI_RDATA_BACK_FAST (BIT(23))
#define SPI_AXI_RDATA_BACK_FAST_M (SPI_AXI_RDATA_BACK_FAST_V << SPI_AXI_RDATA_BACK_FAST_S)
#define SPI_AXI_RDATA_BACK_FAST_V 0x00000001U
#define SPI_AXI_RDATA_BACK_FAST_S 23
#define SPI_AW_SIZE0_1_SUPPORT_EN_S 23
/** SPI_MEM_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0;
* 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
* when there is a ECC error in AXI read data. The ECC error information is recorded
@@ -370,14 +362,14 @@ extern "C" {
*/
#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14)
/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
* In the master mode it must be equal to spi_mem_clkcnt_N.
* In the master mode it must be equal to SPI_MEM_CLKCNT_N.
*/
#define SPI_MEM_CLKCNT_L 0x000000FFU
#define SPI_MEM_CLKCNT_L_M (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S)
#define SPI_MEM_CLKCNT_L_V 0x000000FFU
#define SPI_MEM_CLKCNT_L_S 0
/** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
* In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
* In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1).
*/
#define SPI_MEM_CLKCNT_H 0x000000FFU
#define SPI_MEM_CLKCNT_H_M (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S)
@@ -385,7 +377,7 @@ extern "C" {
#define SPI_MEM_CLKCNT_H_S 8
/** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
* In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
* system/(spi_mem_clkcnt_N+1)
* system/(SPI_MEM_CLKCNT_N+1)
*/
#define SPI_MEM_CLKCNT_N 0x000000FFU
#define SPI_MEM_CLKCNT_N_M (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S)
@@ -488,10 +480,13 @@ extern "C" {
/** SPI_MEM_RD_STATUS_REG register
* SPI0 read control register.
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2c)
/** SPI_MEM_WB_MODE : R/W; bitpos: [23:16]; default: 0;
* Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_WB_MODE 0x000000FFU
#define SPI_MEM_WB_MODE_M (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S)
@@ -499,6 +494,7 @@ extern "C" {
#define SPI_MEM_WB_MODE_S 16
/** SPI_MEM_WB_MODE_BITLEN : R/W; bitpos: [26:24]; default: 0;
* Mode bits length for flash fast read mode.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_WB_MODE_BITLEN 0x00000007U
#define SPI_MEM_WB_MODE_BITLEN_M (SPI_MEM_WB_MODE_BITLEN_V << SPI_MEM_WB_MODE_BITLEN_S)
@@ -506,6 +502,7 @@ extern "C" {
#define SPI_MEM_WB_MODE_BITLEN_S 24
/** SPI_MEM_WB_MODE_EN : R/W; bitpos: [27]; default: 0;
* Mode bits is valid while this bit is enable. 1: enable 0: disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_WB_MODE_EN (BIT(27))
#define SPI_MEM_WB_MODE_EN_M (SPI_MEM_WB_MODE_EN_V << SPI_MEM_WB_MODE_EN_S)
@@ -937,14 +934,16 @@ extern "C" {
*/
#define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x50)
/** SPI_MEM_SCLKCNT_L : R/W; bitpos: [7:0]; default: 3;
* For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N.
* For SPI0 external RAM interface, it must be equal to SPI_MEM_SCLKCNT_N.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_SCLKCNT_L 0x000000FFU
#define SPI_MEM_SCLKCNT_L_M (SPI_MEM_SCLKCNT_L_V << SPI_MEM_SCLKCNT_L_S)
#define SPI_MEM_SCLKCNT_L_V 0x000000FFU
#define SPI_MEM_SCLKCNT_L_S 0
/** SPI_MEM_SCLKCNT_H : R/W; bitpos: [15:8]; default: 1;
* For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).
* For SPI0 external RAM interface, it must be floor((SPI_MEM_SCLKCNT_N+1)/2-1).
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_SCLKCNT_H 0x000000FFU
#define SPI_MEM_SCLKCNT_H_M (SPI_MEM_SCLKCNT_H_V << SPI_MEM_SCLKCNT_H_S)
@@ -952,7 +951,8 @@ extern "C" {
#define SPI_MEM_SCLKCNT_H_S 8
/** SPI_MEM_SCLKCNT_N : R/W; bitpos: [23:16]; default: 3;
* For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk
* frequency is system/(spi_mem_clkcnt_N+1)
* frequency is system/(SPI_MEM_SCLKCNT_N+1)
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_SCLKCNT_N 0x000000FFU
#define SPI_MEM_SCLKCNT_N_M (SPI_MEM_SCLKCNT_N_V << SPI_MEM_SCLKCNT_N_S)
@@ -961,6 +961,7 @@ extern "C" {
/** SPI_MEM_SCLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
* For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk
* is divided from system clock.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31))
#define SPI_MEM_SCLK_EQU_SYSCLK_M (SPI_MEM_SCLK_EQU_SYSCLK_V << SPI_MEM_SCLK_EQU_SYSCLK_S)
@@ -971,27 +972,27 @@ extern "C" {
* SPI0 FSM status register
*/
#define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x54)
/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4;
/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [18:7]; default: 4;
* The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
*/
#define SPI_MEM_LOCK_DELAY_TIME 0x0000001FU
#define SPI_MEM_LOCK_DELAY_TIME 0x00000FFFU
#define SPI_MEM_LOCK_DELAY_TIME_M (SPI_MEM_LOCK_DELAY_TIME_V << SPI_MEM_LOCK_DELAY_TIME_S)
#define SPI_MEM_LOCK_DELAY_TIME_V 0x0000001FU
#define SPI_MEM_LOCK_DELAY_TIME_V 0x00000FFFU
#define SPI_MEM_LOCK_DELAY_TIME_S 7
/** SPI_MEM_FLASH_LOCK_EN : R/W; bitpos: [12]; default: 0;
/** SPI_MEM_FLASH_LOCK_EN : R/W; bitpos: [19]; default: 0;
* The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable.
*/
#define SPI_MEM_FLASH_LOCK_EN (BIT(12))
#define SPI_MEM_FLASH_LOCK_EN (BIT(19))
#define SPI_MEM_FLASH_LOCK_EN_M (SPI_MEM_FLASH_LOCK_EN_V << SPI_MEM_FLASH_LOCK_EN_S)
#define SPI_MEM_FLASH_LOCK_EN_V 0x00000001U
#define SPI_MEM_FLASH_LOCK_EN_S 12
/** SPI_MEM_SRAM_LOCK_EN : R/W; bitpos: [13]; default: 0;
#define SPI_MEM_FLASH_LOCK_EN_S 19
/** SPI_MEM_SRAM_LOCK_EN : R/W; bitpos: [20]; default: 0;
* The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable.
*/
#define SPI_MEM_SRAM_LOCK_EN (BIT(13))
#define SPI_MEM_SRAM_LOCK_EN (BIT(20))
#define SPI_MEM_SRAM_LOCK_EN_M (SPI_MEM_SRAM_LOCK_EN_V << SPI_MEM_SRAM_LOCK_EN_S)
#define SPI_MEM_SRAM_LOCK_EN_V 0x00000001U
#define SPI_MEM_SRAM_LOCK_EN_S 13
#define SPI_MEM_SRAM_LOCK_EN_S 20
/** SPI_MEM_INT_ENA_REG register
* SPI0 interrupt enable register
@@ -1593,7 +1594,7 @@ extern "C" {
#define SPI_SMEM_HYPERBUS_CA_S 30
/** SPI_FMEM_PMS0_ATTR_REG register
* MSPI flash PMS section 0 attribute register
* SPI1 flash PMS section 0 attribute register
*/
#define SPI_FMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x100)
/** SPI_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1;
@@ -1621,7 +1622,7 @@ extern "C" {
#define SPI_FMEM_PMS0_ECC_S 2
/** SPI_FMEM_PMS1_ATTR_REG register
* MSPI flash PMS section 1 attribute register
* SPI1 flash PMS section 1 attribute register
*/
#define SPI_FMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x104)
/** SPI_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1;
@@ -1649,7 +1650,7 @@ extern "C" {
#define SPI_FMEM_PMS1_ECC_S 2
/** SPI_FMEM_PMS2_ATTR_REG register
* MSPI flash PMS section 2 attribute register
* SPI1 flash PMS section 2 attribute register
*/
#define SPI_FMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x108)
/** SPI_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1;
@@ -1677,7 +1678,7 @@ extern "C" {
#define SPI_FMEM_PMS2_ECC_S 2
/** SPI_FMEM_PMS3_ATTR_REG register
* MSPI flash PMS section 3 attribute register
* SPI1 flash PMS section 3 attribute register
*/
#define SPI_FMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x10c)
/** SPI_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1;
@@ -1805,7 +1806,7 @@ extern "C" {
#define SPI_FMEM_PMS3_SIZE_S 0
/** SPI_SMEM_PMS0_ATTR_REG register
* SPI1 flash PMS section 0 start address register
* SPI1 external RAM PMS section 0 attribute register
*/
#define SPI_SMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x130)
/** SPI_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1;
@@ -1833,7 +1834,7 @@ extern "C" {
#define SPI_SMEM_PMS0_ECC_S 2
/** SPI_SMEM_PMS1_ATTR_REG register
* SPI1 flash PMS section 1 start address register
* SPI1 external RAM PMS section 1 attribute register
*/
#define SPI_SMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x134)
/** SPI_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1;
@@ -1861,7 +1862,7 @@ extern "C" {
#define SPI_SMEM_PMS1_ECC_S 2
/** SPI_SMEM_PMS2_ATTR_REG register
* SPI1 flash PMS section 2 start address register
* SPI1 external RAM PMS section 2 attribute register
*/
#define SPI_SMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x138)
/** SPI_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1;
@@ -1889,7 +1890,7 @@ extern "C" {
#define SPI_SMEM_PMS2_ECC_S 2
/** SPI_SMEM_PMS3_ATTR_REG register
* SPI1 flash PMS section 3 start address register
* SPI1 external RAM PMS section 3 attribute register
*/
#define SPI_SMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x13c)
/** SPI_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1;
@@ -2669,7 +2670,7 @@ extern "C" {
#define SPI_SMEM_DLL_TIMING_CALI_M (SPI_SMEM_DLL_TIMING_CALI_V << SPI_SMEM_DLL_TIMING_CALI_S)
#define SPI_SMEM_DLL_TIMING_CALI_V 0x00000001U
#define SPI_SMEM_DLL_TIMING_CALI_S 5
/** SPI_SMEM_DQS0_270_SEL : R/W; bitpos: [8:7]; default: 1;
/** SPI_SMEM_DQS0_270_SEL : HRO; bitpos: [8:7]; default: 1;
* Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust.
* 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns.
*/
@@ -2677,7 +2678,7 @@ extern "C" {
#define SPI_SMEM_DQS0_270_SEL_M (SPI_SMEM_DQS0_270_SEL_V << SPI_SMEM_DQS0_270_SEL_S)
#define SPI_SMEM_DQS0_270_SEL_V 0x00000003U
#define SPI_SMEM_DQS0_270_SEL_S 7
/** SPI_SMEM_DQS0_90_SEL : R/W; bitpos: [10:9]; default: 1;
/** SPI_SMEM_DQS0_90_SEL : HRO; bitpos: [10:9]; default: 1;
* Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns,
* 2'd2: 1.5ns 2'd3: 2.0ns.
*/
@@ -2685,6 +2686,22 @@ extern "C" {
#define SPI_SMEM_DQS0_90_SEL_M (SPI_SMEM_DQS0_90_SEL_V << SPI_SMEM_DQS0_90_SEL_S)
#define SPI_SMEM_DQS0_90_SEL_V 0x00000003U
#define SPI_SMEM_DQS0_90_SEL_S 9
/** SPI_SMEM_DQS1_270_SEL : HRO; bitpos: [12:11]; default: 1;
* Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust.
* 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns.
*/
#define SPI_SMEM_DQS1_270_SEL 0x00000003U
#define SPI_SMEM_DQS1_270_SEL_M (SPI_SMEM_DQS1_270_SEL_V << SPI_SMEM_DQS1_270_SEL_S)
#define SPI_SMEM_DQS1_270_SEL_V 0x00000003U
#define SPI_SMEM_DQS1_270_SEL_S 11
/** SPI_SMEM_DQS1_90_SEL : HRO; bitpos: [14:13]; default: 1;
* Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns,
* 2'd2: 1.5ns 2'd3: 2.0ns.
*/
#define SPI_SMEM_DQS1_90_SEL 0x00000003U
#define SPI_SMEM_DQS1_90_SEL_M (SPI_SMEM_DQS1_90_SEL_V << SPI_SMEM_DQS1_90_SEL_S)
#define SPI_SMEM_DQS1_90_SEL_V 0x00000003U
#define SPI_SMEM_DQS1_90_SEL_S 13
/** SPI_SMEM_DIN_MODE_REG register
* MSPI external RAM input timing delay mode control register
@@ -3309,6 +3326,13 @@ extern "C" {
#define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S)
#define SPI_CLK_EN_V 0x00000001U
#define SPI_CLK_EN_S 0
/** SPI_MSPI_CLK_FORCE_ON : HRO; bitpos: [1]; default: 1;
* MSPI lowpower function clock gate force on signal. 1: Enable. 0: Disable.
*/
#define SPI_MSPI_CLK_FORCE_ON (BIT(1))
#define SPI_MSPI_CLK_FORCE_ON_M (SPI_MSPI_CLK_FORCE_ON_V << SPI_MSPI_CLK_FORCE_ON_S)
#define SPI_MSPI_CLK_FORCE_ON_V 0x00000001U
#define SPI_MSPI_CLK_FORCE_ON_S 1
/** SPI_MEM_NAND_FLASH_EN_REG register
* NAND FLASH control register
@@ -3755,14 +3779,14 @@ extern "C" {
#define SPI_MMU_MEM_FORCE_ON_M (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S)
#define SPI_MMU_MEM_FORCE_ON_V 0x00000001U
#define SPI_MMU_MEM_FORCE_ON_S 0
/** SPI_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 1;
/** SPI_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
* Set this bit to force mmu-memory powerdown
*/
#define SPI_MMU_MEM_FORCE_PD (BIT(1))
#define SPI_MMU_MEM_FORCE_PD_M (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S)
#define SPI_MMU_MEM_FORCE_PD_V 0x00000001U
#define SPI_MMU_MEM_FORCE_PD_S 1
/** SPI_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
/** SPI_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
* Set this bit to force mmu-memory powerup, in this case, the power should also be
* controlled by rtc.
*/
@@ -3770,7 +3794,7 @@ extern "C" {
#define SPI_MMU_MEM_FORCE_PU_M (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S)
#define SPI_MMU_MEM_FORCE_PU_V 0x00000001U
#define SPI_MMU_MEM_FORCE_PU_S 2
/** SPI_MMU_PAGE_SIZE : HRO; bitpos: [4:3]; default: 0;
/** SPI_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0;
* 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8
*/
#define SPI_MMU_PAGE_SIZE 0x00000003U
@@ -3786,6 +3810,7 @@ extern "C" {
#define SPI_MEM_AUX_CTRL_S 16
/** SPI_MEM_RDN_ENA : R/W; bitpos: [30]; default: 0;
* ECO register enable bit
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_RDN_ENA (BIT(30))
#define SPI_MEM_RDN_ENA_M (SPI_MEM_RDN_ENA_V << SPI_MEM_RDN_ENA_S)
@@ -3793,6 +3818,7 @@ extern "C" {
#define SPI_MEM_RDN_ENA_S 30
/** SPI_MEM_RDN_RESULT : RO; bitpos: [31]; default: 0;
* MSPI module clock domain and AXI clock domain ECO register result register
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_RDN_RESULT (BIT(31))
#define SPI_MEM_RDN_RESULT_M (SPI_MEM_RDN_RESULT_V << SPI_MEM_RDN_RESULT_S)
@@ -3894,7 +3920,7 @@ extern "C" {
* SPI0 version control register
*/
#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3fc)
/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 36774400;
/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37822512;
* SPI0 register version.
*/
#define SPI_MEM_DATE 0x0FFFFFFFU

3988
components/soc/esp32c5/register/soc/spi_mem_c_reg_eco2.h
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261
components/soc/esp32c5/register/soc/spi_mem_c_struct.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -30,7 +30,7 @@ typedef union {
uint32_t mem_slv_st:4;
uint32_t reserved_8:10;
/** mem_usr : HRO; bitpos: [18]; default: 0;
* SPI0 USR_CMD start bit, only used when spi_mem_c_AXI_REQ_EN is cleared. An operation
* SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation
* will be triggered when the bit is set. The bit will be cleared once the operation
* done.1: enable 0: disable.
*/
@@ -47,8 +47,8 @@ typedef union {
struct {
/** mem_axi_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0;
* This bits show the first AXI write/read invalid error or AXI write flash error
* address. It is cleared by when spi_mem_c_AXI_WADDR_ERR_INT_CLR,
* spi_mem_c_AXI_WR_FLASH_ERR_IN_CLR or spi_mem_c_AXI_RADDR_ERR_IN_CLR bit is set.
* address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR,
* SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set.
*/
uint32_t mem_axi_err_addr:29;
uint32_t reserved_29:3;
@@ -108,8 +108,8 @@ typedef union {
uint32_t mem_fcmd_oct:1;
uint32_t reserved_10:3;
/** mem_fastrd_mode : R/W; bitpos: [13]; default: 1;
* This bit enable the bits: spi_mem_c_FREAD_QIO, spi_mem_c_FREAD_DIO, spi_mem_c_FREAD_QOUT
* and spi_mem_c_FREAD_DOUT. 1: enable 0: disable.
* This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT
* and SPI_MEM_FREAD_DOUT. 1: enable 0: disable.
*/
uint32_t mem_fastrd_mode:1;
/** mem_fread_dual : R/W; bitpos: [14]; default: 0;
@@ -170,25 +170,20 @@ typedef union {
* SPI clock is always on.
*/
uint32_t mem_clk_mode:2;
uint32_t reserved_2:19;
/** ar_size0_1_support_en : R/W; bitpos: [21]; default: 1;
uint32_t reserved_2:20;
/** ar_size0_1_support_en : R/W; bitpos: [22]; default: 1;
* 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply
* the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.
*/
uint32_t ar_size0_1_support_en:1;
/** aw_size0_1_support_en : R/W; bitpos: [22]; default: 1;
/** aw_size0_1_support_en : R/W; bitpos: [23]; default: 1;
* 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.
*/
uint32_t aw_size0_1_support_en:1;
/** axi_rdata_back_fast : R/W; bitpos: [23]; default: 1;
* 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0:
* Reply AXI read data to AXI bus when all the read data is available.
*/
uint32_t axi_rdata_back_fast:1;
/** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0;
* 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
* when there is a ECC error in AXI read data. The ECC error information is recorded
* in spi_mem_c_ECC_ERR_ADDR_REG.
* in SPI_MEM_ECC_ERR_ADDR_REG.
*/
uint32_t mem_rresp_ecc_err_en:1;
/** mem_ar_splice_en : R/W; bitpos: [25]; default: 0;
@@ -200,9 +195,9 @@ typedef union {
*/
uint32_t mem_aw_splice_en:1;
/** mem_ram0_en : HRO; bitpos: [27]; default: 1;
* When spi_mem_c_DUAL_RAM_EN is 0 and spi_mem_c_RAM0_EN is 1, only EXT_RAM0 will be
* accessed. When spi_mem_c_DUAL_RAM_EN is 0 and spi_mem_c_RAM0_EN is 0, only EXT_RAM1
* will be accessed. When spi_mem_c_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be
* When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be
* accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1
* will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be
* accessed at the same time.
*/
uint32_t mem_ram0_en:1;
@@ -238,16 +233,16 @@ typedef union {
struct {
/** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1;
* (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with
* spi_mem_c_CS_SETUP bit.
* SPI_MEM_CS_SETUP bit.
*/
uint32_t mem_cs_setup_time:5;
/** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1;
* SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with
* spi_mem_c_CS_HOLD bit.
* SPI_MEM_CS_HOLD bit.
*/
uint32_t mem_cs_hold_time:5;
/** mem_ecc_cs_hold_time : R/W; bitpos: [12:10]; default: 3;
* spi_mem_c_CS_HOLD_TIME + spi_mem_c_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
* SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
* mode when accessed flash.
*/
uint32_t mem_ecc_cs_hold_time:3;
@@ -270,7 +265,7 @@ typedef union {
uint32_t mem_split_trans_en:1;
/** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0;
* These bits are used to set the minimum CS high time tSHSL between SPI burst
* transfer when accesses to flash. tSHSL is (spi_mem_c_CS_HOLD_DELAY[5:0] + 1) MSPI
* transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI
* core clock cycles.
*/
uint32_t mem_cs_hold_delay:6;
@@ -424,7 +419,7 @@ typedef union {
uint32_t fmem_usr_ddr_dqs_thd:7;
/** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0;
* 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
* spi0_slv_st is in spi_mem_c_DIN state. It is used when there is no SPI_DQS signal or
* spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
* SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
* negative edge of SPI_DQS.
*/
@@ -471,16 +466,16 @@ typedef union {
typedef union {
struct {
/** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3;
* In the master mode it must be equal to spi_mem_c_clkcnt_N.
* In the master mode it must be equal to SPI_MEM_CLKCNT_N.
*/
uint32_t mem_clkcnt_l:8;
/** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1;
* In the master mode it must be floor((spi_mem_c_clkcnt_N+1)/2-1).
* In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1).
*/
uint32_t mem_clkcnt_h:8;
/** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3;
* In the master mode it is the divider of spi_mem_c_clk. So spi_mem_c_clk frequency is
* system/(spi_mem_c_clkcnt_N+1)
* system/(SPI_MEM_CLKCNT_N+1)
*/
uint32_t mem_clkcnt_n:8;
uint32_t reserved_24:7;
@@ -499,18 +494,18 @@ typedef union {
typedef union {
struct {
/** mem_sclkcnt_l : R/W; bitpos: [7:0]; default: 3;
* For SPI0 external RAM interface, it must be equal to spi_mem_c_clkcnt_N.
* For SPI0 external RAM interface, it must be equal to SPI_MEM_SCLKCNT_N.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t mem_sclkcnt_l:8;
/** mem_sclkcnt_h : R/W; bitpos: [15:8]; default: 1;
* For SPI0 external RAM interface, it must be floor((spi_mem_c_clkcnt_N+1)/2-1).
* For SPI0 external RAM interface, it must be floor((SPI_MEM_SCLKCNT_N+1)/2-1).
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t mem_sclkcnt_h:8;
/** mem_sclkcnt_n : R/W; bitpos: [23:16]; default: 3;
* For SPI0 external RAM interface, it is the divider of spi_mem_c_clk. So spi_mem_c_clk
* frequency is system/(spi_mem_c_clkcnt_N+1)
* frequency is system/(SPI_MEM_SCLKCNT_N+1)
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t mem_sclkcnt_n:8;
@@ -534,7 +529,11 @@ typedef union {
* Register clock gate enable signal. 1: Enable. 0: Disable.
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
/** mspi_clk_force_on : HRO; bitpos: [1]; default: 1;
* MSPI lowpower function clock gate force on signal. 1: Enable. 0: Disable.
*/
uint32_t mspi_clk_force_on:1;
uint32_t reserved_2:30;
};
uint32_t val;
} spi_mem_c_clock_gate_reg_t;
@@ -557,7 +556,7 @@ typedef union {
uint32_t mem_cs_setup:1;
uint32_t reserved_8:1;
/** mem_ck_out_edge : R/W; bitpos: [9]; default: 0;
* The bit combined with spi_mem_c_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
* The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
*/
uint32_t mem_ck_out_edge:1;
uint32_t reserved_10:16;
@@ -933,7 +932,7 @@ typedef union {
uint32_t smem_usr_ddr_dqs_thd:7;
/** smem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0;
* 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
* spi0_slv_st is in spi_mem_c_DIN state. It is used when there is no SPI_DQS signal or
* spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
* SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
* negative edge of SPI_DQS.
*/
@@ -998,7 +997,7 @@ typedef union {
*/
uint32_t smem_cs_hold_time:5;
/** smem_ecc_cs_hold_time : R/W; bitpos: [14:12]; default: 3;
* spi_smem_c_CS_HOLD_TIME + spi_smem_c_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold
* SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold
* cycles in ECC mode when accessed external RAM.
*/
uint32_t smem_ecc_cs_hold_time:3;
@@ -1015,7 +1014,7 @@ typedef union {
uint32_t reserved_17:8;
/** smem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0;
* These bits are used to set the minimum CS high time tSHSL between SPI burst
* transfer when accesses to external RAM. tSHSL is (spi_smem_c_CS_HOLD_DELAY[5:0] + 1)
* transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1)
* MSPI core clock cycles.
*/
uint32_t smem_cs_hold_delay:6;
@@ -1037,19 +1036,19 @@ typedef union {
typedef union {
struct {
uint32_t reserved_0:7;
/** mem_lock_delay_time : R/W; bitpos: [11:7]; default: 4;
/** mem_lock_delay_time : R/W; bitpos: [18:7]; default: 4;
* The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
*/
uint32_t mem_lock_delay_time:5;
/** mem_flash_lock_en : R/W; bitpos: [12]; default: 0;
uint32_t mem_lock_delay_time:12;
/** mem_flash_lock_en : R/W; bitpos: [19]; default: 0;
* The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable.
*/
uint32_t mem_flash_lock_en:1;
/** mem_sram_lock_en : R/W; bitpos: [13]; default: 0;
/** mem_sram_lock_en : R/W; bitpos: [20]; default: 0;
* The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable.
*/
uint32_t mem_sram_lock_en:1;
uint32_t reserved_14:18;
uint32_t reserved_21:11;
};
uint32_t val;
} spi_mem_c_fsm_reg_t;
@@ -1063,48 +1062,48 @@ typedef union {
struct {
uint32_t reserved_0:3;
/** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0;
* The enable bit for spi_mem_c_SLV_ST_END_INT interrupt.
* The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
*/
uint32_t mem_slv_st_end_int_ena:1;
/** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0;
* The enable bit for spi_mem_c_MST_ST_END_INT interrupt.
* The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
*/
uint32_t mem_mst_st_end_int_ena:1;
/** mem_ecc_err_int_ena : R/W; bitpos: [5]; default: 0;
* The enable bit for spi_mem_c_ECC_ERR_INT interrupt.
* The enable bit for SPI_MEM_ECC_ERR_INT interrupt.
*/
uint32_t mem_ecc_err_int_ena:1;
/** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0;
* The enable bit for spi_mem_c_PMS_REJECT_INT interrupt.
* The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.
*/
uint32_t mem_pms_reject_int_ena:1;
/** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0;
* The enable bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt.
* The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
*/
uint32_t mem_axi_raddr_err_int_ena:1;
/** mem_axi_wr_flash_err_int_ena : R/W; bitpos: [8]; default: 0;
* The enable bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt.
* The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
*/
uint32_t mem_axi_wr_flash_err_int_ena:1;
/** mem_axi_waddr_err_int__ena : R/W; bitpos: [9]; default: 0;
* The enable bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt.
* The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
*/
uint32_t mem_axi_waddr_err_int__ena:1;
uint32_t reserved_10:18;
/** mem_dqs0_afifo_ovf_int_ena : R/W; bitpos: [28]; default: 0;
* The enable bit for spi_mem_c_DQS0_AFIFO_OVF_INT interrupt.
* The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.
*/
uint32_t mem_dqs0_afifo_ovf_int_ena:1;
/** mem_dqs1_afifo_ovf_int_ena : R/W; bitpos: [29]; default: 0;
* The enable bit for spi_mem_c_DQS1_AFIFO_OVF_INT interrupt.
* The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.
*/
uint32_t mem_dqs1_afifo_ovf_int_ena:1;
/** mem_bus_fifo1_udf_int_ena : R/W; bitpos: [30]; default: 0;
* The enable bit for spi_mem_c_BUS_FIFO1_UDF_INT interrupt.
* The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.
*/
uint32_t mem_bus_fifo1_udf_int_ena:1;
/** mem_bus_fifo0_udf_int_ena : R/W; bitpos: [31]; default: 0;
* The enable bit for spi_mem_c_BUS_FIFO0_UDF_INT interrupt.
* The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.
*/
uint32_t mem_bus_fifo0_udf_int_ena:1;
};
@@ -1118,48 +1117,48 @@ typedef union {
struct {
uint32_t reserved_0:3;
/** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0;
* The clear bit for spi_mem_c_SLV_ST_END_INT interrupt.
* The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
*/
uint32_t mem_slv_st_end_int_clr:1;
/** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0;
* The clear bit for spi_mem_c_MST_ST_END_INT interrupt.
* The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
*/
uint32_t mem_mst_st_end_int_clr:1;
/** mem_ecc_err_int_clr : WT; bitpos: [5]; default: 0;
* The clear bit for spi_mem_c_ECC_ERR_INT interrupt.
* The clear bit for SPI_MEM_ECC_ERR_INT interrupt.
*/
uint32_t mem_ecc_err_int_clr:1;
/** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0;
* The clear bit for spi_mem_c_PMS_REJECT_INT interrupt.
* The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.
*/
uint32_t mem_pms_reject_int_clr:1;
/** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0;
* The clear bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt.
* The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
*/
uint32_t mem_axi_raddr_err_int_clr:1;
/** mem_axi_wr_flash_err_int_clr : WT; bitpos: [8]; default: 0;
* The clear bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt.
* The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
*/
uint32_t mem_axi_wr_flash_err_int_clr:1;
/** mem_axi_waddr_err_int_clr : WT; bitpos: [9]; default: 0;
* The clear bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt.
* The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
*/
uint32_t mem_axi_waddr_err_int_clr:1;
uint32_t reserved_10:18;
/** mem_dqs0_afifo_ovf_int_clr : WT; bitpos: [28]; default: 0;
* The clear bit for spi_mem_c_DQS0_AFIFO_OVF_INT interrupt.
* The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.
*/
uint32_t mem_dqs0_afifo_ovf_int_clr:1;
/** mem_dqs1_afifo_ovf_int_clr : WT; bitpos: [29]; default: 0;
* The clear bit for spi_mem_c_DQS1_AFIFO_OVF_INT interrupt.
* The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.
*/
uint32_t mem_dqs1_afifo_ovf_int_clr:1;
/** mem_bus_fifo1_udf_int_clr : WT; bitpos: [30]; default: 0;
* The clear bit for spi_mem_c_BUS_FIFO1_UDF_INT interrupt.
* The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.
*/
uint32_t mem_bus_fifo1_udf_int_clr:1;
/** mem_bus_fifo0_udf_int_clr : WT; bitpos: [31]; default: 0;
* The clear bit for spi_mem_c_BUS_FIFO0_UDF_INT interrupt.
* The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.
*/
uint32_t mem_bus_fifo0_udf_int_clr:1;
};
@@ -1173,67 +1172,67 @@ typedef union {
struct {
uint32_t reserved_0:3;
/** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* The raw bit for spi_mem_c_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is
* The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is
* changed from non idle state to idle state. It means that SPI_CS raises high. 0:
* Others
*/
uint32_t mem_slv_st_end_int_raw:1;
/** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* The raw bit for spi_mem_c_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is
* The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is
* changed from non idle state to idle state. 0: Others.
*/
uint32_t mem_mst_st_end_int_raw:1;
/** mem_ecc_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* The raw bit for spi_mem_c_ECC_ERR_INT interrupt. When spi_fmem_c_ECC_ERR_INT_EN is set
* and spi_smem_c_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times
* of SPI0/1 ECC read flash are equal or bigger than spi_mem_c_ECC_ERR_INT_NUM. When
* spi_fmem_c_ECC_ERR_INT_EN is cleared and spi_smem_c_ECC_ERR_INT_EN is set, this bit is
* The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set
* and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times
* of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When
* SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is
* triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger
* than spi_mem_c_ECC_ERR_INT_NUM. When spi_fmem_c_ECC_ERR_INT_EN and
* spi_smem_c_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
* than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and
* SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
* of SPI0/1 ECC read external RAM and flash are equal or bigger than
* spi_mem_c_ECC_ERR_INT_NUM. When spi_fmem_c_ECC_ERR_INT_EN and spi_smem_c_ECC_ERR_INT_EN
* SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN
* are cleared, this bit will not be triggered.
*/
uint32_t mem_ecc_err_int_raw:1;
/** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
* The raw bit for spi_mem_c_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is
* The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is
* rejected. 0: Others.
*/
uint32_t mem_pms_reject_int_raw:1;
/** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
* The raw bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
* The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
* address is invalid by compared to MMU configuration. 0: Others.
*/
uint32_t mem_axi_raddr_err_int_raw:1;
/** mem_axi_wr_flash_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
* The raw bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write
* The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write
* flash request is received. 0: Others.
*/
uint32_t mem_axi_wr_flash_err_int_raw:1;
/** mem_axi_waddr_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
* The raw bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
* The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
* address is invalid by compared to MMU configuration. 0: Others.
*/
uint32_t mem_axi_waddr_err_int_raw:1;
uint32_t reserved_10:18;
/** mem_dqs0_afifo_ovf_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
* The raw bit for spi_mem_c_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO
* The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO
* connected to SPI_DQS1 is overflow.
*/
uint32_t mem_dqs0_afifo_ovf_int_raw:1;
/** mem_dqs1_afifo_ovf_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
* The raw bit for spi_mem_c_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO
* The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO
* connected to SPI_DQS is overflow.
*/
uint32_t mem_dqs1_afifo_ovf_int_raw:1;
/** mem_bus_fifo1_udf_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* The raw bit for spi_mem_c_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is
* The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is
* underflow.
*/
uint32_t mem_bus_fifo1_udf_int_raw:1;
/** mem_bus_fifo0_udf_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* The raw bit for spi_mem_c_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is
* The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is
* underflow.
*/
uint32_t mem_bus_fifo0_udf_int_raw:1;
@@ -1248,48 +1247,48 @@ typedef union {
struct {
uint32_t reserved_0:3;
/** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0;
* The status bit for spi_mem_c_SLV_ST_END_INT interrupt.
* The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
*/
uint32_t mem_slv_st_end_int_st:1;
/** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0;
* The status bit for spi_mem_c_MST_ST_END_INT interrupt.
* The status bit for SPI_MEM_MST_ST_END_INT interrupt.
*/
uint32_t mem_mst_st_end_int_st:1;
/** mem_ecc_err_int_st : RO; bitpos: [5]; default: 0;
* The status bit for spi_mem_c_ECC_ERR_INT interrupt.
* The status bit for SPI_MEM_ECC_ERR_INT interrupt.
*/
uint32_t mem_ecc_err_int_st:1;
/** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0;
* The status bit for spi_mem_c_PMS_REJECT_INT interrupt.
* The status bit for SPI_MEM_PMS_REJECT_INT interrupt.
*/
uint32_t mem_pms_reject_int_st:1;
/** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0;
* The enable bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt.
* The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
*/
uint32_t mem_axi_raddr_err_int_st:1;
/** mem_axi_wr_flash_err_int_st : RO; bitpos: [8]; default: 0;
* The enable bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt.
* The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
*/
uint32_t mem_axi_wr_flash_err_int_st:1;
/** mem_axi_waddr_err_int_st : RO; bitpos: [9]; default: 0;
* The enable bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt.
* The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
*/
uint32_t mem_axi_waddr_err_int_st:1;
uint32_t reserved_10:18;
/** mem_dqs0_afifo_ovf_int_st : RO; bitpos: [28]; default: 0;
* The status bit for spi_mem_c_DQS0_AFIFO_OVF_INT interrupt.
* The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.
*/
uint32_t mem_dqs0_afifo_ovf_int_st:1;
/** mem_dqs1_afifo_ovf_int_st : RO; bitpos: [29]; default: 0;
* The status bit for spi_mem_c_DQS1_AFIFO_OVF_INT interrupt.
* The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.
*/
uint32_t mem_dqs1_afifo_ovf_int_st:1;
/** mem_bus_fifo1_udf_int_st : RO; bitpos: [30]; default: 0;
* The status bit for spi_mem_c_BUS_FIFO1_UDF_INT interrupt.
* The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.
*/
uint32_t mem_bus_fifo1_udf_int_st:1;
/** mem_bus_fifo0_udf_int_st : RO; bitpos: [31]; default: 0;
* The status bit for spi_mem_c_BUS_FIFO0_UDF_INT interrupt.
* The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.
*/
uint32_t mem_bus_fifo0_udf_int_st:1;
};
@@ -1313,8 +1312,8 @@ typedef union {
uint32_t fmem_pmsn_wr_attr:1;
/** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0;
* SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
* section n is configured by registers spi_fmem_c_PMSn_ADDR_REG and
* spi_fmem_c_PMSn_SIZE_REG.
* section n is configured by registers SPI_FMEM_PMSn_ADDR_REG and
* SPI_FMEM_PMSn_SIZE_REG.
*/
uint32_t fmem_pmsn_ecc:1;
uint32_t reserved_3:29;
@@ -1342,8 +1341,8 @@ typedef union {
typedef union {
struct {
/** fmem_pmsn_size : R/W; bitpos: [16:0]; default: 4096;
* SPI1 flash PMS section n address region is (spi_fmem_c_PMSn_ADDR_S,
* spi_fmem_c_PMSn_ADDR_S + spi_fmem_c_PMSn_SIZE)
* SPI1 flash PMS section n address region is (SPI_FMEM_PMSn_ADDR_S,
* SPI_FMEM_PMSn_ADDR_S + SPI_FMEM_PMSn_SIZE)
*/
uint32_t fmem_pmsn_size:17;
uint32_t reserved_17:15;
@@ -1366,8 +1365,8 @@ typedef union {
uint32_t smem_pmsn_wr_attr:1;
/** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0;
* SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The
* external RAM PMS section n is configured by registers spi_smem_c_PMSn_ADDR_REG and
* spi_smem_c_PMSn_SIZE_REG.
* external RAM PMS section n is configured by registers SPI_SMEM_PMSn_ADDR_REG and
* SPI_SMEM_PMSn_SIZE_REG.
*/
uint32_t smem_pmsn_ecc:1;
uint32_t reserved_3:29;
@@ -1395,8 +1394,8 @@ typedef union {
typedef union {
struct {
/** smem_pmsn_size : R/W; bitpos: [16:0]; default: 4096;
* SPI1 external RAM PMS section n address region is (spi_smem_c_PMSn_ADDR_S,
* spi_smem_c_PMSn_ADDR_S + spi_smem_c_PMSn_SIZE)
* SPI1 external RAM PMS section n address region is (SPI_SMEM_PMSn_ADDR_S,
* SPI_SMEM_PMSn_ADDR_S + SPI_SMEM_PMSn_SIZE)
*/
uint32_t smem_pmsn_size:17;
uint32_t reserved_17:15;
@@ -1416,22 +1415,22 @@ typedef union {
uint32_t mem_pm_en:1;
/** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0;
* 1: SPI1 write access error. 0: No write access error. It is cleared by when
* spi_mem_c_PMS_REJECT_INT_CLR bit is set.
* SPI_MEM_PMS_REJECT_INT_CLR bit is set.
*/
uint32_t mem_pms_ld:1;
/** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0;
* 1: SPI1 read access error. 0: No read access error. It is cleared by when
* spi_mem_c_PMS_REJECT_INT_CLR bit is set.
* SPI_MEM_PMS_REJECT_INT_CLR bit is set.
*/
uint32_t mem_pms_st:1;
/** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0;
* 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is
* cleared by when spi_mem_c_PMS_REJECT_INT_CLR bit is set.
* cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set.
*/
uint32_t mem_pms_multi_hit:1;
/** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0;
* 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
* error. It is cleared by when spi_mem_c_PMS_REJECT_INT_CLR bit is set.
* error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set.
*/
uint32_t mem_pms_ivd:1;
};
@@ -1445,7 +1444,7 @@ typedef union {
struct {
/** mem_reject_addr : R/SS/WTC; bitpos: [28:0]; default: 0;
* This bits show the first SPI1 access error address. It is cleared by when
* spi_mem_c_PMS_REJECT_INT_CLR bit is set.
* SPI_MEM_PMS_REJECT_INT_CLR bit is set.
*/
uint32_t mem_reject_addr:29;
uint32_t reserved_29:3;
@@ -1463,11 +1462,11 @@ typedef union {
uint32_t reserved_0:5;
/** mem_ecc_err_cnt : R/SS/WTC; bitpos: [10:5]; default: 0;
* This bits show the error times of MSPI ECC read. It is cleared by when
* spi_mem_c_ECC_ERR_INT_CLR bit is set.
* SPI_MEM_ECC_ERR_INT_CLR bit is set.
*/
uint32_t mem_ecc_err_cnt:6;
/** fmem_ecc_err_int_num : R/W; bitpos: [16:11]; default: 10;
* Set the error times of MSPI ECC read to generate MSPI spi_mem_c_ECC_ERR_INT interrupt.
* Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.
*/
uint32_t fmem_ecc_err_int_num:6;
/** fmem_ecc_err_int_en : R/W; bitpos: [17]; default: 0;
@@ -1492,9 +1491,9 @@ typedef union {
uint32_t mem_usr_ecc_addr_en:1;
uint32_t reserved_23:1;
/** mem_ecc_continue_record_err_en : R/W; bitpos: [24]; default: 1;
* 1: The error information in spi_mem_c_ECC_ERR_BITS and spi_mem_c_ECC_ERR_ADDR is
* updated when there is an ECC error. 0: spi_mem_c_ECC_ERR_BITS and
* spi_mem_c_ECC_ERR_ADDR record the first ECC error information.
* 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is
* updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and
* SPI_MEM_ECC_ERR_ADDR record the first ECC error information.
*/
uint32_t mem_ecc_continue_record_err_en:1;
/** mem_ecc_err_bits : R/SS/WTC; bitpos: [31:25]; default: 0;
@@ -1513,7 +1512,7 @@ typedef union {
struct {
/** mem_ecc_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0;
* This bits show the first MSPI ECC error address. It is cleared by when
* spi_mem_c_ECC_ERR_INT_CLR bit is set.
* SPI_MEM_ECC_ERR_INT_CLR bit is set.
*/
uint32_t mem_ecc_err_addr:29;
uint32_t reserved_29:3;
@@ -1895,17 +1894,27 @@ typedef union {
*/
uint32_t smem_dll_timing_cali:1;
uint32_t reserved_6:1;
/** smem_dqs0_270_sel : R/W; bitpos: [8:7]; default: 1;
/** smem_dqs0_270_sel : HRO; bitpos: [8:7]; default: 1;
* Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust.
* 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns.
*/
uint32_t smem_dqs0_270_sel:2;
/** smem_dqs0_90_sel : R/W; bitpos: [10:9]; default: 1;
/** smem_dqs0_90_sel : HRO; bitpos: [10:9]; default: 1;
* Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns,
* 2'd2: 1.5ns 2'd3: 2.0ns.
*/
uint32_t smem_dqs0_90_sel:2;
uint32_t reserved_11:21;
/** smem_dqs1_270_sel : HRO; bitpos: [12:11]; default: 1;
* Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust.
* 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns.
*/
uint32_t smem_dqs1_270_sel:2;
/** smem_dqs1_90_sel : HRO; bitpos: [14:13]; default: 1;
* Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns,
* 2'd2: 1.5ns 2'd3: 2.0ns.
*/
uint32_t smem_dqs1_90_sel:2;
uint32_t reserved_15:17;
};
uint32_t val;
} spi_smem_c_timing_cali_reg_t;
@@ -2330,8 +2339,8 @@ typedef union {
*/
uint32_t mem_nand_flash_seq_hd_index:15;
/** mem_nand_flash_seq_usr_trig : HRO; bitpos: [16]; default: 0;
* NAND FLASH spi seq user trigger configure register. spi_mem_c_NAND_FLASH_SEQ_USR_TRIG
* is corresponds to spi_mem_c_NAND_FLASH_SEQ_HD_INDEX[14:10].1: enable 0: disable.
* NAND FLASH spi seq user trigger configure register. SPI_MEM_NAND_FLASH_SEQ_USR_TRIG
* is corresponds to SPI_MEM_NAND_FLASH_SEQ_HD_INDEX[14:10].1: enable 0: disable.
*/
uint32_t mem_nand_flash_seq_usr_trig:1;
/** mem_nand_flash_lut_en : HRO; bitpos: [17]; default: 0;
@@ -2339,7 +2348,7 @@ typedef union {
*/
uint32_t mem_nand_flash_lut_en:1;
/** mem_nand_flash_seq_usr_wend : HRO; bitpos: [18]; default: 0;
* Used with spi_mem_c_NAND_FLASH_SEQ_USR_TRIG to indicate the last page program ,and to
* Used with SPI_MEM_NAND_FLASH_SEQ_USR_TRIG to indicate the last page program ,and to
* execute page execute. 1: write end 0: write in a page size.
*/
uint32_t mem_nand_flash_seq_usr_wend:1;
@@ -2384,22 +2393,22 @@ typedef union {
struct {
/** mem_nand_flash_sr_din0 : RO; bitpos: [7:0]; default: 0;
* spi read state register data to this register for SPI SEQ need.
* spi_mem_c_NAND_FLASH_SR_DIN0_REG corresponds to spi_mem_c_NAND_FLASH_SR_ADDR0_REG.
* SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG.
*/
uint32_t mem_nand_flash_sr_din0:8;
/** mem_nand_flash_sr_din1 : RO; bitpos: [15:8]; default: 0;
* spi read state register data to this register for SPI SEQ need.
* spi_mem_c_NAND_FLASH_SR_DIN0_REG corresponds to spi_mem_c_NAND_FLASH_SR_ADDR0_REG.
* SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG.
*/
uint32_t mem_nand_flash_sr_din1:8;
/** mem_nand_flash_sr_din2 : RO; bitpos: [23:16]; default: 0;
* spi read state register data to this register for SPI SEQ need.
* spi_mem_c_NAND_FLASH_SR_DIN0_REG corresponds to spi_mem_c_NAND_FLASH_SR_ADDR0_REG.
* SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG.
*/
uint32_t mem_nand_flash_sr_din2:8;
/** mem_nand_flash_sr_din3 : RO; bitpos: [31:24]; default: 0;
* spi read state register data to this register for SPI SEQ need.
* spi_mem_c_NAND_FLASH_SR_DIN0_REG corresponds to spi_mem_c_NAND_FLASH_SR_ADDR0_REG.
* SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG.
*/
uint32_t mem_nand_flash_sr_din3:8;
};
@@ -2492,7 +2501,7 @@ typedef union {
/** mem_nand_flash_lut_bus_en0 : HRO; bitpos: [30]; default: 0;
* MSPI NAND FLASH config spi_bus_en at cmd lut address 0,SPI could use DUAL/QUAD mode
* while enable, SPI could use SINGLE mode while disable.1:Enable. 0:Disable.(Note
* these registers are described to indicate the spi_mem_c_NAND_FLASH_CMD_LUT0_REG's
* these registers are described to indicate the SPI_MEM_NAND_FLASH_CMD_LUT0_REG's
* field. The number of CMD LUT entries can be defined by the user, but cannot exceed
* 16 )
*/
@@ -2518,12 +2527,12 @@ typedef union {
uint32_t mem_nand_flash_sr_chk_en0:1;
/** mem_nand_flash_din_index0 : HRO; bitpos: [5:2]; default: 0;
* MSPI NAND FLASH config din_index at spi seq index 0. Use with
* spi_mem_c_NAND_FLASH_CFG_DATA
* SPI_MEM_NAND_FLASH_CFG_DATA
*/
uint32_t mem_nand_flash_din_index0:4;
/** mem_nand_flash_addr_index0 : HRO; bitpos: [9:6]; default: 0;
* MSPI NAND FLASH config addr_index at spi seq index 0. Use with
* spi_mem_c_NAND_FLASH_SR_ADDR
* SPI_MEM_NAND_FLASH_SR_ADDR
*/
uint32_t mem_nand_flash_addr_index0:4;
/** mem_nand_flash_req_or_cfg0 : HRO; bitpos: [10]; default: 0;
@@ -2534,7 +2543,7 @@ typedef union {
/** mem_nand_flash_cmd_index0 : HRO; bitpos: [14:11]; default: 0;
* MSPI NAND FLASH config spi_cmd_index at spi seq index 0. Use to find SPI command in
* CMD LUT.(Note these registers are described to indicate the
* spi_mem_c_NAND_FLASH_SPI_SEQ_REG' fieldd The number of CMD LUT entries can be defined
* SPI_MEM_NAND_FLASH_SPI_SEQ_REG' fieldd The number of CMD LUT entries can be defined
* by the user, but cannot exceed 16 )
*/
uint32_t mem_nand_flash_cmd_index0:4;
@@ -2730,16 +2739,16 @@ typedef union {
* Set this bit to enable mmu-memory clock force on
*/
uint32_t mmu_mem_force_on:1;
/** mmu_mem_force_pd : R/W; bitpos: [1]; default: 1;
/** mmu_mem_force_pd : R/W; bitpos: [1]; default: 0;
* Set this bit to force mmu-memory powerdown
*/
uint32_t mmu_mem_force_pd:1;
/** mmu_mem_force_pu : R/W; bitpos: [2]; default: 0;
/** mmu_mem_force_pu : R/W; bitpos: [2]; default: 1;
* Set this bit to force mmu-memory powerup, in this case, the power should also be
* controlled by rtc.
*/
uint32_t mmu_mem_force_pu:1;
/** mmu_page_size : HRO; bitpos: [4:3]; default: 0;
/** mmu_page_size : R/W; bitpos: [4:3]; default: 0;
* 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8
*/
uint32_t mmu_page_size:2;
@@ -2859,7 +2868,7 @@ typedef union {
*/
typedef union {
struct {
/** mem_date : R/W; bitpos: [27:0]; default: 36774400;
/** mem_date : R/W; bitpos: [27:0]; default: 37822512;
* SPI0 register version.
*/
uint32_t mem_date:28;

2982
components/soc/esp32c5/register/soc/spi_mem_c_struct_eco2.h
View File

File diff suppressed because it is too large Load Diff

4
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
View File

@@ -807,6 +807,10 @@ config SOC_SPI_MEM_SUPPORT_WRAP
bool
default y
config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
bool
default y
config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
bool
default y

1
components/soc/esp32c61/include/soc/soc_caps.h
View File

@@ -344,6 +344,7 @@
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
#define SOC_SPI_MEM_SUPPORT_WRAP (1)
#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1)
#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1

12
components/spi_flash/Kconfig
View File

@@ -109,6 +109,18 @@ menu "Main Flash configuration"
This config is used for setting Tsus parameter. Tsus means CS# high to next command after
suspend. You can refer to the chapter of AC CHARACTERISTICS of flash datasheet.
config SPI_FLASH_SUSPEND_TRS_VAL_US
int "SPI flash tRS value (refer to chapter AC CHARACTERISTICS)"
default 50
range 20 200
depends on SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
help
This config is used for setting Trs parameter. Trs means CS Latency Between Resume And Next Suspend.
You can refer to the chapter of AC CHARACTERISTICS of flash datasheet.
For high-performance scenarios, some flash chips allow this set value to be smaller than the
given value in the datasheet without causing errors in the flash state machine.
When you have any related needs, please contact espressif business team.
config SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND
bool "Enable XMC-C series flash chip suspend feature anyway"
default n

15
components/spi_flash/esp_flash_spi_init.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -129,6 +129,9 @@ esp_flash_t *esp_flash_default_chip = NULL;
.cs_setup = 1,\
}
#define TSUS_VAL_SUSPEND CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US
#if SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
#define TRS_VAL_SUSPEND CONFIG_SPI_FLASH_SUSPEND_TRS_VAL_US
#endif // SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
#endif //!CONFIG_SPI_FLASH_AUTO_SUSPEND
#endif // Other target
@@ -396,6 +399,16 @@ esp_err_t esp_flash_init_default_chip(void)
return ESP_ERR_INVALID_ARG;
}
cfg.tsus_val = TSUS_VAL_SUSPEND;
#if SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
if (TRS_VAL_SUSPEND > 400 || TRS_VAL_SUSPEND < 20) {
// Assume that the TRS value cannot larger than 400 (because the performance might be really bad)
// And value cannot smaller than 20 (never see that small tsus value, might be wrong)
return ESP_ERR_INVALID_ARG;
}
cfg.trs_val = TRS_VAL_SUSPEND;
#endif // SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
#endif // CONFIG_SPI_FLASH_AUTO_SUSPEND
#if CONFIG_SPI_FLASH_AUTO_CHECK_SUSPEND_STATUS