mirror of
https://github.com/espressif/esp-idf.git
synced 2025-07-30 02:37:19 +02:00
Merge branch 'feat/sd_host_ng' into 'master'
sd: driver NG for host layer, supported SDR104 (200 MHz) speed mode Closes IDF-10545 and IDF-10547 See merge request espressif/esp-idf!37378
This commit is contained in:
Armando (Dou Yiwen)
13
components/esp_driver_sd_intf/CMakeLists.txt
Normal file
13
components/esp_driver_sd_intf/CMakeLists.txt
Normal file
@ -0,0 +1,13 @@
|
||||
idf_build_get_property(target IDF_TARGET)
|
||||
|
||||
if(${target} STREQUAL "linux")
|
||||
return() # This component is not supported by the POSIX/Linux simulator
|
||||
endif()
|
||||
|
||||
set(srcs "sd_host.c")
|
||||
|
||||
set(public_include "include")
|
||||
|
||||
idf_component_register(SRCS ${srcs}
|
||||
INCLUDE_DIRS ${public_include}
|
||||
PRIV_REQUIRES sdmmc)
|
||||
3
components/esp_driver_sd_intf/README.md
Normal file
3
components/esp_driver_sd_intf/README.md
Normal file
@ -0,0 +1,3 @@
|
||||
# SD Host Driver Interface Layer
|
||||
|
||||
This component provides the SD Host driver APIs.
|
||||
133
components/esp_driver_sd_intf/include/driver/sd_host.h
Normal file
133
components/esp_driver_sd_intf/include/driver/sd_host.h
Normal file
@ -0,0 +1,133 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "esp_err.h"
|
||||
#include "soc/gpio_num.h"
|
||||
#include "driver/sd_types.h"
|
||||
#include "sd_protocol_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Configure SD Host slot
|
||||
*
|
||||
* @param[in] slot SD Host slot handle
|
||||
* @param[in] config SD Host slot configuration
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument
|
||||
*/
|
||||
esp_err_t sd_host_slot_configure(sd_host_slot_handle_t slot, const sd_host_slot_cfg_t *config);
|
||||
|
||||
/**
|
||||
* @brief Do a transaction for the slot
|
||||
*
|
||||
* @param[in] slot SD Host slot handle
|
||||
* @param[in] cmdinfo SD command info, see `sdmmc_command_t`
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument
|
||||
*/
|
||||
esp_err_t sd_host_slot_do_transaction(sd_host_slot_handle_t slot, sdmmc_command_t *cmdinfo);
|
||||
|
||||
/**
|
||||
* @brief Register SD event callbacks
|
||||
*
|
||||
* @note User can deregister a previously registered callback by calling this function and setting the to-be-deregistered callback member in
|
||||
* the `cbs` structure to NULL.
|
||||
*
|
||||
* @param[in] slot SD Host slot handle
|
||||
* @param[in] cbs Group of callback functions
|
||||
* @param[in] user_data User data, which will be delivered to the callback functions directly
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid arguments
|
||||
* - ESP_ERR_INVALID_STATE: Driver state is invalid, you shouldn't call this API at this moment
|
||||
*/
|
||||
esp_err_t sd_host_slot_register_event_callbacks(sd_host_slot_handle_t slot, const sd_host_evt_cbs_t *cbs, void *user_data);
|
||||
|
||||
/**
|
||||
* @brief Remove an SD Host slot
|
||||
*
|
||||
* @param[in] slot SD Host slot handle
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_STATE: Invalid state, slot is not available
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument
|
||||
*/
|
||||
esp_err_t sd_host_remove_slot(sd_host_slot_handle_t slot);
|
||||
|
||||
/**
|
||||
* @brief Set an SD Host slot clock always on
|
||||
*
|
||||
* @param[in] slot SD Host slot handle
|
||||
* @param[in] always_on Always on or not
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument
|
||||
*/
|
||||
esp_err_t sd_host_slot_set_cclk_always_on(sd_host_slot_handle_t slot, bool always_on);
|
||||
|
||||
/**
|
||||
* @brief Enable an SD Host slot IO interrupt
|
||||
*
|
||||
* @param[in] slot SD Host slot handle
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument
|
||||
*/
|
||||
esp_err_t sd_host_slot_enable_io_int(sd_host_slot_handle_t slot);
|
||||
|
||||
/**
|
||||
* @brief Wait for IO interrupt event
|
||||
*
|
||||
* @param[in] slot SD Host slot handle
|
||||
* @param[in] timeout_ticks Timeout ticks
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument
|
||||
* - ESP_ERR_TIMEOUT: Timeout
|
||||
*/
|
||||
esp_err_t sd_host_slot_wait_io_int(sd_host_slot_handle_t slot, TickType_t timeout_ticks);
|
||||
|
||||
/**
|
||||
* @brief Get slot info
|
||||
*
|
||||
* @param[in] slot SD Host slot handle
|
||||
* @param[out] info SD slot info
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument
|
||||
*/
|
||||
esp_err_t sd_host_slot_get_info(sd_host_slot_handle_t slot, sd_host_slot_info_t *info);
|
||||
|
||||
/**
|
||||
* @brief Delete an SD Host controller
|
||||
*
|
||||
* @param[in] ctlr SD Host controller handle
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument
|
||||
* - ESP_ERR_INVALID_STATE: Invalid state, there's still registered slot(s)
|
||||
*/
|
||||
esp_err_t sd_host_del_controller(sd_host_ctlr_handle_t ctlr);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
80
components/esp_driver_sd_intf/include/driver/sd_types.h
Normal file
80
components/esp_driver_sd_intf/include/driver/sd_types.h
Normal file
@ -0,0 +1,80 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "esp_err.h"
|
||||
#include "hal/sd_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SD Host controller handle
|
||||
*/
|
||||
typedef struct sd_host_driver_t *sd_host_ctlr_handle_t;
|
||||
|
||||
/**
|
||||
* @brief SD Host slot handle
|
||||
*/
|
||||
typedef struct sd_slot_driver_t *sd_host_slot_handle_t;
|
||||
|
||||
/**
|
||||
* @brief SD Host slot configuration
|
||||
*/
|
||||
typedef struct {
|
||||
int freq_hz; ///< Frequency in Hz
|
||||
sd_bus_width_t width; ///< Bus width
|
||||
sd_sampling_mode_t sampling_mode; ///< Sampling mode, see `sd_sampling_mode_t`
|
||||
sdmmc_delay_phase_t delayphase; ///< Delay phase, see `sdmmc_delay_phase_t`
|
||||
sdmmc_delay_line_t delayline; ///< Delay line, see `sdmmc_delay_line_t`
|
||||
} sd_host_slot_cfg_t;
|
||||
|
||||
/**
|
||||
* @brief Slot info
|
||||
*/
|
||||
typedef struct {
|
||||
int freq_hz; ///< Frequency in Hz
|
||||
sd_bus_width_t width; ///< Bus width
|
||||
sd_mode_t sd_mode; ///< SD mode, see `sd_mode_t`
|
||||
sd_sampling_mode_t sampling_mode; ///< Sampling mode, see `sd_sampling_mode_t`
|
||||
} sd_host_slot_info_t;
|
||||
|
||||
/*---------------------------------------------
|
||||
Event Callbacks
|
||||
----------------------------------------------*/
|
||||
/**
|
||||
* @brief SD event data structure
|
||||
*/
|
||||
typedef struct {
|
||||
//leave empty for future-proof
|
||||
} sd_host_evt_data_t;
|
||||
|
||||
/**
|
||||
* @brief Prototype of SD event callback
|
||||
*
|
||||
* @param[in] slot Slot handle
|
||||
* @param[in] edata SD event data
|
||||
* @param[in] user_data User registered context, registered when in `esp_isp_register_event_callbacks()`
|
||||
*
|
||||
* @return Whether a high priority task is woken up by this function
|
||||
*/
|
||||
typedef bool (*sd_host_callback_t)(sd_host_slot_handle_t slot, const sd_host_evt_data_t *edata, void *user_data);
|
||||
|
||||
/**
|
||||
* @brief SD event callbacks
|
||||
*/
|
||||
typedef struct {
|
||||
sd_host_callback_t on_trans_done; ///< Event callback, invoked when one transaction done
|
||||
sd_host_callback_t on_io_interrupt; ///< Event callback, invoked when IO interrupts
|
||||
} sd_host_evt_cbs_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -0,0 +1,141 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "esp_err.h"
|
||||
#include "driver/sd_types.h"
|
||||
#include "sd_protocol_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct sd_host_driver_t sd_host_driver_t; /*!< Type of SD driver host context */
|
||||
typedef struct sd_slot_driver_t sd_slot_driver_t; /*!< Type of SD driver slot context */
|
||||
|
||||
/**
|
||||
* @brief SD driver host driver context
|
||||
*/
|
||||
struct sd_host_driver_t {
|
||||
/**
|
||||
* @brief Delete an SD Host controller
|
||||
*
|
||||
* @param[in] ctlr_ctx SD driver host controller context
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument
|
||||
* - ESP_ERR_INVALID_STATE: Invalid state, there's still registered slot(s)
|
||||
*/
|
||||
esp_err_t (*del_ctlr)(sd_host_driver_t *ctlr_ctx);
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief SD driver API definition
|
||||
*/
|
||||
struct sd_slot_driver_t {
|
||||
/**
|
||||
* @brief Configure SD Host slot
|
||||
*
|
||||
* @param[in] slot_drv SD Host slot driver handle
|
||||
* @param[in] config SD Host slot configuration
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument
|
||||
*/
|
||||
esp_err_t (*configure)(sd_slot_driver_t *slot_drv, const sd_host_slot_cfg_t *config);
|
||||
|
||||
/**
|
||||
* @brief Do a transaction for the slot
|
||||
*
|
||||
* @param[in] slot_drv SD Host slot driver handle
|
||||
* @param[in] cmdinfo SD command info, see `sdmmc_command_t`
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument
|
||||
*/
|
||||
esp_err_t (*do_transaction)(sd_slot_driver_t *slot_drv, sdmmc_command_t *cmdinfo);
|
||||
|
||||
/**
|
||||
* @brief Register SD event callbacks
|
||||
*
|
||||
* @note User can deregister a previously registered callback by calling this function and setting the to-be-deregistered callback member in
|
||||
* the `cbs` structure to NULL.
|
||||
*
|
||||
* @param[in] slot_drv SD Host slot driver handle
|
||||
* @param[in] cbs Group of callback functions
|
||||
* @param[in] user_data User data, which will be delivered to the callback functions directly
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid arguments
|
||||
* - ESP_ERR_INVALID_STATE: Driver state is invalid, you shouldn't call this API at this moment
|
||||
*/
|
||||
esp_err_t (*register_cbs)(sd_slot_driver_t *slot_drv, const sd_host_evt_cbs_t *cbs, void *user_data);
|
||||
|
||||
/**
|
||||
* @brief Remove an SD Host slot
|
||||
*
|
||||
* @param[in] slot_drv SD Host slot driver handle
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_STATE: Invalid state, slot is not available
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument
|
||||
*/
|
||||
esp_err_t (*remove_slot)(sd_slot_driver_t *slot_drv);
|
||||
|
||||
/**
|
||||
* @brief Set an SD Host slot clock always on
|
||||
*
|
||||
* @param[in] slot_drv SD Host slot driver handle
|
||||
* @param[in] always_on Always on or not
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument
|
||||
*/
|
||||
esp_err_t (*set_cclk_always_on)(sd_slot_driver_t *slot_drv, bool always_on);
|
||||
|
||||
/**
|
||||
* @brief Enable an SD Host slot IO interrupt
|
||||
*
|
||||
* @param[in] slot_drv SD Host slot driver handle
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument
|
||||
*/
|
||||
esp_err_t (*enable_io_int)(sd_slot_driver_t *slot_drv);
|
||||
|
||||
/**
|
||||
* @brief Wait for IO interrupt event
|
||||
*
|
||||
* @param[in] slot SD Host slot handle
|
||||
* @param[in] timeout_ticks Timeout ticks
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument
|
||||
* - ESP_ERR_TIMEOUT: Timeout
|
||||
*/
|
||||
esp_err_t (*wait_io_int)(sd_slot_driver_t *slot_drv, TickType_t timeout_ticks);
|
||||
|
||||
/**
|
||||
* @brief Get slot info
|
||||
*
|
||||
* @param[in] slot SD Host slot handle
|
||||
* @param[out] info SD slot info
|
||||
*/
|
||||
esp_err_t (*get_info)(sd_slot_driver_t *slot_drv, sd_host_slot_info_t *info);
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
102
components/esp_driver_sd_intf/sd_host.c
Normal file
102
components/esp_driver_sd_intf/sd_host.c
Normal file
@ -0,0 +1,102 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include "esp_types.h"
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_check.h"
|
||||
#include "driver/sd_host.h"
|
||||
#include "esp_private/sd_driver_interface.h"
|
||||
|
||||
static const char *TAG = "SD_HOST";
|
||||
|
||||
#define SD_HOST_ARG_CHECK(arg) do { \
|
||||
if (unlikely(!(arg))) { \
|
||||
ESP_LOGE(TAG, "invalid argument: null pointer"); \
|
||||
return ESP_ERR_INVALID_ARG; \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
#define SD_HOST_FUNC_CHECK(arg) do { \
|
||||
if (unlikely(!(arg))) { \
|
||||
ESP_LOGE(TAG, "controller driver function not supported"); \
|
||||
return ESP_ERR_NOT_SUPPORTED; \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
esp_err_t sd_host_slot_configure(sd_host_slot_handle_t slot, const sd_host_slot_cfg_t *config)
|
||||
{
|
||||
SD_HOST_ARG_CHECK(slot && config);
|
||||
SD_HOST_FUNC_CHECK(slot->configure);
|
||||
|
||||
return slot->configure(slot, config);
|
||||
}
|
||||
|
||||
esp_err_t sd_host_slot_do_transaction(sd_host_slot_handle_t slot, sdmmc_command_t *cmdinfo)
|
||||
{
|
||||
SD_HOST_ARG_CHECK(slot);
|
||||
SD_HOST_FUNC_CHECK(slot->do_transaction);
|
||||
|
||||
return slot->do_transaction(slot, cmdinfo);
|
||||
}
|
||||
|
||||
esp_err_t sd_host_slot_register_event_callbacks(sd_host_slot_handle_t slot, const sd_host_evt_cbs_t *cbs, void *user_data)
|
||||
{
|
||||
SD_HOST_ARG_CHECK(slot);
|
||||
SD_HOST_FUNC_CHECK(slot->register_cbs);
|
||||
|
||||
return slot->register_cbs(slot, cbs, user_data);
|
||||
}
|
||||
|
||||
esp_err_t sd_host_remove_slot(sd_host_slot_handle_t slot)
|
||||
{
|
||||
SD_HOST_ARG_CHECK(slot);
|
||||
SD_HOST_FUNC_CHECK(slot->remove_slot);
|
||||
|
||||
return slot->remove_slot(slot);
|
||||
}
|
||||
|
||||
esp_err_t sd_host_del_controller(sd_host_ctlr_handle_t ctlr)
|
||||
{
|
||||
SD_HOST_ARG_CHECK(ctlr);
|
||||
SD_HOST_FUNC_CHECK(ctlr->del_ctlr);
|
||||
|
||||
return ctlr->del_ctlr(ctlr);
|
||||
}
|
||||
|
||||
esp_err_t sd_host_slot_set_cclk_always_on(sd_host_slot_handle_t slot, bool always_on)
|
||||
{
|
||||
SD_HOST_ARG_CHECK(slot);
|
||||
SD_HOST_FUNC_CHECK(slot->set_cclk_always_on);
|
||||
|
||||
return slot->set_cclk_always_on(slot, always_on);
|
||||
}
|
||||
|
||||
esp_err_t sd_host_slot_enable_io_int(sd_host_slot_handle_t slot)
|
||||
{
|
||||
SD_HOST_ARG_CHECK(slot);
|
||||
SD_HOST_FUNC_CHECK(slot->enable_io_int);
|
||||
|
||||
return slot->enable_io_int(slot);
|
||||
}
|
||||
|
||||
esp_err_t sd_host_slot_wait_io_int(sd_host_slot_handle_t slot, TickType_t timeout_ticks)
|
||||
{
|
||||
SD_HOST_ARG_CHECK(slot);
|
||||
SD_HOST_FUNC_CHECK(slot->wait_io_int);
|
||||
|
||||
return slot->wait_io_int(slot, timeout_ticks);
|
||||
}
|
||||
|
||||
esp_err_t sd_host_slot_get_info(sd_host_slot_handle_t slot, sd_host_slot_info_t *info)
|
||||
{
|
||||
SD_HOST_ARG_CHECK(slot);
|
||||
SD_HOST_FUNC_CHECK(slot->get_info);
|
||||
|
||||
return slot->get_info(slot, info);
|
||||
}
|
||||
@ -105,12 +105,12 @@ def test_sdio_speed_frhost_flow(dut: Tuple[IdfDut, IdfDut], expected_4b_speed: i
|
||||
dut[0].write('"SDIO_SDMMC: test from host (Performance)"')
|
||||
|
||||
dut[0].expect('Probe using SD 4-bit')
|
||||
res = dut[0].expect(r'Throughput: compensated (\d+)')
|
||||
res = dut[0].expect(r'Throughput: compensated (\d+)KB\/s')
|
||||
frhost_speed_4bit = res.group(1).decode('utf8')
|
||||
assert int(frhost_speed_4bit) > expected_4b_speed
|
||||
|
||||
dut[0].expect('Probe using SD 1-bit')
|
||||
res = dut[0].expect(r'Throughput: compensated (\d+)')
|
||||
res = dut[0].expect(r'Throughput: compensated (\d+)KB\/s')
|
||||
frhost_speed_1bit = res.group(1).decode('utf8')
|
||||
assert int(frhost_speed_1bit) > expected_1b_speed
|
||||
|
||||
@ -164,12 +164,12 @@ def test_sdio_speed_tohost_flow(dut: Tuple[IdfDut, IdfDut], expected_4b_speed: i
|
||||
dut[0].write('"SDIO_SDMMC: test to host (Performance)"')
|
||||
|
||||
dut[0].expect('Probe using SD 4-bit')
|
||||
res = dut[0].expect(r'Throughput: compensated (\d+)')
|
||||
res = dut[0].expect(r'Throughput: compensated (\d+)KB\/s')
|
||||
tohost_speed_4bit = res.group(1).decode('utf8')
|
||||
assert int(tohost_speed_4bit) > expected_4b_speed
|
||||
|
||||
dut[0].expect('Probe using SD 1-bit')
|
||||
res = dut[0].expect(r'Throughput: compensated (\d+)')
|
||||
res = dut[0].expect(r'Throughput: compensated (\d+)KB\/s')
|
||||
tohost_speed_1bit = res.group(1).decode('utf8')
|
||||
assert int(tohost_speed_1bit) > expected_1b_speed
|
||||
|
||||
@ -210,7 +210,7 @@ def test_sdio_speed_tohost_esp32_esp32(dut: Tuple[IdfDut, IdfDut]) -> None:
|
||||
)
|
||||
@pytest.mark.parametrize('app_path, target, config', c5_param_default, indirect=True)
|
||||
def test_sdio_speed_tohost_esp32p4_esp32c5(dut: Tuple[IdfDut, IdfDut]) -> None:
|
||||
test_sdio_speed_tohost_flow(dut, 9000, 4000)
|
||||
test_sdio_speed_tohost_flow(dut, 8500, 4000)
|
||||
|
||||
|
||||
# Retention tests
|
||||
|
||||
@ -2,19 +2,21 @@ idf_build_get_property(target IDF_TARGET)
|
||||
|
||||
set(srcs)
|
||||
|
||||
set(public_include "include")
|
||||
set(public_include "include" "legacy/include")
|
||||
|
||||
# SDMMC related source files
|
||||
if(CONFIG_SOC_SDMMC_HOST_SUPPORTED)
|
||||
list(APPEND srcs "src/sdmmc_transaction.c"
|
||||
"src/sdmmc_host.c")
|
||||
list(APPEND srcs "legacy/src/sdmmc_transaction.c"
|
||||
"legacy/src/sdmmc_host.c"
|
||||
"src/sd_host_sdmmc.c"
|
||||
"src/sd_trans_sdmmc.c")
|
||||
endif()
|
||||
|
||||
if(${target} STREQUAL "linux")
|
||||
set(requires "")
|
||||
set(priv_requires esp_timer)
|
||||
else()
|
||||
set(requires sdmmc esp_driver_gpio)
|
||||
set(requires esp_driver_sd_intf sdmmc esp_driver_gpio)
|
||||
set(priv_requires esp_timer esp_pm esp_mm)
|
||||
endif()
|
||||
|
||||
|
||||
12
components/esp_driver_sdmmc/Kconfig
Normal file
12
components/esp_driver_sdmmc/Kconfig
Normal file
@ -0,0 +1,12 @@
|
||||
menu "ESP-Driver: SD Host SDMMC Controller Configurations"
|
||||
|
||||
depends on SOC_SDMMC_HOST_SUPPORTED
|
||||
|
||||
config SD_HOST_SDMMC_ISR_CACHE_SAFE
|
||||
bool "SD Host ISR Cache-Safe"
|
||||
default n
|
||||
help
|
||||
Ensure the SD Host SDMMC driver ISR is Cache-Safe. When enabled,
|
||||
the ISR handler will be available when the cache is disabled.
|
||||
|
||||
endmenu # SD Host Controller Configurations
|
||||
91
components/esp_driver_sdmmc/include/driver/sd_host_sdmmc.h
Normal file
91
components/esp_driver_sdmmc/include/driver/sd_host_sdmmc.h
Normal file
@ -0,0 +1,91 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "esp_err.h"
|
||||
#include "soc/gpio_num.h"
|
||||
#include "driver/sd_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define SD_HOST_SLOT_WIDTH_DEFAULT 0 ///< use the maximum possible width for the slot
|
||||
|
||||
/**
|
||||
* @brief SD Host SDMMC controller configuration
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t event_queue_items; ///< Event queue items. If 0, fallback to default queue item number (4)
|
||||
uint32_t dma_desc_num; ///< Number of DMA descriptor, fallback to default dma descriptor number (4)
|
||||
} sd_host_sdmmc_cfg_t;
|
||||
|
||||
/**
|
||||
* @brief SD Host slot IO configuration
|
||||
*/
|
||||
typedef struct {
|
||||
sd_bus_width_t width; ///< Slot bus width
|
||||
gpio_num_t clk_io; ///< Clock
|
||||
gpio_num_t cmd_io; ///< Command
|
||||
gpio_num_t cd_io; ///< Card detect
|
||||
gpio_num_t wp_io; ///< Write protect
|
||||
gpio_num_t d0_io; ///< Data0
|
||||
gpio_num_t d1_io; ///< Data1
|
||||
gpio_num_t d2_io; ///< Data2
|
||||
gpio_num_t d3_io; ///< Data3
|
||||
gpio_num_t d4_io; ///< Data4
|
||||
gpio_num_t d5_io; ///< Data5
|
||||
gpio_num_t d6_io; ///< Data6
|
||||
gpio_num_t d7_io; ///< Data7
|
||||
} sd_host_sdmmc_slot_io_cfg_t;
|
||||
|
||||
/**
|
||||
* @brief SD Host slot init configuration
|
||||
*/
|
||||
typedef struct {
|
||||
int slot_id; ///< Slot ID
|
||||
sd_mode_t sd_mode; ///< SD mode, see `sd_mode_t`
|
||||
sd_host_sdmmc_slot_io_cfg_t io_config; ///< IO configuration
|
||||
|
||||
struct {
|
||||
uint32_t internal_pullup: 1; ///< Enable internal pullup or not
|
||||
uint32_t wp_active_high: 1; ///< WP signal is active high or not
|
||||
} slot_flags; ///< Slot flags
|
||||
} sd_host_slot_sdmmc_init_cfg_t;
|
||||
|
||||
/**
|
||||
* @brief Create an SDMMC Host controller
|
||||
*
|
||||
* @param[in] config SDMMC Host controller configuration
|
||||
* @param[out] ret_handle Returned SDMMC Host controller handle
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_NO_MEM: Out of memory
|
||||
* - ESP_ERR_NOT_FOUND: Controller not found
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument
|
||||
*/
|
||||
esp_err_t sd_host_create_sdmmc_controller(const sd_host_sdmmc_cfg_t *config, sd_host_ctlr_handle_t *ret_handle);
|
||||
|
||||
/**
|
||||
* @brief Add an SD slot to the SDMMC Host controller
|
||||
*
|
||||
* @param[in] ctlr SD Host controller handle
|
||||
* @param[in] config SD Host slot init configuration
|
||||
* @param[out] ret_handle Returned SD Host slot handle
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_STATE: Invalid state, slot is not available
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument
|
||||
* - ESP_ERR_NO_MEM: Out of memory
|
||||
*/
|
||||
esp_err_t sd_host_sdmmc_controller_add_slot(sd_host_ctlr_handle_t ctlr, const sd_host_slot_sdmmc_init_cfg_t *config, sd_host_slot_handle_t *ret_handle);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -0,0 +1,389 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include <string.h>
|
||||
#include <sys/param.h>
|
||||
#include "esp_log.h"
|
||||
#include "esp_intr_alloc.h"
|
||||
#include "esp_check.h"
|
||||
#include "esp_pm.h"
|
||||
#include "esp_cache.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/semphr.h"
|
||||
#include "driver/sd_host_sdmmc.h"
|
||||
#include "esp_private/sd_driver_interface.h"
|
||||
#include "sd_protocol_defs.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#if SOC_SDMMC_HOST_SUPPORTED
|
||||
#include "hal/sdmmc_hal.h"
|
||||
#include "hal/sd_types.h"
|
||||
#include "hal/sdmmc_ll.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if SOC_SDMMC_HOST_SUPPORTED
|
||||
#if CONFIG_SD_HOST_SDMMC_ISR_CACHE_SAFE
|
||||
#define SD_HOST_SDMMC_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
|
||||
#else
|
||||
#define SD_HOST_SDMMC_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
|
||||
#endif
|
||||
|
||||
#if !SOC_RCC_IS_INDEPENDENT
|
||||
// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
|
||||
#define SD_HOST_SDMMC_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
|
||||
#else
|
||||
#define SD_HOST_SDMMC_RCC_ATOMIC()
|
||||
#endif
|
||||
|
||||
#if SOC_PERIPH_CLK_CTRL_SHARED
|
||||
// Clock source and related clock settings are mixing with other peripherals, so we need to use a critical section
|
||||
#define SD_HOST_SDMMC_CLK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
|
||||
#else
|
||||
#define SD_HOST_SDMMC_CLK_SRC_ATOMIC()
|
||||
#endif
|
||||
|
||||
#define SD_HOST_SDMMC_CLOCK_UPDATE_CMD_TIMEOUT_US (1000 * 1000)
|
||||
#define SD_HOST_SDMMC_START_CMD_TIMEOUT_US (1000 * 1000)
|
||||
#define SD_HOST_SDMMC_RESET_TIMEOUT_US (5000 * 1000)
|
||||
|
||||
/* Number of DMA descriptors used for transfer.
|
||||
* Increasing this value above 4 doesn't improve performance for the usual case
|
||||
* of SD memory cards (most data transfers are multiples of 512 bytes).
|
||||
*/
|
||||
#define SD_HOST_SDMMC_DMA_DESC_CNT 4
|
||||
|
||||
#define GPIO_NUM_CHECK(_gpio_num) \
|
||||
if (!GPIO_IS_VALID_GPIO(_gpio_num)) { \
|
||||
esp_err_t _err = ESP_ERR_INVALID_ARG; \
|
||||
ESP_LOGE(TAG, "%s: Invalid GPIO number %d, returned 0x%x", __func__, _gpio_num, _err); \
|
||||
return _err; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SD Host SDMMC FSM
|
||||
*/
|
||||
typedef enum {
|
||||
SD_HOST_FSM_INIT = 1,
|
||||
SD_HOST_FSM_ENABLED,
|
||||
SD_HOST_FSM_STARTED,
|
||||
} sd_host_sdmmc_fsm_t;
|
||||
|
||||
/**
|
||||
* @brief SD Host SDMMC event type
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t sdmmc_status; ///< masked SDMMC interrupt status
|
||||
uint32_t dma_status; ///< masked DMA interrupt status
|
||||
} sd_host_sdmmc_event_t;
|
||||
|
||||
/**
|
||||
* @brief SD Host SDMMC slot state
|
||||
*/
|
||||
typedef enum sd_host_sdmmc_slot_state_t {
|
||||
SD_HOST_SLOT_STATE_INIT, ///< Slot is only initialised
|
||||
SD_HOST_SLOT_STATE_READY, ///< Slot is ready
|
||||
} sd_host_sdmmc_slot_state_t;
|
||||
|
||||
/**
|
||||
* @brief SD Host SDMMC transaction state
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t* ptr;
|
||||
size_t size_remaining;
|
||||
size_t next_desc;
|
||||
size_t desc_remaining;
|
||||
} sd_host_sdmmc_trans_state_t;
|
||||
|
||||
typedef struct sd_host_sdmmc_slot_t sd_host_sdmmc_slot_t;
|
||||
typedef struct sd_host_sdmmc_ctlr_t sd_host_sdmmc_ctlr_t;
|
||||
|
||||
/**
|
||||
* @brief SD Host SDMMC slot context
|
||||
*/
|
||||
struct sd_host_sdmmc_slot_t {
|
||||
sd_slot_driver_t drv;
|
||||
int slot_id;
|
||||
sd_mode_t sd_mode;
|
||||
sd_host_sdmmc_slot_io_cfg_t io_config;
|
||||
bool use_gpio_matrix;
|
||||
|
||||
struct {
|
||||
int width;
|
||||
sd_host_sdmmc_slot_state_t width_state;
|
||||
} width;
|
||||
struct {
|
||||
int freq_hz;
|
||||
sd_host_sdmmc_slot_state_t freq_state;
|
||||
int real_freq_hz;
|
||||
} freq;
|
||||
struct {
|
||||
sd_sampling_mode_t mode;
|
||||
sd_host_sdmmc_slot_state_t sampling_mode_state;
|
||||
} sampling_mode;
|
||||
struct {
|
||||
sdmmc_delay_phase_t delayphase;
|
||||
sd_host_sdmmc_slot_state_t delay_phase_state;
|
||||
} delay_phase;
|
||||
struct {
|
||||
sdmmc_delay_line_t delayline;
|
||||
sd_host_sdmmc_slot_state_t delay_line_state;
|
||||
} delay_line;
|
||||
|
||||
bool cclk_always_on;
|
||||
soc_periph_sdmmc_clk_src_t clk_src;
|
||||
|
||||
sd_host_sdmmc_ctlr_t *ctlr;
|
||||
sd_host_evt_cbs_t cbs;
|
||||
void *user_data;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief SD Host context
|
||||
*/
|
||||
struct sd_host_sdmmc_ctlr_t {
|
||||
sd_host_driver_t drv; //host driver
|
||||
int host_id; //host id
|
||||
sd_host_sdmmc_slot_t *slot[SOC_SDMMC_NUM_SLOTS]; //slot
|
||||
int registered_slot_nums; //registered slot nums
|
||||
sdmmc_hal_context_t hal; //hal context
|
||||
|
||||
sdmmc_desc_t *dma_desc; //pointer to dma descriptors
|
||||
int dma_desc_num; //number of DMA descriptor
|
||||
sd_host_sdmmc_trans_state_t cur_transfer; //current dma trans
|
||||
int cur_slot_id; //current slot id
|
||||
bool is_app_cmd; //this flag is set if the next command is an APP command
|
||||
|
||||
portMUX_TYPE spinlock; //spinlock
|
||||
SemaphoreHandle_t io_intr_sem; //io interrupt semaphore
|
||||
SemaphoreHandle_t mutex; //mutex
|
||||
QueueHandle_t event_queue; //event queue
|
||||
|
||||
intr_handle_t intr_handle; //interrupt handle
|
||||
sd_host_evt_cbs_t cbs; //user callbacks
|
||||
void *cbs_user_data; //callback userdata
|
||||
esp_pm_lock_handle_t pm_lock; //power management lock
|
||||
};
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Internal APIs (not used by other components)
|
||||
---------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------
|
||||
IO Control
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Do a transaction for the slot
|
||||
*
|
||||
* @param[in] slot SD Host slot handle
|
||||
* @param[in] cmdinfo SD command info, see `sdmmc_command_t`
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument
|
||||
*/
|
||||
esp_err_t sd_host_slot_sdmmc_do_transaction(sd_host_slot_handle_t slot, sdmmc_command_t *cmdinfo);
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
HW Commands
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief HW command for the slot
|
||||
*
|
||||
* @param[in] slot SD Host Slot handle
|
||||
* @param[in] cmd SD HW command
|
||||
* @param[in] arg SD command argument
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid arguments
|
||||
* - ESP_ERR_NOT_FOUND: Command not found
|
||||
*/
|
||||
esp_err_t sd_host_slot_start_command(sd_host_sdmmc_slot_t *slot, sdmmc_hw_cmd_t cmd, uint32_t arg);
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Configuration APIs
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Set clock for the slot
|
||||
*
|
||||
* @param[in] slot SD Host Slot handle
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid arguments
|
||||
* - ESP_ERR_NOT_FOUND: Command not found
|
||||
*/
|
||||
esp_err_t sd_host_slot_set_card_clk(sd_host_sdmmc_slot_t *slot);
|
||||
|
||||
/**
|
||||
* @brief Set bus width for the slot
|
||||
*
|
||||
* @param[in] slot SD Host Slot handle
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid arguments
|
||||
*/
|
||||
esp_err_t sd_host_slot_set_bus_width(sd_host_sdmmc_slot_t *slot);
|
||||
|
||||
/**
|
||||
* @brief Set sampling mode for the slot
|
||||
*
|
||||
* @param[in] slot SD Host Slot handle
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid arguments
|
||||
*/
|
||||
esp_err_t sd_host_slot_set_bus_sampling_mode(sd_host_sdmmc_slot_t *slot);
|
||||
|
||||
/**
|
||||
* @brief Set delay phase for the slot
|
||||
*
|
||||
* @param[in] slot SD Host Slot handle
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid arguments
|
||||
*/
|
||||
esp_err_t sd_host_set_delay_phase(sd_host_sdmmc_slot_t *slot);
|
||||
|
||||
/**
|
||||
* @brief Set delay line for the slot
|
||||
*
|
||||
* @param[in] slot SD Host Slot handle
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid arguments
|
||||
*/
|
||||
esp_err_t sd_host_set_delay_line(sd_host_sdmmc_slot_t *slot);
|
||||
|
||||
/**
|
||||
* @brief Set clock always on for the slot
|
||||
*
|
||||
* @param[in] slot SD Host Slot handle
|
||||
* @param[in] always_on always on or not
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid arguments
|
||||
* - ESP_ERR_NOT_FOUND: Command not found
|
||||
*/
|
||||
esp_err_t sd_host_slot_set_cclk_always_on_internal(sd_host_sdmmc_slot_t *slot, bool always_on);
|
||||
|
||||
/**
|
||||
* @brief Enable clock and cmd11 mode
|
||||
*
|
||||
* @param[in] slot SD Host Slot handle
|
||||
* @param[in] enable enable or not
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid arguments
|
||||
* - ESP_ERR_NOT_FOUND: Command not found
|
||||
*/
|
||||
void sd_host_slot_enable_clk_cmd11(sd_host_sdmmc_slot_t *slot, bool enable);
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
DMA APIs
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Get free descriptor numbers
|
||||
*
|
||||
* @param[in] slot SD Host Slot handle
|
||||
*
|
||||
* @return
|
||||
* Number of free descriptors
|
||||
*/
|
||||
size_t sd_host_get_free_descriptors_count(sd_host_sdmmc_slot_t *slot);
|
||||
|
||||
/**
|
||||
* @brief Fill descriptor
|
||||
*
|
||||
* @param[in] slot SD Host Slot handle
|
||||
* @param[in] num_desc Number of descriptors to fill
|
||||
*/
|
||||
void sd_host_fill_dma_descriptors(sd_host_sdmmc_slot_t *slot, size_t num_desc);
|
||||
|
||||
/**
|
||||
* @brief Stop DMA
|
||||
*
|
||||
* @param[in] slot SD Host Slot handle
|
||||
*/
|
||||
void sd_host_dma_stop(sd_host_sdmmc_slot_t *slot);
|
||||
|
||||
/**
|
||||
* @brief Resume DMA
|
||||
*
|
||||
* @param[in] slot SD Host Slot handle
|
||||
*/
|
||||
void sd_host_dma_resume(sd_host_sdmmc_slot_t *slot);
|
||||
|
||||
/**
|
||||
* @brief Stop DMA
|
||||
*
|
||||
* @param[in] slot SD Host Slot handle
|
||||
* @param[in] data_ptr Pointer to data
|
||||
* @param[in] data_size Size of data
|
||||
* @param[in] block_size Block size
|
||||
*/
|
||||
void sd_host_dma_prepare(sd_host_sdmmc_slot_t *slot, void* data_ptr, size_t data_size, size_t block_size);
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Info APIs
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Check SD buffer alignment
|
||||
*
|
||||
* @param[in] slot SD Host slot handle
|
||||
* @param[in] buf Buffer pointer
|
||||
* @param[in] size Buffer size
|
||||
*
|
||||
* @return
|
||||
* - True: alignment requirement is satisfied
|
||||
* - False: alignment requirement is not satisfied
|
||||
*/
|
||||
bool sd_host_check_buffer_alignment(sd_host_sdmmc_slot_t *slot, const void *buf, size_t size);
|
||||
|
||||
/**
|
||||
* @brief Get SD Host slot real frequency
|
||||
*
|
||||
* @param[in] slot SD Host Slot handle
|
||||
* @param[out] real_freq_khz Real frequency in Hz
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid arguments
|
||||
*/
|
||||
esp_err_t sd_host_slot_get_real_freq(sd_host_sdmmc_slot_t *slot, int *real_freq_khz);
|
||||
|
||||
/**
|
||||
* @brief Get SD Host slot real calculated frequency
|
||||
*
|
||||
* @note This is used to for protocol layer to get frequency
|
||||
* SD Host driver will only make all registers valid when a real
|
||||
* transaction is done (in `sd_host_slot_do_transaction`). Whereas protocol
|
||||
* layer is querying real frequency in quite early stage
|
||||
*
|
||||
* @param[in] slot SD Host Slot handle
|
||||
* @param[out] real_freq_khz Real frequency in Hz
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: On success
|
||||
* - ESP_ERR_INVALID_ARG: Invalid arguments
|
||||
*/
|
||||
esp_err_t sd_host_slot_get_calc_real_freq(sd_host_sdmmc_slot_t *slot, int *real_freq_khz);
|
||||
#endif //#if SOC_SDMMC_HOST_SUPPORTED
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -47,6 +47,7 @@ extern "C" {
|
||||
.get_real_freq = &sdmmc_host_get_real_freq, \
|
||||
.input_delay_phase = SDMMC_DELAY_PHASE_0, \
|
||||
.set_input_delay = &sdmmc_host_set_input_delay, \
|
||||
.set_input_delayline = &sdmmc_host_set_input_delayline, \
|
||||
.dma_aligned_buffer = NULL, \
|
||||
.pwr_ctrl_handle = NULL, \
|
||||
.get_dma_info = NULL, \
|
||||
@ -274,6 +274,23 @@ esp_err_t sdmmc_host_get_real_freq(int slot, int* real_freq_khz);
|
||||
*/
|
||||
esp_err_t sdmmc_host_set_input_delay(int slot, sdmmc_delay_phase_t delay_phase);
|
||||
|
||||
/**
|
||||
* @brief set input delayline
|
||||
*
|
||||
* - This API sets delay when the SDMMC Host samples the signal from the SD Slave.
|
||||
* - This API will check if the given `delay_line` is valid or not.
|
||||
* - This API will print out the delay time, in picosecond (ps)
|
||||
*
|
||||
* @param slot slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1)
|
||||
* @param delay_line delay line, this API will convert the line into picoseconds and print it out
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK: ON success.
|
||||
* - ESP_ERR_INVALID_ARG: Invalid argument.
|
||||
* - ESP_ERR_NOT_SUPPORTED: Some chips don't support this feature.
|
||||
*/
|
||||
esp_err_t sdmmc_host_set_input_delayline(int slot, sdmmc_delay_line_t delay_line);
|
||||
|
||||
/**
|
||||
* @brief Get the DMA memory information for the host driver
|
||||
*
|
||||
268
components/esp_driver_sdmmc/legacy/src/sdmmc_host.c
Normal file
268
components/esp_driver_sdmmc/legacy/src/sdmmc_host.c
Normal file
@ -0,0 +1,268 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include <string.h>
|
||||
#include <sys/param.h>
|
||||
#include "esp_log.h"
|
||||
#include "esp_check.h"
|
||||
#include "driver/sdmmc_host.h"
|
||||
#include "driver/sd_host_sdmmc.h"
|
||||
#include "driver/sd_host.h"
|
||||
#include "sdmmc_internal.h"
|
||||
|
||||
#define SLOT_CHECK(slot_num) \
|
||||
if (slot_num < 0 || slot_num >= SOC_SDMMC_NUM_SLOTS) { \
|
||||
return ESP_ERR_INVALID_ARG; \
|
||||
}
|
||||
|
||||
#define SDMMC_EVENT_QUEUE_LENGTH 32
|
||||
|
||||
static const char *TAG = "sdmmc_periph";
|
||||
static sd_host_ctlr_handle_t s_ctlr = NULL;
|
||||
static sd_host_slot_handle_t s_slot0 = NULL;
|
||||
static sd_host_slot_handle_t s_slot1 = NULL;
|
||||
|
||||
esp_err_t sdmmc_host_set_card_clk(int slot, uint32_t freq_khz)
|
||||
{
|
||||
SLOT_CHECK(slot);
|
||||
|
||||
sd_host_slot_handle_t hdl = sdmmc_get_slot_handle(slot);
|
||||
sd_host_slot_cfg_t cfg = {
|
||||
.freq_hz = freq_khz * 1000,
|
||||
};
|
||||
ESP_RETURN_ON_ERROR(sd_host_slot_configure(hdl, &cfg), TAG, "failed to configure slot freq");
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_host_get_real_freq(int slot, int *real_freq_khz)
|
||||
{
|
||||
SLOT_CHECK(slot);
|
||||
|
||||
sd_host_slot_handle_t hdl = sdmmc_get_slot_handle(slot);
|
||||
sd_host_sdmmc_slot_t *slot_ctx = __containerof(hdl, sd_host_sdmmc_slot_t, drv);
|
||||
ESP_RETURN_ON_ERROR(sd_host_slot_get_calc_real_freq(slot_ctx, real_freq_khz), TAG, "failed to get slot freq");
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_host_set_input_delay(int slot, sdmmc_delay_phase_t delay_phase)
|
||||
{
|
||||
SLOT_CHECK(slot);
|
||||
sd_host_slot_handle_t hdl = sdmmc_get_slot_handle(slot);
|
||||
sd_host_slot_cfg_t cfg = {
|
||||
.delayphase = delay_phase,
|
||||
};
|
||||
ESP_RETURN_ON_ERROR(sd_host_slot_configure(hdl, &cfg), TAG, "failed to configure slot delay phase");
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_host_set_input_delayline(int slot, sdmmc_delay_line_t delay_line)
|
||||
{
|
||||
SLOT_CHECK(slot);
|
||||
sd_host_slot_handle_t hdl = sdmmc_get_slot_handle(slot);
|
||||
sd_host_slot_cfg_t cfg = {
|
||||
.delayline = delay_line,
|
||||
};
|
||||
ESP_RETURN_ON_ERROR(sd_host_slot_configure(hdl, &cfg), TAG, "failed to configure slot delay line");
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_host_init(void)
|
||||
{
|
||||
sd_host_sdmmc_cfg_t cfg = {
|
||||
.event_queue_items = SDMMC_EVENT_QUEUE_LENGTH,
|
||||
};
|
||||
esp_err_t ret = sd_host_create_sdmmc_controller(&cfg, &s_ctlr);
|
||||
ESP_RETURN_ON_ERROR(ret, TAG, "failed to create new SD controller");
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
sd_host_slot_handle_t sdmmc_get_slot_handle(int slot_id)
|
||||
{
|
||||
return slot_id == 0 ? s_slot0 : s_slot1;
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_host_is_slot_set_to_uhs1(int slot, bool *is_uhs1)
|
||||
{
|
||||
SLOT_CHECK(slot);
|
||||
sd_host_slot_handle_t hdl = sdmmc_get_slot_handle(slot);
|
||||
|
||||
sd_host_slot_info_t info = {};
|
||||
ESP_RETURN_ON_ERROR(sd_host_slot_get_info(hdl, &info), TAG, "failed to get slot info");
|
||||
if (info.sd_mode == SD_MODE_UHS1) {
|
||||
*is_uhs1 = true;
|
||||
}
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_host_init_slot(int slot, const sdmmc_slot_config_t *slot_config)
|
||||
{
|
||||
esp_err_t ret = ESP_FAIL;
|
||||
|
||||
bool internal_pullup = (slot_config->flags & SDMMC_SLOT_FLAG_INTERNAL_PULLUP);
|
||||
bool wp_active_high = (slot_config->flags & SDMMC_SLOT_FLAG_WP_ACTIVE_HIGH);
|
||||
sd_host_slot_sdmmc_init_cfg_t cfg = {
|
||||
.slot_id = slot,
|
||||
.sd_mode = (slot_config->flags & SDMMC_SLOT_FLAG_UHS1) ? SD_MODE_UHS1 : SD_MODE_NORMAL,
|
||||
.io_config = {
|
||||
.width = slot_config->width,
|
||||
.clk_io = slot_config->clk,
|
||||
.cmd_io = slot_config->cmd,
|
||||
.cd_io = slot_config->cd,
|
||||
.wp_io = slot_config->wp,
|
||||
.d0_io = slot_config->d0,
|
||||
.d1_io = slot_config->d1,
|
||||
.d2_io = slot_config->d2,
|
||||
.d3_io = slot_config->d3,
|
||||
.d4_io = slot_config->d4,
|
||||
.d5_io = slot_config->d5,
|
||||
.d6_io = slot_config->d6,
|
||||
.d7_io = slot_config->d7,
|
||||
},
|
||||
.slot_flags.internal_pullup = internal_pullup,
|
||||
.slot_flags.wp_active_high = wp_active_high,
|
||||
};
|
||||
if (slot == 0) {
|
||||
ret = sd_host_sdmmc_controller_add_slot(s_ctlr, &cfg, &s_slot0);
|
||||
} else {
|
||||
ret = sd_host_sdmmc_controller_add_slot(s_ctlr, &cfg, &s_slot1);
|
||||
}
|
||||
ESP_RETURN_ON_ERROR(ret, TAG, "failed to add new SD slot");
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_host_deinit_slot(int slot)
|
||||
{
|
||||
esp_err_t ret = ESP_FAIL;
|
||||
sd_host_slot_handle_t hdl = sdmmc_get_slot_handle(slot);
|
||||
ESP_RETURN_ON_ERROR(sd_host_remove_slot(hdl), TAG, "failed to remove slot");
|
||||
|
||||
ret = sd_host_del_controller(s_ctlr);
|
||||
//for backward compatibility, return ESP_OK when only slot is removed and host is still there
|
||||
if (ret == ESP_ERR_INVALID_STATE) {
|
||||
ret = ESP_OK;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_host_deinit(void)
|
||||
{
|
||||
esp_err_t ret = ESP_FAIL;
|
||||
sd_host_slot_handle_t hdl[2] = {s_slot0, s_slot1};
|
||||
for (int i = 0; i < 2; i++) {
|
||||
if (hdl[i]) {
|
||||
ret = sd_host_remove_slot(hdl[i]);
|
||||
ESP_RETURN_ON_ERROR(ret, TAG, "failed to remove slot%d", i);
|
||||
}
|
||||
}
|
||||
ESP_RETURN_ON_ERROR(sd_host_del_controller(s_ctlr), TAG, "failed to delete controller");
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_host_set_bus_width(int slot, size_t width)
|
||||
{
|
||||
SLOT_CHECK(slot);
|
||||
|
||||
sd_host_slot_handle_t hdl = sdmmc_get_slot_handle(slot);
|
||||
sd_host_slot_cfg_t cfg = {
|
||||
.width = width,
|
||||
};
|
||||
ESP_RETURN_ON_ERROR(sd_host_slot_configure(hdl, &cfg), TAG, "failed to configure slot bus width");
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
size_t sdmmc_host_get_slot_width(int slot)
|
||||
{
|
||||
SLOT_CHECK(slot);
|
||||
|
||||
sd_host_slot_handle_t hdl = sdmmc_get_slot_handle(slot);
|
||||
sd_host_slot_info_t info = {};
|
||||
esp_err_t ret = sd_host_slot_get_info(hdl, &info);
|
||||
assert(ret == ESP_OK);
|
||||
|
||||
return info.width;
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_host_set_bus_ddr_mode(int slot, bool ddr_enabled)
|
||||
{
|
||||
sd_host_slot_handle_t hdl = sdmmc_get_slot_handle(slot);
|
||||
sd_host_slot_cfg_t cfg = {
|
||||
.sampling_mode = ddr_enabled ? SD_SAMPLING_MODE_DDR : SD_SAMPLING_MODE_SDR,
|
||||
};
|
||||
ESP_RETURN_ON_ERROR(sd_host_slot_configure(hdl, &cfg), TAG, "failed to configure slot ddr mode");
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_host_set_cclk_always_on(int slot, bool cclk_always_on)
|
||||
{
|
||||
SLOT_CHECK(slot);
|
||||
|
||||
sd_host_slot_handle_t hdl = sdmmc_get_slot_handle(slot);
|
||||
ESP_RETURN_ON_ERROR(sd_host_slot_set_cclk_always_on(hdl, cclk_always_on), TAG, "failed to configure slot cclk always on");
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_host_io_int_enable(int slot)
|
||||
{
|
||||
sd_host_slot_handle_t hdl = sdmmc_get_slot_handle(slot);
|
||||
return sd_host_slot_enable_io_int(hdl);
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_host_io_int_wait(int slot, TickType_t timeout_ticks)
|
||||
{
|
||||
assert(slot == 0 || slot == 1);
|
||||
sd_host_slot_handle_t hdl = sdmmc_get_slot_handle(slot);
|
||||
ESP_RETURN_ON_ERROR(sd_host_slot_wait_io_int(hdl, timeout_ticks), TAG, "failed to wait io interrupt");
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_host_get_dma_info(int slot, esp_dma_mem_info_t *dma_mem_info)
|
||||
{
|
||||
SLOT_CHECK(slot);
|
||||
|
||||
if (dma_mem_info == NULL) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
dma_mem_info->extra_heap_caps = MALLOC_CAP_DMA;
|
||||
dma_mem_info->dma_alignment_bytes = 4;
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
bool sdmmc_host_check_buffer_alignment(int slot, const void *buf, size_t size)
|
||||
{
|
||||
assert(slot == 0 || slot == 1);
|
||||
sd_host_slot_handle_t hdl = sdmmc_get_slot_handle(slot);
|
||||
sd_host_sdmmc_slot_t *slot_ctx = __containerof(hdl, sd_host_sdmmc_slot_t, drv);
|
||||
|
||||
return sd_host_check_buffer_alignment(slot_ctx, buf, size);
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_host_get_state(sdmmc_host_state_t* state)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(state, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
|
||||
if (s_ctlr) {
|
||||
state->host_initialized = true;
|
||||
sd_host_sdmmc_ctlr_t *ctlr_ctx = __containerof(s_ctlr, sd_host_sdmmc_ctlr_t, drv);
|
||||
state->num_of_init_slots = ctlr_ctx->registered_slot_nums;
|
||||
}
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -12,23 +12,13 @@
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/queue.h"
|
||||
#include "soc/sdmmc_periph.h"
|
||||
|
||||
typedef struct {
|
||||
uint32_t sdmmc_status; ///< masked SDMMC interrupt status
|
||||
uint32_t dma_status; ///< masked DMA interrupt status
|
||||
} sdmmc_event_t;
|
||||
|
||||
#define SDMMC_HOST_CLOCK_UPDATE_CMD_TIMEOUT_US 1000 * 1000
|
||||
#define SDMMC_HOST_START_CMD_TIMEOUT_US 1000 * 1000
|
||||
#define SDMMC_HOST_RESET_TIMEOUT_US 5000 * 1000
|
||||
#include "esp_private/sd_host_private.h"
|
||||
|
||||
esp_err_t sdmmc_host_reset(void);
|
||||
|
||||
esp_err_t sdmmc_host_start_command(int slot, sdmmc_hw_cmd_t cmd, uint32_t arg);
|
||||
|
||||
esp_err_t sdmmc_host_wait_for_event(int tick_count, sdmmc_event_t* out_event);
|
||||
|
||||
void sdmmc_host_dma_prepare(void* data_ptr, size_t data_size, size_t block_size);
|
||||
esp_err_t sdmmc_host_wait_for_event(int tick_count, sd_host_sdmmc_event_t* out_event);
|
||||
|
||||
void sdmmc_host_dma_stop(void);
|
||||
|
||||
@ -41,3 +31,6 @@ void sdmmc_host_enable_clk_cmd11(int slot, bool enable);
|
||||
esp_err_t sdmmc_host_transaction_handler_init(void);
|
||||
|
||||
void sdmmc_host_transaction_handler_deinit(void);
|
||||
|
||||
//get slot handle, for legacy driver compatibility
|
||||
sd_host_slot_handle_t sdmmc_get_slot_handle(int slot_id);
|
||||
27
components/esp_driver_sdmmc/legacy/src/sdmmc_transaction.c
Normal file
27
components/esp_driver_sdmmc/legacy/src/sdmmc_transaction.c
Normal file
@ -0,0 +1,27 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <unistd.h>
|
||||
#include "esp_err.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_check.h"
|
||||
#include "driver/sdmmc_types.h"
|
||||
#include "driver/sdmmc_defs.h"
|
||||
#include "driver/sdmmc_host.h"
|
||||
#include "driver/sd_host.h"
|
||||
#include "sdmmc_internal.h"
|
||||
|
||||
static const char* TAG = "sdmmc_req";
|
||||
|
||||
esp_err_t sdmmc_host_do_transaction(int slot, sdmmc_command_t* cmdinfo)
|
||||
{
|
||||
sd_host_slot_handle_t slot_hdl = sdmmc_get_slot_handle(slot);
|
||||
esp_err_t ret = sd_host_slot_do_transaction(slot_hdl, cmdinfo);
|
||||
ESP_RETURN_ON_ERROR(ret, TAG, "failed to do SD transaction");
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
1335
components/esp_driver_sdmmc/src/sd_host_sdmmc.c
Normal file
1335
components/esp_driver_sdmmc/src/sd_host_sdmmc.c
Normal file
File diff suppressed because it is too large
Load Diff
588
components/esp_driver_sdmmc/src/sd_trans_sdmmc.c
Normal file
588
components/esp_driver_sdmmc/src/sd_trans_sdmmc.c
Normal file
@ -0,0 +1,588 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include <string.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/param.h>
|
||||
#include "esp_log.h"
|
||||
#include "esp_intr_alloc.h"
|
||||
#include "esp_check.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "driver/sd_host.h"
|
||||
#include "esp_private/sd_host_private.h"
|
||||
|
||||
typedef enum {
|
||||
SDMMC_IDLE,
|
||||
SDMMC_SENDING_CMD,
|
||||
SDMMC_SENDING_DATA,
|
||||
SDMMC_BUSY,
|
||||
SDMMC_SENDING_VOLTAGE_SWITCH,
|
||||
SDMMC_WAITING_VOLTAGE_SWITCH,
|
||||
} sdmmc_req_state_t;
|
||||
|
||||
static const char *TAG = "SD_TRANS";
|
||||
|
||||
const uint32_t SD_DATA_ERR_MASK =
|
||||
SDMMC_INTMASK_DTO | SDMMC_INTMASK_DCRC |
|
||||
SDMMC_INTMASK_HTO | SDMMC_INTMASK_SBE |
|
||||
SDMMC_INTMASK_EBE;
|
||||
|
||||
const uint32_t SD_DMA_DONE_MASK =
|
||||
SDMMC_IDMAC_INTMASK_RI | SDMMC_IDMAC_INTMASK_TI |
|
||||
SDMMC_IDMAC_INTMASK_NI;
|
||||
|
||||
const uint32_t SD_CMD_ERR_MASK =
|
||||
SDMMC_INTMASK_RTO |
|
||||
SDMMC_INTMASK_RCRC |
|
||||
SDMMC_INTMASK_RESP_ERR;
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Voltage
|
||||
---------------------------------------------------------------*/
|
||||
static void handle_voltage_switch_stage1(sd_host_sdmmc_slot_t *slot, sdmmc_command_t* cmd)
|
||||
{
|
||||
ESP_LOGV(TAG, "%s: enabling clock", __func__);
|
||||
sd_host_slot_set_cclk_always_on_internal(slot, true);
|
||||
}
|
||||
|
||||
static void handle_voltage_switch_stage2(sd_host_sdmmc_slot_t *slot, sdmmc_command_t* cmd)
|
||||
{
|
||||
ESP_LOGV(TAG, "%s: disabling clock", __func__);
|
||||
sd_host_slot_enable_clk_cmd11(slot, false);
|
||||
usleep(100);
|
||||
ESP_LOGV(TAG, "%s: switching voltage", __func__);
|
||||
esp_err_t err = cmd->volt_switch_cb(cmd->volt_switch_cb_arg, 1800);
|
||||
if (err != ESP_OK) {
|
||||
ESP_LOGE(TAG, "failed to switch voltage (0x%x)", err);
|
||||
cmd->error = err;
|
||||
}
|
||||
ESP_LOGV(TAG, "%s: waiting 10ms", __func__);
|
||||
usleep(10000);
|
||||
ESP_LOGV(TAG, "%s: enabling clock", __func__);
|
||||
sd_host_slot_enable_clk_cmd11(slot, true);
|
||||
}
|
||||
|
||||
static void handle_voltage_switch_stage3(sd_host_sdmmc_slot_t *slot, sdmmc_command_t* cmd)
|
||||
{
|
||||
ESP_LOGV(TAG, "%s: voltage switch complete, clock back to low-power mode", __func__);
|
||||
sd_host_slot_set_cclk_always_on_internal(slot, false);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
DMA
|
||||
---------------------------------------------------------------*/
|
||||
size_t sd_host_get_free_descriptors_count(sd_host_sdmmc_slot_t *slot)
|
||||
{
|
||||
const size_t next = slot->ctlr->cur_transfer.next_desc;
|
||||
size_t count = 0;
|
||||
/* Starting with the current DMA descriptor, count the number of
|
||||
* descriptors which have 'owned_by_idmac' set to 0. These are the
|
||||
* descriptors already processed by the DMA engine.
|
||||
*/
|
||||
int dma_desc_num = slot->ctlr->dma_desc_num;
|
||||
for (size_t i = 0; i < dma_desc_num; ++i) {
|
||||
sdmmc_desc_t *desc = slot->ctlr->dma_desc + ((next + i) % dma_desc_num);
|
||||
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
|
||||
esp_err_t ret = esp_cache_msync((void *)desc, sizeof(sdmmc_desc_t), ESP_CACHE_MSYNC_FLAG_DIR_M2C);
|
||||
assert(ret == ESP_OK);
|
||||
#endif
|
||||
if (desc->owned_by_idmac) {
|
||||
break;
|
||||
}
|
||||
++count;
|
||||
if (desc->next_desc_ptr == NULL) {
|
||||
/* final descriptor in the chain */
|
||||
break;
|
||||
}
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
void sd_host_fill_dma_descriptors(sd_host_sdmmc_slot_t *slot, size_t num_desc)
|
||||
{
|
||||
sd_host_sdmmc_trans_state_t *cur_trans = &slot->ctlr->cur_transfer;
|
||||
for (size_t i = 0; i < num_desc; ++i) {
|
||||
if (cur_trans->size_remaining == 0) {
|
||||
return;
|
||||
}
|
||||
const size_t next = cur_trans->next_desc;
|
||||
sdmmc_desc_t *desc = slot->ctlr->dma_desc + next;
|
||||
assert(!desc->owned_by_idmac);
|
||||
size_t size_to_fill =
|
||||
(cur_trans->size_remaining < SDMMC_DMA_MAX_BUF_LEN) ?
|
||||
cur_trans->size_remaining : SDMMC_DMA_MAX_BUF_LEN;
|
||||
bool last = size_to_fill == cur_trans->size_remaining;
|
||||
desc->last_descriptor = last;
|
||||
desc->second_address_chained = 1;
|
||||
desc->owned_by_idmac = 1;
|
||||
desc->buffer1_ptr = cur_trans->ptr;
|
||||
desc->next_desc_ptr = (last) ? NULL : slot->ctlr->dma_desc + ((next + 1) % num_desc);
|
||||
assert(size_to_fill < 4 || size_to_fill % 4 == 0);
|
||||
desc->buffer1_size = (size_to_fill + 3) & (~3);
|
||||
|
||||
cur_trans->size_remaining -= size_to_fill;
|
||||
cur_trans->ptr += size_to_fill;
|
||||
cur_trans->next_desc = (cur_trans->next_desc + 1) % num_desc;
|
||||
ESP_LOGV(TAG, "fill %d desc=%d rem=%d next=%d last=%d sz=%d",
|
||||
num_desc, next, cur_trans->size_remaining,
|
||||
cur_trans->next_desc, desc->last_descriptor, desc->buffer1_size);
|
||||
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
|
||||
esp_err_t ret = esp_cache_msync((void *)desc, sizeof(sdmmc_desc_t), ESP_CACHE_MSYNC_FLAG_DIR_C2M);
|
||||
assert(ret == ESP_OK);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
void sd_host_dma_stop(sd_host_sdmmc_slot_t *slot)
|
||||
{
|
||||
sdmmc_ll_stop_dma(slot->ctlr->hal.dev);
|
||||
}
|
||||
|
||||
void sd_host_dma_resume(sd_host_sdmmc_slot_t *slot)
|
||||
{
|
||||
sdmmc_ll_poll_demand(slot->ctlr->hal.dev);
|
||||
}
|
||||
|
||||
void sd_host_dma_prepare(sd_host_sdmmc_slot_t *slot, void *data_ptr, size_t data_size, size_t block_size)
|
||||
{
|
||||
// this clears "owned by IDMAC" bits
|
||||
memset(slot->ctlr->dma_desc, 0, sizeof(sdmmc_desc_t) * slot->ctlr->dma_desc_num);
|
||||
// initialize first descriptor
|
||||
sdmmc_desc_t *desc = slot->ctlr->dma_desc;
|
||||
desc->first_descriptor = 1;
|
||||
// save transfer info
|
||||
slot->ctlr->cur_transfer.ptr = data_ptr;
|
||||
slot->ctlr->cur_transfer.size_remaining = data_size;
|
||||
slot->ctlr->cur_transfer.next_desc = 0;
|
||||
slot->ctlr->cur_transfer.desc_remaining = (data_size + SDMMC_DMA_MAX_BUF_LEN - 1) / SDMMC_DMA_MAX_BUF_LEN;
|
||||
// prepare descriptors
|
||||
sd_host_fill_dma_descriptors(slot, slot->ctlr->dma_desc_num);
|
||||
|
||||
// Set size of data and DMA descriptor pointer
|
||||
sdmmc_ll_set_data_transfer_len(slot->ctlr->hal.dev, data_size);
|
||||
sdmmc_ll_set_block_size(slot->ctlr->hal.dev, block_size);
|
||||
sdmmc_ll_set_desc_addr(slot->ctlr->hal.dev, (uint32_t)desc);
|
||||
// Enable everything needed to use DMA
|
||||
sdmmc_ll_enable_dma(slot->ctlr->hal.dev, true);
|
||||
sd_host_dma_resume(slot);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
CMD
|
||||
---------------------------------------------------------------*/
|
||||
static bool cmd_needs_auto_stop(const sdmmc_command_t *cmd)
|
||||
{
|
||||
/* SDMMC host needs an "auto stop" flag for the following commands: */
|
||||
return cmd->datalen > 0 &&
|
||||
(cmd->opcode == MMC_WRITE_BLOCK_MULTIPLE ||
|
||||
cmd->opcode == MMC_READ_BLOCK_MULTIPLE ||
|
||||
cmd->opcode == MMC_WRITE_DAT_UNTIL_STOP ||
|
||||
cmd->opcode == MMC_READ_DAT_UNTIL_STOP);
|
||||
}
|
||||
|
||||
static sdmmc_hw_cmd_t make_hw_cmd(sdmmc_command_t *cmd)
|
||||
{
|
||||
sdmmc_hw_cmd_t res = { 0 };
|
||||
|
||||
res.cmd_index = cmd->opcode;
|
||||
if (cmd->opcode == MMC_STOP_TRANSMISSION) {
|
||||
res.stop_abort_cmd = 1;
|
||||
} else if (cmd->opcode == MMC_GO_IDLE_STATE) {
|
||||
res.send_init = 1;
|
||||
} else if (cmd->opcode == SD_SWITCH_VOLTAGE) {
|
||||
res.volt_switch = 1;
|
||||
} else {
|
||||
res.wait_complete = 1;
|
||||
}
|
||||
if (cmd->opcode == MMC_GO_IDLE_STATE) {
|
||||
res.send_init = 1;
|
||||
}
|
||||
|
||||
if (cmd->flags & SCF_RSP_PRESENT) {
|
||||
res.response_expect = 1;
|
||||
if (cmd->flags & SCF_RSP_136) {
|
||||
res.response_long = 1;
|
||||
}
|
||||
}
|
||||
if (cmd->flags & SCF_RSP_CRC) {
|
||||
res.check_response_crc = 1;
|
||||
}
|
||||
if (cmd->data) {
|
||||
res.data_expected = 1;
|
||||
if ((cmd->flags & SCF_CMD_READ) == 0) {
|
||||
res.rw = 1;
|
||||
}
|
||||
assert(cmd->datalen % cmd->blklen == 0);
|
||||
res.send_auto_stop = cmd_needs_auto_stop(cmd) ? 1 : 0;
|
||||
}
|
||||
ESP_LOGV(TAG, "%s: opcode=%d, rexp=%d, crc=%d, auto_stop=%d", __func__,
|
||||
res.cmd_index, res.response_expect, res.check_response_crc,
|
||||
res.send_auto_stop);
|
||||
return res;
|
||||
}
|
||||
|
||||
static inline bool mask_check_and_clear(uint32_t *state, uint32_t mask)
|
||||
{
|
||||
bool ret = ((*state) & mask) != 0;
|
||||
*state &= ~mask;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void process_command_response(sd_host_sdmmc_slot_t *slot, uint32_t status, sdmmc_command_t *cmd)
|
||||
{
|
||||
if (cmd->flags & SCF_RSP_PRESENT) {
|
||||
if (cmd->flags & SCF_RSP_136) {
|
||||
/* Destination is 4-byte aligned, can memcopy from peripheral registers */
|
||||
memcpy(cmd->response, (uint32_t*) SDMMC.resp, 4 * sizeof(uint32_t));
|
||||
} else {
|
||||
cmd->response[0] = SDMMC.resp[0];
|
||||
cmd->response[1] = 0;
|
||||
cmd->response[2] = 0;
|
||||
cmd->response[3] = 0;
|
||||
}
|
||||
}
|
||||
esp_err_t err = ESP_OK;
|
||||
if (status & SDMMC_INTMASK_RTO) {
|
||||
// response timeout is only possible when response is expected
|
||||
assert(cmd->flags & SCF_RSP_PRESENT);
|
||||
err = ESP_ERR_TIMEOUT;
|
||||
} else if ((cmd->flags & SCF_RSP_CRC) && (status & SDMMC_INTMASK_RCRC)) {
|
||||
err = ESP_ERR_INVALID_CRC;
|
||||
} else if (status & SDMMC_INTMASK_RESP_ERR) {
|
||||
err = ESP_ERR_INVALID_RESPONSE;
|
||||
}
|
||||
if (err != ESP_OK) {
|
||||
cmd->error = err;
|
||||
if (cmd->data) {
|
||||
sd_host_dma_stop(slot);
|
||||
}
|
||||
ESP_LOGD(TAG, "%s: error 0x%x (status=%08"PRIx32")", __func__, err, status);
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Events
|
||||
---------------------------------------------------------------*/
|
||||
static esp_err_t sd_host_wait_for_event(sd_host_sdmmc_slot_t *slot, int tick_count, sd_host_sdmmc_event_t *out_event)
|
||||
{
|
||||
assert(out_event);
|
||||
assert(slot->ctlr->event_queue);
|
||||
|
||||
int ret = xQueueReceive(slot->ctlr->event_queue, out_event, tick_count);
|
||||
if (ret == pdFALSE) {
|
||||
return ESP_ERR_TIMEOUT;
|
||||
}
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static esp_err_t sd_host_handle_idle_state_events(sd_host_sdmmc_slot_t *slot)
|
||||
{
|
||||
/* Handle any events which have happened in between transfers.
|
||||
* Under current assumptions (no SDIO support) only card detect events
|
||||
* can happen in the idle state.
|
||||
*/
|
||||
sd_host_sdmmc_event_t evt;
|
||||
while (sd_host_wait_for_event(slot, 0, &evt) == ESP_OK) {
|
||||
if (evt.sdmmc_status & SDMMC_INTMASK_CD) {
|
||||
ESP_LOGV(TAG, "card detect event");
|
||||
evt.sdmmc_status &= ~SDMMC_INTMASK_CD;
|
||||
}
|
||||
if (evt.sdmmc_status != 0 || evt.dma_status != 0) {
|
||||
ESP_LOGE(TAG, "handle_idle_state_events unhandled: %08"PRIx32" %08"PRIx32,
|
||||
evt.sdmmc_status, evt.dma_status);
|
||||
}
|
||||
|
||||
}
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static void process_data_status(sd_host_sdmmc_slot_t *slot, uint32_t status, sdmmc_command_t *cmd)
|
||||
{
|
||||
if (status & SD_DATA_ERR_MASK) {
|
||||
if (status & SDMMC_INTMASK_DTO) {
|
||||
cmd->error = ESP_ERR_TIMEOUT;
|
||||
} else if (status & SDMMC_INTMASK_DCRC) {
|
||||
cmd->error = ESP_ERR_INVALID_CRC;
|
||||
} else if ((status & SDMMC_INTMASK_EBE) &&
|
||||
(cmd->flags & SCF_CMD_READ) == 0) {
|
||||
cmd->error = ESP_ERR_TIMEOUT;
|
||||
} else {
|
||||
cmd->error = ESP_FAIL;
|
||||
}
|
||||
SDMMC.ctrl.fifo_reset = 1;
|
||||
}
|
||||
if (cmd->error != 0) {
|
||||
if (cmd->data) {
|
||||
sd_host_dma_stop(slot);
|
||||
}
|
||||
ESP_LOGD(TAG, "%s: error 0x%x (status=%08"PRIx32")", __func__, cmd->error, status);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static esp_err_t process_events(sd_host_sdmmc_slot_t *slot, sd_host_sdmmc_event_t evt, sdmmc_command_t *cmd,
|
||||
sdmmc_req_state_t *pstate, sd_host_sdmmc_event_t *unhandled_events)
|
||||
{
|
||||
const char* const s_state_names[] __attribute__((unused)) = {
|
||||
"IDLE",
|
||||
"SENDING_CMD",
|
||||
"SENDIND_DATA",
|
||||
"BUSY",
|
||||
"SENDING_VOLTAGE_SWITCH",
|
||||
"WAITING_VOLTAGE_SWITCH",
|
||||
};
|
||||
sd_host_sdmmc_event_t orig_evt = evt;
|
||||
ESP_LOGV(TAG, "%s: slot_id=%d state=%s evt=%"PRIx32" dma=%"PRIx32, __func__, slot->slot_id,
|
||||
s_state_names[*pstate], evt.sdmmc_status, evt.dma_status);
|
||||
sdmmc_req_state_t next_state = *pstate;
|
||||
sdmmc_req_state_t state = (sdmmc_req_state_t) -1;
|
||||
while (next_state != state) {
|
||||
state = next_state;
|
||||
switch (state) {
|
||||
case SDMMC_IDLE:
|
||||
break;
|
||||
|
||||
case SDMMC_SENDING_CMD:
|
||||
if (mask_check_and_clear(&evt.sdmmc_status, SD_CMD_ERR_MASK)) {
|
||||
process_command_response(slot, orig_evt.sdmmc_status, cmd);
|
||||
// In addition to the error interrupt, CMD_DONE will also be
|
||||
// reported. It may occur immediately (in the same sd_host_sdmmc_event_t) or
|
||||
// be delayed until the next interrupt.
|
||||
}
|
||||
if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_CMD_DONE)) {
|
||||
process_command_response(slot, orig_evt.sdmmc_status, cmd);
|
||||
if (cmd->error != ESP_OK) {
|
||||
next_state = SDMMC_IDLE;
|
||||
break;
|
||||
}
|
||||
|
||||
if (cmd->data == NULL) {
|
||||
next_state = SDMMC_IDLE;
|
||||
} else {
|
||||
next_state = SDMMC_SENDING_DATA;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case SDMMC_SENDING_VOLTAGE_SWITCH:
|
||||
if (mask_check_and_clear(&evt.sdmmc_status, SD_CMD_ERR_MASK)) {
|
||||
process_command_response(slot, orig_evt.sdmmc_status, cmd);
|
||||
next_state = SDMMC_IDLE;
|
||||
}
|
||||
if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_VOLT_SW)) {
|
||||
handle_voltage_switch_stage2(slot, cmd);
|
||||
if (cmd->error != ESP_OK) {
|
||||
next_state = SDMMC_IDLE;
|
||||
} else {
|
||||
next_state = SDMMC_WAITING_VOLTAGE_SWITCH;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case SDMMC_WAITING_VOLTAGE_SWITCH:
|
||||
if (mask_check_and_clear(&evt.sdmmc_status, SD_CMD_ERR_MASK)) {
|
||||
process_command_response(slot, orig_evt.sdmmc_status, cmd);
|
||||
next_state = SDMMC_IDLE;
|
||||
}
|
||||
if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_VOLT_SW)) {
|
||||
handle_voltage_switch_stage3(slot, cmd);
|
||||
next_state = SDMMC_IDLE;
|
||||
}
|
||||
break;
|
||||
|
||||
case SDMMC_SENDING_DATA:
|
||||
if (mask_check_and_clear(&evt.sdmmc_status, SD_DATA_ERR_MASK)) {
|
||||
process_data_status(slot, orig_evt.sdmmc_status, cmd);
|
||||
sd_host_dma_stop(slot);
|
||||
}
|
||||
if (mask_check_and_clear(&evt.dma_status, SD_DMA_DONE_MASK)) {
|
||||
next_state = SDMMC_BUSY;
|
||||
}
|
||||
if (orig_evt.sdmmc_status & (SDMMC_INTMASK_SBE | SDMMC_INTMASK_DATA_OVER)) {
|
||||
// On start bit error, DATA_DONE interrupt will not be generated
|
||||
next_state = SDMMC_IDLE;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case SDMMC_BUSY:
|
||||
if (!mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_DATA_OVER)) {
|
||||
break;
|
||||
}
|
||||
process_data_status(slot, orig_evt.sdmmc_status, cmd);
|
||||
next_state = SDMMC_IDLE;
|
||||
break;
|
||||
}
|
||||
ESP_LOGV(TAG, "%s state=%s next_state=%s", __func__, s_state_names[state], s_state_names[next_state]);
|
||||
}
|
||||
*pstate = state;
|
||||
*unhandled_events = evt;
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static esp_err_t handle_event(sd_host_sdmmc_slot_t *slot, sdmmc_command_t* cmd, sdmmc_req_state_t *state,
|
||||
sd_host_sdmmc_event_t *unhandled_events)
|
||||
{
|
||||
sd_host_sdmmc_event_t event;
|
||||
esp_err_t err = sd_host_wait_for_event(slot, cmd->timeout_ms / portTICK_PERIOD_MS, &event);
|
||||
if (err != ESP_OK) {
|
||||
ESP_LOGE(TAG, "sd_host_wait_for_event returned 0x%x", err);
|
||||
if (err == ESP_ERR_TIMEOUT) {
|
||||
sd_host_dma_stop(slot);
|
||||
}
|
||||
return err;
|
||||
}
|
||||
ESP_LOGV(TAG, "sdmmc_handle_event: slot_id %d event %08"PRIx32" %08"PRIx32", unhandled %08"PRIx32" %08"PRIx32,
|
||||
slot->slot_id, event.sdmmc_status, event.dma_status,
|
||||
unhandled_events->sdmmc_status, unhandled_events->dma_status);
|
||||
event.sdmmc_status |= unhandled_events->sdmmc_status;
|
||||
event.dma_status |= unhandled_events->dma_status;
|
||||
process_events(slot, event, cmd, state, unhandled_events);
|
||||
ESP_LOGV(TAG, "sdmmc_handle_event: slot_id %d events unhandled: %08"PRIx32" %08"PRIx32, slot->slot_id, unhandled_events->sdmmc_status, unhandled_events->dma_status);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static bool sd_host_card_busy(sd_host_sdmmc_slot_t *slot)
|
||||
{
|
||||
return sdmmc_ll_is_card_data_busy(slot->ctlr->hal.dev);
|
||||
}
|
||||
|
||||
static bool wait_for_busy_cleared(sd_host_sdmmc_slot_t *slot, uint32_t timeout_ms)
|
||||
{
|
||||
if (timeout_ms == 0) {
|
||||
return !sd_host_card_busy(slot);
|
||||
}
|
||||
|
||||
/* It would have been nice to do this without polling, however the peripheral
|
||||
* can only generate Busy Clear Interrupt for data write commands, and waiting
|
||||
* for busy clear is mostly needed for other commands such as MMC_SWITCH.
|
||||
*/
|
||||
uint32_t timeout_ticks = (timeout_ms + portTICK_PERIOD_MS - 1) / portTICK_PERIOD_MS;
|
||||
while (timeout_ticks-- > 0) {
|
||||
if (!sd_host_card_busy(slot)) {
|
||||
return true;
|
||||
}
|
||||
vTaskDelay(1);
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Public API Impl
|
||||
---------------------------------------------------------------*/
|
||||
esp_err_t sd_host_slot_sdmmc_do_transaction(sd_host_slot_handle_t slot, sdmmc_command_t *cmdinfo)
|
||||
{
|
||||
esp_err_t ret = ESP_FAIL;
|
||||
ESP_RETURN_ON_FALSE(slot && cmdinfo, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
sd_host_sdmmc_slot_t *slot_ctx = __containerof(slot, sd_host_sdmmc_slot_t, drv);
|
||||
|
||||
xSemaphoreTake(slot_ctx->ctlr->mutex, portMAX_DELAY);
|
||||
if (slot_ctx->ctlr->pm_lock) {
|
||||
ESP_GOTO_ON_ERROR(esp_pm_lock_acquire(slot_ctx->ctlr->pm_lock), out, TAG, "acquire pm_lock failed");
|
||||
}
|
||||
slot_ctx->ctlr->cur_slot_id = slot_ctx->slot_id;
|
||||
|
||||
// By default, set probing frequency (400kHz) and 1-bit bus
|
||||
if (slot_ctx->freq.freq_state != SD_HOST_SLOT_STATE_READY) {
|
||||
ESP_GOTO_ON_ERROR(sd_host_slot_set_card_clk(slot_ctx), out, TAG, "failed to set clk");
|
||||
} else {
|
||||
int real_freq_khz = 0;
|
||||
ret = sd_host_slot_get_real_freq(slot_ctx, &real_freq_khz);
|
||||
assert(ret == ESP_OK);
|
||||
if (real_freq_khz != (slot_ctx->freq.freq_hz / 1000)) {
|
||||
ESP_GOTO_ON_ERROR(sd_host_slot_set_card_clk(slot_ctx), out, TAG, "failed to set clk");
|
||||
}
|
||||
}
|
||||
ESP_GOTO_ON_ERROR(sd_host_slot_set_bus_width(slot_ctx), out, TAG, "failed to set width");
|
||||
ESP_GOTO_ON_ERROR(sd_host_slot_set_bus_sampling_mode(slot_ctx), out, TAG, "failed to set sampling mode");
|
||||
ESP_GOTO_ON_ERROR(sd_host_set_delay_phase(slot_ctx), out, TAG, "failed to set delay phase");
|
||||
ESP_GOTO_ON_ERROR(sd_host_set_delay_line(slot_ctx), out, TAG, "failed to set delay line");
|
||||
|
||||
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
|
||||
// cache sync related
|
||||
size_t cache_sync_len = 0;
|
||||
#endif
|
||||
|
||||
// dispose of any events which happened asynchronously
|
||||
sd_host_handle_idle_state_events(slot_ctx);
|
||||
|
||||
// special handling for voltage switch command
|
||||
if (cmdinfo->opcode == SD_SWITCH_VOLTAGE) {
|
||||
handle_voltage_switch_stage1(slot_ctx, cmdinfo);
|
||||
}
|
||||
|
||||
// convert cmdinfo to hardware register value
|
||||
sdmmc_hw_cmd_t hw_cmd = make_hw_cmd(cmdinfo);
|
||||
if (cmdinfo->data) {
|
||||
// Length should be either <4 or >=4 and =0 (mod 4).
|
||||
if (cmdinfo->datalen >= 4 && cmdinfo->datalen % 4 != 0) {
|
||||
ESP_LOGE(TAG, "%s: invalid size: total=%d",
|
||||
__func__, cmdinfo->datalen);
|
||||
ret = ESP_ERR_INVALID_SIZE;
|
||||
goto out;
|
||||
}
|
||||
|
||||
bool is_aligned = sd_host_check_buffer_alignment(slot_ctx, cmdinfo->data, cmdinfo->buflen);
|
||||
if (!is_aligned) {
|
||||
ESP_LOGE(TAG, "%s: buffer %p can not be used for DMA", __func__, cmdinfo->data);
|
||||
ret = ESP_ERR_INVALID_ARG;
|
||||
goto out;
|
||||
}
|
||||
|
||||
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
|
||||
cache_sync_len = cmdinfo->buflen;
|
||||
ret = esp_cache_msync((void *)cmdinfo->data, cache_sync_len, ESP_CACHE_MSYNC_FLAG_DIR_C2M);
|
||||
if (ret != ESP_OK) {
|
||||
goto out;
|
||||
}
|
||||
#endif
|
||||
// write transfer info into hardware
|
||||
sd_host_dma_prepare(slot_ctx, cmdinfo->data, cmdinfo->datalen, cmdinfo->blklen);
|
||||
}
|
||||
// write command into hardware, this also sends the command to the card
|
||||
ret = sd_host_slot_start_command(slot_ctx, hw_cmd, cmdinfo->arg);
|
||||
if (ret != ESP_OK) {
|
||||
goto out;
|
||||
}
|
||||
// process events until transfer is complete
|
||||
cmdinfo->error = ESP_OK;
|
||||
sdmmc_req_state_t state = SDMMC_SENDING_CMD;
|
||||
if (cmdinfo->opcode == SD_SWITCH_VOLTAGE) {
|
||||
state = SDMMC_SENDING_VOLTAGE_SWITCH;
|
||||
}
|
||||
sd_host_sdmmc_event_t unhandled_events = {};
|
||||
while (state != SDMMC_IDLE) {
|
||||
ret = handle_event(slot_ctx, cmdinfo, &state, &unhandled_events);
|
||||
if (ret != ESP_OK) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (ret == ESP_OK && (cmdinfo->flags & SCF_WAIT_BUSY)) {
|
||||
if (!wait_for_busy_cleared(slot_ctx, cmdinfo->timeout_ms)) {
|
||||
ret = ESP_ERR_TIMEOUT;
|
||||
}
|
||||
}
|
||||
slot_ctx->ctlr->is_app_cmd = (ret == ESP_OK && cmdinfo->opcode == MMC_APP_CMD);
|
||||
|
||||
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
|
||||
if (cmdinfo->data) {
|
||||
ret = esp_cache_msync((void *)cmdinfo->data, cache_sync_len, ESP_CACHE_MSYNC_FLAG_DIR_M2C);
|
||||
if (ret != ESP_OK) {
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
out:
|
||||
if (slot_ctx->ctlr->pm_lock) {
|
||||
ESP_RETURN_ON_ERROR(esp_pm_lock_release(slot_ctx->ctlr->pm_lock), TAG, "release pm_lock failed");
|
||||
}
|
||||
xSemaphoreGive(slot_ctx->ctlr->mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,497 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <unistd.h>
|
||||
#include "esp_err.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_check.h"
|
||||
#include "esp_pm.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/queue.h"
|
||||
#include "freertos/semphr.h"
|
||||
#include "freertos/task.h"
|
||||
#include "soc/sdmmc_periph.h"
|
||||
#include "driver/sdmmc_types.h"
|
||||
#include "driver/sdmmc_defs.h"
|
||||
#include "driver/sdmmc_host.h"
|
||||
#include "esp_cache.h"
|
||||
#include "esp_private/esp_cache_private.h"
|
||||
#include "sdmmc_internal.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/sdmmc_ll.h"
|
||||
|
||||
#define ALIGN_UP_BY(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
|
||||
|
||||
static const char* TAG = "sdmmc_req";
|
||||
|
||||
typedef enum {
|
||||
SDMMC_IDLE,
|
||||
SDMMC_SENDING_CMD,
|
||||
SDMMC_SENDING_DATA,
|
||||
SDMMC_BUSY,
|
||||
SDMMC_SENDING_VOLTAGE_SWITCH,
|
||||
SDMMC_WAITING_VOLTAGE_SWITCH,
|
||||
} sdmmc_req_state_t;
|
||||
|
||||
const uint32_t SDMMC_DATA_ERR_MASK =
|
||||
SDMMC_INTMASK_DTO | SDMMC_INTMASK_DCRC |
|
||||
SDMMC_INTMASK_HTO | SDMMC_INTMASK_SBE |
|
||||
SDMMC_INTMASK_EBE;
|
||||
|
||||
const uint32_t SDMMC_DMA_DONE_MASK =
|
||||
SDMMC_IDMAC_INTMASK_RI | SDMMC_IDMAC_INTMASK_TI |
|
||||
SDMMC_IDMAC_INTMASK_NI;
|
||||
|
||||
const uint32_t SDMMC_CMD_ERR_MASK =
|
||||
SDMMC_INTMASK_RTO |
|
||||
SDMMC_INTMASK_RCRC |
|
||||
SDMMC_INTMASK_RESP_ERR;
|
||||
|
||||
static QueueHandle_t s_request_mutex;
|
||||
static bool s_is_app_cmd; // This flag is set if the next command is an APP command
|
||||
#ifdef CONFIG_PM_ENABLE
|
||||
static esp_pm_lock_handle_t s_pm_lock;
|
||||
#endif
|
||||
|
||||
static esp_err_t handle_idle_state_events(void);
|
||||
static sdmmc_hw_cmd_t make_hw_cmd(sdmmc_command_t* cmd);
|
||||
static esp_err_t handle_event(int slot, sdmmc_command_t* cmd, sdmmc_req_state_t* state,
|
||||
sdmmc_event_t* unhandled_events);
|
||||
static esp_err_t process_events(int slot, sdmmc_event_t evt, sdmmc_command_t* cmd,
|
||||
sdmmc_req_state_t* pstate, sdmmc_event_t* unhandled_events);
|
||||
static void process_command_response(uint32_t status, sdmmc_command_t* cmd);
|
||||
static bool wait_for_busy_cleared(uint32_t timeout_ms);
|
||||
static void handle_voltage_switch_stage1(int slot, sdmmc_command_t* cmd);
|
||||
static void handle_voltage_switch_stage2(int slot, sdmmc_command_t* cmd);
|
||||
static void handle_voltage_switch_stage3(int slot, sdmmc_command_t* cmd);
|
||||
|
||||
esp_err_t sdmmc_host_transaction_handler_init(void)
|
||||
{
|
||||
assert(s_request_mutex == NULL);
|
||||
s_request_mutex = xSemaphoreCreateMutex();
|
||||
if (!s_request_mutex) {
|
||||
return ESP_ERR_NO_MEM;
|
||||
}
|
||||
s_is_app_cmd = false;
|
||||
#ifdef CONFIG_PM_ENABLE
|
||||
esp_err_t err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "sdmmc", &s_pm_lock);
|
||||
if (err != ESP_OK) {
|
||||
vSemaphoreDelete(s_request_mutex);
|
||||
s_request_mutex = NULL;
|
||||
return err;
|
||||
}
|
||||
#endif
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
void sdmmc_host_transaction_handler_deinit(void)
|
||||
{
|
||||
assert(s_request_mutex);
|
||||
#ifdef CONFIG_PM_ENABLE
|
||||
esp_pm_lock_delete(s_pm_lock);
|
||||
s_pm_lock = NULL;
|
||||
#endif
|
||||
vSemaphoreDelete(s_request_mutex);
|
||||
s_request_mutex = NULL;
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_host_do_transaction(int slot, sdmmc_command_t* cmdinfo)
|
||||
{
|
||||
esp_err_t ret;
|
||||
xSemaphoreTake(s_request_mutex, portMAX_DELAY);
|
||||
#ifdef CONFIG_PM_ENABLE
|
||||
esp_pm_lock_acquire(s_pm_lock);
|
||||
#endif
|
||||
|
||||
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
|
||||
// cache sync related
|
||||
size_t cache_sync_len = 0;
|
||||
#endif
|
||||
|
||||
// dispose of any events which happened asynchronously
|
||||
handle_idle_state_events();
|
||||
|
||||
// special handling for voltage switch command
|
||||
if (cmdinfo->opcode == SD_SWITCH_VOLTAGE) {
|
||||
handle_voltage_switch_stage1(slot, cmdinfo);
|
||||
}
|
||||
|
||||
// convert cmdinfo to hardware register value
|
||||
sdmmc_hw_cmd_t hw_cmd = make_hw_cmd(cmdinfo);
|
||||
if (cmdinfo->data) {
|
||||
// Length should be either <4 or >=4 and =0 (mod 4).
|
||||
if (cmdinfo->datalen >= 4 && cmdinfo->datalen % 4 != 0) {
|
||||
ESP_LOGE(TAG, "%s: invalid size: total=%d",
|
||||
__func__, cmdinfo->datalen);
|
||||
ret = ESP_ERR_INVALID_SIZE;
|
||||
goto out;
|
||||
}
|
||||
|
||||
bool is_aligned = sdmmc_host_check_buffer_alignment(slot, cmdinfo->data, cmdinfo->buflen);
|
||||
if (!is_aligned) {
|
||||
ESP_LOGE(TAG, "%s: buffer %p can not be used for DMA", __func__, cmdinfo->data);
|
||||
ret = ESP_ERR_INVALID_ARG;
|
||||
goto out;
|
||||
}
|
||||
|
||||
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
|
||||
cache_sync_len = cmdinfo->buflen;
|
||||
ret = esp_cache_msync((void *)cmdinfo->data, cache_sync_len, ESP_CACHE_MSYNC_FLAG_DIR_C2M);
|
||||
if (ret != ESP_OK) {
|
||||
goto out;
|
||||
}
|
||||
#endif
|
||||
// write transfer info into hardware
|
||||
sdmmc_host_dma_prepare(cmdinfo->data, cmdinfo->datalen, cmdinfo->blklen);
|
||||
}
|
||||
// write command into hardware, this also sends the command to the card
|
||||
ret = sdmmc_host_start_command(slot, hw_cmd, cmdinfo->arg);
|
||||
if (ret != ESP_OK) {
|
||||
goto out;
|
||||
}
|
||||
// process events until transfer is complete
|
||||
cmdinfo->error = ESP_OK;
|
||||
sdmmc_req_state_t state = SDMMC_SENDING_CMD;
|
||||
if (cmdinfo->opcode == SD_SWITCH_VOLTAGE) {
|
||||
state = SDMMC_SENDING_VOLTAGE_SWITCH;
|
||||
}
|
||||
sdmmc_event_t unhandled_events = { 0 };
|
||||
while (state != SDMMC_IDLE) {
|
||||
ret = handle_event(slot, cmdinfo, &state, &unhandled_events);
|
||||
if (ret != ESP_OK) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (ret == ESP_OK && (cmdinfo->flags & SCF_WAIT_BUSY)) {
|
||||
if (!wait_for_busy_cleared(cmdinfo->timeout_ms)) {
|
||||
ret = ESP_ERR_TIMEOUT;
|
||||
}
|
||||
}
|
||||
s_is_app_cmd = (ret == ESP_OK && cmdinfo->opcode == MMC_APP_CMD);
|
||||
|
||||
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
|
||||
if (cmdinfo->data) {
|
||||
ret = esp_cache_msync((void *)cmdinfo->data, cache_sync_len, ESP_CACHE_MSYNC_FLAG_DIR_M2C);
|
||||
if (ret != ESP_OK) {
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
out:
|
||||
#ifdef CONFIG_PM_ENABLE
|
||||
esp_pm_lock_release(s_pm_lock);
|
||||
#endif
|
||||
xSemaphoreGive(s_request_mutex);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static esp_err_t handle_idle_state_events(void)
|
||||
{
|
||||
/* Handle any events which have happened in between transfers.
|
||||
* Under current assumptions (no SDIO support) only card detect events
|
||||
* can happen in the idle state.
|
||||
*/
|
||||
sdmmc_event_t evt;
|
||||
while (sdmmc_host_wait_for_event(0, &evt) == ESP_OK) {
|
||||
if (evt.sdmmc_status & SDMMC_INTMASK_CD) {
|
||||
ESP_LOGV(TAG, "card detect event");
|
||||
evt.sdmmc_status &= ~SDMMC_INTMASK_CD;
|
||||
}
|
||||
if (evt.sdmmc_status != 0 || evt.dma_status != 0) {
|
||||
ESP_LOGE(TAG, "handle_idle_state_events unhandled: %08"PRIx32" %08"PRIx32,
|
||||
evt.sdmmc_status, evt.dma_status);
|
||||
}
|
||||
|
||||
}
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static esp_err_t handle_event(int slot, sdmmc_command_t* cmd, sdmmc_req_state_t* state,
|
||||
sdmmc_event_t* unhandled_events)
|
||||
{
|
||||
sdmmc_event_t event;
|
||||
esp_err_t err = sdmmc_host_wait_for_event(cmd->timeout_ms / portTICK_PERIOD_MS, &event);
|
||||
if (err != ESP_OK) {
|
||||
ESP_LOGE(TAG, "sdmmc_host_wait_for_event returned 0x%x", err);
|
||||
if (err == ESP_ERR_TIMEOUT) {
|
||||
sdmmc_host_dma_stop();
|
||||
}
|
||||
return err;
|
||||
}
|
||||
ESP_LOGV(TAG, "sdmmc_handle_event: slot %d event %08"PRIx32" %08"PRIx32", unhandled %08"PRIx32" %08"PRIx32,
|
||||
slot, event.sdmmc_status, event.dma_status,
|
||||
unhandled_events->sdmmc_status, unhandled_events->dma_status);
|
||||
event.sdmmc_status |= unhandled_events->sdmmc_status;
|
||||
event.dma_status |= unhandled_events->dma_status;
|
||||
process_events(slot, event, cmd, state, unhandled_events);
|
||||
ESP_LOGV(TAG, "sdmmc_handle_event: slot %d events unhandled: %08"PRIx32" %08"PRIx32, slot, unhandled_events->sdmmc_status, unhandled_events->dma_status);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static bool cmd_needs_auto_stop(const sdmmc_command_t* cmd)
|
||||
{
|
||||
/* SDMMC host needs an "auto stop" flag for the following commands: */
|
||||
return cmd->datalen > 0 &&
|
||||
(cmd->opcode == MMC_WRITE_BLOCK_MULTIPLE ||
|
||||
cmd->opcode == MMC_READ_BLOCK_MULTIPLE ||
|
||||
cmd->opcode == MMC_WRITE_DAT_UNTIL_STOP ||
|
||||
cmd->opcode == MMC_READ_DAT_UNTIL_STOP);
|
||||
}
|
||||
|
||||
static sdmmc_hw_cmd_t make_hw_cmd(sdmmc_command_t* cmd)
|
||||
{
|
||||
sdmmc_hw_cmd_t res = { 0 };
|
||||
|
||||
res.cmd_index = cmd->opcode;
|
||||
if (cmd->opcode == MMC_STOP_TRANSMISSION) {
|
||||
res.stop_abort_cmd = 1;
|
||||
} else if (cmd->opcode == MMC_GO_IDLE_STATE) {
|
||||
res.send_init = 1;
|
||||
} else if (cmd->opcode == SD_SWITCH_VOLTAGE) {
|
||||
res.volt_switch = 1;
|
||||
} else {
|
||||
res.wait_complete = 1;
|
||||
}
|
||||
if (cmd->opcode == MMC_GO_IDLE_STATE) {
|
||||
res.send_init = 1;
|
||||
}
|
||||
|
||||
if (cmd->flags & SCF_RSP_PRESENT) {
|
||||
res.response_expect = 1;
|
||||
if (cmd->flags & SCF_RSP_136) {
|
||||
res.response_long = 1;
|
||||
}
|
||||
}
|
||||
if (cmd->flags & SCF_RSP_CRC) {
|
||||
res.check_response_crc = 1;
|
||||
}
|
||||
if (cmd->data) {
|
||||
res.data_expected = 1;
|
||||
if ((cmd->flags & SCF_CMD_READ) == 0) {
|
||||
res.rw = 1;
|
||||
}
|
||||
assert(cmd->datalen % cmd->blklen == 0);
|
||||
res.send_auto_stop = cmd_needs_auto_stop(cmd) ? 1 : 0;
|
||||
}
|
||||
ESP_LOGV(TAG, "%s: opcode=%d, rexp=%d, crc=%d, auto_stop=%d", __func__,
|
||||
res.cmd_index, res.response_expect, res.check_response_crc,
|
||||
res.send_auto_stop);
|
||||
return res;
|
||||
}
|
||||
|
||||
static void process_command_response(uint32_t status, sdmmc_command_t* cmd)
|
||||
{
|
||||
if (cmd->flags & SCF_RSP_PRESENT) {
|
||||
if (cmd->flags & SCF_RSP_136) {
|
||||
/* Destination is 4-byte aligned, can memcopy from peripheral registers */
|
||||
memcpy(cmd->response, (uint32_t*) SDMMC.resp, 4 * sizeof(uint32_t));
|
||||
} else {
|
||||
cmd->response[0] = SDMMC.resp[0];
|
||||
cmd->response[1] = 0;
|
||||
cmd->response[2] = 0;
|
||||
cmd->response[3] = 0;
|
||||
}
|
||||
}
|
||||
esp_err_t err = ESP_OK;
|
||||
if (status & SDMMC_INTMASK_RTO) {
|
||||
// response timeout is only possible when response is expected
|
||||
assert(cmd->flags & SCF_RSP_PRESENT);
|
||||
err = ESP_ERR_TIMEOUT;
|
||||
} else if ((cmd->flags & SCF_RSP_CRC) && (status & SDMMC_INTMASK_RCRC)) {
|
||||
err = ESP_ERR_INVALID_CRC;
|
||||
} else if (status & SDMMC_INTMASK_RESP_ERR) {
|
||||
err = ESP_ERR_INVALID_RESPONSE;
|
||||
}
|
||||
if (err != ESP_OK) {
|
||||
cmd->error = err;
|
||||
if (cmd->data) {
|
||||
sdmmc_host_dma_stop();
|
||||
}
|
||||
ESP_LOGD(TAG, "%s: error 0x%x (status=%08"PRIx32")", __func__, err, status);
|
||||
}
|
||||
}
|
||||
|
||||
static void process_data_status(uint32_t status, sdmmc_command_t* cmd)
|
||||
{
|
||||
if (status & SDMMC_DATA_ERR_MASK) {
|
||||
if (status & SDMMC_INTMASK_DTO) {
|
||||
cmd->error = ESP_ERR_TIMEOUT;
|
||||
} else if (status & SDMMC_INTMASK_DCRC) {
|
||||
cmd->error = ESP_ERR_INVALID_CRC;
|
||||
} else if ((status & SDMMC_INTMASK_EBE) &&
|
||||
(cmd->flags & SCF_CMD_READ) == 0) {
|
||||
cmd->error = ESP_ERR_TIMEOUT;
|
||||
} else {
|
||||
cmd->error = ESP_FAIL;
|
||||
}
|
||||
SDMMC.ctrl.fifo_reset = 1;
|
||||
}
|
||||
if (cmd->error != 0) {
|
||||
if (cmd->data) {
|
||||
sdmmc_host_dma_stop();
|
||||
}
|
||||
ESP_LOGD(TAG, "%s: error 0x%x (status=%08"PRIx32")", __func__, cmd->error, status);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static inline bool mask_check_and_clear(uint32_t* state, uint32_t mask)
|
||||
{
|
||||
bool ret = ((*state) & mask) != 0;
|
||||
*state &= ~mask;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static esp_err_t process_events(int slot, sdmmc_event_t evt, sdmmc_command_t* cmd,
|
||||
sdmmc_req_state_t* pstate, sdmmc_event_t* unhandled_events)
|
||||
{
|
||||
const char* const s_state_names[] __attribute__((unused)) = {
|
||||
"IDLE",
|
||||
"SENDING_CMD",
|
||||
"SENDIND_DATA",
|
||||
"BUSY",
|
||||
"SENDING_VOLTAGE_SWITCH",
|
||||
"WAITING_VOLTAGE_SWITCH",
|
||||
};
|
||||
sdmmc_event_t orig_evt = evt;
|
||||
ESP_LOGV(TAG, "%s: slot=%d state=%s evt=%"PRIx32" dma=%"PRIx32, __func__, slot,
|
||||
s_state_names[*pstate], evt.sdmmc_status, evt.dma_status);
|
||||
sdmmc_req_state_t next_state = *pstate;
|
||||
sdmmc_req_state_t state = (sdmmc_req_state_t) -1;
|
||||
while (next_state != state) {
|
||||
state = next_state;
|
||||
switch (state) {
|
||||
case SDMMC_IDLE:
|
||||
break;
|
||||
|
||||
case SDMMC_SENDING_CMD:
|
||||
if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_CMD_ERR_MASK)) {
|
||||
process_command_response(orig_evt.sdmmc_status, cmd);
|
||||
// In addition to the error interrupt, CMD_DONE will also be
|
||||
// reported. It may occur immediately (in the same sdmmc_event_t) or
|
||||
// be delayed until the next interrupt.
|
||||
}
|
||||
if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_CMD_DONE)) {
|
||||
process_command_response(orig_evt.sdmmc_status, cmd);
|
||||
if (cmd->error != ESP_OK) {
|
||||
next_state = SDMMC_IDLE;
|
||||
break;
|
||||
}
|
||||
|
||||
if (cmd->data == NULL) {
|
||||
next_state = SDMMC_IDLE;
|
||||
} else {
|
||||
next_state = SDMMC_SENDING_DATA;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case SDMMC_SENDING_VOLTAGE_SWITCH:
|
||||
if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_CMD_ERR_MASK)) {
|
||||
process_command_response(orig_evt.sdmmc_status, cmd);
|
||||
next_state = SDMMC_IDLE;
|
||||
}
|
||||
if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_VOLT_SW)) {
|
||||
handle_voltage_switch_stage2(slot, cmd);
|
||||
if (cmd->error != ESP_OK) {
|
||||
next_state = SDMMC_IDLE;
|
||||
} else {
|
||||
next_state = SDMMC_WAITING_VOLTAGE_SWITCH;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case SDMMC_WAITING_VOLTAGE_SWITCH:
|
||||
if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_CMD_ERR_MASK)) {
|
||||
process_command_response(orig_evt.sdmmc_status, cmd);
|
||||
next_state = SDMMC_IDLE;
|
||||
}
|
||||
if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_VOLT_SW)) {
|
||||
handle_voltage_switch_stage3(slot, cmd);
|
||||
next_state = SDMMC_IDLE;
|
||||
}
|
||||
break;
|
||||
|
||||
case SDMMC_SENDING_DATA:
|
||||
if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_DATA_ERR_MASK)) {
|
||||
process_data_status(orig_evt.sdmmc_status, cmd);
|
||||
sdmmc_host_dma_stop();
|
||||
}
|
||||
if (mask_check_and_clear(&evt.dma_status, SDMMC_DMA_DONE_MASK)) {
|
||||
next_state = SDMMC_BUSY;
|
||||
}
|
||||
if (orig_evt.sdmmc_status & (SDMMC_INTMASK_SBE | SDMMC_INTMASK_DATA_OVER)) {
|
||||
// On start bit error, DATA_DONE interrupt will not be generated
|
||||
next_state = SDMMC_IDLE;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case SDMMC_BUSY:
|
||||
if (!mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_DATA_OVER)) {
|
||||
break;
|
||||
}
|
||||
process_data_status(orig_evt.sdmmc_status, cmd);
|
||||
next_state = SDMMC_IDLE;
|
||||
break;
|
||||
}
|
||||
ESP_LOGV(TAG, "%s state=%s next_state=%s", __func__, s_state_names[state], s_state_names[next_state]);
|
||||
}
|
||||
*pstate = state;
|
||||
*unhandled_events = evt;
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static bool wait_for_busy_cleared(uint32_t timeout_ms)
|
||||
{
|
||||
if (timeout_ms == 0) {
|
||||
return !sdmmc_host_card_busy();
|
||||
}
|
||||
|
||||
/* It would have been nice to do this without polling, however the peripheral
|
||||
* can only generate Busy Clear Interrupt for data write commands, and waiting
|
||||
* for busy clear is mostly needed for other commands such as MMC_SWITCH.
|
||||
*/
|
||||
uint32_t timeout_ticks = (timeout_ms + portTICK_PERIOD_MS - 1) / portTICK_PERIOD_MS;
|
||||
while (timeout_ticks-- > 0) {
|
||||
if (!sdmmc_host_card_busy()) {
|
||||
return true;
|
||||
}
|
||||
vTaskDelay(1);
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
static void handle_voltage_switch_stage1(int slot, sdmmc_command_t* cmd)
|
||||
{
|
||||
ESP_LOGV(TAG, "%s: enabling clock", __func__);
|
||||
sdmmc_host_set_cclk_always_on(slot, true);
|
||||
}
|
||||
|
||||
static void handle_voltage_switch_stage2(int slot, sdmmc_command_t* cmd)
|
||||
{
|
||||
ESP_LOGV(TAG, "%s: disabling clock", __func__);
|
||||
sdmmc_host_enable_clk_cmd11(slot, false);
|
||||
usleep(100);
|
||||
ESP_LOGV(TAG, "%s: switching voltage", __func__);
|
||||
esp_err_t err = cmd->volt_switch_cb(cmd->volt_switch_cb_arg, 1800);
|
||||
if (err != ESP_OK) {
|
||||
ESP_LOGE(TAG, "failed to switch voltage (0x%x)", err);
|
||||
cmd->error = err;
|
||||
}
|
||||
ESP_LOGV(TAG, "%s: waiting 10ms", __func__);
|
||||
usleep(10000);
|
||||
ESP_LOGV(TAG, "%s: enabling clock", __func__);
|
||||
sdmmc_host_enable_clk_cmd11(slot, true);
|
||||
}
|
||||
|
||||
static void handle_voltage_switch_stage3(int slot, sdmmc_command_t* cmd)
|
||||
{
|
||||
ESP_LOGV(TAG, "%s: voltage switch complete, clock back to low-power mode", __func__);
|
||||
sdmmc_host_set_cclk_always_on(slot, false);
|
||||
}
|
||||
@ -158,7 +158,7 @@ void sdmmc_test_rw_performance(sdmmc_card_t *card, FILE *perf_log)
|
||||
void sdmmc_test_rw_with_offset(sdmmc_card_t* card)
|
||||
{
|
||||
sdmmc_card_print_info(stdout, card);
|
||||
printf(" sector | count | align | size(kB) | wr_time(ms) | wr_speed(MB/s) | rd_time(ms) | rd_speed(MB/s)\n");
|
||||
printf(" sector | count | align | alloc | size(kB) | wr_time(ms) | wr_speed(MB/s) | rd_time(ms) | rd_speed(MB/s)\n");
|
||||
/* aligned */
|
||||
do_single_rw_perf_test(card, 1, 16, 4, NULL, 0);
|
||||
do_single_rw_perf_test(card, 16, 32, 4, NULL, 0);
|
||||
@ -216,6 +216,7 @@ void sdmmc_test_rw_highprio_task(sdmmc_card_t* card)
|
||||
|
||||
xSemaphoreGive(args.stop);
|
||||
xSemaphoreTake(args.done, portMAX_DELAY);
|
||||
vTaskDelay(1);
|
||||
vSemaphoreDelete(args.stop);
|
||||
vSemaphoreDelete(args.done);
|
||||
}
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
set(srcs "test_app_main.c")
|
||||
set(srcs "test_app_main.c" "test_sd_driver_resource.c")
|
||||
|
||||
set(priv_requires
|
||||
# tests reside in this component, also available for `sdmmc_console`
|
||||
@ -7,6 +7,7 @@ set(priv_requires
|
||||
unity
|
||||
# for PSRAM tests
|
||||
esp_psram
|
||||
esp_driver_sdmmc
|
||||
)
|
||||
|
||||
idf_component_register(SRCS ${srcs}
|
||||
|
||||
@ -0,0 +1,120 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <stdio.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "unity.h"
|
||||
#include "driver/sd_host_sdmmc.h"
|
||||
#include "driver/sd_host.h"
|
||||
#include "hal/sdmmc_ll.h"
|
||||
#include "soc/sdmmc_pins.h"
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
SDMMC
|
||||
---------------------------------------------------------------*/
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#define SDMMC_SLOT0_CLK SDMMC_SLOT0_IOMUX_PIN_NUM_CLK
|
||||
#define SDMMC_SLOT0_CMD SDMMC_SLOT0_IOMUX_PIN_NUM_CMD
|
||||
#define SDMMC_SLOT0_D0 SDMMC_SLOT0_IOMUX_PIN_NUM_D0
|
||||
#define SDMMC_SLOT0_D1 SDMMC_SLOT0_IOMUX_PIN_NUM_D1
|
||||
#define SDMMC_SLOT0_D2 SDMMC_SLOT0_IOMUX_PIN_NUM_D2
|
||||
#define SDMMC_SLOT0_D3 SDMMC_SLOT0_IOMUX_PIN_NUM_D3
|
||||
#define SDMMC_SLOT1_CLK SDMMC_SLOT1_IOMUX_PIN_NUM_CLK
|
||||
#define SDMMC_SLOT1_CMD SDMMC_SLOT1_IOMUX_PIN_NUM_CMD
|
||||
#define SDMMC_SLOT1_D0 SDMMC_SLOT1_IOMUX_PIN_NUM_D0
|
||||
#define SDMMC_SLOT1_D1 SDMMC_SLOT1_IOMUX_PIN_NUM_D1
|
||||
#define SDMMC_SLOT1_D2 SDMMC_SLOT1_IOMUX_PIN_NUM_D2
|
||||
#define SDMMC_SLOT1_D3 SDMMC_SLOT1_IOMUX_PIN_NUM_D3
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#define SDMMC_SLOT0_CLK 10
|
||||
#define SDMMC_SLOT0_CMD 11
|
||||
#define SDMMC_SLOT0_D0 12
|
||||
#define SDMMC_SLOT0_D1 13
|
||||
#define SDMMC_SLOT0_D2 14
|
||||
#define SDMMC_SLOT0_D3 15
|
||||
#define SDMMC_SLOT1_CLK 10
|
||||
#define SDMMC_SLOT1_CMD 11
|
||||
#define SDMMC_SLOT1_D0 12
|
||||
#define SDMMC_SLOT1_D1 13
|
||||
#define SDMMC_SLOT1_D2 14
|
||||
#define SDMMC_SLOT1_D3 15
|
||||
#elif CONFIG_IDF_TARGET_ESP32P4
|
||||
#define SDMMC_SLOT0_CLK SDMMC_SLOT0_IOMUX_PIN_NUM_CLK
|
||||
#define SDMMC_SLOT0_CMD SDMMC_SLOT0_IOMUX_PIN_NUM_CMD
|
||||
#define SDMMC_SLOT0_D0 SDMMC_SLOT0_IOMUX_PIN_NUM_D0
|
||||
#define SDMMC_SLOT0_D1 SDMMC_SLOT0_IOMUX_PIN_NUM_D1
|
||||
#define SDMMC_SLOT0_D2 SDMMC_SLOT0_IOMUX_PIN_NUM_D2
|
||||
#define SDMMC_SLOT0_D3 SDMMC_SLOT0_IOMUX_PIN_NUM_D3
|
||||
#define SDMMC_SLOT1_CLK 10
|
||||
#define SDMMC_SLOT1_CMD 11
|
||||
#define SDMMC_SLOT1_D0 12
|
||||
#define SDMMC_SLOT1_D1 13
|
||||
#define SDMMC_SLOT1_D2 14
|
||||
#define SDMMC_SLOT1_D3 15
|
||||
#endif
|
||||
|
||||
TEST_CASE("SDMMC controller exhausted allocation", "[sdmmc]")
|
||||
{
|
||||
sd_host_sdmmc_cfg_t cfg = {
|
||||
.event_queue_items = 4,
|
||||
};
|
||||
sd_host_ctlr_handle_t ctlr[SDMMC_LL_HOST_CTLR_NUMS + 1] = {};
|
||||
for (int i = 0; i < SDMMC_LL_HOST_CTLR_NUMS; i++) {
|
||||
TEST_ESP_OK(sd_host_create_sdmmc_controller(&cfg, &ctlr[i]));
|
||||
}
|
||||
|
||||
TEST_ESP_ERR(ESP_ERR_NOT_FOUND, sd_host_create_sdmmc_controller(&cfg, &ctlr[SDMMC_LL_HOST_CTLR_NUMS]));
|
||||
|
||||
for (int i = 0; i < SDMMC_LL_HOST_CTLR_NUMS; i++) {
|
||||
TEST_ESP_OK(sd_host_del_controller(ctlr[i]));
|
||||
}
|
||||
}
|
||||
|
||||
TEST_CASE("SDMMC slot exhausted allocation", "[sdmmc]")
|
||||
{
|
||||
sd_host_sdmmc_cfg_t cfg = {
|
||||
.event_queue_items = 4,
|
||||
};
|
||||
sd_host_ctlr_handle_t ctlr = NULL;
|
||||
TEST_ESP_OK(sd_host_create_sdmmc_controller(&cfg, &ctlr));
|
||||
|
||||
sd_host_slot_sdmmc_init_cfg_t slot_cfg = {
|
||||
.slot_id = 0,
|
||||
.sd_mode = SD_MODE_NORMAL,
|
||||
.io_config = {
|
||||
.width = 1,
|
||||
.clk_io = SDMMC_SLOT0_CLK,
|
||||
.cmd_io = SDMMC_SLOT0_CMD,
|
||||
.d0_io = SDMMC_SLOT0_D0,
|
||||
.d1_io = SDMMC_SLOT0_D1,
|
||||
.d2_io = SDMMC_SLOT0_D2,
|
||||
.d3_io = SDMMC_SLOT0_D3,
|
||||
}
|
||||
};
|
||||
sd_host_slot_handle_t slot[SOC_SDMMC_NUM_SLOTS] = {};
|
||||
|
||||
#if !CONFIG_IDF_TARGET_ESP32
|
||||
//Slot 0 on the ESP32 overlaps with the default SPI Flash pins
|
||||
TEST_ESP_OK(sd_host_sdmmc_controller_add_slot(ctlr, &slot_cfg, &slot[0]));
|
||||
#endif
|
||||
|
||||
slot_cfg.slot_id = 1;
|
||||
slot_cfg.io_config.clk_io = SDMMC_SLOT1_CLK;
|
||||
slot_cfg.io_config.cmd_io = SDMMC_SLOT1_CMD;
|
||||
slot_cfg.io_config.d0_io = SDMMC_SLOT1_D0;
|
||||
slot_cfg.io_config.d1_io = SDMMC_SLOT1_D1;
|
||||
slot_cfg.io_config.d2_io = SDMMC_SLOT1_D2;
|
||||
slot_cfg.io_config.d3_io = SDMMC_SLOT1_D3;
|
||||
TEST_ESP_OK(sd_host_sdmmc_controller_add_slot(ctlr, &slot_cfg, &slot[1]));
|
||||
|
||||
TEST_ESP_ERR(ESP_ERR_INVALID_STATE, sd_host_sdmmc_controller_add_slot(ctlr, &slot_cfg, &slot[SOC_SDMMC_NUM_SLOTS]));
|
||||
|
||||
#if !CONFIG_IDF_TARGET_ESP32
|
||||
//Slot 0 on the ESP32 overlaps with the default SPI Flash pins
|
||||
TEST_ESP_OK(sd_host_remove_slot(slot[0]));
|
||||
#endif
|
||||
TEST_ESP_OK(sd_host_remove_slot(slot[1]));
|
||||
TEST_ESP_OK(sd_host_del_controller(ctlr));
|
||||
}
|
||||
@ -60,6 +60,7 @@ typedef int sdspi_dev_handle_t;
|
||||
.get_real_freq = &sdspi_host_get_real_freq, \
|
||||
.input_delay_phase = SDMMC_DELAY_PHASE_0, \
|
||||
.set_input_delay = NULL, \
|
||||
.set_input_delayline = NULL, \
|
||||
.dma_aligned_buffer = NULL, \
|
||||
.pwr_ctrl_handle = NULL, \
|
||||
.get_dma_info = NULL, \
|
||||
|
||||
@ -84,9 +84,8 @@ extern "C" {
|
||||
* SDMMC capabilities
|
||||
*/
|
||||
#define SDMMC_LL_SLOT_SUPPORT_GPIO_MATRIX(SLOT_ID) 0
|
||||
|
||||
|
||||
#define SDMMC_LL_IOMUX_FUNC 3
|
||||
#define SDMMC_LL_IOMUX_FUNC 3
|
||||
#define SDMMC_LL_HOST_CTLR_NUMS 1U
|
||||
|
||||
typedef enum {
|
||||
SDMMC_LL_DELAY_PHASE_0,
|
||||
@ -102,11 +101,12 @@ typedef enum {
|
||||
/**
|
||||
* @brief Enable the bus clock for SDMMC module
|
||||
*
|
||||
* @param hw hardware instance address
|
||||
* @param en enable / disable
|
||||
* @param group_id Group ID
|
||||
* @param en enable / disable
|
||||
*/
|
||||
static inline void sdmmc_ll_enable_bus_clock(sdmmc_dev_t *hw, bool en)
|
||||
static inline void sdmmc_ll_enable_bus_clock(int group_id, bool en)
|
||||
{
|
||||
(void)group_id;
|
||||
if (en) {
|
||||
DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_SDIO_HOST_EN);
|
||||
} else {
|
||||
@ -121,10 +121,11 @@ static inline void sdmmc_ll_enable_bus_clock(sdmmc_dev_t *hw, bool en)
|
||||
/**
|
||||
* @brief Reset the SDMMC module
|
||||
*
|
||||
* @param hw hardware instance address
|
||||
* @param group_id Group ID
|
||||
*/
|
||||
static inline void sdmmc_ll_reset_register(sdmmc_dev_t *hw)
|
||||
static inline void sdmmc_ll_reset_register(int group_id)
|
||||
{
|
||||
(void)group_id;
|
||||
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_SDIO_HOST_RST);
|
||||
DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_SDIO_HOST_RST);
|
||||
}
|
||||
@ -256,10 +257,8 @@ static inline uint32_t sdmmc_ll_get_card_clock_div(sdmmc_dev_t *hw, uint32_t slo
|
||||
uint32_t card_div = 0;
|
||||
|
||||
if (slot == 0) {
|
||||
HAL_ASSERT(hw->clksrc.card0 == 0);
|
||||
card_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clkdiv, div0);
|
||||
} else if (slot == 1) {
|
||||
HAL_ASSERT(hw->clksrc.card1 == 1);
|
||||
card_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clkdiv, div1);
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
|
||||
@ -87,16 +87,46 @@ extern "C" {
|
||||
* SDMMC capabilities
|
||||
*/
|
||||
#define SDMMC_LL_SLOT_SUPPORT_GPIO_MATRIX(SLOT_ID) ((SLOT_ID == 0) ? 0 : 1)
|
||||
#define SDMMC_LL_IOMUX_FUNC 0
|
||||
#define SDMMC_LL_HOST_CTLR_NUMS 1U
|
||||
#define SDMMC_LL_DELAY_MAX_NUMS_LS 4
|
||||
#define SDMMC_LL_DELAY_PHASE_SUPPORTED 1
|
||||
|
||||
#define SDMMC_LL_IOMUX_FUNC 0
|
||||
|
||||
/**
|
||||
* SDMMC delay phase
|
||||
*/
|
||||
typedef enum {
|
||||
SDMMC_LL_DELAY_PHASE_0,
|
||||
SDMMC_LL_DELAY_PHASE_1,
|
||||
SDMMC_LL_DELAY_PHASE_2,
|
||||
SDMMC_LL_DELAY_PHASE_3,
|
||||
SDMMC_LL_DELAY_PHASE_4,
|
||||
SDMMC_LL_DELAY_PHASE_5,
|
||||
SDMMC_LL_DELAY_PHASE_6,
|
||||
SDMMC_LL_DELAY_PHASE_7,
|
||||
} sdmmc_ll_delay_phase_t;
|
||||
|
||||
/**
|
||||
* SDMMC delayline
|
||||
*/
|
||||
typedef enum {
|
||||
SDMMC_LL_DELAY_LINE_0,
|
||||
SDMMC_LL_DELAY_LINE_1,
|
||||
SDMMC_LL_DELAY_LINE_2,
|
||||
SDMMC_LL_DELAY_LINE_3,
|
||||
SDMMC_LL_DELAY_LINE_4,
|
||||
SDMMC_LL_DELAY_LINE_5,
|
||||
SDMMC_LL_DELAY_LINE_6,
|
||||
SDMMC_LL_DELAY_LINE_7,
|
||||
} sdmmc_ll_delay_line_t;
|
||||
|
||||
/**
|
||||
* SDMMC speed mode
|
||||
*/
|
||||
typedef enum {
|
||||
SDMMC_LL_SPEED_MODE_LS,
|
||||
SDMMC_LL_SPEED_MODE_HS,
|
||||
} sdmmc_ll_speed_mode_t;
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Clock & Reset
|
||||
@ -104,11 +134,12 @@ typedef enum {
|
||||
/**
|
||||
* @brief Enable the bus clock for SDMMC module
|
||||
*
|
||||
* @param hw hardware instance address
|
||||
* @param en enable / disable
|
||||
* @param group_id Group ID
|
||||
* @param en enable / disable
|
||||
*/
|
||||
static inline void sdmmc_ll_enable_bus_clock(sdmmc_dev_t *hw, bool en)
|
||||
static inline void sdmmc_ll_enable_bus_clock(int group_id, bool en)
|
||||
{
|
||||
(void)group_id;
|
||||
HP_SYS_CLKRST.soc_clk_ctrl1.reg_sdmmc_sys_clk_en = en;
|
||||
}
|
||||
|
||||
@ -119,10 +150,11 @@ static inline void sdmmc_ll_enable_bus_clock(sdmmc_dev_t *hw, bool en)
|
||||
/**
|
||||
* @brief Reset the SDMMC module
|
||||
*
|
||||
* @param hw hardware instance address
|
||||
* @param group_id Group ID
|
||||
*/
|
||||
static inline void sdmmc_ll_reset_register(sdmmc_dev_t *hw)
|
||||
static inline void sdmmc_ll_reset_register(int group_id)
|
||||
{
|
||||
(void)group_id;
|
||||
LP_AON_CLKRST.hp_sdmmc_emac_rst_ctrl.rst_en_sdmmc = 1;
|
||||
LP_AON_CLKRST.hp_sdmmc_emac_rst_ctrl.rst_en_sdmmc = 0;
|
||||
}
|
||||
@ -272,32 +304,85 @@ static inline void sdmmc_ll_init_phase_delay(sdmmc_dev_t *hw)
|
||||
#define sdmmc_ll_init_phase_delay(...) (void)__DECLARE_RCC_ATOMIC_ENV; sdmmc_ll_init_phase_delay(__VA_ARGS__)
|
||||
|
||||
/**
|
||||
* @brief Set SDMMC din delay
|
||||
* @brief Set SDMMC din delay phase
|
||||
*
|
||||
* @param hw hardware instance address
|
||||
* @param phase delay phase
|
||||
* @param mode speed mode
|
||||
*/
|
||||
static inline void sdmmc_ll_set_din_delay(sdmmc_dev_t *hw, sdmmc_ll_delay_phase_t phase)
|
||||
static inline void sdmmc_ll_set_din_delay_phase(sdmmc_dev_t *hw, sdmmc_ll_delay_phase_t phase, sdmmc_ll_speed_mode_t mode)
|
||||
{
|
||||
switch (phase) {
|
||||
case SDMMC_LL_DELAY_PHASE_1:
|
||||
HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x1;
|
||||
break;
|
||||
case SDMMC_LL_DELAY_PHASE_2:
|
||||
HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x2;
|
||||
break;
|
||||
case SDMMC_LL_DELAY_PHASE_3:
|
||||
HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x3;
|
||||
break;
|
||||
default:
|
||||
HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x0;
|
||||
break;
|
||||
if (mode == SDMMC_LL_SPEED_MODE_LS) {
|
||||
switch (phase) {
|
||||
case SDMMC_LL_DELAY_PHASE_1:
|
||||
HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x1;
|
||||
break;
|
||||
case SDMMC_LL_DELAY_PHASE_2:
|
||||
HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x2;
|
||||
break;
|
||||
case SDMMC_LL_DELAY_PHASE_3:
|
||||
HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x3;
|
||||
break;
|
||||
default:
|
||||
HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x0;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
SDMMC.dll_clk_conf.dll_cclk_in_sam_phase = (phase << 3);
|
||||
}
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define sdmmc_ll_set_din_delay(...) (void)__DECLARE_RCC_ATOMIC_ENV; sdmmc_ll_set_din_delay(__VA_ARGS__)
|
||||
#define sdmmc_ll_set_din_delay_phase(...) (void)__DECLARE_RCC_ATOMIC_ENV; sdmmc_ll_set_din_delay_phase(__VA_ARGS__)
|
||||
|
||||
/**
|
||||
* @brief Set SDMMC dout delay phase
|
||||
*
|
||||
* @param hw hardware instance address
|
||||
* @param phase delay phase
|
||||
* @param mode speed mode
|
||||
*/
|
||||
static inline void sdmmc_ll_set_dout_delay_phase(sdmmc_dev_t *hw, sdmmc_ll_delay_phase_t phase, sdmmc_ll_speed_mode_t mode)
|
||||
{
|
||||
if (mode == SDMMC_LL_SPEED_MODE_HS) {
|
||||
SDMMC.dll_clk_conf.dll_cclk_in_drv_phase = (phase << 3);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set SDMMC din delay line
|
||||
*
|
||||
* @param hw hardware instance address
|
||||
* @param phase delay line
|
||||
* @param mode speed mode
|
||||
*/
|
||||
static inline void sdmmc_ll_set_din_delay_line(sdmmc_dev_t *hw, sdmmc_ll_delay_line_t phase, sdmmc_ll_speed_mode_t mode)
|
||||
{
|
||||
SDMMC.dll_clk_conf.dll_cclk_in_sam_phase &= ~0x7;
|
||||
if (mode == SDMMC_LL_SPEED_MODE_HS) {
|
||||
SDMMC.dll_clk_conf.dll_cclk_in_sam_phase |= phase;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set SDMMC dout delay line
|
||||
*
|
||||
* @param hw hardware instance address
|
||||
* @param phase delay line
|
||||
* @param mode speed mode
|
||||
*/
|
||||
static inline void sdmmc_ll_set_dout_delay_line(sdmmc_dev_t *hw, sdmmc_ll_delay_line_t phase, sdmmc_ll_speed_mode_t mode)
|
||||
{
|
||||
SDMMC.dll_clk_conf.dll_cclk_in_drv_phase &= ~0x7;
|
||||
if (mode == SDMMC_LL_SPEED_MODE_HS) {
|
||||
SDMMC.dll_clk_conf.dll_cclk_in_drv_phase |= phase;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable card clock
|
||||
@ -348,10 +433,8 @@ static inline uint32_t sdmmc_ll_get_card_clock_div(sdmmc_dev_t *hw, uint32_t slo
|
||||
uint32_t card_div = 0;
|
||||
|
||||
if (slot == 0) {
|
||||
HAL_ASSERT(hw->clksrc.card0 == 0);
|
||||
card_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clkdiv, clk_divider0);
|
||||
} else if (slot == 1) {
|
||||
HAL_ASSERT(hw->clksrc.card1 == 1);
|
||||
card_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clkdiv, clk_divider1);
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
|
||||
@ -84,9 +84,14 @@ extern "C" {
|
||||
* SDMMC capabilities
|
||||
*/
|
||||
#define SDMMC_LL_SLOT_SUPPORT_GPIO_MATRIX(SLOT_ID) 1
|
||||
#define SDMMC_LL_IOMUX_FUNC -1
|
||||
#define SDMMC_LL_HOST_CTLR_NUMS 1U
|
||||
#define SDMMC_LL_DELAY_MAX_NUMS_LS 4
|
||||
#define SDMMC_LL_DELAY_PHASE_SUPPORTED 1
|
||||
|
||||
#define SDMMC_LL_IOMUX_FUNC -1
|
||||
|
||||
/**
|
||||
* SDMMC delay phase
|
||||
*/
|
||||
typedef enum {
|
||||
SDMMC_LL_DELAY_PHASE_0,
|
||||
SDMMC_LL_DELAY_PHASE_1,
|
||||
@ -94,6 +99,13 @@ typedef enum {
|
||||
SDMMC_LL_DELAY_PHASE_3,
|
||||
} sdmmc_ll_delay_phase_t;
|
||||
|
||||
/**
|
||||
* SDMMC speed mode
|
||||
*/
|
||||
typedef enum {
|
||||
SDMMC_LL_SPEED_MODE_LS,
|
||||
SDMMC_LL_SPEED_MODE_HS,
|
||||
} sdmmc_ll_speed_mode_t;
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Clock & Reset
|
||||
@ -101,11 +113,12 @@ typedef enum {
|
||||
/**
|
||||
* @brief Enable the bus clock for SDMMC module
|
||||
*
|
||||
* @param hw hardware instance address
|
||||
* @param en enable / disable
|
||||
* @param group_id Group ID
|
||||
* @param en enable / disable
|
||||
*/
|
||||
static inline void sdmmc_ll_enable_bus_clock(sdmmc_dev_t *hw, bool en)
|
||||
static inline void sdmmc_ll_enable_bus_clock(int group_id, bool en)
|
||||
{
|
||||
(void)group_id;
|
||||
SYSTEM.perip_clk_en1.sdio_host_clk_en = en;
|
||||
}
|
||||
|
||||
@ -116,10 +129,11 @@ static inline void sdmmc_ll_enable_bus_clock(sdmmc_dev_t *hw, bool en)
|
||||
/**
|
||||
* @brief Reset the SDMMC module
|
||||
*
|
||||
* @param hw hardware instance address
|
||||
* @param group_id Group ID
|
||||
*/
|
||||
static inline void sdmmc_ll_reset_register(sdmmc_dev_t *hw)
|
||||
static inline void sdmmc_ll_reset_register(int group_id)
|
||||
{
|
||||
(void)group_id;
|
||||
SYSTEM.perip_rst_en1.sdio_host_rst = 1;
|
||||
SYSTEM.perip_rst_en1.sdio_host_rst = 0;
|
||||
}
|
||||
@ -218,13 +232,15 @@ static inline void sdmmc_ll_init_phase_delay(sdmmc_dev_t *hw)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set SDMMC din delay
|
||||
* @brief Set SDMMC din delay phase
|
||||
*
|
||||
* @param hw hardware instance address
|
||||
* @param phase delay phase
|
||||
* @param mode speed mode
|
||||
*/
|
||||
static inline void sdmmc_ll_set_din_delay(sdmmc_dev_t *hw, sdmmc_ll_delay_phase_t phase)
|
||||
static inline void sdmmc_ll_set_din_delay_phase(sdmmc_dev_t *hw, sdmmc_ll_delay_phase_t phase, sdmmc_ll_speed_mode_t mode)
|
||||
{
|
||||
(void)mode;
|
||||
switch (phase) {
|
||||
case SDMMC_LL_DELAY_PHASE_1:
|
||||
hw->clock.phase_din = 0x1;
|
||||
@ -241,6 +257,18 @@ static inline void sdmmc_ll_set_din_delay(sdmmc_dev_t *hw, sdmmc_ll_delay_phase_
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set SDMMC dout delay phase
|
||||
*
|
||||
* @param hw hardware instance address
|
||||
* @param phase delay phase
|
||||
* @param mode speed mode
|
||||
*/
|
||||
static inline void sdmmc_ll_set_dout_delay_phase(sdmmc_dev_t *hw, sdmmc_ll_delay_phase_t phase, sdmmc_ll_speed_mode_t mode)
|
||||
{
|
||||
//for compatibility
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable card clock
|
||||
*
|
||||
@ -292,10 +320,8 @@ static inline uint32_t sdmmc_ll_get_card_clock_div(sdmmc_dev_t *hw, uint32_t slo
|
||||
uint32_t card_div = 0;
|
||||
|
||||
if (slot == 0) {
|
||||
HAL_ASSERT(hw->clksrc.card0 == 0);
|
||||
card_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clkdiv, div0);
|
||||
} else if (slot == 1) {
|
||||
HAL_ASSERT(hw->clksrc.card1 == 1);
|
||||
card_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clkdiv, div1);
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -16,11 +16,73 @@ extern "C" {
|
||||
* @brief SD bus width
|
||||
*/
|
||||
typedef enum {
|
||||
SD_BUS_WIDTH_1_BIT, ///< 1 bit
|
||||
SD_BUS_WIDTH_4_BIT, ///< 4 bit
|
||||
SD_BUS_WIDTH_8_BIT, ///< 8 bit
|
||||
SD_BUS_WIDTH_1_BIT = 1, ///< 1 bit
|
||||
SD_BUS_WIDTH_4_BIT = 4, ///< 4 bit
|
||||
SD_BUS_WIDTH_8_BIT = 8, ///< 8 bit
|
||||
} sd_bus_width_t;
|
||||
|
||||
/**
|
||||
* @brief SD mode
|
||||
*/
|
||||
typedef enum {
|
||||
SD_MODE_NORMAL, ///< Normal SD mode
|
||||
SD_MODE_UHS1, ///< UHS-I SD mode
|
||||
} sd_mode_t;
|
||||
|
||||
/**
|
||||
* @brief SD sampling mode
|
||||
*/
|
||||
typedef enum {
|
||||
SD_SAMPLING_MODE_SDR = 1, ///< Single data rate mode
|
||||
SD_SAMPLING_MODE_DDR, ///< Double data rate mode
|
||||
} sd_sampling_mode_t;
|
||||
|
||||
/**
|
||||
* @brief SD/MMC Host clock timing delay phases
|
||||
*
|
||||
* This will only take effect when the host works in
|
||||
* - SDMMC_FREQ_HIGHSPEED
|
||||
* - SDMMC_FREQ_52M
|
||||
* - SDR50
|
||||
* - DDR50
|
||||
* - SDR104
|
||||
* Driver will print out how long the delay is, in picosecond (ps).
|
||||
*/
|
||||
typedef enum {
|
||||
SDMMC_DELAY_PHASE_0 = 1, /*!< Delay phase 0 */
|
||||
SDMMC_DELAY_PHASE_1, /*!< Delay phase 1 */
|
||||
SDMMC_DELAY_PHASE_2, /*!< Delay phase 2 */
|
||||
SDMMC_DELAY_PHASE_3, /*!< Delay phase 3 */
|
||||
SDMMC_DELAY_PHASE_4, /*!< Delay phase 4 */
|
||||
SDMMC_DELAY_PHASE_5, /*!< Delay phase 5 */
|
||||
SDMMC_DELAY_PHASE_6, /*!< Delay phase 6 */
|
||||
SDMMC_DELAY_PHASE_7, /*!< Delay phase 7 */
|
||||
SDMMC_DELAY_PHASE_AUTO, /*!< Auto detect phase, only valid for UHS-I modes */
|
||||
} sdmmc_delay_phase_t;
|
||||
|
||||
/**
|
||||
* @brief SD/MMC Host clock timing delay lines
|
||||
*/
|
||||
typedef enum {
|
||||
SDMMC_DELAY_LINE_0 = 1, /*!< Delay line 0 */
|
||||
SDMMC_DELAY_LINE_1, /*!< Delay line 1 */
|
||||
SDMMC_DELAY_LINE_2, /*!< Delay line 2 */
|
||||
SDMMC_DELAY_LINE_3, /*!< Delay line 3 */
|
||||
SDMMC_DELAY_LINE_4, /*!< Delay line 4 */
|
||||
SDMMC_DELAY_LINE_5, /*!< Delay line 5 */
|
||||
SDMMC_DELAY_LINE_6, /*!< Delay line 6 */
|
||||
SDMMC_DELAY_LINE_7, /*!< Delay line 7 */
|
||||
SDMMC_DELAY_LINE_AUTO, /*!< Auto detect line */
|
||||
} sdmmc_delay_line_t;
|
||||
|
||||
#if SOC_SDMMC_DATA_WIDTH_MAX
|
||||
#define SDMMC_DATA_SIG_NUM SOC_SDMMC_DATA_WIDTH_MAX ///< Number of data signals
|
||||
#else
|
||||
#define SDMMC_DATA_SIG_NUM 0 ///< Number of data signals
|
||||
#endif
|
||||
|
||||
#define SDMMC_DMA_ALIGNMENT 4
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -62,7 +62,13 @@ extern "C" {
|
||||
#define SDMMC_MMC_TRIM_ARG 1
|
||||
#define SDMMC_MMC_DISCARD_ARG 3
|
||||
|
||||
#define SDMMC_FREQ_SDR104 208000 /*!< MMC 208MHz speed */
|
||||
/**
|
||||
* Delay mode
|
||||
*/
|
||||
typedef enum {
|
||||
SDMMC_DELAY_MODE_PHASE,
|
||||
SDMMC_DELAY_MODE_LINE,
|
||||
} sdmmc_delay_mode_t;
|
||||
|
||||
/* Functions to send individual commands */
|
||||
esp_err_t sdmmc_send_cmd(sdmmc_card_t* card, sdmmc_command_t* cmd);
|
||||
@ -97,7 +103,7 @@ esp_err_t sdmmc_read_sectors_dma(sdmmc_card_t* card, void* dst,
|
||||
uint32_t sdmmc_get_erase_timeout_ms(const sdmmc_card_t* card, int arg, size_t erase_size_kb);
|
||||
esp_err_t sdmmc_select_driver_strength(sdmmc_card_t *card, sdmmc_driver_strength_t driver_strength);
|
||||
esp_err_t sdmmc_select_current_limit(sdmmc_card_t *card, sdmmc_current_limit_t current_limit);
|
||||
esp_err_t sdmmc_do_timing_tuning(sdmmc_card_t *card);
|
||||
esp_err_t sdmmc_do_timing_tuning(sdmmc_card_t *card, sdmmc_delay_mode_t delay_mode);
|
||||
|
||||
/* SD specific */
|
||||
esp_err_t sdmmc_check_scr(sdmmc_card_t* card);
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* SPDX-License-Identifier: ISC
|
||||
*
|
||||
* SPDX-FileContributor: 2016-2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileContributor: 2016-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*/
|
||||
/*
|
||||
* Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
|
||||
@ -29,6 +29,7 @@
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "sd_pwr_ctrl.h"
|
||||
#include "esp_dma_utils.h"
|
||||
#include "hal/sd_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -153,24 +154,6 @@ typedef struct {
|
||||
void* volt_switch_cb_arg; /*!< argument to be passed to the CMD11 callback */
|
||||
} sdmmc_command_t;
|
||||
|
||||
/**
|
||||
* SD/MMC Host clock timing delay phases
|
||||
*
|
||||
* This will only take effect when the host works in
|
||||
* - SDMMC_FREQ_HIGHSPEED
|
||||
* - SDMMC_FREQ_52M
|
||||
* - SDR50
|
||||
* - DDR50
|
||||
* Driver will print out how long the delay is, in picosecond (ps).
|
||||
*/
|
||||
typedef enum {
|
||||
SDMMC_DELAY_PHASE_0, /*!< Delay phase 0 */
|
||||
SDMMC_DELAY_PHASE_1, /*!< Delay phase 1 */
|
||||
SDMMC_DELAY_PHASE_2, /*!< Delay phase 2 */
|
||||
SDMMC_DELAY_PHASE_3, /*!< Delay phase 3 */
|
||||
SDMMC_DELAY_PHASE_AUTO, /*!< Auto detect phase, only valid for UHS-I mode */
|
||||
} sdmmc_delay_phase_t;
|
||||
|
||||
/**
|
||||
* @brief SD/MMC Driver Strength
|
||||
*/
|
||||
@ -219,6 +202,7 @@ typedef struct {
|
||||
#define SDMMC_FREQ_26M 26000 /*!< MMC 26MHz speed */
|
||||
#define SDMMC_FREQ_DDR50 50000 /*!< MMC 50MHz speed */
|
||||
#define SDMMC_FREQ_SDR50 100000 /*!< MMC 100MHz speed */
|
||||
#define SDMMC_FREQ_SDR104 200000 /*!< MMC 200MHz speed */
|
||||
float io_voltage; /*!< I/O voltage used by the controller (voltage switching is not supported) */
|
||||
sdmmc_driver_strength_t driver_strength; /*!< Driver Strength */
|
||||
sdmmc_current_limit_t current_limit; /*!< Current Limit */
|
||||
@ -239,6 +223,7 @@ typedef struct {
|
||||
esp_err_t (*get_real_freq)(int slot, int* real_freq); /*!< Host function to provide real working freq, based on SDMMC controller setup */
|
||||
sdmmc_delay_phase_t input_delay_phase; /*!< input delay phase, this will only take into effect when the host works in SDMMC_FREQ_HIGHSPEED or SDMMC_FREQ_52M. Driver will print out how long the delay is*/
|
||||
esp_err_t (*set_input_delay)(int slot, sdmmc_delay_phase_t delay_phase); /*!< set input delay phase */
|
||||
esp_err_t (*set_input_delayline)(int slot, sdmmc_delay_line_t delay_line); /*!< set input delay line */
|
||||
void* dma_aligned_buffer; /*!< Leave it NULL. Reserved for cache aligned buffers for SDIO mode */
|
||||
sd_pwr_ctrl_handle_t pwr_ctrl_handle; /*!< Power control handle */
|
||||
esp_err_t (*get_dma_info)(int slot, esp_dma_mem_info_t *dma_mem_info); /*!< host function to dma memory information*/
|
||||
|
||||
@ -206,7 +206,12 @@ esp_err_t sdmmc_init_sd_current_limit(sdmmc_card_t *card)
|
||||
|
||||
esp_err_t sdmmc_init_sd_timing_tuning(sdmmc_card_t *card)
|
||||
{
|
||||
return sdmmc_do_timing_tuning(card);
|
||||
ESP_RETURN_ON_ERROR(sdmmc_do_timing_tuning(card, SDMMC_DELAY_MODE_PHASE), TAG, "failed to do phase timing tuning");
|
||||
if (card->host.max_freq_khz == SDMMC_FREQ_SDR104) {
|
||||
ESP_RETURN_ON_ERROR(sdmmc_do_timing_tuning(card, SDMMC_DELAY_MODE_LINE), TAG, "failed to do delayline timing tuning");
|
||||
}
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_init_host_bus_width(sdmmc_card_t* card)
|
||||
|
||||
@ -21,6 +21,8 @@
|
||||
#include "esp_cache.h"
|
||||
#include "esp_private/sdmmc_common.h"
|
||||
|
||||
#define SDMMC_DELAY_NUMS_MAX 10
|
||||
|
||||
static const char* TAG = "sdmmc_sd";
|
||||
|
||||
esp_err_t sdmmc_init_sd_if_cond(sdmmc_card_t* card)
|
||||
@ -332,7 +334,7 @@ static const uint8_t s_tuning_block_pattern[] = {
|
||||
* Find consecutive successful sampling points.
|
||||
* e.g. array: {1, 1, 0, 0, 1, 1, 1, 0}
|
||||
* out_length: 3
|
||||
* outout_end_index: 6
|
||||
* out_end_index: 6
|
||||
*/
|
||||
static void find_max_consecutive_success_points(int *array, size_t size, size_t *out_length, uint32_t *out_end_index)
|
||||
{
|
||||
@ -354,8 +356,17 @@ static void find_max_consecutive_success_points(int *array, size_t size, size_t
|
||||
i++;
|
||||
}
|
||||
|
||||
*out_length = match_num > max ? match_num : max;
|
||||
*out_end_index = match_num == size ? size : end;
|
||||
/**
|
||||
* this is to deal with the case when the last points are consecutive 1, e.g.
|
||||
* {1, 0, 0, 1, 1, 1, 1, 1, 1}
|
||||
*/
|
||||
if (match_num > max) {
|
||||
max = match_num;
|
||||
end = i - 1;
|
||||
}
|
||||
|
||||
*out_length = max;
|
||||
*out_end_index = end;
|
||||
}
|
||||
|
||||
static esp_err_t read_tuning_block(sdmmc_card_t *card)
|
||||
@ -415,44 +426,64 @@ static esp_err_t read_tuning_block(sdmmc_card_t *card)
|
||||
return success ? ESP_OK : ESP_FAIL;
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_do_timing_tuning(sdmmc_card_t *card)
|
||||
esp_err_t sdmmc_do_timing_tuning(sdmmc_card_t *card, sdmmc_delay_mode_t delay_mode)
|
||||
{
|
||||
esp_err_t ret = ESP_FAIL;
|
||||
|
||||
ESP_RETURN_ON_FALSE(!host_is_spi(card), ESP_ERR_NOT_SUPPORTED, TAG, "sdspi not supported timing tuning");
|
||||
ESP_RETURN_ON_FALSE(card->host.set_input_delay, ESP_ERR_NOT_SUPPORTED, TAG, "input phase delay feature isn't supported");
|
||||
if (delay_mode == SDMMC_DELAY_MODE_PHASE) {
|
||||
ESP_RETURN_ON_FALSE(card->host.set_input_delay, ESP_ERR_NOT_SUPPORTED, TAG, "phase delay feature isn't supported");
|
||||
} else {
|
||||
ESP_RETURN_ON_FALSE(card->host.set_input_delayline, ESP_ERR_NOT_SUPPORTED, TAG, "line delay feature isn't supported");
|
||||
}
|
||||
|
||||
int results[SDMMC_DELAY_PHASE_AUTO] = {};
|
||||
int results[SDMMC_DELAY_NUMS_MAX] = {};
|
||||
int start_delay_item = (delay_mode == SDMMC_DELAY_MODE_PHASE) ? SDMMC_DELAY_PHASE_0 : SDMMC_DELAY_LINE_0;
|
||||
int slot = card->host.slot;
|
||||
for (int i = SDMMC_DELAY_PHASE_0; i < SDMMC_DELAY_PHASE_AUTO; i++) {
|
||||
ESP_RETURN_ON_ERROR((*card->host.set_input_delay)(slot, i), TAG, "failed to set input delay");
|
||||
|
||||
int delay_total_nums = 4;
|
||||
if (delay_mode == SDMMC_DELAY_MODE_PHASE) {
|
||||
if (card->host.max_freq_khz == SDMMC_FREQ_SDR104) {
|
||||
delay_total_nums = SDMMC_DELAY_PHASE_AUTO;
|
||||
}
|
||||
} else {
|
||||
delay_total_nums = SDMMC_DELAY_LINE_AUTO;
|
||||
}
|
||||
for (int i = start_delay_item; i < delay_total_nums; i++) {
|
||||
if (delay_mode == SDMMC_DELAY_MODE_PHASE) {
|
||||
ESP_RETURN_ON_ERROR((*card->host.set_input_delay)(slot, i), TAG, "failed to set delay phase");
|
||||
} else {
|
||||
ESP_RETURN_ON_ERROR((*card->host.set_input_delayline)(slot, i), TAG, "failed to set delay line");
|
||||
}
|
||||
ret = read_tuning_block(card);
|
||||
if (ret == ESP_OK) {
|
||||
results[i] += 1;
|
||||
}
|
||||
}
|
||||
|
||||
for (int i = 0; i < 4; i++) {
|
||||
for (int i = 0; i < delay_total_nums; i++) {
|
||||
ESP_LOGV(TAG, "results[%d]: %d", i, results[i]);
|
||||
}
|
||||
|
||||
size_t consecutive_len = 0;
|
||||
uint32_t end = 0;
|
||||
find_max_consecutive_success_points(results, SDMMC_DELAY_PHASE_AUTO, &consecutive_len, &end);
|
||||
find_max_consecutive_success_points(results, delay_total_nums, &consecutive_len, &end);
|
||||
|
||||
sdmmc_delay_phase_t proper_delay_phase = SDMMC_DELAY_PHASE_AUTO;
|
||||
int proper_delay_id = SDMMC_DELAY_PHASE_AUTO;
|
||||
if (consecutive_len == 1) {
|
||||
proper_delay_phase = end;
|
||||
proper_delay_id = end;
|
||||
} else if (consecutive_len <= SDMMC_DELAY_PHASE_AUTO) {
|
||||
proper_delay_phase = end / 2;
|
||||
proper_delay_id = end - (consecutive_len / 2);
|
||||
} else {
|
||||
assert(false && "exceeds max tuning point");
|
||||
}
|
||||
ESP_LOGV(TAG, "%s: proper_delay_phase: %d\n", __func__, proper_delay_phase);
|
||||
ESP_LOGI(TAG, "%s: proper delay phase/line id: %d", __func__, proper_delay_id);
|
||||
|
||||
if (proper_delay_phase != SDMMC_DELAY_PHASE_AUTO) {
|
||||
ESP_RETURN_ON_ERROR((*card->host.set_input_delay)(slot, proper_delay_phase), TAG, "failed to set input delay");
|
||||
if (proper_delay_id != SDMMC_DELAY_PHASE_AUTO) {
|
||||
if (delay_mode == SDMMC_DELAY_MODE_PHASE) {
|
||||
ESP_RETURN_ON_ERROR((*card->host.set_input_delay)(slot, proper_delay_id), TAG, "failed to set delay phase");
|
||||
} else {
|
||||
ESP_RETURN_ON_ERROR((*card->host.set_input_delayline)(slot, proper_delay_id), TAG, "failed to set delay line");
|
||||
}
|
||||
}
|
||||
|
||||
return ESP_OK;
|
||||
|
||||
@ -943,6 +943,10 @@ config SOC_SDMMC_NUM_SLOTS
|
||||
int
|
||||
default 2
|
||||
|
||||
config SOC_SDMMC_DATA_WIDTH_MAX
|
||||
int
|
||||
default 8
|
||||
|
||||
config SOC_WIFI_WAPI_SUPPORT
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -442,8 +442,9 @@
|
||||
/* On ESP32, clock/cmd/data pins use IO MUX.
|
||||
* Card detect, write protect, interrupt use GPIO Matrix on all chips.
|
||||
*/
|
||||
#define SOC_SDMMC_USE_IOMUX 1
|
||||
#define SOC_SDMMC_NUM_SLOTS 2
|
||||
#define SOC_SDMMC_USE_IOMUX 1
|
||||
#define SOC_SDMMC_NUM_SLOTS 2
|
||||
#define SOC_SDMMC_DATA_WIDTH_MAX 8
|
||||
|
||||
/*-------------------------- WI-FI HARDWARE CAPS -------------------------------*/
|
||||
#define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */
|
||||
|
||||
@ -1419,9 +1419,13 @@ config SOC_SDMMC_NUM_SLOTS
|
||||
int
|
||||
default 2
|
||||
|
||||
config SOC_SDMMC_DATA_WIDTH_MAX
|
||||
int
|
||||
default 8
|
||||
|
||||
config SOC_SDMMC_DELAY_PHASE_NUM
|
||||
int
|
||||
default 4
|
||||
default 8
|
||||
|
||||
config SOC_SDMMC_IO_POWER_EXTERNAL
|
||||
bool
|
||||
|
||||
@ -512,8 +512,9 @@
|
||||
#define SOC_SDMMC_USE_IOMUX 1
|
||||
#define SOC_SDMMC_USE_GPIO_MATRIX 1
|
||||
#define SOC_SDMMC_NUM_SLOTS 2
|
||||
#define SOC_SDMMC_DATA_WIDTH_MAX 8
|
||||
/* Supported host clock delay phase number */
|
||||
#define SOC_SDMMC_DELAY_PHASE_NUM 4
|
||||
#define SOC_SDMMC_DELAY_PHASE_NUM 8
|
||||
#define SOC_SDMMC_IO_POWER_EXTERNAL 1 ///< SDMMC IO power controlled by external power supply
|
||||
#define SOC_SDMMC_PSRAM_DMA_CAPABLE 1 ///< SDMMC peripheral can do DMA transfer to/from PSRAM
|
||||
#define SOC_SDMMC_UHS_I_SUPPORTED 1
|
||||
|
||||
@ -1463,6 +1463,10 @@ config SOC_SDMMC_NUM_SLOTS
|
||||
int
|
||||
default 2
|
||||
|
||||
config SOC_SDMMC_DATA_WIDTH_MAX
|
||||
int
|
||||
default 8
|
||||
|
||||
config SOC_SDMMC_SUPPORT_XTAL_CLOCK
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -574,6 +574,7 @@
|
||||
*/
|
||||
#define SOC_SDMMC_USE_GPIO_MATRIX 1
|
||||
#define SOC_SDMMC_NUM_SLOTS 2
|
||||
#define SOC_SDMMC_DATA_WIDTH_MAX 8
|
||||
/* Indicates that there is an option to use XTAL clock instead of PLL for SDMMC */
|
||||
#define SOC_SDMMC_SUPPORT_XTAL_CLOCK 1
|
||||
/* Supported host clock delay phase number */
|
||||
|
||||
@ -134,9 +134,12 @@ INPUT = \
|
||||
$(PROJECT_PATH)/components/esp_driver_rmt/include/driver/rmt_types.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_sdio/include/driver/sdio_slave.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_sdm/include/driver/sdm.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_sdmmc/include/driver/sdmmc_default_configs.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_sdmmc/include/driver/sdmmc_host.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_sdmmc/include/driver/sdmmc_types.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_sdmmc/include/driver/sd_host_sdmmc.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_sdmmc/legacy/include/driver/sdmmc_default_configs.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_sdmmc/legacy/include/driver/sdmmc_host.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_sdmmc/legacy/include/driver/sdmmc_types.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_sd_intf/include/driver/sd_host.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_sd_intf/include/driver/sd_types.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_sdspi/include/driver/sdspi_host.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_spi/include/driver/spi_common.h \
|
||||
$(PROJECT_PATH)/components/esp_driver_spi/include/driver/spi_master.h \
|
||||
|
||||
@ -9,7 +9,7 @@ Overview
|
||||
The SD/SDIO/MMC driver supports SD memory, SDIO cards, and eMMC chips. This is a protocol layer driver (:component_file:`sdmmc/include/sdmmc_cmd.h`) which can work together with:
|
||||
|
||||
.. list::
|
||||
:SOC_SDMMC_HOST_SUPPORTED: - SDMMC host driver (:component_file:`esp_driver_sdmmc/include/driver/sdmmc_host.h`), see :doc:`SDMMC Host API <../peripherals/sdmmc_host>` for more details.
|
||||
:SOC_SDMMC_HOST_SUPPORTED: - SDMMC host driver (:component_file:`esp_driver_sdmmc/legacy/include/driver/sdmmc_host.h`), see :doc:`SDMMC Host API <../peripherals/sdmmc_host>` for more details.
|
||||
:SOC_GPSPI_SUPPORTED: - SDSPI host driver (:component_file:`esp_driver_sdspi/include/driver/sdspi_host.h`), see :doc:`SD SPI Host API <../peripherals/sdspi_host>` for more details.
|
||||
|
||||
Protocol Layer vs Host Layer
|
||||
|
||||
@ -9,7 +9,7 @@ SD/SDIO/MMC 驱动程序
|
||||
SD/SDIO/MMC 驱动支持 SD 存储器、SDIO 卡和 eMMC 芯片。这是一个协议层驱动 (:component_file:`sdmmc/include/sdmmc_cmd.h`)，可以与以下驱动配合使用：
|
||||
|
||||
.. list::
|
||||
:SOC_SDMMC_HOST_SUPPORTED: - SDMMC 主机驱动 (:component_file:`esp_driver_sdmmc/include/driver/sdmmc_host.h`)，详情请参阅 :doc:`SDMMC Host API <../peripherals/sdmmc_host>`。
|
||||
:SOC_SDMMC_HOST_SUPPORTED: - SDMMC 主机驱动 (:component_file:`esp_driver_sdmmc/legacy/include/driver/sdmmc_host.h`)，详情请参阅 :doc:`SDMMC Host API <../peripherals/sdmmc_host>`。
|
||||
:SOC_GPSPI_SUPPORTED: - SDSPI 主机驱动 (:component_file:`esp_driver_sdspi/include/driver/sdspi_host.h`)，详情请参阅 :doc:`SD SPI Host API <../peripherals/sdspi_host>`。
|
||||
|
||||
协议层与主机层
|
||||
|
||||
@ -42,6 +42,9 @@ menu "SD/MMC Example Configuration"
|
||||
config EXAMPLE_SDMMC_SPEED_UHS_I_DDR50
|
||||
bool "UHS-I DDR50 (50 MHz, 50 MB/s)"
|
||||
depends on SOC_SDMMC_UHS_I_SUPPORTED
|
||||
config EXAMPLE_SDMMC_SPEED_UHS_I_SDR104
|
||||
bool "UHS-I SDR104 (200 MHz, 100 MB/s)"
|
||||
depends on SOC_SDMMC_UHS_I_SUPPORTED
|
||||
endchoice
|
||||
|
||||
if SOC_SDMMC_USE_GPIO_MATRIX
|
||||
|
||||
@ -24,7 +24,7 @@
|
||||
static const char *TAG = "example";
|
||||
|
||||
#define MOUNT_POINT "/sdcard"
|
||||
#define EXAMPLE_IS_UHS1 (CONFIG_EXAMPLE_SDMMC_SPEED_UHS_I_SDR50 || CONFIG_EXAMPLE_SDMMC_SPEED_UHS_I_DDR50)
|
||||
#define EXAMPLE_IS_UHS1 (CONFIG_EXAMPLE_SDMMC_SPEED_UHS_I_SDR50 || CONFIG_EXAMPLE_SDMMC_SPEED_UHS_I_DDR50 || CONFIG_EXAMPLE_SDMMC_SPEED_UHS_I_SDR104)
|
||||
|
||||
#ifdef CONFIG_EXAMPLE_DEBUG_PIN_CONNECTIONS
|
||||
const char* names[] = {"CLK", "CMD", "D0", "D1", "D2", "D3"};
|
||||
@ -138,6 +138,10 @@ void app_main(void)
|
||||
#elif CONFIG_EXAMPLE_SDMMC_SPEED_UHS_I_DDR50
|
||||
host.slot = SDMMC_HOST_SLOT_0;
|
||||
host.max_freq_khz = SDMMC_FREQ_DDR50;
|
||||
#elif CONFIG_EXAMPLE_SDMMC_SPEED_UHS_I_SDR104
|
||||
host.slot = SDMMC_HOST_SLOT_0;
|
||||
host.max_freq_khz = SDMMC_FREQ_SDR104;
|
||||
host.flags &= ~SDMMC_HOST_FLAG_DDR;
|
||||
#endif
|
||||
|
||||
// For SoCs where the SD power can be supplied both via an internal or external (e.g. on-board LDO) power supply.
|
||||
|
||||
Reference in New Issue
Block a user