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Merge branch 'feat/p4_eco5_soc_part2' into 'master'

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p4: eco5 soc registers (part2)

See merge request espressif/esp-idf!40694
This commit is contained in:
Armando (Dou Yiwen)
2025-07-23 10:08:11 +00:00
parent 33493d43e0 ee68450342
commit b22fcf6dbd
90 changed files with 175473 additions and 0 deletions
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components/soc/esp32p4/register/hw_ver2/soc/adc_eco5_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ADC_CTRL_REG_REG register
* Register
*/
#define ADC_CTRL_REG_REG (DR_REG_ADC_BASE + 0x0)
/** ADC_START_FORCE : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define ADC_START_FORCE (BIT(0))
#define ADC_START_FORCE_M (ADC_START_FORCE_V << ADC_START_FORCE_S)
#define ADC_START_FORCE_V 0x00000001U
#define ADC_START_FORCE_S 0
/** ADC_START : R/W; bitpos: [1]; default: 0;
* need_des
*/
#define ADC_START (BIT(1))
#define ADC_START_M (ADC_START_V << ADC_START_S)
#define ADC_START_V 0x00000001U
#define ADC_START_S 1
/** ADC_WORK_MODE : R/W; bitpos: [3:2]; default: 0;
* 0: single mode, 1: double mode, 2: alternate mode
*/
#define ADC_WORK_MODE 0x00000003U
#define ADC_WORK_MODE_M (ADC_WORK_MODE_V << ADC_WORK_MODE_S)
#define ADC_WORK_MODE_V 0x00000003U
#define ADC_WORK_MODE_S 2
/** ADC_SAR_SEL : R/W; bitpos: [4]; default: 0;
* 0: SAR1, 1: SAR2, only work for single SAR mode
*/
#define ADC_SAR_SEL (BIT(4))
#define ADC_SAR_SEL_M (ADC_SAR_SEL_V << ADC_SAR_SEL_S)
#define ADC_SAR_SEL_V 0x00000001U
#define ADC_SAR_SEL_S 4
/** ADC_SAR_CLK_GATED : R/W; bitpos: [5]; default: 1;
* need_des
*/
#define ADC_SAR_CLK_GATED (BIT(5))
#define ADC_SAR_CLK_GATED_M (ADC_SAR_CLK_GATED_V << ADC_SAR_CLK_GATED_S)
#define ADC_SAR_CLK_GATED_V 0x00000001U
#define ADC_SAR_CLK_GATED_S 5
/** ADC_SAR_CLK_DIV : R/W; bitpos: [13:6]; default: 4;
* SAR clock divider
*/
#define ADC_SAR_CLK_DIV 0x000000FFU
#define ADC_SAR_CLK_DIV_M (ADC_SAR_CLK_DIV_V << ADC_SAR_CLK_DIV_S)
#define ADC_SAR_CLK_DIV_V 0x000000FFU
#define ADC_SAR_CLK_DIV_S 6
/** ADC_SAR1_PATT_LEN : R/W; bitpos: [17:14]; default: 15;
* 0 ~ 15 means length 1 ~ 16
*/
#define ADC_SAR1_PATT_LEN 0x0000000FU
#define ADC_SAR1_PATT_LEN_M (ADC_SAR1_PATT_LEN_V << ADC_SAR1_PATT_LEN_S)
#define ADC_SAR1_PATT_LEN_V 0x0000000FU
#define ADC_SAR1_PATT_LEN_S 14
/** ADC_SAR2_PATT_LEN : R/W; bitpos: [21:18]; default: 15;
* 0 ~ 15 means length 1 ~ 16
*/
#define ADC_SAR2_PATT_LEN 0x0000000FU
#define ADC_SAR2_PATT_LEN_M (ADC_SAR2_PATT_LEN_V << ADC_SAR2_PATT_LEN_S)
#define ADC_SAR2_PATT_LEN_V 0x0000000FU
#define ADC_SAR2_PATT_LEN_S 18
/** ADC_SAR1_PATT_P_CLEAR : R/W; bitpos: [22]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
#define ADC_SAR1_PATT_P_CLEAR (BIT(22))
#define ADC_SAR1_PATT_P_CLEAR_M (ADC_SAR1_PATT_P_CLEAR_V << ADC_SAR1_PATT_P_CLEAR_S)
#define ADC_SAR1_PATT_P_CLEAR_V 0x00000001U
#define ADC_SAR1_PATT_P_CLEAR_S 22
/** ADC_SAR2_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0;
* clear the pointer of pattern table for DIG ADC2 CTRL
*/
#define ADC_SAR2_PATT_P_CLEAR (BIT(23))
#define ADC_SAR2_PATT_P_CLEAR_M (ADC_SAR2_PATT_P_CLEAR_V << ADC_SAR2_PATT_P_CLEAR_S)
#define ADC_SAR2_PATT_P_CLEAR_V 0x00000001U
#define ADC_SAR2_PATT_P_CLEAR_S 23
/** ADC_DATA_SAR_SEL : R/W; bitpos: [24]; default: 0;
* 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
* resolution should not be larger than 11 bits.
*/
#define ADC_DATA_SAR_SEL (BIT(24))
#define ADC_DATA_SAR_SEL_M (ADC_DATA_SAR_SEL_V << ADC_DATA_SAR_SEL_S)
#define ADC_DATA_SAR_SEL_V 0x00000001U
#define ADC_DATA_SAR_SEL_S 24
/** ADC_DATA_TO_I2S : R/W; bitpos: [25]; default: 0;
* 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
*/
#define ADC_DATA_TO_I2S (BIT(25))
#define ADC_DATA_TO_I2S_M (ADC_DATA_TO_I2S_V << ADC_DATA_TO_I2S_S)
#define ADC_DATA_TO_I2S_V 0x00000001U
#define ADC_DATA_TO_I2S_S 25
/** ADC_XPD_SAR1_FORCE : R/W; bitpos: [27:26]; default: 0;
* force option to xpd sar1 blocks
*/
#define ADC_XPD_SAR1_FORCE 0x00000003U
#define ADC_XPD_SAR1_FORCE_M (ADC_XPD_SAR1_FORCE_V << ADC_XPD_SAR1_FORCE_S)
#define ADC_XPD_SAR1_FORCE_V 0x00000003U
#define ADC_XPD_SAR1_FORCE_S 26
/** ADC_XPD_SAR2_FORCE : R/W; bitpos: [29:28]; default: 0;
* force option to xpd sar2 blocks
*/
#define ADC_XPD_SAR2_FORCE 0x00000003U
#define ADC_XPD_SAR2_FORCE_M (ADC_XPD_SAR2_FORCE_V << ADC_XPD_SAR2_FORCE_S)
#define ADC_XPD_SAR2_FORCE_V 0x00000003U
#define ADC_XPD_SAR2_FORCE_S 28
/** ADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1;
* wait arbit signal stable after sar_done
*/
#define ADC_WAIT_ARB_CYCLE 0x00000003U
#define ADC_WAIT_ARB_CYCLE_M (ADC_WAIT_ARB_CYCLE_V << ADC_WAIT_ARB_CYCLE_S)
#define ADC_WAIT_ARB_CYCLE_V 0x00000003U
#define ADC_WAIT_ARB_CYCLE_S 30
/** ADC_CTRL2_REG register
* Register
*/
#define ADC_CTRL2_REG (DR_REG_ADC_BASE + 0x4)
/** ADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define ADC_MEAS_NUM_LIMIT (BIT(0))
#define ADC_MEAS_NUM_LIMIT_M (ADC_MEAS_NUM_LIMIT_V << ADC_MEAS_NUM_LIMIT_S)
#define ADC_MEAS_NUM_LIMIT_V 0x00000001U
#define ADC_MEAS_NUM_LIMIT_S 0
/** ADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255;
* max conversion number
*/
#define ADC_MAX_MEAS_NUM 0x000000FFU
#define ADC_MAX_MEAS_NUM_M (ADC_MAX_MEAS_NUM_V << ADC_MAX_MEAS_NUM_S)
#define ADC_MAX_MEAS_NUM_V 0x000000FFU
#define ADC_MAX_MEAS_NUM_S 1
/** ADC_SAR1_INV : R/W; bitpos: [9]; default: 0;
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
*/
#define ADC_SAR1_INV (BIT(9))
#define ADC_SAR1_INV_M (ADC_SAR1_INV_V << ADC_SAR1_INV_S)
#define ADC_SAR1_INV_V 0x00000001U
#define ADC_SAR1_INV_S 9
/** ADC_SAR2_INV : R/W; bitpos: [10]; default: 0;
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
*/
#define ADC_SAR2_INV (BIT(10))
#define ADC_SAR2_INV_M (ADC_SAR2_INV_V << ADC_SAR2_INV_S)
#define ADC_SAR2_INV_V 0x00000001U
#define ADC_SAR2_INV_S 10
/** ADC_TIMER_SEL : R/W; bitpos: [11]; default: 0;
* 1: select saradc timer 0: i2s_ws trigger
*/
#define ADC_TIMER_SEL (BIT(11))
#define ADC_TIMER_SEL_M (ADC_TIMER_SEL_V << ADC_TIMER_SEL_S)
#define ADC_TIMER_SEL_V 0x00000001U
#define ADC_TIMER_SEL_S 11
/** ADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
#define ADC_TIMER_TARGET 0x00000FFFU
#define ADC_TIMER_TARGET_M (ADC_TIMER_TARGET_V << ADC_TIMER_TARGET_S)
#define ADC_TIMER_TARGET_V 0x00000FFFU
#define ADC_TIMER_TARGET_S 12
/** ADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
#define ADC_TIMER_EN (BIT(24))
#define ADC_TIMER_EN_M (ADC_TIMER_EN_V << ADC_TIMER_EN_S)
#define ADC_TIMER_EN_V 0x00000001U
#define ADC_TIMER_EN_S 24
/** ADC_FILTER_CTRL1_REG register
* Register
*/
#define ADC_FILTER_CTRL1_REG (DR_REG_ADC_BASE + 0x8)
/** ADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
* need_des
*/
#define ADC_FILTER_FACTOR1 0x00000007U
#define ADC_FILTER_FACTOR1_M (ADC_FILTER_FACTOR1_V << ADC_FILTER_FACTOR1_S)
#define ADC_FILTER_FACTOR1_V 0x00000007U
#define ADC_FILTER_FACTOR1_S 26
/** ADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
* need_des
*/
#define ADC_FILTER_FACTOR0 0x00000007U
#define ADC_FILTER_FACTOR0_M (ADC_FILTER_FACTOR0_V << ADC_FILTER_FACTOR0_S)
#define ADC_FILTER_FACTOR0_V 0x00000007U
#define ADC_FILTER_FACTOR0_S 29
/** ADC_SAR1_PATT_TAB1_REG register
* Register
*/
#define ADC_SAR1_PATT_TAB1_REG (DR_REG_ADC_BASE + 0x18)
/** ADC_SAR1_PATT_TAB1 : R/W; bitpos: [23:0]; default: 0;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
#define ADC_SAR1_PATT_TAB1 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB1_M (ADC_SAR1_PATT_TAB1_V << ADC_SAR1_PATT_TAB1_S)
#define ADC_SAR1_PATT_TAB1_V 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB1_S 0
/** ADC_SAR1_PATT_TAB2_REG register
* Register
*/
#define ADC_SAR1_PATT_TAB2_REG (DR_REG_ADC_BASE + 0x1c)
/** ADC_SAR1_PATT_TAB2 : R/W; bitpos: [23:0]; default: 0;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
#define ADC_SAR1_PATT_TAB2 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB2_M (ADC_SAR1_PATT_TAB2_V << ADC_SAR1_PATT_TAB2_S)
#define ADC_SAR1_PATT_TAB2_V 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB2_S 0
/** ADC_SAR1_PATT_TAB3_REG register
* Register
*/
#define ADC_SAR1_PATT_TAB3_REG (DR_REG_ADC_BASE + 0x20)
/** ADC_SAR1_PATT_TAB3 : R/W; bitpos: [23:0]; default: 0;
* Item 8 ~ 11 for pattern table 1 (each item one byte)
*/
#define ADC_SAR1_PATT_TAB3 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB3_M (ADC_SAR1_PATT_TAB3_V << ADC_SAR1_PATT_TAB3_S)
#define ADC_SAR1_PATT_TAB3_V 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB3_S 0
/** ADC_SAR1_PATT_TAB4_REG register
* Register
*/
#define ADC_SAR1_PATT_TAB4_REG (DR_REG_ADC_BASE + 0x24)
/** ADC_SAR1_PATT_TAB4 : R/W; bitpos: [23:0]; default: 0;
* Item 12 ~ 15 for pattern table 1 (each item one byte)
*/
#define ADC_SAR1_PATT_TAB4 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB4_M (ADC_SAR1_PATT_TAB4_V << ADC_SAR1_PATT_TAB4_S)
#define ADC_SAR1_PATT_TAB4_V 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB4_S 0
/** ADC_SAR2_PATT_TAB1_REG register
* Register
*/
#define ADC_SAR2_PATT_TAB1_REG (DR_REG_ADC_BASE + 0x28)
/** ADC_SAR2_PATT_TAB1 : R/W; bitpos: [23:0]; default: 0;
* item 0 ~ 3 for pattern table 2 (each item one byte)
*/
#define ADC_SAR2_PATT_TAB1 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB1_M (ADC_SAR2_PATT_TAB1_V << ADC_SAR2_PATT_TAB1_S)
#define ADC_SAR2_PATT_TAB1_V 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB1_S 0
/** ADC_SAR2_PATT_TAB2_REG register
* Register
*/
#define ADC_SAR2_PATT_TAB2_REG (DR_REG_ADC_BASE + 0x2c)
/** ADC_SAR2_PATT_TAB2 : R/W; bitpos: [23:0]; default: 0;
* Item 4 ~ 7 for pattern table 2 (each item one byte)
*/
#define ADC_SAR2_PATT_TAB2 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB2_M (ADC_SAR2_PATT_TAB2_V << ADC_SAR2_PATT_TAB2_S)
#define ADC_SAR2_PATT_TAB2_V 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB2_S 0
/** ADC_SAR2_PATT_TAB3_REG register
* Register
*/
#define ADC_SAR2_PATT_TAB3_REG (DR_REG_ADC_BASE + 0x30)
/** ADC_SAR2_PATT_TAB3 : R/W; bitpos: [23:0]; default: 0;
* Item 8 ~ 11 for pattern table 2 (each item one byte)
*/
#define ADC_SAR2_PATT_TAB3 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB3_M (ADC_SAR2_PATT_TAB3_V << ADC_SAR2_PATT_TAB3_S)
#define ADC_SAR2_PATT_TAB3_V 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB3_S 0
/** ADC_SAR2_PATT_TAB4_REG register
* Register
*/
#define ADC_SAR2_PATT_TAB4_REG (DR_REG_ADC_BASE + 0x34)
/** ADC_SAR2_PATT_TAB4 : R/W; bitpos: [23:0]; default: 0;
* Item 12 ~ 15 for pattern table 2 (each item one byte)
*/
#define ADC_SAR2_PATT_TAB4 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB4_M (ADC_SAR2_PATT_TAB4_V << ADC_SAR2_PATT_TAB4_S)
#define ADC_SAR2_PATT_TAB4_V 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB4_S 0
/** ADC_ARB_CTRL_REG register
* Register
*/
#define ADC_ARB_CTRL_REG (DR_REG_ADC_BASE + 0x38)
/** ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0;
* adc2 arbiter force to enableapb controller
*/
#define ADC_ARB_APB_FORCE (BIT(2))
#define ADC_ARB_APB_FORCE_M (ADC_ARB_APB_FORCE_V << ADC_ARB_APB_FORCE_S)
#define ADC_ARB_APB_FORCE_V 0x00000001U
#define ADC_ARB_APB_FORCE_S 2
/** ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0;
* adc2 arbiter force to enable rtc controller
*/
#define ADC_ARB_RTC_FORCE (BIT(3))
#define ADC_ARB_RTC_FORCE_M (ADC_ARB_RTC_FORCE_V << ADC_ARB_RTC_FORCE_S)
#define ADC_ARB_RTC_FORCE_V 0x00000001U
#define ADC_ARB_RTC_FORCE_S 3
/** ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0;
* adc2 arbiter force to enable wifi controller
*/
#define ADC_ARB_WIFI_FORCE (BIT(4))
#define ADC_ARB_WIFI_FORCE_M (ADC_ARB_WIFI_FORCE_V << ADC_ARB_WIFI_FORCE_S)
#define ADC_ARB_WIFI_FORCE_V 0x00000001U
#define ADC_ARB_WIFI_FORCE_S 4
/** ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0;
* adc2 arbiter force grant
*/
#define ADC_ARB_GRANT_FORCE (BIT(5))
#define ADC_ARB_GRANT_FORCE_M (ADC_ARB_GRANT_FORCE_V << ADC_ARB_GRANT_FORCE_S)
#define ADC_ARB_GRANT_FORCE_V 0x00000001U
#define ADC_ARB_GRANT_FORCE_S 5
/** ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0;
* Set adc2 arbiterapb priority
*/
#define ADC_ARB_APB_PRIORITY 0x00000003U
#define ADC_ARB_APB_PRIORITY_M (ADC_ARB_APB_PRIORITY_V << ADC_ARB_APB_PRIORITY_S)
#define ADC_ARB_APB_PRIORITY_V 0x00000003U
#define ADC_ARB_APB_PRIORITY_S 6
/** ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1;
* Set adc2 arbiter rtc priority
*/
#define ADC_ARB_RTC_PRIORITY 0x00000003U
#define ADC_ARB_RTC_PRIORITY_M (ADC_ARB_RTC_PRIORITY_V << ADC_ARB_RTC_PRIORITY_S)
#define ADC_ARB_RTC_PRIORITY_V 0x00000003U
#define ADC_ARB_RTC_PRIORITY_S 8
/** ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2;
* Set adc2 arbiter wifi priority
*/
#define ADC_ARB_WIFI_PRIORITY 0x00000003U
#define ADC_ARB_WIFI_PRIORITY_M (ADC_ARB_WIFI_PRIORITY_V << ADC_ARB_WIFI_PRIORITY_S)
#define ADC_ARB_WIFI_PRIORITY_V 0x00000003U
#define ADC_ARB_WIFI_PRIORITY_S 10
/** ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0;
* adc2 arbiter uses fixed priority
*/
#define ADC_ARB_FIX_PRIORITY (BIT(12))
#define ADC_ARB_FIX_PRIORITY_M (ADC_ARB_FIX_PRIORITY_V << ADC_ARB_FIX_PRIORITY_S)
#define ADC_ARB_FIX_PRIORITY_V 0x00000001U
#define ADC_ARB_FIX_PRIORITY_S 12
/** ADC_FILTER_CTRL0_REG register
* Register
*/
#define ADC_FILTER_CTRL0_REG (DR_REG_ADC_BASE + 0x3c)
/** ADC_FILTER_CHANNEL1 : R/W; bitpos: [18:14]; default: 13;
* need_des
*/
#define ADC_FILTER_CHANNEL1 0x0000001FU
#define ADC_FILTER_CHANNEL1_M (ADC_FILTER_CHANNEL1_V << ADC_FILTER_CHANNEL1_S)
#define ADC_FILTER_CHANNEL1_V 0x0000001FU
#define ADC_FILTER_CHANNEL1_S 14
/** ADC_FILTER_CHANNEL0 : R/W; bitpos: [23:19]; default: 13;
* apb_adc1_filter_factor
*/
#define ADC_FILTER_CHANNEL0 0x0000001FU
#define ADC_FILTER_CHANNEL0_M (ADC_FILTER_CHANNEL0_V << ADC_FILTER_CHANNEL0_S)
#define ADC_FILTER_CHANNEL0_V 0x0000001FU
#define ADC_FILTER_CHANNEL0_S 19
/** ADC_FILTER_RESET : R/W; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
#define ADC_FILTER_RESET (BIT(31))
#define ADC_FILTER_RESET_M (ADC_FILTER_RESET_V << ADC_FILTER_RESET_S)
#define ADC_FILTER_RESET_V 0x00000001U
#define ADC_FILTER_RESET_S 31
/** ADC_SAR1_DATA_STATUS_REG register
* Register
*/
#define ADC_SAR1_DATA_STATUS_REG (DR_REG_ADC_BASE + 0x40)
/** ADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0;
* need_des
*/
#define ADC_APB_SARADC1_DATA 0x0001FFFFU
#define ADC_APB_SARADC1_DATA_M (ADC_APB_SARADC1_DATA_V << ADC_APB_SARADC1_DATA_S)
#define ADC_APB_SARADC1_DATA_V 0x0001FFFFU
#define ADC_APB_SARADC1_DATA_S 0
/** ADC_THRES0_CTRL_REG register
* Register
*/
#define ADC_THRES0_CTRL_REG (DR_REG_ADC_BASE + 0x44)
/** ADC_THRES0_CHANNEL : R/W; bitpos: [4:0]; default: 13;
* need_des
*/
#define ADC_THRES0_CHANNEL 0x0000001FU
#define ADC_THRES0_CHANNEL_M (ADC_THRES0_CHANNEL_V << ADC_THRES0_CHANNEL_S)
#define ADC_THRES0_CHANNEL_V 0x0000001FU
#define ADC_THRES0_CHANNEL_S 0
/** ADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191;
* saradc1's thres0 monitor thres
*/
#define ADC_THRES0_HIGH 0x00001FFFU
#define ADC_THRES0_HIGH_M (ADC_THRES0_HIGH_V << ADC_THRES0_HIGH_S)
#define ADC_THRES0_HIGH_V 0x00001FFFU
#define ADC_THRES0_HIGH_S 5
/** ADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0;
* saradc1's thres0 monitor thres
*/
#define ADC_THRES0_LOW 0x00001FFFU
#define ADC_THRES0_LOW_M (ADC_THRES0_LOW_V << ADC_THRES0_LOW_S)
#define ADC_THRES0_LOW_V 0x00001FFFU
#define ADC_THRES0_LOW_S 18
/** ADC_THRES1_CTRL_REG register
* Register
*/
#define ADC_THRES1_CTRL_REG (DR_REG_ADC_BASE + 0x48)
/** ADC_THRES1_CHANNEL : R/W; bitpos: [4:0]; default: 13;
* need_des
*/
#define ADC_THRES1_CHANNEL 0x0000001FU
#define ADC_THRES1_CHANNEL_M (ADC_THRES1_CHANNEL_V << ADC_THRES1_CHANNEL_S)
#define ADC_THRES1_CHANNEL_V 0x0000001FU
#define ADC_THRES1_CHANNEL_S 0
/** ADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191;
* saradc1's thres0 monitor thres
*/
#define ADC_THRES1_HIGH 0x00001FFFU
#define ADC_THRES1_HIGH_M (ADC_THRES1_HIGH_V << ADC_THRES1_HIGH_S)
#define ADC_THRES1_HIGH_V 0x00001FFFU
#define ADC_THRES1_HIGH_S 5
/** ADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0;
* saradc1's thres0 monitor thres
*/
#define ADC_THRES1_LOW 0x00001FFFU
#define ADC_THRES1_LOW_M (ADC_THRES1_LOW_V << ADC_THRES1_LOW_S)
#define ADC_THRES1_LOW_V 0x00001FFFU
#define ADC_THRES1_LOW_S 18
/** ADC_THRES_CTRL_REG register
* Register
*/
#define ADC_THRES_CTRL_REG (DR_REG_ADC_BASE + 0x4c)
/** ADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES_ALL_EN (BIT(27))
#define ADC_THRES_ALL_EN_M (ADC_THRES_ALL_EN_V << ADC_THRES_ALL_EN_S)
#define ADC_THRES_ALL_EN_V 0x00000001U
#define ADC_THRES_ALL_EN_S 27
/** ADC_THRES3_EN : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define ADC_THRES3_EN (BIT(28))
#define ADC_THRES3_EN_M (ADC_THRES3_EN_V << ADC_THRES3_EN_S)
#define ADC_THRES3_EN_V 0x00000001U
#define ADC_THRES3_EN_S 28
/** ADC_THRES2_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define ADC_THRES2_EN (BIT(29))
#define ADC_THRES2_EN_M (ADC_THRES2_EN_V << ADC_THRES2_EN_S)
#define ADC_THRES2_EN_V 0x00000001U
#define ADC_THRES2_EN_S 29
/** ADC_THRES1_EN : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define ADC_THRES1_EN (BIT(30))
#define ADC_THRES1_EN_M (ADC_THRES1_EN_V << ADC_THRES1_EN_S)
#define ADC_THRES1_EN_V 0x00000001U
#define ADC_THRES1_EN_S 30
/** ADC_THRES0_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_THRES0_EN (BIT(31))
#define ADC_THRES0_EN_M (ADC_THRES0_EN_V << ADC_THRES0_EN_S)
#define ADC_THRES0_EN_V 0x00000001U
#define ADC_THRES0_EN_S 31
/** ADC_INT_ENA_REG register
* Register
*/
#define ADC_INT_ENA_REG (DR_REG_ADC_BASE + 0x50)
/** ADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
* need_des
*/
#define ADC_THRES1_LOW_INT_ENA (BIT(26))
#define ADC_THRES1_LOW_INT_ENA_M (ADC_THRES1_LOW_INT_ENA_V << ADC_THRES1_LOW_INT_ENA_S)
#define ADC_THRES1_LOW_INT_ENA_V 0x00000001U
#define ADC_THRES1_LOW_INT_ENA_S 26
/** ADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES0_LOW_INT_ENA (BIT(27))
#define ADC_THRES0_LOW_INT_ENA_M (ADC_THRES0_LOW_INT_ENA_V << ADC_THRES0_LOW_INT_ENA_S)
#define ADC_THRES0_LOW_INT_ENA_V 0x00000001U
#define ADC_THRES0_LOW_INT_ENA_S 27
/** ADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define ADC_THRES1_HIGH_INT_ENA (BIT(28))
#define ADC_THRES1_HIGH_INT_ENA_M (ADC_THRES1_HIGH_INT_ENA_V << ADC_THRES1_HIGH_INT_ENA_S)
#define ADC_THRES1_HIGH_INT_ENA_V 0x00000001U
#define ADC_THRES1_HIGH_INT_ENA_S 28
/** ADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define ADC_THRES0_HIGH_INT_ENA (BIT(29))
#define ADC_THRES0_HIGH_INT_ENA_M (ADC_THRES0_HIGH_INT_ENA_V << ADC_THRES0_HIGH_INT_ENA_S)
#define ADC_THRES0_HIGH_INT_ENA_V 0x00000001U
#define ADC_THRES0_HIGH_INT_ENA_S 29
/** ADC_SAR2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define ADC_SAR2_DONE_INT_ENA (BIT(30))
#define ADC_SAR2_DONE_INT_ENA_M (ADC_SAR2_DONE_INT_ENA_V << ADC_SAR2_DONE_INT_ENA_S)
#define ADC_SAR2_DONE_INT_ENA_V 0x00000001U
#define ADC_SAR2_DONE_INT_ENA_S 30
/** ADC_SAR1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_SAR1_DONE_INT_ENA (BIT(31))
#define ADC_SAR1_DONE_INT_ENA_M (ADC_SAR1_DONE_INT_ENA_V << ADC_SAR1_DONE_INT_ENA_S)
#define ADC_SAR1_DONE_INT_ENA_V 0x00000001U
#define ADC_SAR1_DONE_INT_ENA_S 31
/** ADC_INT_RAW_REG register
* Register
*/
#define ADC_INT_RAW_REG (DR_REG_ADC_BASE + 0x54)
/** ADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
* need_des
*/
#define ADC_THRES1_LOW_INT_RAW (BIT(26))
#define ADC_THRES1_LOW_INT_RAW_M (ADC_THRES1_LOW_INT_RAW_V << ADC_THRES1_LOW_INT_RAW_S)
#define ADC_THRES1_LOW_INT_RAW_V 0x00000001U
#define ADC_THRES1_LOW_INT_RAW_S 26
/** ADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES0_LOW_INT_RAW (BIT(27))
#define ADC_THRES0_LOW_INT_RAW_M (ADC_THRES0_LOW_INT_RAW_V << ADC_THRES0_LOW_INT_RAW_S)
#define ADC_THRES0_LOW_INT_RAW_V 0x00000001U
#define ADC_THRES0_LOW_INT_RAW_S 27
/** ADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
* need_des
*/
#define ADC_THRES1_HIGH_INT_RAW (BIT(28))
#define ADC_THRES1_HIGH_INT_RAW_M (ADC_THRES1_HIGH_INT_RAW_V << ADC_THRES1_HIGH_INT_RAW_S)
#define ADC_THRES1_HIGH_INT_RAW_V 0x00000001U
#define ADC_THRES1_HIGH_INT_RAW_S 28
/** ADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
* need_des
*/
#define ADC_THRES0_HIGH_INT_RAW (BIT(29))
#define ADC_THRES0_HIGH_INT_RAW_M (ADC_THRES0_HIGH_INT_RAW_V << ADC_THRES0_HIGH_INT_RAW_S)
#define ADC_THRES0_HIGH_INT_RAW_V 0x00000001U
#define ADC_THRES0_HIGH_INT_RAW_S 29
/** ADC_SAR2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
#define ADC_SAR2_DONE_INT_RAW (BIT(30))
#define ADC_SAR2_DONE_INT_RAW_M (ADC_SAR2_DONE_INT_RAW_V << ADC_SAR2_DONE_INT_RAW_S)
#define ADC_SAR2_DONE_INT_RAW_V 0x00000001U
#define ADC_SAR2_DONE_INT_RAW_S 30
/** ADC_SAR1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_SAR1_DONE_INT_RAW (BIT(31))
#define ADC_SAR1_DONE_INT_RAW_M (ADC_SAR1_DONE_INT_RAW_V << ADC_SAR1_DONE_INT_RAW_S)
#define ADC_SAR1_DONE_INT_RAW_V 0x00000001U
#define ADC_SAR1_DONE_INT_RAW_S 31
/** ADC_INT_ST_REG register
* Register
*/
#define ADC_INT_ST_REG (DR_REG_ADC_BASE + 0x58)
/** ADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
* need_des
*/
#define ADC_THRES1_LOW_INT_ST (BIT(26))
#define ADC_THRES1_LOW_INT_ST_M (ADC_THRES1_LOW_INT_ST_V << ADC_THRES1_LOW_INT_ST_S)
#define ADC_THRES1_LOW_INT_ST_V 0x00000001U
#define ADC_THRES1_LOW_INT_ST_S 26
/** ADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES0_LOW_INT_ST (BIT(27))
#define ADC_THRES0_LOW_INT_ST_M (ADC_THRES0_LOW_INT_ST_V << ADC_THRES0_LOW_INT_ST_S)
#define ADC_THRES0_LOW_INT_ST_V 0x00000001U
#define ADC_THRES0_LOW_INT_ST_S 27
/** ADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
* need_des
*/
#define ADC_THRES1_HIGH_INT_ST (BIT(28))
#define ADC_THRES1_HIGH_INT_ST_M (ADC_THRES1_HIGH_INT_ST_V << ADC_THRES1_HIGH_INT_ST_S)
#define ADC_THRES1_HIGH_INT_ST_V 0x00000001U
#define ADC_THRES1_HIGH_INT_ST_S 28
/** ADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
* need_des
*/
#define ADC_THRES0_HIGH_INT_ST (BIT(29))
#define ADC_THRES0_HIGH_INT_ST_M (ADC_THRES0_HIGH_INT_ST_V << ADC_THRES0_HIGH_INT_ST_S)
#define ADC_THRES0_HIGH_INT_ST_V 0x00000001U
#define ADC_THRES0_HIGH_INT_ST_S 29
/** ADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define ADC_APB_SARADC2_DONE_INT_ST (BIT(30))
#define ADC_APB_SARADC2_DONE_INT_ST_M (ADC_APB_SARADC2_DONE_INT_ST_V << ADC_APB_SARADC2_DONE_INT_ST_S)
#define ADC_APB_SARADC2_DONE_INT_ST_V 0x00000001U
#define ADC_APB_SARADC2_DONE_INT_ST_S 30
/** ADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_APB_SARADC1_DONE_INT_ST (BIT(31))
#define ADC_APB_SARADC1_DONE_INT_ST_M (ADC_APB_SARADC1_DONE_INT_ST_V << ADC_APB_SARADC1_DONE_INT_ST_S)
#define ADC_APB_SARADC1_DONE_INT_ST_V 0x00000001U
#define ADC_APB_SARADC1_DONE_INT_ST_S 31
/** ADC_INT_CLR_REG register
* Register
*/
#define ADC_INT_CLR_REG (DR_REG_ADC_BASE + 0x5c)
/** ADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
* need_des
*/
#define ADC_THRES1_LOW_INT_CLR (BIT(26))
#define ADC_THRES1_LOW_INT_CLR_M (ADC_THRES1_LOW_INT_CLR_V << ADC_THRES1_LOW_INT_CLR_S)
#define ADC_THRES1_LOW_INT_CLR_V 0x00000001U
#define ADC_THRES1_LOW_INT_CLR_S 26
/** ADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES0_LOW_INT_CLR (BIT(27))
#define ADC_THRES0_LOW_INT_CLR_M (ADC_THRES0_LOW_INT_CLR_V << ADC_THRES0_LOW_INT_CLR_S)
#define ADC_THRES0_LOW_INT_CLR_V 0x00000001U
#define ADC_THRES0_LOW_INT_CLR_S 27
/** ADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
* need_des
*/
#define ADC_THRES1_HIGH_INT_CLR (BIT(28))
#define ADC_THRES1_HIGH_INT_CLR_M (ADC_THRES1_HIGH_INT_CLR_V << ADC_THRES1_HIGH_INT_CLR_S)
#define ADC_THRES1_HIGH_INT_CLR_V 0x00000001U
#define ADC_THRES1_HIGH_INT_CLR_S 28
/** ADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
* need_des
*/
#define ADC_THRES0_HIGH_INT_CLR (BIT(29))
#define ADC_THRES0_HIGH_INT_CLR_M (ADC_THRES0_HIGH_INT_CLR_V << ADC_THRES0_HIGH_INT_CLR_S)
#define ADC_THRES0_HIGH_INT_CLR_V 0x00000001U
#define ADC_THRES0_HIGH_INT_CLR_S 29
/** ADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define ADC_APB_SARADC2_DONE_INT_CLR (BIT(30))
#define ADC_APB_SARADC2_DONE_INT_CLR_M (ADC_APB_SARADC2_DONE_INT_CLR_V << ADC_APB_SARADC2_DONE_INT_CLR_S)
#define ADC_APB_SARADC2_DONE_INT_CLR_V 0x00000001U
#define ADC_APB_SARADC2_DONE_INT_CLR_S 30
/** ADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_APB_SARADC1_DONE_INT_CLR (BIT(31))
#define ADC_APB_SARADC1_DONE_INT_CLR_M (ADC_APB_SARADC1_DONE_INT_CLR_V << ADC_APB_SARADC1_DONE_INT_CLR_S)
#define ADC_APB_SARADC1_DONE_INT_CLR_V 0x00000001U
#define ADC_APB_SARADC1_DONE_INT_CLR_S 31
/** ADC_DMA_CONF_REG register
* Register
*/
#define ADC_DMA_CONF_REG (DR_REG_ADC_BASE + 0x60)
/** ADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
#define ADC_APB_ADC_EOF_NUM 0x0000FFFFU
#define ADC_APB_ADC_EOF_NUM_M (ADC_APB_ADC_EOF_NUM_V << ADC_APB_ADC_EOF_NUM_S)
#define ADC_APB_ADC_EOF_NUM_V 0x0000FFFFU
#define ADC_APB_ADC_EOF_NUM_S 0
/** ADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0;
* reset_apb_adc_state
*/
#define ADC_APB_ADC_RESET_FSM (BIT(30))
#define ADC_APB_ADC_RESET_FSM_M (ADC_APB_ADC_RESET_FSM_V << ADC_APB_ADC_RESET_FSM_S)
#define ADC_APB_ADC_RESET_FSM_V 0x00000001U
#define ADC_APB_ADC_RESET_FSM_S 30
/** ADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
#define ADC_APB_ADC_TRANS (BIT(31))
#define ADC_APB_ADC_TRANS_M (ADC_APB_ADC_TRANS_V << ADC_APB_ADC_TRANS_S)
#define ADC_APB_ADC_TRANS_V 0x00000001U
#define ADC_APB_ADC_TRANS_S 31
/** ADC_SAR2_DATA_STATUS_REG register
* Register
*/
#define ADC_SAR2_DATA_STATUS_REG (DR_REG_ADC_BASE + 0x64)
/** ADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0;
* need_des
*/
#define ADC_APB_SARADC2_DATA 0x0001FFFFU
#define ADC_APB_SARADC2_DATA_M (ADC_APB_SARADC2_DATA_V << ADC_APB_SARADC2_DATA_S)
#define ADC_APB_SARADC2_DATA_V 0x0001FFFFU
#define ADC_APB_SARADC2_DATA_S 0
/** ADC_CALI_REG register
* Register
*/
#define ADC_CALI_REG (DR_REG_ADC_BASE + 0x68)
/** ADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768;
* need_des
*/
#define ADC_CALI_CFG 0x0001FFFFU
#define ADC_CALI_CFG_M (ADC_CALI_CFG_V << ADC_CALI_CFG_S)
#define ADC_CALI_CFG_V 0x0001FFFFU
#define ADC_CALI_CFG_S 0
/** ADC_RND_ECO_LOW_REG register
* Register
*/
#define ADC_RND_ECO_LOW_REG (DR_REG_ADC_BASE + 0x6c)
/** ADC_RND_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
* rnd eco low
*/
#define ADC_RND_ECO_LOW 0xFFFFFFFFU
#define ADC_RND_ECO_LOW_M (ADC_RND_ECO_LOW_V << ADC_RND_ECO_LOW_S)
#define ADC_RND_ECO_LOW_V 0xFFFFFFFFU
#define ADC_RND_ECO_LOW_S 0
/** ADC_RND_ECO_HIGH_REG register
* Register
*/
#define ADC_RND_ECO_HIGH_REG (DR_REG_ADC_BASE + 0x70)
/** ADC_RND_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
* rnd eco high
*/
#define ADC_RND_ECO_HIGH 0xFFFFFFFFU
#define ADC_RND_ECO_HIGH_M (ADC_RND_ECO_HIGH_V << ADC_RND_ECO_HIGH_S)
#define ADC_RND_ECO_HIGH_V 0xFFFFFFFFU
#define ADC_RND_ECO_HIGH_S 0
/** ADC_RND_ECO_CS_REG register
* Register
*/
#define ADC_RND_ECO_CS_REG (DR_REG_ADC_BASE + 0x74)
/** ADC_RND_ECO_EN : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define ADC_RND_ECO_EN (BIT(0))
#define ADC_RND_ECO_EN_M (ADC_RND_ECO_EN_V << ADC_RND_ECO_EN_S)
#define ADC_RND_ECO_EN_V 0x00000001U
#define ADC_RND_ECO_EN_S 0
/** ADC_RND_ECO_RESULT : RO; bitpos: [1]; default: 0;
* need_des
*/
#define ADC_RND_ECO_RESULT (BIT(1))
#define ADC_RND_ECO_RESULT_M (ADC_RND_ECO_RESULT_V << ADC_RND_ECO_RESULT_S)
#define ADC_RND_ECO_RESULT_V 0x00000001U
#define ADC_RND_ECO_RESULT_S 1
/** ADC_CTRL_DATE_REG register
* Register
*/
#define ADC_CTRL_DATE_REG (DR_REG_ADC_BASE + 0x3fc)
/** ADC_CTRL_DATE : R/W; bitpos: [30:0]; default: 35725920;
* need_des
*/
#define ADC_CTRL_DATE 0x7FFFFFFFU
#define ADC_CTRL_DATE_M (ADC_CTRL_DATE_V << ADC_CTRL_DATE_S)
#define ADC_CTRL_DATE_V 0x7FFFFFFFU
#define ADC_CTRL_DATE_S 0
/** ADC_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_CLK_EN (BIT(31))
#define ADC_CLK_EN_M (ADC_CLK_EN_V << ADC_CLK_EN_S)
#define ADC_CLK_EN_V 0x00000001U
#define ADC_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/register/hw_ver2/soc/adc_eco5_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configure Register */
/** Type of ctrl_reg register
* Register
*/
typedef union {
struct {
/** start_force : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t start_force:1;
/** start : R/W; bitpos: [1]; default: 0;
* need_des
*/
uint32_t start:1;
/** work_mode : R/W; bitpos: [3:2]; default: 0;
* 0: single mode, 1: double mode, 2: alternate mode
*/
uint32_t work_mode:2;
/** sar_sel : R/W; bitpos: [4]; default: 0;
* 0: SAR1, 1: SAR2, only work for single SAR mode
*/
uint32_t sar_sel:1;
/** sar_clk_gated : R/W; bitpos: [5]; default: 1;
* need_des
*/
uint32_t sar_clk_gated:1;
/** sar_clk_div : R/W; bitpos: [13:6]; default: 4;
* SAR clock divider
*/
uint32_t sar_clk_div:8;
/** sar1_patt_len : R/W; bitpos: [17:14]; default: 15;
* 0 ~ 15 means length 1 ~ 16
*/
uint32_t sar1_patt_len:4;
/** sar2_patt_len : R/W; bitpos: [21:18]; default: 15;
* 0 ~ 15 means length 1 ~ 16
*/
uint32_t sar2_patt_len:4;
/** sar1_patt_p_clear : R/W; bitpos: [22]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
uint32_t sar1_patt_p_clear:1;
/** sar2_patt_p_clear : R/W; bitpos: [23]; default: 0;
* clear the pointer of pattern table for DIG ADC2 CTRL
*/
uint32_t sar2_patt_p_clear:1;
/** data_sar_sel : R/W; bitpos: [24]; default: 0;
* 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
* resolution should not be larger than 11 bits.
*/
uint32_t data_sar_sel:1;
/** data_to_i2s : R/W; bitpos: [25]; default: 0;
* 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
*/
uint32_t data_to_i2s:1;
/** xpd_sar1_force : R/W; bitpos: [27:26]; default: 0;
* force option to xpd sar1 blocks
*/
uint32_t xpd_sar1_force:2;
/** xpd_sar2_force : R/W; bitpos: [29:28]; default: 0;
* force option to xpd sar2 blocks
*/
uint32_t xpd_sar2_force:2;
/** wait_arb_cycle : R/W; bitpos: [31:30]; default: 1;
* wait arbit signal stable after sar_done
*/
uint32_t wait_arb_cycle:2;
};
uint32_t val;
} adc_ctrl_reg_reg_t;
/** Type of ctrl2 register
* Register
*/
typedef union {
struct {
/** meas_num_limit : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t meas_num_limit:1;
/** max_meas_num : R/W; bitpos: [8:1]; default: 255;
* max conversion number
*/
uint32_t max_meas_num:8;
/** sar1_inv : R/W; bitpos: [9]; default: 0;
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
*/
uint32_t sar1_inv:1;
/** sar2_inv : R/W; bitpos: [10]; default: 0;
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
*/
uint32_t sar2_inv:1;
/** timer_sel : R/W; bitpos: [11]; default: 0;
* 1: select saradc timer 0: i2s_ws trigger
*/
uint32_t timer_sel:1;
/** timer_target : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
uint32_t timer_target:12;
/** timer_en : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
uint32_t timer_en:1;
uint32_t reserved_25:7;
};
uint32_t val;
} adc_ctrl2_reg_t;
/** Type of filter_ctrl1 register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** filter_factor1 : R/W; bitpos: [28:26]; default: 0;
* need_des
*/
uint32_t filter_factor1:3;
/** filter_factor0 : R/W; bitpos: [31:29]; default: 0;
* need_des
*/
uint32_t filter_factor0:3;
};
uint32_t val;
} adc_filter_ctrl1_reg_t;
/** Type of sar1_patt_tab1 register
* Register
*/
typedef union {
struct {
/** sar1_patt_tab1 : R/W; bitpos: [23:0]; default: 0;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
uint32_t sar1_patt_tab1:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar1_patt_tab1_reg_t;
/** Type of sar1_patt_tab2 register
* Register
*/
typedef union {
struct {
/** sar1_patt_tab2 : R/W; bitpos: [23:0]; default: 0;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
uint32_t sar1_patt_tab2:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar1_patt_tab2_reg_t;
/** Type of sar1_patt_tab3 register
* Register
*/
typedef union {
struct {
/** sar1_patt_tab3 : R/W; bitpos: [23:0]; default: 0;
* Item 8 ~ 11 for pattern table 1 (each item one byte)
*/
uint32_t sar1_patt_tab3:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar1_patt_tab3_reg_t;
/** Type of sar1_patt_tab4 register
* Register
*/
typedef union {
struct {
/** sar1_patt_tab4 : R/W; bitpos: [23:0]; default: 0;
* Item 12 ~ 15 for pattern table 1 (each item one byte)
*/
uint32_t sar1_patt_tab4:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar1_patt_tab4_reg_t;
/** Type of sar2_patt_tab1 register
* Register
*/
typedef union {
struct {
/** sar2_patt_tab1 : R/W; bitpos: [23:0]; default: 0;
* item 0 ~ 3 for pattern table 2 (each item one byte)
*/
uint32_t sar2_patt_tab1:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar2_patt_tab1_reg_t;
/** Type of sar2_patt_tab2 register
* Register
*/
typedef union {
struct {
/** sar2_patt_tab2 : R/W; bitpos: [23:0]; default: 0;
* Item 4 ~ 7 for pattern table 2 (each item one byte)
*/
uint32_t sar2_patt_tab2:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar2_patt_tab2_reg_t;
/** Type of sar2_patt_tab3 register
* Register
*/
typedef union {
struct {
/** sar2_patt_tab3 : R/W; bitpos: [23:0]; default: 0;
* Item 8 ~ 11 for pattern table 2 (each item one byte)
*/
uint32_t sar2_patt_tab3:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar2_patt_tab3_reg_t;
/** Type of sar2_patt_tab4 register
* Register
*/
typedef union {
struct {
/** sar2_patt_tab4 : R/W; bitpos: [23:0]; default: 0;
* Item 12 ~ 15 for pattern table 2 (each item one byte)
*/
uint32_t sar2_patt_tab4:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar2_patt_tab4_reg_t;
/** Type of arb_ctrl register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** arb_apb_force : R/W; bitpos: [2]; default: 0;
* adc2 arbiter force to enableapb controller
*/
uint32_t arb_apb_force:1;
/** arb_rtc_force : R/W; bitpos: [3]; default: 0;
* adc2 arbiter force to enable rtc controller
*/
uint32_t arb_rtc_force:1;
/** arb_wifi_force : R/W; bitpos: [4]; default: 0;
* adc2 arbiter force to enable wifi controller
*/
uint32_t arb_wifi_force:1;
/** arb_grant_force : R/W; bitpos: [5]; default: 0;
* adc2 arbiter force grant
*/
uint32_t arb_grant_force:1;
/** arb_apb_priority : R/W; bitpos: [7:6]; default: 0;
* Set adc2 arbiterapb priority
*/
uint32_t arb_apb_priority:2;
/** arb_rtc_priority : R/W; bitpos: [9:8]; default: 1;
* Set adc2 arbiter rtc priority
*/
uint32_t arb_rtc_priority:2;
/** arb_wifi_priority : R/W; bitpos: [11:10]; default: 2;
* Set adc2 arbiter wifi priority
*/
uint32_t arb_wifi_priority:2;
/** arb_fix_priority : R/W; bitpos: [12]; default: 0;
* adc2 arbiter uses fixed priority
*/
uint32_t arb_fix_priority:1;
uint32_t reserved_13:19;
};
uint32_t val;
} adc_arb_ctrl_reg_t;
/** Type of filter_ctrl0 register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:14;
/** filter_channel1 : R/W; bitpos: [18:14]; default: 13;
* need_des
*/
uint32_t filter_channel1:5;
/** filter_channel0 : R/W; bitpos: [23:19]; default: 13;
* apb_adc1_filter_factor
*/
uint32_t filter_channel0:5;
uint32_t reserved_24:7;
/** filter_reset : R/W; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
uint32_t filter_reset:1;
};
uint32_t val;
} adc_filter_ctrl0_reg_t;
/** Type of sar1_data_status register
* Register
*/
typedef union {
struct {
/** apb_saradc1_data : RO; bitpos: [16:0]; default: 0;
* need_des
*/
uint32_t apb_saradc1_data:17;
uint32_t reserved_17:15;
};
uint32_t val;
} adc_sar1_data_status_reg_t;
/** Type of thres0_ctrl register
* Register
*/
typedef union {
struct {
/** thres0_channel : R/W; bitpos: [4:0]; default: 13;
* need_des
*/
uint32_t thres0_channel:5;
/** thres0_high : R/W; bitpos: [17:5]; default: 8191;
* saradc1's thres0 monitor thres
*/
uint32_t thres0_high:13;
/** thres0_low : R/W; bitpos: [30:18]; default: 0;
* saradc1's thres0 monitor thres
*/
uint32_t thres0_low:13;
uint32_t reserved_31:1;
};
uint32_t val;
} adc_thres0_ctrl_reg_t;
/** Type of thres1_ctrl register
* Register
*/
typedef union {
struct {
/** thres1_channel : R/W; bitpos: [4:0]; default: 13;
* need_des
*/
uint32_t thres1_channel:5;
/** thres1_high : R/W; bitpos: [17:5]; default: 8191;
* saradc1's thres0 monitor thres
*/
uint32_t thres1_high:13;
/** thres1_low : R/W; bitpos: [30:18]; default: 0;
* saradc1's thres0 monitor thres
*/
uint32_t thres1_low:13;
uint32_t reserved_31:1;
};
uint32_t val;
} adc_thres1_ctrl_reg_t;
/** Type of thres_ctrl register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** thres_all_en : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres_all_en:1;
/** thres3_en : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t thres3_en:1;
/** thres2_en : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t thres2_en:1;
/** thres1_en : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t thres1_en:1;
/** thres0_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t thres0_en:1;
};
uint32_t val;
} adc_thres_ctrl_reg_t;
/** Type of int_ena register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
* need_des
*/
uint32_t thres1_low_int_ena:1;
/** thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres0_low_int_ena:1;
/** thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t thres1_high_int_ena:1;
/** thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t thres0_high_int_ena:1;
/** sar2_done_int_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t sar2_done_int_ena:1;
/** sar1_done_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t sar1_done_int_ena:1;
};
uint32_t val;
} adc_int_ena_reg_t;
/** Type of int_raw register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
* need_des
*/
uint32_t thres1_low_int_raw:1;
/** thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres0_low_int_raw:1;
/** thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
* need_des
*/
uint32_t thres1_high_int_raw:1;
/** thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
* need_des
*/
uint32_t thres0_high_int_raw:1;
/** sar2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t sar2_done_int_raw:1;
/** sar1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t sar1_done_int_raw:1;
};
uint32_t val;
} adc_int_raw_reg_t;
/** Type of int_st register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** thres1_low_int_st : RO; bitpos: [26]; default: 0;
* need_des
*/
uint32_t thres1_low_int_st:1;
/** thres0_low_int_st : RO; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres0_low_int_st:1;
/** thres1_high_int_st : RO; bitpos: [28]; default: 0;
* need_des
*/
uint32_t thres1_high_int_st:1;
/** thres0_high_int_st : RO; bitpos: [29]; default: 0;
* need_des
*/
uint32_t thres0_high_int_st:1;
/** apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t apb_saradc2_done_int_st:1;
/** apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t apb_saradc1_done_int_st:1;
};
uint32_t val;
} adc_int_st_reg_t;
/** Type of int_clr register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** thres1_low_int_clr : WT; bitpos: [26]; default: 0;
* need_des
*/
uint32_t thres1_low_int_clr:1;
/** thres0_low_int_clr : WT; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres0_low_int_clr:1;
/** thres1_high_int_clr : WT; bitpos: [28]; default: 0;
* need_des
*/
uint32_t thres1_high_int_clr:1;
/** thres0_high_int_clr : WT; bitpos: [29]; default: 0;
* need_des
*/
uint32_t thres0_high_int_clr:1;
/** apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t apb_saradc2_done_int_clr:1;
/** apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t apb_saradc1_done_int_clr:1;
};
uint32_t val;
} adc_int_clr_reg_t;
/** Type of dma_conf register
* Register
*/
typedef union {
struct {
/** apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
uint32_t apb_adc_eof_num:16;
uint32_t reserved_16:14;
/** apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0;
* reset_apb_adc_state
*/
uint32_t apb_adc_reset_fsm:1;
/** apb_adc_trans : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
uint32_t apb_adc_trans:1;
};
uint32_t val;
} adc_dma_conf_reg_t;
/** Type of sar2_data_status register
* Register
*/
typedef union {
struct {
/** apb_saradc2_data : RO; bitpos: [16:0]; default: 0;
* need_des
*/
uint32_t apb_saradc2_data:17;
uint32_t reserved_17:15;
};
uint32_t val;
} adc_sar2_data_status_reg_t;
/** Type of cali register
* Register
*/
typedef union {
struct {
/** cali_cfg : R/W; bitpos: [16:0]; default: 32768;
* need_des
*/
uint32_t cali_cfg:17;
uint32_t reserved_17:15;
};
uint32_t val;
} adc_cali_reg_t;
/** Type of rnd_eco_low register
* Register
*/
typedef union {
struct {
/** rnd_eco_low : R/W; bitpos: [31:0]; default: 0;
* rnd eco low
*/
uint32_t rnd_eco_low:32;
};
uint32_t val;
} adc_rnd_eco_low_reg_t;
/** Type of rnd_eco_high register
* Register
*/
typedef union {
struct {
/** rnd_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
* rnd eco high
*/
uint32_t rnd_eco_high:32;
};
uint32_t val;
} adc_rnd_eco_high_reg_t;
/** Type of rnd_eco_cs register
* Register
*/
typedef union {
struct {
/** rnd_eco_en : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t rnd_eco_en:1;
/** rnd_eco_result : RO; bitpos: [1]; default: 0;
* need_des
*/
uint32_t rnd_eco_result:1;
uint32_t reserved_2:30;
};
uint32_t val;
} adc_rnd_eco_cs_reg_t;
/** Type of ctrl_date register
* Register
*/
typedef union {
struct {
/** ctrl_date : R/W; bitpos: [30:0]; default: 35725920;
* need_des
*/
uint32_t ctrl_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} adc_ctrl_date_reg_t;
typedef struct {
volatile adc_ctrl_reg_reg_t ctrl_reg;
volatile adc_ctrl2_reg_t ctrl2;
volatile adc_filter_ctrl1_reg_t filter_ctrl1;
uint32_t reserved_00c[3];
volatile adc_sar1_patt_tab1_reg_t sar1_patt_tab1;
volatile adc_sar1_patt_tab2_reg_t sar1_patt_tab2;
volatile adc_sar1_patt_tab3_reg_t sar1_patt_tab3;
volatile adc_sar1_patt_tab4_reg_t sar1_patt_tab4;
volatile adc_sar2_patt_tab1_reg_t sar2_patt_tab1;
volatile adc_sar2_patt_tab2_reg_t sar2_patt_tab2;
volatile adc_sar2_patt_tab3_reg_t sar2_patt_tab3;
volatile adc_sar2_patt_tab4_reg_t sar2_patt_tab4;
volatile adc_arb_ctrl_reg_t arb_ctrl;
volatile adc_filter_ctrl0_reg_t filter_ctrl0;
volatile adc_sar1_data_status_reg_t sar1_data_status;
volatile adc_thres0_ctrl_reg_t thres0_ctrl;
volatile adc_thres1_ctrl_reg_t thres1_ctrl;
volatile adc_thres_ctrl_reg_t thres_ctrl;
volatile adc_int_ena_reg_t int_ena;
volatile adc_int_raw_reg_t int_raw;
volatile adc_int_st_reg_t int_st;
volatile adc_int_clr_reg_t int_clr;
volatile adc_dma_conf_reg_t dma_conf;
volatile adc_sar2_data_status_reg_t sar2_data_status;
volatile adc_cali_reg_t cali;
volatile adc_rnd_eco_low_reg_t rnd_eco_low;
volatile adc_rnd_eco_high_reg_t rnd_eco_high;
volatile adc_rnd_eco_cs_reg_t rnd_eco_cs;
uint32_t reserved_078[225];
volatile adc_ctrl_date_reg_t ctrl_date;
} adc_dev_t;
extern adc_dev_t ADC;
#ifndef __cplusplus
_Static_assert(sizeof(adc_dev_t) == 0x400, "Invalid size of adc_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

809
components/soc/esp32p4/register/hw_ver2/soc/adc_reg.h Normal file
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@@ -0,0 +1,809 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
// TODO: IDF-13426
/** ADC_CTRL_REG_REG register
* Register
*/
#define ADC_CTRL_REG_REG (DR_REG_ADC_BASE + 0x0)
/** ADC_START_FORCE : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define ADC_START_FORCE (BIT(0))
#define ADC_START_FORCE_M (ADC_START_FORCE_V << ADC_START_FORCE_S)
#define ADC_START_FORCE_V 0x00000001U
#define ADC_START_FORCE_S 0
/** ADC_START : R/W; bitpos: [1]; default: 0;
* need_des
*/
#define ADC_START (BIT(1))
#define ADC_START_M (ADC_START_V << ADC_START_S)
#define ADC_START_V 0x00000001U
#define ADC_START_S 1
/** ADC_WORK_MODE : R/W; bitpos: [3:2]; default: 0;
* 0: single mode, 1: double mode, 2: alternate mode
*/
#define ADC_WORK_MODE 0x00000003U
#define ADC_WORK_MODE_M (ADC_WORK_MODE_V << ADC_WORK_MODE_S)
#define ADC_WORK_MODE_V 0x00000003U
#define ADC_WORK_MODE_S 2
/** ADC_SAR_SEL : R/W; bitpos: [4]; default: 0;
* 0: SAR1, 1: SAR2, only work for single SAR mode
*/
#define ADC_SAR_SEL (BIT(4))
#define ADC_SAR_SEL_M (ADC_SAR_SEL_V << ADC_SAR_SEL_S)
#define ADC_SAR_SEL_V 0x00000001U
#define ADC_SAR_SEL_S 4
/** ADC_SAR_CLK_GATED : R/W; bitpos: [5]; default: 1;
* need_des
*/
#define ADC_SAR_CLK_GATED (BIT(5))
#define ADC_SAR_CLK_GATED_M (ADC_SAR_CLK_GATED_V << ADC_SAR_CLK_GATED_S)
#define ADC_SAR_CLK_GATED_V 0x00000001U
#define ADC_SAR_CLK_GATED_S 5
/** ADC_SAR_CLK_DIV : R/W; bitpos: [13:6]; default: 4;
* SAR clock divider
*/
#define ADC_SAR_CLK_DIV 0x000000FFU
#define ADC_SAR_CLK_DIV_M (ADC_SAR_CLK_DIV_V << ADC_SAR_CLK_DIV_S)
#define ADC_SAR_CLK_DIV_V 0x000000FFU
#define ADC_SAR_CLK_DIV_S 6
/** ADC_SAR1_PATT_LEN : R/W; bitpos: [17:14]; default: 15;
* 0 ~ 15 means length 1 ~ 16
*/
#define ADC_SAR1_PATT_LEN 0x0000000FU
#define ADC_SAR1_PATT_LEN_M (ADC_SAR1_PATT_LEN_V << ADC_SAR1_PATT_LEN_S)
#define ADC_SAR1_PATT_LEN_V 0x0000000FU
#define ADC_SAR1_PATT_LEN_S 14
/** ADC_SAR2_PATT_LEN : R/W; bitpos: [21:18]; default: 15;
* 0 ~ 15 means length 1 ~ 16
*/
#define ADC_SAR2_PATT_LEN 0x0000000FU
#define ADC_SAR2_PATT_LEN_M (ADC_SAR2_PATT_LEN_V << ADC_SAR2_PATT_LEN_S)
#define ADC_SAR2_PATT_LEN_V 0x0000000FU
#define ADC_SAR2_PATT_LEN_S 18
/** ADC_SAR1_PATT_P_CLEAR : R/W; bitpos: [22]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
#define ADC_SAR1_PATT_P_CLEAR (BIT(22))
#define ADC_SAR1_PATT_P_CLEAR_M (ADC_SAR1_PATT_P_CLEAR_V << ADC_SAR1_PATT_P_CLEAR_S)
#define ADC_SAR1_PATT_P_CLEAR_V 0x00000001U
#define ADC_SAR1_PATT_P_CLEAR_S 22
/** ADC_SAR2_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0;
* clear the pointer of pattern table for DIG ADC2 CTRL
*/
#define ADC_SAR2_PATT_P_CLEAR (BIT(23))
#define ADC_SAR2_PATT_P_CLEAR_M (ADC_SAR2_PATT_P_CLEAR_V << ADC_SAR2_PATT_P_CLEAR_S)
#define ADC_SAR2_PATT_P_CLEAR_V 0x00000001U
#define ADC_SAR2_PATT_P_CLEAR_S 23
/** ADC_DATA_SAR_SEL : R/W; bitpos: [24]; default: 0;
* 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
* resolution should not be larger than 11 bits.
*/
#define ADC_DATA_SAR_SEL (BIT(24))
#define ADC_DATA_SAR_SEL_M (ADC_DATA_SAR_SEL_V << ADC_DATA_SAR_SEL_S)
#define ADC_DATA_SAR_SEL_V 0x00000001U
#define ADC_DATA_SAR_SEL_S 24
/** ADC_DATA_TO_I2S : R/W; bitpos: [25]; default: 0;
* 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
*/
#define ADC_DATA_TO_I2S (BIT(25))
#define ADC_DATA_TO_I2S_M (ADC_DATA_TO_I2S_V << ADC_DATA_TO_I2S_S)
#define ADC_DATA_TO_I2S_V 0x00000001U
#define ADC_DATA_TO_I2S_S 25
/** ADC_XPD_SAR1_FORCE : R/W; bitpos: [27:26]; default: 0;
* force option to xpd sar1 blocks
*/
#define ADC_XPD_SAR1_FORCE 0x00000003U
#define ADC_XPD_SAR1_FORCE_M (ADC_XPD_SAR1_FORCE_V << ADC_XPD_SAR1_FORCE_S)
#define ADC_XPD_SAR1_FORCE_V 0x00000003U
#define ADC_XPD_SAR1_FORCE_S 26
/** ADC_XPD_SAR2_FORCE : R/W; bitpos: [29:28]; default: 0;
* force option to xpd sar2 blocks
*/
#define ADC_XPD_SAR2_FORCE 0x00000003U
#define ADC_XPD_SAR2_FORCE_M (ADC_XPD_SAR2_FORCE_V << ADC_XPD_SAR2_FORCE_S)
#define ADC_XPD_SAR2_FORCE_V 0x00000003U
#define ADC_XPD_SAR2_FORCE_S 28
/** ADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1;
* wait arbit signal stable after sar_done
*/
#define ADC_WAIT_ARB_CYCLE 0x00000003U
#define ADC_WAIT_ARB_CYCLE_M (ADC_WAIT_ARB_CYCLE_V << ADC_WAIT_ARB_CYCLE_S)
#define ADC_WAIT_ARB_CYCLE_V 0x00000003U
#define ADC_WAIT_ARB_CYCLE_S 30
/** ADC_CTRL2_REG register
* Register
*/
#define ADC_CTRL2_REG (DR_REG_ADC_BASE + 0x4)
/** ADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define ADC_MEAS_NUM_LIMIT (BIT(0))
#define ADC_MEAS_NUM_LIMIT_M (ADC_MEAS_NUM_LIMIT_V << ADC_MEAS_NUM_LIMIT_S)
#define ADC_MEAS_NUM_LIMIT_V 0x00000001U
#define ADC_MEAS_NUM_LIMIT_S 0
/** ADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255;
* max conversion number
*/
#define ADC_MAX_MEAS_NUM 0x000000FFU
#define ADC_MAX_MEAS_NUM_M (ADC_MAX_MEAS_NUM_V << ADC_MAX_MEAS_NUM_S)
#define ADC_MAX_MEAS_NUM_V 0x000000FFU
#define ADC_MAX_MEAS_NUM_S 1
/** ADC_SAR1_INV : R/W; bitpos: [9]; default: 0;
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
*/
#define ADC_SAR1_INV (BIT(9))
#define ADC_SAR1_INV_M (ADC_SAR1_INV_V << ADC_SAR1_INV_S)
#define ADC_SAR1_INV_V 0x00000001U
#define ADC_SAR1_INV_S 9
/** ADC_SAR2_INV : R/W; bitpos: [10]; default: 0;
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
*/
#define ADC_SAR2_INV (BIT(10))
#define ADC_SAR2_INV_M (ADC_SAR2_INV_V << ADC_SAR2_INV_S)
#define ADC_SAR2_INV_V 0x00000001U
#define ADC_SAR2_INV_S 10
/** ADC_TIMER_SEL : R/W; bitpos: [11]; default: 0;
* 1: select saradc timer 0: i2s_ws trigger
*/
#define ADC_TIMER_SEL (BIT(11))
#define ADC_TIMER_SEL_M (ADC_TIMER_SEL_V << ADC_TIMER_SEL_S)
#define ADC_TIMER_SEL_V 0x00000001U
#define ADC_TIMER_SEL_S 11
/** ADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
#define ADC_TIMER_TARGET 0x00000FFFU
#define ADC_TIMER_TARGET_M (ADC_TIMER_TARGET_V << ADC_TIMER_TARGET_S)
#define ADC_TIMER_TARGET_V 0x00000FFFU
#define ADC_TIMER_TARGET_S 12
/** ADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
#define ADC_TIMER_EN (BIT(24))
#define ADC_TIMER_EN_M (ADC_TIMER_EN_V << ADC_TIMER_EN_S)
#define ADC_TIMER_EN_V 0x00000001U
#define ADC_TIMER_EN_S 24
/** ADC_FILTER_CTRL1_REG register
* Register
*/
#define ADC_FILTER_CTRL1_REG (DR_REG_ADC_BASE + 0x8)
/** ADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
* need_des
*/
#define ADC_FILTER_FACTOR1 0x00000007U
#define ADC_FILTER_FACTOR1_M (ADC_FILTER_FACTOR1_V << ADC_FILTER_FACTOR1_S)
#define ADC_FILTER_FACTOR1_V 0x00000007U
#define ADC_FILTER_FACTOR1_S 26
/** ADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
* need_des
*/
#define ADC_FILTER_FACTOR0 0x00000007U
#define ADC_FILTER_FACTOR0_M (ADC_FILTER_FACTOR0_V << ADC_FILTER_FACTOR0_S)
#define ADC_FILTER_FACTOR0_V 0x00000007U
#define ADC_FILTER_FACTOR0_S 29
#define ADC_FSM_WAIT_REG (DR_REG_ADC_BASE + 0xC)
/* ADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
/*description: need_des.*/
#define ADC_STANDBY_WAIT 0x000000FF
#define ADC_STANDBY_WAIT_M ((ADC_STANDBY_WAIT_V)<<(ADC_STANDBY_WAIT_S))
#define ADC_STANDBY_WAIT_V 0xFF
#define ADC_STANDBY_WAIT_S 16
/* ADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
/*description: need_des.*/
#define ADC_RSTB_WAIT 0x000000FF
#define ADC_RSTB_WAIT_M ((ADC_RSTB_WAIT_V)<<(ADC_RSTB_WAIT_S))
#define ADC_RSTB_WAIT_V 0xFF
#define ADC_RSTB_WAIT_S 8
/* ADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
/*description: need_des.*/
#define ADC_XPD_WAIT 0x000000FF
#define ADC_XPD_WAIT_M ((ADC_XPD_WAIT_V)<<(ADC_XPD_WAIT_S))
#define ADC_XPD_WAIT_V 0xFF
#define ADC_XPD_WAIT_S 0
/** ADC_SAR1_PATT_TAB1_REG register
* Register
*/
#define ADC_SAR1_PATT_TAB1_REG (DR_REG_ADC_BASE + 0x18)
/** ADC_SAR1_PATT_TAB1 : R/W; bitpos: [23:0]; default: 0;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
#define ADC_SAR1_PATT_TAB1 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB1_M (ADC_SAR1_PATT_TAB1_V << ADC_SAR1_PATT_TAB1_S)
#define ADC_SAR1_PATT_TAB1_V 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB1_S 0
/** ADC_SAR1_PATT_TAB2_REG register
* Register
*/
#define ADC_SAR1_PATT_TAB2_REG (DR_REG_ADC_BASE + 0x1c)
/** ADC_SAR1_PATT_TAB2 : R/W; bitpos: [23:0]; default: 0;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
#define ADC_SAR1_PATT_TAB2 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB2_M (ADC_SAR1_PATT_TAB2_V << ADC_SAR1_PATT_TAB2_S)
#define ADC_SAR1_PATT_TAB2_V 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB2_S 0
/** ADC_SAR1_PATT_TAB3_REG register
* Register
*/
#define ADC_SAR1_PATT_TAB3_REG (DR_REG_ADC_BASE + 0x20)
/** ADC_SAR1_PATT_TAB3 : R/W; bitpos: [23:0]; default: 0;
* Item 8 ~ 11 for pattern table 1 (each item one byte)
*/
#define ADC_SAR1_PATT_TAB3 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB3_M (ADC_SAR1_PATT_TAB3_V << ADC_SAR1_PATT_TAB3_S)
#define ADC_SAR1_PATT_TAB3_V 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB3_S 0
/** ADC_SAR1_PATT_TAB4_REG register
* Register
*/
#define ADC_SAR1_PATT_TAB4_REG (DR_REG_ADC_BASE + 0x24)
/** ADC_SAR1_PATT_TAB4 : R/W; bitpos: [23:0]; default: 0;
* Item 12 ~ 15 for pattern table 1 (each item one byte)
*/
#define ADC_SAR1_PATT_TAB4 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB4_M (ADC_SAR1_PATT_TAB4_V << ADC_SAR1_PATT_TAB4_S)
#define ADC_SAR1_PATT_TAB4_V 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB4_S 0
/** ADC_SAR2_PATT_TAB1_REG register
* Register
*/
#define ADC_SAR2_PATT_TAB1_REG (DR_REG_ADC_BASE + 0x28)
/** ADC_SAR2_PATT_TAB1 : R/W; bitpos: [23:0]; default: 0;
* item 0 ~ 3 for pattern table 2 (each item one byte)
*/
#define ADC_SAR2_PATT_TAB1 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB1_M (ADC_SAR2_PATT_TAB1_V << ADC_SAR2_PATT_TAB1_S)
#define ADC_SAR2_PATT_TAB1_V 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB1_S 0
/** ADC_SAR2_PATT_TAB2_REG register
* Register
*/
#define ADC_SAR2_PATT_TAB2_REG (DR_REG_ADC_BASE + 0x2c)
/** ADC_SAR2_PATT_TAB2 : R/W; bitpos: [23:0]; default: 0;
* Item 4 ~ 7 for pattern table 2 (each item one byte)
*/
#define ADC_SAR2_PATT_TAB2 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB2_M (ADC_SAR2_PATT_TAB2_V << ADC_SAR2_PATT_TAB2_S)
#define ADC_SAR2_PATT_TAB2_V 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB2_S 0
/** ADC_SAR2_PATT_TAB3_REG register
* Register
*/
#define ADC_SAR2_PATT_TAB3_REG (DR_REG_ADC_BASE + 0x30)
/** ADC_SAR2_PATT_TAB3 : R/W; bitpos: [23:0]; default: 0;
* Item 8 ~ 11 for pattern table 2 (each item one byte)
*/
#define ADC_SAR2_PATT_TAB3 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB3_M (ADC_SAR2_PATT_TAB3_V << ADC_SAR2_PATT_TAB3_S)
#define ADC_SAR2_PATT_TAB3_V 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB3_S 0
/** ADC_SAR2_PATT_TAB4_REG register
* Register
*/
#define ADC_SAR2_PATT_TAB4_REG (DR_REG_ADC_BASE + 0x34)
/** ADC_SAR2_PATT_TAB4 : R/W; bitpos: [23:0]; default: 0;
* Item 12 ~ 15 for pattern table 2 (each item one byte)
*/
#define ADC_SAR2_PATT_TAB4 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB4_M (ADC_SAR2_PATT_TAB4_V << ADC_SAR2_PATT_TAB4_S)
#define ADC_SAR2_PATT_TAB4_V 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB4_S 0
/** ADC_ARB_CTRL_REG register
* Register
*/
#define ADC_ARB_CTRL_REG (DR_REG_ADC_BASE + 0x38)
/** ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0;
* adc2 arbiter force to enableapb controller
*/
#define ADC_ARB_APB_FORCE (BIT(2))
#define ADC_ARB_APB_FORCE_M (ADC_ARB_APB_FORCE_V << ADC_ARB_APB_FORCE_S)
#define ADC_ARB_APB_FORCE_V 0x00000001U
#define ADC_ARB_APB_FORCE_S 2
/** ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0;
* adc2 arbiter force to enable rtc controller
*/
#define ADC_ARB_RTC_FORCE (BIT(3))
#define ADC_ARB_RTC_FORCE_M (ADC_ARB_RTC_FORCE_V << ADC_ARB_RTC_FORCE_S)
#define ADC_ARB_RTC_FORCE_V 0x00000001U
#define ADC_ARB_RTC_FORCE_S 3
/** ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0;
* adc2 arbiter force to enable wifi controller
*/
#define ADC_ARB_WIFI_FORCE (BIT(4))
#define ADC_ARB_WIFI_FORCE_M (ADC_ARB_WIFI_FORCE_V << ADC_ARB_WIFI_FORCE_S)
#define ADC_ARB_WIFI_FORCE_V 0x00000001U
#define ADC_ARB_WIFI_FORCE_S 4
/** ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0;
* adc2 arbiter force grant
*/
#define ADC_ARB_GRANT_FORCE (BIT(5))
#define ADC_ARB_GRANT_FORCE_M (ADC_ARB_GRANT_FORCE_V << ADC_ARB_GRANT_FORCE_S)
#define ADC_ARB_GRANT_FORCE_V 0x00000001U
#define ADC_ARB_GRANT_FORCE_S 5
/** ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0;
* Set adc2 arbiterapb priority
*/
#define ADC_ARB_APB_PRIORITY 0x00000003U
#define ADC_ARB_APB_PRIORITY_M (ADC_ARB_APB_PRIORITY_V << ADC_ARB_APB_PRIORITY_S)
#define ADC_ARB_APB_PRIORITY_V 0x00000003U
#define ADC_ARB_APB_PRIORITY_S 6
/** ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1;
* Set adc2 arbiter rtc priority
*/
#define ADC_ARB_RTC_PRIORITY 0x00000003U
#define ADC_ARB_RTC_PRIORITY_M (ADC_ARB_RTC_PRIORITY_V << ADC_ARB_RTC_PRIORITY_S)
#define ADC_ARB_RTC_PRIORITY_V 0x00000003U
#define ADC_ARB_RTC_PRIORITY_S 8
/** ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2;
* Set adc2 arbiter wifi priority
*/
#define ADC_ARB_WIFI_PRIORITY 0x00000003U
#define ADC_ARB_WIFI_PRIORITY_M (ADC_ARB_WIFI_PRIORITY_V << ADC_ARB_WIFI_PRIORITY_S)
#define ADC_ARB_WIFI_PRIORITY_V 0x00000003U
#define ADC_ARB_WIFI_PRIORITY_S 10
/** ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0;
* adc2 arbiter uses fixed priority
*/
#define ADC_ARB_FIX_PRIORITY (BIT(12))
#define ADC_ARB_FIX_PRIORITY_M (ADC_ARB_FIX_PRIORITY_V << ADC_ARB_FIX_PRIORITY_S)
#define ADC_ARB_FIX_PRIORITY_V 0x00000001U
#define ADC_ARB_FIX_PRIORITY_S 12
/** ADC_FILTER_CTRL0_REG register
* Register
*/
#define ADC_FILTER_CTRL0_REG (DR_REG_ADC_BASE + 0x3c)
/** ADC_FILTER_CHANNEL1 : R/W; bitpos: [18:14]; default: 13;
* need_des
*/
#define ADC_FILTER_CHANNEL1 0x0000001FU
#define ADC_FILTER_CHANNEL1_M (ADC_FILTER_CHANNEL1_V << ADC_FILTER_CHANNEL1_S)
#define ADC_FILTER_CHANNEL1_V 0x0000001FU
#define ADC_FILTER_CHANNEL1_S 14
/** ADC_FILTER_CHANNEL0 : R/W; bitpos: [23:19]; default: 13;
* apb_adc1_filter_factor
*/
#define ADC_FILTER_CHANNEL0 0x0000001FU
#define ADC_FILTER_CHANNEL0_M (ADC_FILTER_CHANNEL0_V << ADC_FILTER_CHANNEL0_S)
#define ADC_FILTER_CHANNEL0_V 0x0000001FU
#define ADC_FILTER_CHANNEL0_S 19
/** ADC_FILTER_RESET : R/W; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
#define ADC_FILTER_RESET (BIT(31))
#define ADC_FILTER_RESET_M (ADC_FILTER_RESET_V << ADC_FILTER_RESET_S)
#define ADC_FILTER_RESET_V 0x00000001U
#define ADC_FILTER_RESET_S 31
/** ADC_SAR1_DATA_STATUS_REG register
* Register
*/
#define ADC_SAR1_DATA_STATUS_REG (DR_REG_ADC_BASE + 0x40)
/** ADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0;
* need_des
*/
#define ADC_APB_SARADC1_DATA 0x0001FFFFU
#define ADC_APB_SARADC1_DATA_M (ADC_APB_SARADC1_DATA_V << ADC_APB_SARADC1_DATA_S)
#define ADC_APB_SARADC1_DATA_V 0x0001FFFFU
#define ADC_APB_SARADC1_DATA_S 0
/** ADC_THRES0_CTRL_REG register
* Register
*/
#define ADC_THRES0_CTRL_REG (DR_REG_ADC_BASE + 0x44)
/** ADC_THRES0_CHANNEL : R/W; bitpos: [4:0]; default: 13;
* need_des
*/
#define ADC_THRES0_CHANNEL 0x0000001FU
#define ADC_THRES0_CHANNEL_M (ADC_THRES0_CHANNEL_V << ADC_THRES0_CHANNEL_S)
#define ADC_THRES0_CHANNEL_V 0x0000001FU
#define ADC_THRES0_CHANNEL_S 0
/** ADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191;
* saradc1's thres0 monitor thres
*/
#define ADC_THRES0_HIGH 0x00001FFFU
#define ADC_THRES0_HIGH_M (ADC_THRES0_HIGH_V << ADC_THRES0_HIGH_S)
#define ADC_THRES0_HIGH_V 0x00001FFFU
#define ADC_THRES0_HIGH_S 5
/** ADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0;
* saradc1's thres0 monitor thres
*/
#define ADC_THRES0_LOW 0x00001FFFU
#define ADC_THRES0_LOW_M (ADC_THRES0_LOW_V << ADC_THRES0_LOW_S)
#define ADC_THRES0_LOW_V 0x00001FFFU
#define ADC_THRES0_LOW_S 18
/** ADC_THRES1_CTRL_REG register
* Register
*/
#define ADC_THRES1_CTRL_REG (DR_REG_ADC_BASE + 0x48)
/** ADC_THRES1_CHANNEL : R/W; bitpos: [4:0]; default: 13;
* need_des
*/
#define ADC_THRES1_CHANNEL 0x0000001FU
#define ADC_THRES1_CHANNEL_M (ADC_THRES1_CHANNEL_V << ADC_THRES1_CHANNEL_S)
#define ADC_THRES1_CHANNEL_V 0x0000001FU
#define ADC_THRES1_CHANNEL_S 0
/** ADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191;
* saradc1's thres0 monitor thres
*/
#define ADC_THRES1_HIGH 0x00001FFFU
#define ADC_THRES1_HIGH_M (ADC_THRES1_HIGH_V << ADC_THRES1_HIGH_S)
#define ADC_THRES1_HIGH_V 0x00001FFFU
#define ADC_THRES1_HIGH_S 5
/** ADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0;
* saradc1's thres0 monitor thres
*/
#define ADC_THRES1_LOW 0x00001FFFU
#define ADC_THRES1_LOW_M (ADC_THRES1_LOW_V << ADC_THRES1_LOW_S)
#define ADC_THRES1_LOW_V 0x00001FFFU
#define ADC_THRES1_LOW_S 18
/** ADC_THRES_CTRL_REG register
* Register
*/
#define ADC_THRES_CTRL_REG (DR_REG_ADC_BASE + 0x4c)
/** ADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES_ALL_EN (BIT(27))
#define ADC_THRES_ALL_EN_M (ADC_THRES_ALL_EN_V << ADC_THRES_ALL_EN_S)
#define ADC_THRES_ALL_EN_V 0x00000001U
#define ADC_THRES_ALL_EN_S 27
/** ADC_THRES3_EN : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define ADC_THRES3_EN (BIT(28))
#define ADC_THRES3_EN_M (ADC_THRES3_EN_V << ADC_THRES3_EN_S)
#define ADC_THRES3_EN_V 0x00000001U
#define ADC_THRES3_EN_S 28
/** ADC_THRES2_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define ADC_THRES2_EN (BIT(29))
#define ADC_THRES2_EN_M (ADC_THRES2_EN_V << ADC_THRES2_EN_S)
#define ADC_THRES2_EN_V 0x00000001U
#define ADC_THRES2_EN_S 29
/** ADC_THRES1_EN : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define ADC_THRES1_EN (BIT(30))
#define ADC_THRES1_EN_M (ADC_THRES1_EN_V << ADC_THRES1_EN_S)
#define ADC_THRES1_EN_V 0x00000001U
#define ADC_THRES1_EN_S 30
/** ADC_THRES0_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_THRES0_EN (BIT(31))
#define ADC_THRES0_EN_M (ADC_THRES0_EN_V << ADC_THRES0_EN_S)
#define ADC_THRES0_EN_V 0x00000001U
#define ADC_THRES0_EN_S 31
/** ADC_INT_ENA_REG register
* Register
*/
#define ADC_INT_ENA_REG (DR_REG_ADC_BASE + 0x50)
/** ADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
* need_des
*/
#define ADC_THRES1_LOW_INT_ENA (BIT(26))
#define ADC_THRES1_LOW_INT_ENA_M (ADC_THRES1_LOW_INT_ENA_V << ADC_THRES1_LOW_INT_ENA_S)
#define ADC_THRES1_LOW_INT_ENA_V 0x00000001U
#define ADC_THRES1_LOW_INT_ENA_S 26
/** ADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES0_LOW_INT_ENA (BIT(27))
#define ADC_THRES0_LOW_INT_ENA_M (ADC_THRES0_LOW_INT_ENA_V << ADC_THRES0_LOW_INT_ENA_S)
#define ADC_THRES0_LOW_INT_ENA_V 0x00000001U
#define ADC_THRES0_LOW_INT_ENA_S 27
/** ADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define ADC_THRES1_HIGH_INT_ENA (BIT(28))
#define ADC_THRES1_HIGH_INT_ENA_M (ADC_THRES1_HIGH_INT_ENA_V << ADC_THRES1_HIGH_INT_ENA_S)
#define ADC_THRES1_HIGH_INT_ENA_V 0x00000001U
#define ADC_THRES1_HIGH_INT_ENA_S 28
/** ADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define ADC_THRES0_HIGH_INT_ENA (BIT(29))
#define ADC_THRES0_HIGH_INT_ENA_M (ADC_THRES0_HIGH_INT_ENA_V << ADC_THRES0_HIGH_INT_ENA_S)
#define ADC_THRES0_HIGH_INT_ENA_V 0x00000001U
#define ADC_THRES0_HIGH_INT_ENA_S 29
/** ADC_SAR2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define ADC_SAR2_DONE_INT_ENA (BIT(30))
#define ADC_SAR2_DONE_INT_ENA_M (ADC_SAR2_DONE_INT_ENA_V << ADC_SAR2_DONE_INT_ENA_S)
#define ADC_SAR2_DONE_INT_ENA_V 0x00000001U
#define ADC_SAR2_DONE_INT_ENA_S 30
/** ADC_SAR1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_SAR1_DONE_INT_ENA (BIT(31))
#define ADC_SAR1_DONE_INT_ENA_M (ADC_SAR1_DONE_INT_ENA_V << ADC_SAR1_DONE_INT_ENA_S)
#define ADC_SAR1_DONE_INT_ENA_V 0x00000001U
#define ADC_SAR1_DONE_INT_ENA_S 31
/** ADC_INT_RAW_REG register
* Register
*/
#define ADC_INT_RAW_REG (DR_REG_ADC_BASE + 0x54)
/** ADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
* need_des
*/
#define ADC_THRES1_LOW_INT_RAW (BIT(26))
#define ADC_THRES1_LOW_INT_RAW_M (ADC_THRES1_LOW_INT_RAW_V << ADC_THRES1_LOW_INT_RAW_S)
#define ADC_THRES1_LOW_INT_RAW_V 0x00000001U
#define ADC_THRES1_LOW_INT_RAW_S 26
/** ADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES0_LOW_INT_RAW (BIT(27))
#define ADC_THRES0_LOW_INT_RAW_M (ADC_THRES0_LOW_INT_RAW_V << ADC_THRES0_LOW_INT_RAW_S)
#define ADC_THRES0_LOW_INT_RAW_V 0x00000001U
#define ADC_THRES0_LOW_INT_RAW_S 27
/** ADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
* need_des
*/
#define ADC_THRES1_HIGH_INT_RAW (BIT(28))
#define ADC_THRES1_HIGH_INT_RAW_M (ADC_THRES1_HIGH_INT_RAW_V << ADC_THRES1_HIGH_INT_RAW_S)
#define ADC_THRES1_HIGH_INT_RAW_V 0x00000001U
#define ADC_THRES1_HIGH_INT_RAW_S 28
/** ADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
* need_des
*/
#define ADC_THRES0_HIGH_INT_RAW (BIT(29))
#define ADC_THRES0_HIGH_INT_RAW_M (ADC_THRES0_HIGH_INT_RAW_V << ADC_THRES0_HIGH_INT_RAW_S)
#define ADC_THRES0_HIGH_INT_RAW_V 0x00000001U
#define ADC_THRES0_HIGH_INT_RAW_S 29
/** ADC_SAR2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
#define ADC_SAR2_DONE_INT_RAW (BIT(30))
#define ADC_SAR2_DONE_INT_RAW_M (ADC_SAR2_DONE_INT_RAW_V << ADC_SAR2_DONE_INT_RAW_S)
#define ADC_SAR2_DONE_INT_RAW_V 0x00000001U
#define ADC_SAR2_DONE_INT_RAW_S 30
/** ADC_SAR1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_SAR1_DONE_INT_RAW (BIT(31))
#define ADC_SAR1_DONE_INT_RAW_M (ADC_SAR1_DONE_INT_RAW_V << ADC_SAR1_DONE_INT_RAW_S)
#define ADC_SAR1_DONE_INT_RAW_V 0x00000001U
#define ADC_SAR1_DONE_INT_RAW_S 31
/** ADC_INT_ST_REG register
* Register
*/
#define ADC_INT_ST_REG (DR_REG_ADC_BASE + 0x58)
/** ADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
* need_des
*/
#define ADC_THRES1_LOW_INT_ST (BIT(26))
#define ADC_THRES1_LOW_INT_ST_M (ADC_THRES1_LOW_INT_ST_V << ADC_THRES1_LOW_INT_ST_S)
#define ADC_THRES1_LOW_INT_ST_V 0x00000001U
#define ADC_THRES1_LOW_INT_ST_S 26
/** ADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES0_LOW_INT_ST (BIT(27))
#define ADC_THRES0_LOW_INT_ST_M (ADC_THRES0_LOW_INT_ST_V << ADC_THRES0_LOW_INT_ST_S)
#define ADC_THRES0_LOW_INT_ST_V 0x00000001U
#define ADC_THRES0_LOW_INT_ST_S 27
/** ADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
* need_des
*/
#define ADC_THRES1_HIGH_INT_ST (BIT(28))
#define ADC_THRES1_HIGH_INT_ST_M (ADC_THRES1_HIGH_INT_ST_V << ADC_THRES1_HIGH_INT_ST_S)
#define ADC_THRES1_HIGH_INT_ST_V 0x00000001U
#define ADC_THRES1_HIGH_INT_ST_S 28
/** ADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
* need_des
*/
#define ADC_THRES0_HIGH_INT_ST (BIT(29))
#define ADC_THRES0_HIGH_INT_ST_M (ADC_THRES0_HIGH_INT_ST_V << ADC_THRES0_HIGH_INT_ST_S)
#define ADC_THRES0_HIGH_INT_ST_V 0x00000001U
#define ADC_THRES0_HIGH_INT_ST_S 29
/** ADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define ADC_APB_SARADC2_DONE_INT_ST (BIT(30))
#define ADC_APB_SARADC2_DONE_INT_ST_M (ADC_APB_SARADC2_DONE_INT_ST_V << ADC_APB_SARADC2_DONE_INT_ST_S)
#define ADC_APB_SARADC2_DONE_INT_ST_V 0x00000001U
#define ADC_APB_SARADC2_DONE_INT_ST_S 30
/** ADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_APB_SARADC1_DONE_INT_ST (BIT(31))
#define ADC_APB_SARADC1_DONE_INT_ST_M (ADC_APB_SARADC1_DONE_INT_ST_V << ADC_APB_SARADC1_DONE_INT_ST_S)
#define ADC_APB_SARADC1_DONE_INT_ST_V 0x00000001U
#define ADC_APB_SARADC1_DONE_INT_ST_S 31
/** ADC_INT_CLR_REG register
* Register
*/
#define ADC_INT_CLR_REG (DR_REG_ADC_BASE + 0x5c)
/** ADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
* need_des
*/
#define ADC_THRES1_LOW_INT_CLR (BIT(26))
#define ADC_THRES1_LOW_INT_CLR_M (ADC_THRES1_LOW_INT_CLR_V << ADC_THRES1_LOW_INT_CLR_S)
#define ADC_THRES1_LOW_INT_CLR_V 0x00000001U
#define ADC_THRES1_LOW_INT_CLR_S 26
/** ADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES0_LOW_INT_CLR (BIT(27))
#define ADC_THRES0_LOW_INT_CLR_M (ADC_THRES0_LOW_INT_CLR_V << ADC_THRES0_LOW_INT_CLR_S)
#define ADC_THRES0_LOW_INT_CLR_V 0x00000001U
#define ADC_THRES0_LOW_INT_CLR_S 27
/** ADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
* need_des
*/
#define ADC_THRES1_HIGH_INT_CLR (BIT(28))
#define ADC_THRES1_HIGH_INT_CLR_M (ADC_THRES1_HIGH_INT_CLR_V << ADC_THRES1_HIGH_INT_CLR_S)
#define ADC_THRES1_HIGH_INT_CLR_V 0x00000001U
#define ADC_THRES1_HIGH_INT_CLR_S 28
/** ADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
* need_des
*/
#define ADC_THRES0_HIGH_INT_CLR (BIT(29))
#define ADC_THRES0_HIGH_INT_CLR_M (ADC_THRES0_HIGH_INT_CLR_V << ADC_THRES0_HIGH_INT_CLR_S)
#define ADC_THRES0_HIGH_INT_CLR_V 0x00000001U
#define ADC_THRES0_HIGH_INT_CLR_S 29
/** ADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define ADC_APB_SARADC2_DONE_INT_CLR (BIT(30))
#define ADC_APB_SARADC2_DONE_INT_CLR_M (ADC_APB_SARADC2_DONE_INT_CLR_V << ADC_APB_SARADC2_DONE_INT_CLR_S)
#define ADC_APB_SARADC2_DONE_INT_CLR_V 0x00000001U
#define ADC_APB_SARADC2_DONE_INT_CLR_S 30
/** ADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_APB_SARADC1_DONE_INT_CLR (BIT(31))
#define ADC_APB_SARADC1_DONE_INT_CLR_M (ADC_APB_SARADC1_DONE_INT_CLR_V << ADC_APB_SARADC1_DONE_INT_CLR_S)
#define ADC_APB_SARADC1_DONE_INT_CLR_V 0x00000001U
#define ADC_APB_SARADC1_DONE_INT_CLR_S 31
/** ADC_DMA_CONF_REG register
* Register
*/
#define ADC_DMA_CONF_REG (DR_REG_ADC_BASE + 0x60)
/** ADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
#define ADC_APB_ADC_EOF_NUM 0x0000FFFFU
#define ADC_APB_ADC_EOF_NUM_M (ADC_APB_ADC_EOF_NUM_V << ADC_APB_ADC_EOF_NUM_S)
#define ADC_APB_ADC_EOF_NUM_V 0x0000FFFFU
#define ADC_APB_ADC_EOF_NUM_S 0
/** ADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0;
* reset_apb_adc_state
*/
#define ADC_APB_ADC_RESET_FSM (BIT(30))
#define ADC_APB_ADC_RESET_FSM_M (ADC_APB_ADC_RESET_FSM_V << ADC_APB_ADC_RESET_FSM_S)
#define ADC_APB_ADC_RESET_FSM_V 0x00000001U
#define ADC_APB_ADC_RESET_FSM_S 30
/** ADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
#define ADC_APB_ADC_TRANS (BIT(31))
#define ADC_APB_ADC_TRANS_M (ADC_APB_ADC_TRANS_V << ADC_APB_ADC_TRANS_S)
#define ADC_APB_ADC_TRANS_V 0x00000001U
#define ADC_APB_ADC_TRANS_S 31
/** ADC_SAR2_DATA_STATUS_REG register
* Register
*/
#define ADC_SAR2_DATA_STATUS_REG (DR_REG_ADC_BASE + 0x64)
/** ADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0;
* need_des
*/
#define ADC_APB_SARADC2_DATA 0x0001FFFFU
#define ADC_APB_SARADC2_DATA_M (ADC_APB_SARADC2_DATA_V << ADC_APB_SARADC2_DATA_S)
#define ADC_APB_SARADC2_DATA_V 0x0001FFFFU
#define ADC_APB_SARADC2_DATA_S 0
/** ADC_CALI_REG register
* Register
*/
#define ADC_CALI_REG (DR_REG_ADC_BASE + 0x68)
/** ADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768;
* need_des
*/
#define ADC_CALI_CFG 0x0001FFFFU
#define ADC_CALI_CFG_M (ADC_CALI_CFG_V << ADC_CALI_CFG_S)
#define ADC_CALI_CFG_V 0x0001FFFFU
#define ADC_CALI_CFG_S 0
/** ADC_RND_ECO_LOW_REG register
* Register
*/
#define ADC_RND_ECO_LOW_REG (DR_REG_ADC_BASE + 0x6c)
/** ADC_RND_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
* rnd eco low
*/
#define ADC_RND_ECO_LOW 0xFFFFFFFFU
#define ADC_RND_ECO_LOW_M (ADC_RND_ECO_LOW_V << ADC_RND_ECO_LOW_S)
#define ADC_RND_ECO_LOW_V 0xFFFFFFFFU
#define ADC_RND_ECO_LOW_S 0
/** ADC_RND_ECO_HIGH_REG register
* Register
*/
#define ADC_RND_ECO_HIGH_REG (DR_REG_ADC_BASE + 0x70)
/** ADC_RND_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
* rnd eco high
*/
#define ADC_RND_ECO_HIGH 0xFFFFFFFFU
#define ADC_RND_ECO_HIGH_M (ADC_RND_ECO_HIGH_V << ADC_RND_ECO_HIGH_S)
#define ADC_RND_ECO_HIGH_V 0xFFFFFFFFU
#define ADC_RND_ECO_HIGH_S 0
/** ADC_RND_ECO_CS_REG register
* Register
*/
#define ADC_RND_ECO_CS_REG (DR_REG_ADC_BASE + 0x74)
/** ADC_RND_ECO_EN : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define ADC_RND_ECO_EN (BIT(0))
#define ADC_RND_ECO_EN_M (ADC_RND_ECO_EN_V << ADC_RND_ECO_EN_S)
#define ADC_RND_ECO_EN_V 0x00000001U
#define ADC_RND_ECO_EN_S 0
/** ADC_RND_ECO_RESULT : RO; bitpos: [1]; default: 0;
* need_des
*/
#define ADC_RND_ECO_RESULT (BIT(1))
#define ADC_RND_ECO_RESULT_M (ADC_RND_ECO_RESULT_V << ADC_RND_ECO_RESULT_S)
#define ADC_RND_ECO_RESULT_V 0x00000001U
#define ADC_RND_ECO_RESULT_S 1
/** ADC_CTRL_DATE_REG register
* Register
*/
#define ADC_CTRL_DATE_REG (DR_REG_ADC_BASE + 0x3fc)
/** ADC_CTRL_DATE : R/W; bitpos: [30:0]; default: 35725920;
* need_des
*/
#define ADC_CTRL_DATE 0x7FFFFFFFU
#define ADC_CTRL_DATE_M (ADC_CTRL_DATE_V << ADC_CTRL_DATE_S)
#define ADC_CTRL_DATE_V 0x7FFFFFFFU
#define ADC_CTRL_DATE_S 0
/** ADC_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_CLK_EN (BIT(31))
#define ADC_CLK_EN_M (ADC_CLK_EN_V << ADC_CLK_EN_S)
#define ADC_CLK_EN_V 0x00000001U
#define ADC_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/register/hw_ver2/soc/adc_struct.h Normal file
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@@ -0,0 +1,621 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
// TODO: IDF-13426
/** Group: Configure Register */
/** Type of ctrl_reg register
* Register
*/
typedef union {
struct {
/** start_force : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t start_force:1;
/** start : R/W; bitpos: [1]; default: 0;
* need_des
*/
uint32_t start:1;
/** work_mode : R/W; bitpos: [3:2]; default: 0;
* 0: single mode, 1: double mode, 2: alternate mode
*/
uint32_t work_mode:2;
/** sar_sel : R/W; bitpos: [4]; default: 0;
* 0: SAR1, 1: SAR2, only work for single SAR mode
*/
uint32_t sar_sel:1;
/** sar_clk_gated : R/W; bitpos: [5]; default: 1;
* need_des
*/
uint32_t sar_clk_gated:1;
/** sar_clk_div : R/W; bitpos: [13:6]; default: 4;
* SAR clock divider
*/
uint32_t sar_clk_div:8;
/** sar1_patt_len : R/W; bitpos: [17:14]; default: 15;
* 0 ~ 15 means length 1 ~ 16
*/
uint32_t sar1_patt_len:4;
/** sar2_patt_len : R/W; bitpos: [21:18]; default: 15;
* 0 ~ 15 means length 1 ~ 16
*/
uint32_t sar2_patt_len:4;
/** sar1_patt_p_clear : R/W; bitpos: [22]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
uint32_t sar1_patt_p_clear:1;
/** sar2_patt_p_clear : R/W; bitpos: [23]; default: 0;
* clear the pointer of pattern table for DIG ADC2 CTRL
*/
uint32_t sar2_patt_p_clear:1;
/** data_sar_sel : R/W; bitpos: [24]; default: 0;
* 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
* resolution should not be larger than 11 bits.
*/
uint32_t data_sar_sel:1;
/** data_to_i2s : R/W; bitpos: [25]; default: 0;
* 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
*/
uint32_t data_to_i2s:1;
/** xpd_sar1_force : R/W; bitpos: [27:26]; default: 0;
* force option to xpd sar1 blocks
*/
uint32_t xpd_sar1_force:2;
/** xpd_sar2_force : R/W; bitpos: [29:28]; default: 0;
* force option to xpd sar2 blocks
*/
uint32_t xpd_sar2_force:2;
/** wait_arb_cycle : R/W; bitpos: [31:30]; default: 1;
* wait arbit signal stable after sar_done
*/
uint32_t wait_arb_cycle:2;
};
uint32_t val;
} adc_ctrl_reg_reg_t;
/** Type of ctrl2 register
* Register
*/
typedef union {
struct {
/** meas_num_limit : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t meas_num_limit:1;
/** max_meas_num : R/W; bitpos: [8:1]; default: 255;
* max conversion number
*/
uint32_t max_meas_num:8;
/** sar1_inv : R/W; bitpos: [9]; default: 0;
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
*/
uint32_t sar1_inv:1;
/** sar2_inv : R/W; bitpos: [10]; default: 0;
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
*/
uint32_t sar2_inv:1;
/** timer_sel : R/W; bitpos: [11]; default: 0;
* 1: select saradc timer 0: i2s_ws trigger
*/
uint32_t timer_sel:1;
/** timer_target : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
uint32_t timer_target:12;
/** timer_en : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
uint32_t timer_en:1;
uint32_t reserved_25:7;
};
uint32_t val;
} adc_ctrl2_reg_t;
/** Type of filter_ctrl1 register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** filter_factor1 : R/W; bitpos: [28:26]; default: 0;
* need_des
*/
uint32_t filter_factor1:3;
/** filter_factor0 : R/W; bitpos: [31:29]; default: 0;
* need_des
*/
uint32_t filter_factor0:3;
};
uint32_t val;
} adc_filter_ctrl1_reg_t;
/** Type of filter_ctrl1 register
* Register
*/
typedef union {
struct {
uint32_t xpd_wait:8;
uint32_t rstb_wait:8;
uint32_t standby_wait:8;
uint32_t reserved24:8;
};
uint32_t val;
} adc_fsm_wait_reg_t;
/** Type of sar1_patt_tab register
* Register
*/
typedef union {
struct {
/** sar1_patt_tab : R/W; bitpos: [23:0]; default: 0;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
uint32_t sar1_patt_tab:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar1_patt_tab_reg_t;
/** Type of sar2_patt_tab1 register
* Register
*/
typedef union {
struct {
/** sar2_patt_tab : R/W; bitpos: [23:0]; default: 0;
* item 0 ~ 3 for pattern table 2 (each item one byte)
*/
uint32_t sar2_patt_tab:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar2_patt_tab_reg_t;
/** Type of arb_ctrl register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** arb_apb_force : R/W; bitpos: [2]; default: 0;
* adc2 arbiter force to enableapb controller
*/
uint32_t arb_apb_force:1;
/** arb_rtc_force : R/W; bitpos: [3]; default: 0;
* adc2 arbiter force to enable rtc controller
*/
uint32_t arb_rtc_force:1;
/** arb_wifi_force : R/W; bitpos: [4]; default: 0;
* adc2 arbiter force to enable wifi controller
*/
uint32_t arb_wifi_force:1;
/** arb_grant_force : R/W; bitpos: [5]; default: 0;
* adc2 arbiter force grant
*/
uint32_t arb_grant_force:1;
/** arb_apb_priority : R/W; bitpos: [7:6]; default: 0;
* Set adc2 arbiterapb priority
*/
uint32_t arb_apb_priority:2;
/** arb_rtc_priority : R/W; bitpos: [9:8]; default: 1;
* Set adc2 arbiter rtc priority
*/
uint32_t arb_rtc_priority:2;
/** arb_wifi_priority : R/W; bitpos: [11:10]; default: 2;
* Set adc2 arbiter wifi priority
*/
uint32_t arb_wifi_priority:2;
/** arb_fix_priority : R/W; bitpos: [12]; default: 0;
* adc2 arbiter uses fixed priority
*/
uint32_t arb_fix_priority:1;
uint32_t reserved_13:19;
};
uint32_t val;
} adc_arb_ctrl_reg_t;
/** Type of filter_ctrl0 register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:14;
/** filter_channel1 : R/W; bitpos: [18:14]; default: 13;
* need_des
*/
uint32_t filter_channel1:5;
/** filter_channel0 : R/W; bitpos: [23:19]; default: 13;
* apb_adc1_filter_factor
*/
uint32_t filter_channel0:5;
uint32_t reserved_24:7;
/** filter_reset : R/W; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
uint32_t filter_reset:1;
};
uint32_t val;
} adc_filter_ctrl0_reg_t;
/** Type of sar1_data_status register
* Register
*/
typedef union {
struct {
/** apb_saradc1_data : RO; bitpos: [16:0]; default: 0;
* need_des
*/
uint32_t apb_saradc1_data:17;
uint32_t reserved_17:15;
};
uint32_t val;
} adc_sar1_data_status_reg_t;
/** Type of thres0_ctrl register
* Register
*/
typedef union {
struct {
/** thres0_channel : R/W; bitpos: [4:0]; default: 13;
* need_des
*/
uint32_t thres0_channel:5;
/** thres0_high : R/W; bitpos: [17:5]; default: 8191;
* saradc1's thres0 monitor thres
*/
uint32_t thres0_high:13;
/** thres0_low : R/W; bitpos: [30:18]; default: 0;
* saradc1's thres0 monitor thres
*/
uint32_t thres0_low:13;
uint32_t reserved_31:1;
};
uint32_t val;
} adc_thres0_ctrl_reg_t;
/** Type of thres1_ctrl register
* Register
*/
typedef union {
struct {
/** thres1_channel : R/W; bitpos: [4:0]; default: 13;
* need_des
*/
uint32_t thres1_channel:5;
/** thres1_high : R/W; bitpos: [17:5]; default: 8191;
* saradc1's thres0 monitor thres
*/
uint32_t thres1_high:13;
/** thres1_low : R/W; bitpos: [30:18]; default: 0;
* saradc1's thres0 monitor thres
*/
uint32_t thres1_low:13;
uint32_t reserved_31:1;
};
uint32_t val;
} adc_thres1_ctrl_reg_t;
/** Type of thres_ctrl register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** thres_all_en : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres_all_en:1;
/** thres3_en : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t thres3_en:1;
/** thres2_en : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t thres2_en:1;
/** thres1_en : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t thres1_en:1;
/** thres0_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t thres0_en:1;
};
uint32_t val;
} adc_thres_ctrl_reg_t;
/** Type of int_ena register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
* need_des
*/
uint32_t thres1_low_int_ena:1;
/** thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres0_low_int_ena:1;
/** thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t thres1_high_int_ena:1;
/** thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t thres0_high_int_ena:1;
/** sar2_done_int_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t sar2_done_int_ena:1;
/** sar1_done_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t sar1_done_int_ena:1;
};
uint32_t val;
} adc_int_ena_reg_t;
/** Type of int_raw register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
* need_des
*/
uint32_t thres1_low_int_raw:1;
/** thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres0_low_int_raw:1;
/** thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
* need_des
*/
uint32_t thres1_high_int_raw:1;
/** thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
* need_des
*/
uint32_t thres0_high_int_raw:1;
/** sar2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t sar2_done_int_raw:1;
/** sar1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t sar1_done_int_raw:1;
};
uint32_t val;
} adc_int_raw_reg_t;
/** Type of int_st register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** thres1_low_int_st : RO; bitpos: [26]; default: 0;
* need_des
*/
uint32_t thres1_low_int_st:1;
/** thres0_low_int_st : RO; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres0_low_int_st:1;
/** thres1_high_int_st : RO; bitpos: [28]; default: 0;
* need_des
*/
uint32_t thres1_high_int_st:1;
/** thres0_high_int_st : RO; bitpos: [29]; default: 0;
* need_des
*/
uint32_t thres0_high_int_st:1;
/** apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t apb_saradc2_done_int_st:1;
/** apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t apb_saradc1_done_int_st:1;
};
uint32_t val;
} adc_int_st_reg_t;
/** Type of int_clr register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** thres1_low_int_clr : WT; bitpos: [26]; default: 0;
* need_des
*/
uint32_t thres1_low_int_clr:1;
/** thres0_low_int_clr : WT; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres0_low_int_clr:1;
/** thres1_high_int_clr : WT; bitpos: [28]; default: 0;
* need_des
*/
uint32_t thres1_high_int_clr:1;
/** thres0_high_int_clr : WT; bitpos: [29]; default: 0;
* need_des
*/
uint32_t thres0_high_int_clr:1;
/** apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t apb_saradc2_done_int_clr:1;
/** apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t apb_saradc1_done_int_clr:1;
};
uint32_t val;
} adc_int_clr_reg_t;
/** Type of dma_conf register
* Register
*/
typedef union {
struct {
/** apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
uint32_t apb_adc_eof_num:16;
uint32_t reserved_16:14;
/** apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0;
* reset_apb_adc_state
*/
uint32_t apb_adc_reset_fsm:1;
/** apb_adc_trans : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
uint32_t apb_adc_trans:1;
};
uint32_t val;
} adc_dma_conf_reg_t;
/** Type of sar2_data_status register
* Register
*/
typedef union {
struct {
/** apb_saradc2_data : RO; bitpos: [16:0]; default: 0;
* need_des
*/
uint32_t apb_saradc2_data:17;
uint32_t reserved_17:15;
};
uint32_t val;
} adc_sar2_data_status_reg_t;
/** Type of cali register
* Register
*/
typedef union {
struct {
/** cali_cfg : R/W; bitpos: [16:0]; default: 32768;
* need_des
*/
uint32_t cali_cfg:17;
uint32_t reserved_17:15;
};
uint32_t val;
} adc_cali_reg_t;
/** Type of rnd_eco_low register
* Register
*/
typedef union {
struct {
/** rnd_eco_low : R/W; bitpos: [31:0]; default: 0;
* rnd eco low
*/
uint32_t rnd_eco_low:32;
};
uint32_t val;
} adc_rnd_eco_low_reg_t;
/** Type of rnd_eco_high register
* Register
*/
typedef union {
struct {
/** rnd_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
* rnd eco high
*/
uint32_t rnd_eco_high:32;
};
uint32_t val;
} adc_rnd_eco_high_reg_t;
/** Type of rnd_eco_cs register
* Register
*/
typedef union {
struct {
/** rnd_eco_en : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t rnd_eco_en:1;
/** rnd_eco_result : RO; bitpos: [1]; default: 0;
* need_des
*/
uint32_t rnd_eco_result:1;
uint32_t reserved_2:30;
};
uint32_t val;
} adc_rnd_eco_cs_reg_t;
/** Type of ctrl_date register
* Register
*/
typedef union {
struct {
/** ctrl_date : R/W; bitpos: [30:0]; default: 35725920;
* need_des
*/
uint32_t ctrl_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} adc_ctrl_date_reg_t;
typedef struct {
volatile adc_ctrl_reg_reg_t ctrl_reg;
volatile adc_ctrl2_reg_t ctrl2;
volatile adc_filter_ctrl1_reg_t filter_ctrl1;
volatile adc_fsm_wait_reg_t fsm_wait;
uint32_t reserved_00c[2];
volatile adc_sar1_patt_tab_reg_t sar1_patt_tab[4];
volatile adc_sar2_patt_tab_reg_t sar2_patt_tab[4];
volatile adc_arb_ctrl_reg_t arb_ctrl;
volatile adc_filter_ctrl0_reg_t filter_ctrl0;
volatile adc_sar1_data_status_reg_t sar1_data_status;
volatile adc_thres0_ctrl_reg_t thres0_ctrl;
volatile adc_thres1_ctrl_reg_t thres1_ctrl;
volatile adc_thres_ctrl_reg_t thres_ctrl;
volatile adc_int_ena_reg_t int_ena;
volatile adc_int_raw_reg_t int_raw;
volatile adc_int_st_reg_t int_st;
volatile adc_int_clr_reg_t int_clr;
volatile adc_dma_conf_reg_t dma_conf;
volatile adc_sar2_data_status_reg_t sar2_data_status;
volatile adc_cali_reg_t cali;
volatile adc_rnd_eco_low_reg_t rnd_eco_low;
volatile adc_rnd_eco_high_reg_t rnd_eco_high;
volatile adc_rnd_eco_cs_reg_t rnd_eco_cs;
uint32_t reserved_078[225];
volatile adc_ctrl_date_reg_t ctrl_date;
} adc_dev_t;
extern adc_dev_t ADC;
#ifndef __cplusplus
_Static_assert(sizeof(adc_dev_t) == 0x400, "Invalid size of adc_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/register/hw_ver2/soc/aes_eco5_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** AES_KEY_0_REG register
* AES key data register 0
*/
#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_1_REG register
* AES key data register 1
*/
#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_2_REG register
* AES key data register 2
*/
#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_3_REG register
* AES key data register 3
*/
#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_4_REG register
* AES key data register 4
*/
#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_5_REG register
* AES key data register 5
*/
#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_6_REG register
* AES key data register 6
*/
#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_7_REG register
* AES key data register 7
*/
#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_TEXT_IN_0_REG register
* Source text data register 0
*/
#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_1_REG register
* Source text data register 1
*/
#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_2_REG register
* Source text data register 2
*/
#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_3_REG register
* Source text data register 3
*/
#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_OUT_0_REG register
* Result text data register 0
*/
#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_1_REG register
* Result text data register 1
*/
#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_2_REG register
* Result text data register 2
*/
#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_3_REG register
* Result text data register 3
*/
#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_MODE_REG register
* Defines key length and encryption / decryption
*/
#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
/** AES_MODE : R/W; bitpos: [2:0]; default: 0;
* Configures the key length and encryption / decryption of the AES accelerator.
* 0: AES-128 encryption
* 1: AES-192 encryption
* 2: AES-256 encryption
* 3: Reserved
* 4: AES-128 decryption
* 5: AES-192 decryption
* 6: AES-256 decryption
* 7: Reserved
*/
#define AES_MODE 0x00000007U
#define AES_MODE_M (AES_MODE_V << AES_MODE_S)
#define AES_MODE_V 0x00000007U
#define AES_MODE_S 0
/** AES_TRIGGER_REG register
* Operation start controlling register
*/
#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
/** AES_TRIGGER : WT; bitpos: [0]; default: 0;
* Configures whether or not to start AES operation.
* 0: No effect
* 1: Start
*/
#define AES_TRIGGER (BIT(0))
#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S)
#define AES_TRIGGER_V 0x00000001U
#define AES_TRIGGER_S 0
/** AES_STATE_REG register
* Operation status register
*/
#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
/** AES_STATE : RO; bitpos: [1:0]; default: 0;
* Represents the working status of the AES accelerator.
* In Typical AES working mode:
* 0: IDLE
* 1: WORK
* 2: No effect
* 3: No effect
* In DMA-AES working mode:
* 0: IDLE
* 1: WORK
* 2: DONE
* 3: No effect
*/
#define AES_STATE 0x00000003U
#define AES_STATE_M (AES_STATE_V << AES_STATE_S)
#define AES_STATE_V 0x00000003U
#define AES_STATE_S 0
/** AES_IV_MEM register
* The memory that stores initialization vector
*/
#define AES_IV_MEM (DR_REG_AES_BASE + 0x50)
#define AES_IV_MEM_SIZE_BYTES 16
/** AES_H_MEM register
* The memory that stores GCM hash subkey
*/
#define AES_H_MEM (DR_REG_AES_BASE + 0x60)
#define AES_H_MEM_SIZE_BYTES 16
/** AES_J0_MEM register
* The memory that stores J0
*/
#define AES_J0_MEM (DR_REG_AES_BASE + 0x70)
#define AES_J0_MEM_SIZE_BYTES 16
/** AES_T0_MEM register
* The memory that stores T0
*/
#define AES_T0_MEM (DR_REG_AES_BASE + 0x80)
#define AES_T0_MEM_SIZE_BYTES 16
/** AES_DMA_ENABLE_REG register
* Selects the working mode of the AES accelerator
*/
#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
* Configures the working mode of the AES accelerator.
* 0: Typical AES
* 1: DMA-AES
*/
#define AES_DMA_ENABLE (BIT(0))
#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
#define AES_DMA_ENABLE_V 0x00000001U
#define AES_DMA_ENABLE_S 0
/** AES_BLOCK_MODE_REG register
* Defines the block cipher mode
*/
#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
* Configures the block cipher mode of the AES accelerator operating under the DMA-AES
* working mode.
* 0: ECB (Electronic Code Block)
* 1: CBC (Cipher Block Chaining)
* 2: OFB (Output FeedBack)
* 3: CTR (Counter)
* 4: CFB8 (8-bit Cipher FeedBack)
* 5: CFB128 (128-bit Cipher FeedBack)
* 6: GCM
* 7: Reserved
*/
#define AES_BLOCK_MODE 0x00000007U
#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
#define AES_BLOCK_MODE_V 0x00000007U
#define AES_BLOCK_MODE_S 0
/** AES_BLOCK_NUM_REG register
* Block number configuration register
*/
#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
* Represents the Block Number of plaintext or ciphertext when the AES accelerator
* operates under the DMA-AES working mode. For details, see Section . "
*/
#define AES_BLOCK_NUM 0xFFFFFFFFU
#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
#define AES_BLOCK_NUM_V 0xFFFFFFFFU
#define AES_BLOCK_NUM_S 0
/** AES_INC_SEL_REG register
* Standard incrementing function register
*/
#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
/** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
* Configures the Standard Incrementing Function for CTR block operation.
* 0: INC_32
* 1: INC_128
*/
#define AES_INC_SEL (BIT(0))
#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S)
#define AES_INC_SEL_V 0x00000001U
#define AES_INC_SEL_S 0
/** AES_INT_CLEAR_REG register
* DMA-AES interrupt clear register
*/
#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear AES interrupt.
* 0: No effect
* 1: Clear
*/
#define AES_INT_CLEAR (BIT(0))
#define AES_INT_CLEAR_M (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
#define AES_INT_CLEAR_V 0x00000001U
#define AES_INT_CLEAR_S 0
/** AES_INT_ENA_REG register
* DMA-AES interrupt enable register
*/
#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
/** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable AES interrupt.
* 0: Disable
* 1: Enable
*/
#define AES_INT_ENA (BIT(0))
#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S)
#define AES_INT_ENA_V 0x00000001U
#define AES_INT_ENA_S 0
/** AES_DATE_REG register
* AES version control register
*/
#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
/** AES_DATE : R/W; bitpos: [27:0]; default: 36774000;
* This bits stores the version information of AES.
*/
#define AES_DATE 0x0FFFFFFFU
#define AES_DATE_M (AES_DATE_V << AES_DATE_S)
#define AES_DATE_V 0x0FFFFFFFU
#define AES_DATE_S 0
/** AES_DMA_EXIT_REG register
* Operation exit controlling register
*/
#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
* Configures whether or not to exit AES operation.
* 0: No effect
* 1: Exit
* Only valid for DMA-AES operation.
*/
#define AES_DMA_EXIT (BIT(0))
#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
#define AES_DMA_EXIT_V 0x00000001U
#define AES_DMA_EXIT_S 0
/** AES_RX_RESET_REG register
* AES-DMA reset rx-fifo register
*/
#define AES_RX_RESET_REG (DR_REG_AES_BASE + 0xc0)
/** AES_RX_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset rx_fifo under dma_aes working mode.
*/
#define AES_RX_RESET (BIT(0))
#define AES_RX_RESET_M (AES_RX_RESET_V << AES_RX_RESET_S)
#define AES_RX_RESET_V 0x00000001U
#define AES_RX_RESET_S 0
/** AES_TX_RESET_REG register
* AES-DMA reset tx-fifo register
*/
#define AES_TX_RESET_REG (DR_REG_AES_BASE + 0xc4)
/** AES_TX_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset tx_fifo under dma_aes working mode.
*/
#define AES_TX_RESET (BIT(0))
#define AES_TX_RESET_M (AES_TX_RESET_V << AES_TX_RESET_S)
#define AES_TX_RESET_V 0x00000001U
#define AES_TX_RESET_S 0
/** AES_PSEUDO_REG register
* AES PSEUDO function configure register
*/
#define AES_PSEUDO_REG (DR_REG_AES_BASE + 0xd0)
/** AES_PSEUDO_EN : R/W; bitpos: [0]; default: 0;
* This bit decides whether the pseudo round function is enable or not.
*/
#define AES_PSEUDO_EN (BIT(0))
#define AES_PSEUDO_EN_M (AES_PSEUDO_EN_V << AES_PSEUDO_EN_S)
#define AES_PSEUDO_EN_V 0x00000001U
#define AES_PSEUDO_EN_S 0
/** AES_PSEUDO_BASE : R/W; bitpos: [4:1]; default: 2;
* Those bits decides the basic number of pseudo round number.
*/
#define AES_PSEUDO_BASE 0x0000000FU
#define AES_PSEUDO_BASE_M (AES_PSEUDO_BASE_V << AES_PSEUDO_BASE_S)
#define AES_PSEUDO_BASE_V 0x0000000FU
#define AES_PSEUDO_BASE_S 1
/** AES_PSEUDO_INC : R/W; bitpos: [6:5]; default: 2;
* Those bits decides the increment number of pseudo round number
*/
#define AES_PSEUDO_INC 0x00000003U
#define AES_PSEUDO_INC_M (AES_PSEUDO_INC_V << AES_PSEUDO_INC_S)
#define AES_PSEUDO_INC_V 0x00000003U
#define AES_PSEUDO_INC_S 5
/** AES_PSEUDO_RNG_CNT : R/W; bitpos: [9:7]; default: 7;
* Those bits decides the update frequency of the pseudo-key.
*/
#define AES_PSEUDO_RNG_CNT 0x00000007U
#define AES_PSEUDO_RNG_CNT_M (AES_PSEUDO_RNG_CNT_V << AES_PSEUDO_RNG_CNT_S)
#define AES_PSEUDO_RNG_CNT_V 0x00000007U
#define AES_PSEUDO_RNG_CNT_S 7
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** AES_KEY_0_REG register
* Key material key_0 configure register
*/
#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_1_REG register
* Key material key_1 configure register
*/
#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
/** AES_KEY_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_1 that is a part of key material.
*/
#define AES_KEY_1 0xFFFFFFFFU
#define AES_KEY_1_M (AES_KEY_1_V << AES_KEY_1_S)
#define AES_KEY_1_V 0xFFFFFFFFU
#define AES_KEY_1_S 0
/** AES_KEY_2_REG register
* Key material key_2 configure register
*/
#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
/** AES_KEY_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_2 that is a part of key material.
*/
#define AES_KEY_2 0xFFFFFFFFU
#define AES_KEY_2_M (AES_KEY_2_V << AES_KEY_2_S)
#define AES_KEY_2_V 0xFFFFFFFFU
#define AES_KEY_2_S 0
/** AES_KEY_3_REG register
* Key material key_3 configure register
*/
#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
/** AES_KEY_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_3 that is a part of key material.
*/
#define AES_KEY_3 0xFFFFFFFFU
#define AES_KEY_3_M (AES_KEY_3_V << AES_KEY_3_S)
#define AES_KEY_3_V 0xFFFFFFFFU
#define AES_KEY_3_S 0
/** AES_KEY_4_REG register
* Key material key_4 configure register
*/
#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
/** AES_KEY_4 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_4 that is a part of key material.
*/
#define AES_KEY_4 0xFFFFFFFFU
#define AES_KEY_4_M (AES_KEY_4_V << AES_KEY_4_S)
#define AES_KEY_4_V 0xFFFFFFFFU
#define AES_KEY_4_S 0
/** AES_KEY_5_REG register
* Key material key_5 configure register
*/
#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
/** AES_KEY_5 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_5 that is a part of key material.
*/
#define AES_KEY_5 0xFFFFFFFFU
#define AES_KEY_5_M (AES_KEY_5_V << AES_KEY_5_S)
#define AES_KEY_5_V 0xFFFFFFFFU
#define AES_KEY_5_S 0
/** AES_KEY_6_REG register
* Key material key_6 configure register
*/
#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
/** AES_KEY_6 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_6 that is a part of key material.
*/
#define AES_KEY_6 0xFFFFFFFFU
#define AES_KEY_6_M (AES_KEY_6_V << AES_KEY_6_S)
#define AES_KEY_6_V 0xFFFFFFFFU
#define AES_KEY_6_S 0
/** AES_KEY_7_REG register
* Key material key_7 configure register
*/
#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
/** AES_KEY_7 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_7 that is a part of key material.
*/
#define AES_KEY_7 0xFFFFFFFFU
#define AES_KEY_7_M (AES_KEY_7_V << AES_KEY_7_S)
#define AES_KEY_7_V 0xFFFFFFFFU
#define AES_KEY_7_S 0
/** AES_TEXT_IN_0_REG register
* source text material text_in_0 configure register
*/
#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_1_REG register
* source text material text_in_1 configure register
*/
#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
/** AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_1 that is a part of source text material.
*/
#define AES_TEXT_IN_1 0xFFFFFFFFU
#define AES_TEXT_IN_1_M (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S)
#define AES_TEXT_IN_1_V 0xFFFFFFFFU
#define AES_TEXT_IN_1_S 0
/** AES_TEXT_IN_2_REG register
* source text material text_in_2 configure register
*/
#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
/** AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_2 that is a part of source text material.
*/
#define AES_TEXT_IN_2 0xFFFFFFFFU
#define AES_TEXT_IN_2_M (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S)
#define AES_TEXT_IN_2_V 0xFFFFFFFFU
#define AES_TEXT_IN_2_S 0
/** AES_TEXT_IN_3_REG register
* source text material text_in_3 configure register
*/
#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
/** AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_3 that is a part of source text material.
*/
#define AES_TEXT_IN_3 0xFFFFFFFFU
#define AES_TEXT_IN_3_M (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S)
#define AES_TEXT_IN_3_V 0xFFFFFFFFU
#define AES_TEXT_IN_3_S 0
/** AES_TEXT_OUT_0_REG register
* result text material text_out_0 configure register
*/
#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_1_REG register
* result text material text_out_1 configure register
*/
#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
/** AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_1 that is a part of result text material.
*/
#define AES_TEXT_OUT_1 0xFFFFFFFFU
#define AES_TEXT_OUT_1_M (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S)
#define AES_TEXT_OUT_1_V 0xFFFFFFFFU
#define AES_TEXT_OUT_1_S 0
/** AES_TEXT_OUT_2_REG register
* result text material text_out_2 configure register
*/
#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
/** AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_2 that is a part of result text material.
*/
#define AES_TEXT_OUT_2 0xFFFFFFFFU
#define AES_TEXT_OUT_2_M (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S)
#define AES_TEXT_OUT_2_V 0xFFFFFFFFU
#define AES_TEXT_OUT_2_S 0
/** AES_TEXT_OUT_3_REG register
* result text material text_out_3 configure register
*/
#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
/** AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_3 that is a part of result text material.
*/
#define AES_TEXT_OUT_3 0xFFFFFFFFU
#define AES_TEXT_OUT_3_M (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S)
#define AES_TEXT_OUT_3_V 0xFFFFFFFFU
#define AES_TEXT_OUT_3_S 0
/** AES_MODE_REG register
* AES Mode register
*/
#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
/** AES_MODE : R/W; bitpos: [2:0]; default: 0;
* This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
* Reserved, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: Reserved, 3'd6: AES-DE-256.
*/
#define AES_MODE 0x00000007U
#define AES_MODE_M (AES_MODE_V << AES_MODE_S)
#define AES_MODE_V 0x00000007U
#define AES_MODE_S 0
/** AES_ENDIAN_REG register
* AES Endian configure register
*/
#define AES_ENDIAN_REG (DR_REG_AES_BASE + 0x44)
/** AES_ENDIAN : R/W; bitpos: [5:0]; default: 0;
* endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out
* endian or out_stream endian
*/
#define AES_ENDIAN 0x0000003FU
#define AES_ENDIAN_M (AES_ENDIAN_V << AES_ENDIAN_S)
#define AES_ENDIAN_V 0x0000003FU
#define AES_ENDIAN_S 0
/** AES_TRIGGER_REG register
* AES trigger register
*/
#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
/** AES_TRIGGER : WT; bitpos: [0]; default: 0;
* Set this bit to start AES calculation.
*/
#define AES_TRIGGER (BIT(0))
#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S)
#define AES_TRIGGER_V 0x00000001U
#define AES_TRIGGER_S 0
/** AES_STATE_REG register
* AES state register
*/
#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
/** AES_STATE : RO; bitpos: [1:0]; default: 0;
* Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0:
* idle, 1: busy, 2: calculation_done.
*/
#define AES_STATE 0x00000003U
#define AES_STATE_M (AES_STATE_V << AES_STATE_S)
#define AES_STATE_V 0x00000003U
#define AES_STATE_S 0
/** AES_IV_MEM register
* The memory that stores initialization vector
*/
#define AES_IV_MEM (DR_REG_AES_BASE + 0x50)
#define AES_IV_MEM_SIZE_BYTES 16
/** AES_H_MEM register
* The memory that stores GCM hash subkey
*/
#define AES_H_MEM (DR_REG_AES_BASE + 0x60)
#define AES_H_MEM_SIZE_BYTES 16
/** AES_J0_MEM register
* The memory that stores J0
*/
#define AES_J0_MEM (DR_REG_AES_BASE + 0x70)
#define AES_J0_MEM_SIZE_BYTES 16
/** AES_T0_MEM register
* The memory that stores T0
*/
#define AES_T0_MEM (DR_REG_AES_BASE + 0x80)
#define AES_T0_MEM_SIZE_BYTES 16
/** AES_DMA_ENABLE_REG register
* DMA-AES working mode register
*/
#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
* 1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
*/
#define AES_DMA_ENABLE (BIT(0))
#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
#define AES_DMA_ENABLE_V 0x00000001U
#define AES_DMA_ENABLE_S 0
/** AES_BLOCK_MODE_REG register
* AES cipher block mode register
*/
#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
* Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB,
* 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
*/
#define AES_BLOCK_MODE 0x00000007U
#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
#define AES_BLOCK_MODE_V 0x00000007U
#define AES_BLOCK_MODE_S 0
/** AES_BLOCK_NUM_REG register
* AES block number register
*/
#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
* Those bits stores the number of Plaintext/ciphertext block.
*/
#define AES_BLOCK_NUM 0xFFFFFFFFU
#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
#define AES_BLOCK_NUM_V 0xFFFFFFFFU
#define AES_BLOCK_NUM_S 0
/** AES_INC_SEL_REG register
* Standard incrementing function configure register
*/
#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
/** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
* This bit decides the standard incrementing function. 0: INC32. 1: INC128.
*/
#define AES_INC_SEL (BIT(0))
#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S)
#define AES_INC_SEL_V 0x00000001U
#define AES_INC_SEL_S 0
/** AES_AAD_BLOCK_NUM_REG register
* Additional Authential Data block number register
*/
#define AES_AAD_BLOCK_NUM_REG (DR_REG_AES_BASE + 0xa0)
/** AES_AAD_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
* Those bits stores the number of AAD block.
*/
#define AES_AAD_BLOCK_NUM 0xFFFFFFFFU
#define AES_AAD_BLOCK_NUM_M (AES_AAD_BLOCK_NUM_V << AES_AAD_BLOCK_NUM_S)
#define AES_AAD_BLOCK_NUM_V 0xFFFFFFFFU
#define AES_AAD_BLOCK_NUM_S 0
/** AES_REMAINDER_BIT_NUM_REG register
* AES remainder bit number register
*/
#define AES_REMAINDER_BIT_NUM_REG (DR_REG_AES_BASE + 0xa4)
/** AES_REMAINDER_BIT_NUM : R/W; bitpos: [6:0]; default: 0;
* Those bits stores the number of remainder bit.
*/
#define AES_REMAINDER_BIT_NUM 0x0000007FU
#define AES_REMAINDER_BIT_NUM_M (AES_REMAINDER_BIT_NUM_V << AES_REMAINDER_BIT_NUM_S)
#define AES_REMAINDER_BIT_NUM_V 0x0000007FU
#define AES_REMAINDER_BIT_NUM_S 0
/** AES_CONTINUE_REG register
* AES continue register
*/
#define AES_CONTINUE_REG (DR_REG_AES_BASE + 0xa8)
/** AES_CONTINUE : WT; bitpos: [0]; default: 0;
* Set this bit to continue GCM operation.
*/
#define AES_CONTINUE (BIT(0))
#define AES_CONTINUE_M (AES_CONTINUE_V << AES_CONTINUE_S)
#define AES_CONTINUE_V 0x00000001U
#define AES_CONTINUE_S 0
/** AES_INT_CLEAR_REG register
* AES Interrupt clear register
*/
#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the AES interrupt.
*/
#define AES_INT_CLEAR (BIT(0))
#define AES_INT_CLEAR_M (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
#define AES_INT_CLEAR_V 0x00000001U
#define AES_INT_CLEAR_S 0
/** AES_INT_ENA_REG register
* AES Interrupt enable register
*/
#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
/** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
* Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
*/
#define AES_INT_ENA (BIT(0))
#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S)
#define AES_INT_ENA_V 0x00000001U
#define AES_INT_ENA_S 0
/** AES_DATE_REG register
* AES version control register
*/
#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
/** AES_DATE : R/W; bitpos: [29:0]; default: 538513936;
* This bits stores the version information of AES.
*/
#define AES_DATE 0x3FFFFFFFU
#define AES_DATE_M (AES_DATE_V << AES_DATE_S)
#define AES_DATE_V 0x3FFFFFFFU
#define AES_DATE_S 0
/** AES_DMA_EXIT_REG register
* AES-DMA exit config
*/
#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
* Set this register to leave calculation done stage. Recommend to use it after
* software finishes reading DMA's output buffer.
*/
#define AES_DMA_EXIT (BIT(0))
#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
#define AES_DMA_EXIT_V 0x00000001U
#define AES_DMA_EXIT_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Key Registers */
/** Type of key_n register
* AES key data register n
*/
typedef union {
struct {
/** key_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
uint32_t key_0:32;
};
uint32_t val;
} aes_key_n_reg_t;
/** Group: TEXT_IN Registers */
/** Type of text_in_n register
* Source text data register n
*/
typedef union {
struct {
/** text_in_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
uint32_t text_in_0:32;
};
uint32_t val;
} aes_text_in_n_reg_t;
/** Group: TEXT_OUT Registers */
/** Type of text_out_n register
* Result text data register n
*/
typedef union {
struct {
/** text_out_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
uint32_t text_out_0:32;
};
uint32_t val;
} aes_text_out_n_reg_t;
/** Group: Control / Configuration Registers */
/** Type of mode register
* Defines key length and encryption / decryption
*/
typedef union {
struct {
/** mode : R/W; bitpos: [2:0]; default: 0;
* Configures the key length and encryption / decryption of the AES accelerator.
* 0: AES-128 encryption
* 1: AES-192 encryption
* 2: AES-256 encryption
* 3: Reserved
* 4: AES-128 decryption
* 5: AES-192 decryption
* 6: AES-256 decryption
* 7: Reserved
*/
uint32_t mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} aes_mode_reg_t;
/** Type of trigger register
* Operation start controlling register
*/
typedef union {
struct {
/** trigger : WT; bitpos: [0]; default: 0;
* Configures whether or not to start AES operation.
* 0: No effect
* 1: Start
*/
uint32_t trigger:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_trigger_reg_t;
/** Type of dma_enable register
* Selects the working mode of the AES accelerator
*/
typedef union {
struct {
/** dma_enable : R/W; bitpos: [0]; default: 0;
* Configures the working mode of the AES accelerator.
* 0: Typical AES
* 1: DMA-AES
*/
uint32_t dma_enable:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_dma_enable_reg_t;
/** Type of block_mode register
* Defines the block cipher mode
*/
typedef union {
struct {
/** block_mode : R/W; bitpos: [2:0]; default: 0;
* Configures the block cipher mode of the AES accelerator operating under the DMA-AES
* working mode.
* 0: ECB (Electronic Code Block)
* 1: CBC (Cipher Block Chaining)
* 2: OFB (Output FeedBack)
* 3: CTR (Counter)
* 4: CFB8 (8-bit Cipher FeedBack)
* 5: CFB128 (128-bit Cipher FeedBack)
* 6: GCM
* 7: Reserved
*/
uint32_t block_mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} aes_block_mode_reg_t;
/** Type of block_num register
* Block number configuration register
*/
typedef union {
struct {
/** block_num : R/W; bitpos: [31:0]; default: 0;
* Represents the Block Number of plaintext or ciphertext when the AES accelerator
* operates under the DMA-AES working mode. For details, see Section . "
*/
uint32_t block_num:32;
};
uint32_t val;
} aes_block_num_reg_t;
/** Type of inc_sel register
* Standard incrementing function register
*/
typedef union {
struct {
/** inc_sel : R/W; bitpos: [0]; default: 0;
* Configures the Standard Incrementing Function for CTR block operation.
* 0: INC_32
* 1: INC_128
*/
uint32_t inc_sel:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_inc_sel_reg_t;
/** Type of dma_exit register
* Operation exit controlling register
*/
typedef union {
struct {
/** dma_exit : WT; bitpos: [0]; default: 0;
* Configures whether or not to exit AES operation.
* 0: No effect
* 1: Exit
* Only valid for DMA-AES operation.
*/
uint32_t dma_exit:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_dma_exit_reg_t;
/** Type of rx_reset register
* AES-DMA reset rx-fifo register
*/
typedef union {
struct {
/** rx_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset rx_fifo under dma_aes working mode.
*/
uint32_t rx_reset:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_rx_reset_reg_t;
/** Type of tx_reset register
* AES-DMA reset tx-fifo register
*/
typedef union {
struct {
/** tx_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset tx_fifo under dma_aes working mode.
*/
uint32_t tx_reset:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_tx_reset_reg_t;
/** Group: Configuration register */
/** Type of pseudo register
* AES PSEUDO function configure register
*/
typedef union {
struct {
/** pseudo_en : R/W; bitpos: [0]; default: 0;
* This bit decides whether the pseudo round function is enable or not.
*/
uint32_t pseudo_en:1;
/** pseudo_base : R/W; bitpos: [4:1]; default: 2;
* Those bits decides the basic number of pseudo round number.
*/
uint32_t pseudo_base:4;
/** pseudo_inc : R/W; bitpos: [6:5]; default: 2;
* Those bits decides the increment number of pseudo round number
*/
uint32_t pseudo_inc:2;
/** pseudo_rng_cnt : R/W; bitpos: [9:7]; default: 7;
* Those bits decides the update frequency of the pseudo-key.
*/
uint32_t pseudo_rng_cnt:3;
uint32_t reserved_10:22;
};
uint32_t val;
} aes_pseudo_reg_t;
/** Group: Status Register */
/** Type of state register
* Operation status register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* Represents the working status of the AES accelerator.
* In Typical AES working mode:
* 0: IDLE
* 1: WORK
* 2: No effect
* 3: No effect
* In DMA-AES working mode:
* 0: IDLE
* 1: WORK
* 2: DONE
* 3: No effect
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} aes_state_reg_t;
/** Group: memory type */
/** Group: Interrupt Registers */
/** Type of int_clear register
* DMA-AES interrupt clear register
*/
typedef union {
struct {
/** int_clear : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear AES interrupt.
* 0: No effect
* 1: Clear
*/
uint32_t int_clear:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_int_clear_reg_t;
/** Type of int_ena register
* DMA-AES interrupt enable register
*/
typedef union {
struct {
/** int_ena : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable AES interrupt.
* 0: Disable
* 1: Enable
*/
uint32_t int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_int_ena_reg_t;
/** Group: Version control register */
/** Type of date register
* AES version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36774000;
* This bits stores the version information of AES.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} aes_date_reg_t;
typedef struct {
volatile aes_key_n_reg_t key_n[8];
volatile aes_text_in_n_reg_t text_in_n[4];
volatile aes_text_out_n_reg_t text_out_n[4];
volatile aes_mode_reg_t mode;
uint32_t reserved_044;
volatile aes_trigger_reg_t trigger;
volatile aes_state_reg_t state;
volatile uint32_t iv[4];
volatile uint32_t h[4];
volatile uint32_t j0[4];
volatile uint32_t t0[4];
volatile aes_dma_enable_reg_t dma_enable;
volatile aes_block_mode_reg_t block_mode;
volatile aes_block_num_reg_t block_num;
volatile aes_inc_sel_reg_t inc_sel;
uint32_t reserved_0a0[3];
volatile aes_int_clear_reg_t int_clear;
volatile aes_int_ena_reg_t int_ena;
volatile aes_date_reg_t date;
volatile aes_dma_exit_reg_t dma_exit;
uint32_t reserved_0bc;
volatile aes_rx_reset_reg_t rx_reset;
volatile aes_tx_reset_reg_t tx_reset;
uint32_t reserved_0c8[2];
volatile aes_pseudo_reg_t pseudo;
} aes_dev_t;
extern aes_dev_t AES;
#ifndef __cplusplus
_Static_assert(sizeof(aes_dev_t) == 0xd4, "Invalid size of aes_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Control and configuration registers */
/** Type of tx_inst_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_inst_idx : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
uint32_t tx_inst_idx:3;
/** tx_inst_pos : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
uint32_t tx_inst_pos:4;
uint32_t reserved_7:25;
};
uint32_t val;
} bitscrambler_tx_inst_cfg0_reg_t;
/** Type of tx_inst_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_inst : R/W; bitpos: [31:0]; default: 4;
* write this bits to update instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG
*/
uint32_t tx_inst:32;
};
uint32_t val;
} bitscrambler_tx_inst_cfg1_reg_t;
/** Type of rx_inst_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_inst_idx : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
uint32_t rx_inst_idx:3;
/** rx_inst_pos : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
uint32_t rx_inst_pos:4;
uint32_t reserved_7:25;
};
uint32_t val;
} bitscrambler_rx_inst_cfg0_reg_t;
/** Type of rx_inst_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_inst : R/W; bitpos: [31:0]; default: 12;
* write this bits to update instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG
*/
uint32_t rx_inst:32;
};
uint32_t val;
} bitscrambler_rx_inst_cfg1_reg_t;
/** Type of tx_lut_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_lut_idx : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_tx_lut_mode
*/
uint32_t tx_lut_idx:11;
/** tx_lut_mode : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
uint32_t tx_lut_mode:2;
uint32_t reserved_13:19;
};
uint32_t val;
} bitscrambler_tx_lut_cfg0_reg_t;
/** Type of tx_lut_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_lut : R/W; bitpos: [31:0]; default: 20;
* write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
*/
uint32_t tx_lut:32;
};
uint32_t val;
} bitscrambler_tx_lut_cfg1_reg_t;
/** Type of rx_lut_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_lut_idx : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_rx_lut_mode
*/
uint32_t rx_lut_idx:11;
/** rx_lut_mode : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
uint32_t rx_lut_mode:2;
uint32_t reserved_13:19;
};
uint32_t val;
} bitscrambler_rx_lut_cfg0_reg_t;
/** Type of rx_lut_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_lut : R/W; bitpos: [31:0]; default: 28;
* write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
*/
uint32_t rx_lut:32;
};
uint32_t val;
} bitscrambler_rx_lut_cfg1_reg_t;
/** Group: Configuration registers */
/** Type of tx_tailing_bits register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
uint32_t tx_tailing_bits:16;
uint32_t reserved_16:16;
};
uint32_t val;
} bitscrambler_tx_tailing_bits_reg_t;
/** Type of rx_tailing_bits register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
uint32_t rx_tailing_bits:16;
uint32_t reserved_16:16;
};
uint32_t val;
} bitscrambler_rx_tailing_bits_reg_t;
/** Type of tx_ctrl register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_ena : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler tx
*/
uint32_t tx_ena:1;
/** tx_pause : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler tx core
*/
uint32_t tx_pause:1;
/** tx_halt : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler tx core
*/
uint32_t tx_halt:1;
/** tx_eof_mode : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler tx core EOF signal generating mode which is
* combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
* counter by write peripheral buffer
*/
uint32_t tx_eof_mode:1;
/** tx_cond_mode : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler tx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
uint32_t tx_cond_mode:1;
/** tx_fetch_mode : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instructions
*/
uint32_t tx_fetch_mode:1;
/** tx_halt_mode : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
uint32_t tx_halt_mode:1;
/** tx_rd_dummy : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler tx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
uint32_t tx_rd_dummy:1;
/** tx_fifo_rst : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler tx fifo
*/
uint32_t tx_fifo_rst:1;
uint32_t reserved_9:23;
};
uint32_t val;
} bitscrambler_tx_ctrl_reg_t;
/** Type of rx_ctrl register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_ena : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler rx
*/
uint32_t rx_ena:1;
/** rx_pause : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler rx core
*/
uint32_t rx_pause:1;
/** rx_halt : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler rx core
*/
uint32_t rx_halt:1;
/** rx_eof_mode : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler rx core EOF signal generating mode which is
* combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
* buffer, 0 counter by write dma fifo
*/
uint32_t rx_eof_mode:1;
/** rx_cond_mode : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler rx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
uint32_t rx_cond_mode:1;
/** rx_fetch_mode : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instructions
*/
uint32_t rx_fetch_mode:1;
/** rx_halt_mode : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
uint32_t rx_halt_mode:1;
/** rx_rd_dummy : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler rx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
uint32_t rx_rd_dummy:1;
/** rx_fifo_rst : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler rx fifo
*/
uint32_t rx_fifo_rst:1;
uint32_t reserved_9:23;
};
uint32_t val;
} bitscrambler_rx_ctrl_reg_t;
/** Type of sys register
* Control and configuration registers
*/
typedef union {
struct {
/** loop_mode : R/W; bitpos: [0]; default: 0;
* write this bit to set the bitscrambler tx loop back to DMA rx
*/
uint32_t loop_mode:1;
uint32_t reserved_1:30;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Reserved
*/
uint32_t clk_en:1;
};
uint32_t val;
} bitscrambler_sys_reg_t;
/** Group: Status registers */
/** Type of tx_state register
* Status registers
*/
typedef union {
struct {
/** tx_in_idle : RO; bitpos: [0]; default: 1;
* represents the bitscrambler tx core in halt mode
*/
uint32_t tx_in_idle:1;
/** tx_in_run : RO; bitpos: [1]; default: 0;
* represents the bitscrambler tx core in run mode
*/
uint32_t tx_in_run:1;
/** tx_in_wait : RO; bitpos: [2]; default: 0;
* represents the bitscrambler tx core in wait mode to wait write back done
*/
uint32_t tx_in_wait:1;
/** tx_in_pause : RO; bitpos: [3]; default: 0;
* represents the bitscrambler tx core in pause mode
*/
uint32_t tx_in_pause:1;
/** tx_fifo_empty : RO; bitpos: [4]; default: 0;
* represents the bitscrambler tx fifo in empty state
*/
uint32_t tx_fifo_empty:1;
uint32_t reserved_5:11;
/** tx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler tx core when get EOF
*/
uint32_t tx_eof_get_cnt:14;
/** tx_eof_overload : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler tx core
*/
uint32_t tx_eof_overload:1;
/** tx_eof_trace_clr : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_tx_eof_overload and
* reg_bitscrambler_tx_eof_get_cnt registers
*/
uint32_t tx_eof_trace_clr:1;
};
uint32_t val;
} bitscrambler_tx_state_reg_t;
/** Type of rx_state register
* Status registers
*/
typedef union {
struct {
/** rx_in_idle : RO; bitpos: [0]; default: 1;
* represents the bitscrambler rx core in halt mode
*/
uint32_t rx_in_idle:1;
/** rx_in_run : RO; bitpos: [1]; default: 0;
* represents the bitscrambler rx core in run mode
*/
uint32_t rx_in_run:1;
/** rx_in_wait : RO; bitpos: [2]; default: 0;
* represents the bitscrambler rx core in wait mode to wait write back done
*/
uint32_t rx_in_wait:1;
/** rx_in_pause : RO; bitpos: [3]; default: 0;
* represents the bitscrambler rx core in pause mode
*/
uint32_t rx_in_pause:1;
/** rx_fifo_full : RO; bitpos: [4]; default: 0;
* represents the bitscrambler rx fifo in full state
*/
uint32_t rx_fifo_full:1;
uint32_t reserved_5:11;
/** rx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler rx core when get EOF
*/
uint32_t rx_eof_get_cnt:14;
/** rx_eof_overload : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler rx core
*/
uint32_t rx_eof_overload:1;
/** rx_eof_trace_clr : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_rx_eof_overload and
* reg_bitscrambler_rx_eof_get_cnt registers
*/
uint32_t rx_eof_trace_clr:1;
};
uint32_t val;
} bitscrambler_rx_state_reg_t;
/** Group: Version register */
/** Type of version register
* Control and configuration registers
*/
typedef union {
struct {
/** bitscrambler_ver : R/W; bitpos: [27:0]; default: 36713024;
* Reserved
*/
uint32_t bitscrambler_ver:28;
uint32_t reserved_28:4;
};
uint32_t val;
} bitscrambler_version_reg_t;
typedef struct {
volatile bitscrambler_tx_inst_cfg0_reg_t tx_inst_cfg0;
volatile bitscrambler_tx_inst_cfg1_reg_t tx_inst_cfg1;
volatile bitscrambler_rx_inst_cfg0_reg_t rx_inst_cfg0;
volatile bitscrambler_rx_inst_cfg1_reg_t rx_inst_cfg1;
volatile bitscrambler_tx_lut_cfg0_reg_t tx_lut_cfg0;
volatile bitscrambler_tx_lut_cfg1_reg_t tx_lut_cfg1;
volatile bitscrambler_rx_lut_cfg0_reg_t rx_lut_cfg0;
volatile bitscrambler_rx_lut_cfg1_reg_t rx_lut_cfg1;
volatile bitscrambler_tx_tailing_bits_reg_t tx_tailing_bits;
volatile bitscrambler_rx_tailing_bits_reg_t rx_tailing_bits;
volatile bitscrambler_tx_ctrl_reg_t tx_ctrl;
volatile bitscrambler_rx_ctrl_reg_t rx_ctrl;
volatile bitscrambler_tx_state_reg_t tx_state;
volatile bitscrambler_rx_state_reg_t rx_state;
uint32_t reserved_038[48];
volatile bitscrambler_sys_reg_t sys;
volatile bitscrambler_version_reg_t version;
} bitscrambler_dev_t;
extern bitscrambler_dev_t BITSCRAMBLER;
#ifndef __cplusplus
_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** BITSCRAMBLER_TX_INST_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x0)
/** BITSCRAMBLER_TX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
#define BITSCRAMBLER_TX_INST_IDX 0x00000007U
#define BITSCRAMBLER_TX_INST_IDX_M (BITSCRAMBLER_TX_INST_IDX_V << BITSCRAMBLER_TX_INST_IDX_S)
#define BITSCRAMBLER_TX_INST_IDX_V 0x00000007U
#define BITSCRAMBLER_TX_INST_IDX_S 0
/** BITSCRAMBLER_TX_INST_POS : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
#define BITSCRAMBLER_TX_INST_POS 0x0000000FU
#define BITSCRAMBLER_TX_INST_POS_M (BITSCRAMBLER_TX_INST_POS_V << BITSCRAMBLER_TX_INST_POS_S)
#define BITSCRAMBLER_TX_INST_POS_V 0x0000000FU
#define BITSCRAMBLER_TX_INST_POS_S 3
/** BITSCRAMBLER_TX_INST_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x4)
/** BITSCRAMBLER_TX_INST : R/W; bitpos: [31:0]; default: 4;
* write this bits to update instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG
*/
#define BITSCRAMBLER_TX_INST 0xFFFFFFFFU
#define BITSCRAMBLER_TX_INST_M (BITSCRAMBLER_TX_INST_V << BITSCRAMBLER_TX_INST_S)
#define BITSCRAMBLER_TX_INST_V 0xFFFFFFFFU
#define BITSCRAMBLER_TX_INST_S 0
/** BITSCRAMBLER_RX_INST_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x8)
/** BITSCRAMBLER_RX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
#define BITSCRAMBLER_RX_INST_IDX 0x00000007U
#define BITSCRAMBLER_RX_INST_IDX_M (BITSCRAMBLER_RX_INST_IDX_V << BITSCRAMBLER_RX_INST_IDX_S)
#define BITSCRAMBLER_RX_INST_IDX_V 0x00000007U
#define BITSCRAMBLER_RX_INST_IDX_S 0
/** BITSCRAMBLER_RX_INST_POS : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
#define BITSCRAMBLER_RX_INST_POS 0x0000000FU
#define BITSCRAMBLER_RX_INST_POS_M (BITSCRAMBLER_RX_INST_POS_V << BITSCRAMBLER_RX_INST_POS_S)
#define BITSCRAMBLER_RX_INST_POS_V 0x0000000FU
#define BITSCRAMBLER_RX_INST_POS_S 3
/** BITSCRAMBLER_RX_INST_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0xc)
/** BITSCRAMBLER_RX_INST : R/W; bitpos: [31:0]; default: 12;
* write this bits to update instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG
*/
#define BITSCRAMBLER_RX_INST 0xFFFFFFFFU
#define BITSCRAMBLER_RX_INST_M (BITSCRAMBLER_RX_INST_V << BITSCRAMBLER_RX_INST_S)
#define BITSCRAMBLER_RX_INST_V 0xFFFFFFFFU
#define BITSCRAMBLER_RX_INST_S 0
/** BITSCRAMBLER_TX_LUT_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x10)
/** BITSCRAMBLER_TX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_tx_lut_mode
*/
#define BITSCRAMBLER_TX_LUT_IDX 0x000007FFU
#define BITSCRAMBLER_TX_LUT_IDX_M (BITSCRAMBLER_TX_LUT_IDX_V << BITSCRAMBLER_TX_LUT_IDX_S)
#define BITSCRAMBLER_TX_LUT_IDX_V 0x000007FFU
#define BITSCRAMBLER_TX_LUT_IDX_S 0
/** BITSCRAMBLER_TX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
#define BITSCRAMBLER_TX_LUT_MODE 0x00000003U
#define BITSCRAMBLER_TX_LUT_MODE_M (BITSCRAMBLER_TX_LUT_MODE_V << BITSCRAMBLER_TX_LUT_MODE_S)
#define BITSCRAMBLER_TX_LUT_MODE_V 0x00000003U
#define BITSCRAMBLER_TX_LUT_MODE_S 11
/** BITSCRAMBLER_TX_LUT_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x14)
/** BITSCRAMBLER_TX_LUT : R/W; bitpos: [31:0]; default: 20;
* write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
*/
#define BITSCRAMBLER_TX_LUT 0xFFFFFFFFU
#define BITSCRAMBLER_TX_LUT_M (BITSCRAMBLER_TX_LUT_V << BITSCRAMBLER_TX_LUT_S)
#define BITSCRAMBLER_TX_LUT_V 0xFFFFFFFFU
#define BITSCRAMBLER_TX_LUT_S 0
/** BITSCRAMBLER_RX_LUT_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x18)
/** BITSCRAMBLER_RX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_rx_lut_mode
*/
#define BITSCRAMBLER_RX_LUT_IDX 0x000007FFU
#define BITSCRAMBLER_RX_LUT_IDX_M (BITSCRAMBLER_RX_LUT_IDX_V << BITSCRAMBLER_RX_LUT_IDX_S)
#define BITSCRAMBLER_RX_LUT_IDX_V 0x000007FFU
#define BITSCRAMBLER_RX_LUT_IDX_S 0
/** BITSCRAMBLER_RX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
#define BITSCRAMBLER_RX_LUT_MODE 0x00000003U
#define BITSCRAMBLER_RX_LUT_MODE_M (BITSCRAMBLER_RX_LUT_MODE_V << BITSCRAMBLER_RX_LUT_MODE_S)
#define BITSCRAMBLER_RX_LUT_MODE_V 0x00000003U
#define BITSCRAMBLER_RX_LUT_MODE_S 11
/** BITSCRAMBLER_RX_LUT_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x1c)
/** BITSCRAMBLER_RX_LUT : R/W; bitpos: [31:0]; default: 28;
* write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
*/
#define BITSCRAMBLER_RX_LUT 0xFFFFFFFFU
#define BITSCRAMBLER_RX_LUT_M (BITSCRAMBLER_RX_LUT_V << BITSCRAMBLER_RX_LUT_S)
#define BITSCRAMBLER_RX_LUT_V 0xFFFFFFFFU
#define BITSCRAMBLER_RX_LUT_S 0
/** BITSCRAMBLER_TX_TAILING_BITS_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x20)
/** BITSCRAMBLER_TX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
#define BITSCRAMBLER_TX_TAILING_BITS 0x0000FFFFU
#define BITSCRAMBLER_TX_TAILING_BITS_M (BITSCRAMBLER_TX_TAILING_BITS_V << BITSCRAMBLER_TX_TAILING_BITS_S)
#define BITSCRAMBLER_TX_TAILING_BITS_V 0x0000FFFFU
#define BITSCRAMBLER_TX_TAILING_BITS_S 0
/** BITSCRAMBLER_RX_TAILING_BITS_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x24)
/** BITSCRAMBLER_RX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
#define BITSCRAMBLER_RX_TAILING_BITS 0x0000FFFFU
#define BITSCRAMBLER_RX_TAILING_BITS_M (BITSCRAMBLER_RX_TAILING_BITS_V << BITSCRAMBLER_RX_TAILING_BITS_S)
#define BITSCRAMBLER_RX_TAILING_BITS_V 0x0000FFFFU
#define BITSCRAMBLER_RX_TAILING_BITS_S 0
/** BITSCRAMBLER_TX_CTRL_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x28)
/** BITSCRAMBLER_TX_ENA : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler tx
*/
#define BITSCRAMBLER_TX_ENA (BIT(0))
#define BITSCRAMBLER_TX_ENA_M (BITSCRAMBLER_TX_ENA_V << BITSCRAMBLER_TX_ENA_S)
#define BITSCRAMBLER_TX_ENA_V 0x00000001U
#define BITSCRAMBLER_TX_ENA_S 0
/** BITSCRAMBLER_TX_PAUSE : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler tx core
*/
#define BITSCRAMBLER_TX_PAUSE (BIT(1))
#define BITSCRAMBLER_TX_PAUSE_M (BITSCRAMBLER_TX_PAUSE_V << BITSCRAMBLER_TX_PAUSE_S)
#define BITSCRAMBLER_TX_PAUSE_V 0x00000001U
#define BITSCRAMBLER_TX_PAUSE_S 1
/** BITSCRAMBLER_TX_HALT : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler tx core
*/
#define BITSCRAMBLER_TX_HALT (BIT(2))
#define BITSCRAMBLER_TX_HALT_M (BITSCRAMBLER_TX_HALT_V << BITSCRAMBLER_TX_HALT_S)
#define BITSCRAMBLER_TX_HALT_V 0x00000001U
#define BITSCRAMBLER_TX_HALT_S 2
/** BITSCRAMBLER_TX_EOF_MODE : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler tx core EOF signal generating mode which is
* combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
* counter by write peripheral buffer
*/
#define BITSCRAMBLER_TX_EOF_MODE (BIT(3))
#define BITSCRAMBLER_TX_EOF_MODE_M (BITSCRAMBLER_TX_EOF_MODE_V << BITSCRAMBLER_TX_EOF_MODE_S)
#define BITSCRAMBLER_TX_EOF_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_EOF_MODE_S 3
/** BITSCRAMBLER_TX_COND_MODE : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler tx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
#define BITSCRAMBLER_TX_COND_MODE (BIT(4))
#define BITSCRAMBLER_TX_COND_MODE_M (BITSCRAMBLER_TX_COND_MODE_V << BITSCRAMBLER_TX_COND_MODE_S)
#define BITSCRAMBLER_TX_COND_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_COND_MODE_S 4
/** BITSCRAMBLER_TX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instructions
*/
#define BITSCRAMBLER_TX_FETCH_MODE (BIT(5))
#define BITSCRAMBLER_TX_FETCH_MODE_M (BITSCRAMBLER_TX_FETCH_MODE_V << BITSCRAMBLER_TX_FETCH_MODE_S)
#define BITSCRAMBLER_TX_FETCH_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_FETCH_MODE_S 5
/** BITSCRAMBLER_TX_HALT_MODE : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
#define BITSCRAMBLER_TX_HALT_MODE (BIT(6))
#define BITSCRAMBLER_TX_HALT_MODE_M (BITSCRAMBLER_TX_HALT_MODE_V << BITSCRAMBLER_TX_HALT_MODE_S)
#define BITSCRAMBLER_TX_HALT_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_HALT_MODE_S 6
/** BITSCRAMBLER_TX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler tx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
#define BITSCRAMBLER_TX_RD_DUMMY (BIT(7))
#define BITSCRAMBLER_TX_RD_DUMMY_M (BITSCRAMBLER_TX_RD_DUMMY_V << BITSCRAMBLER_TX_RD_DUMMY_S)
#define BITSCRAMBLER_TX_RD_DUMMY_V 0x00000001U
#define BITSCRAMBLER_TX_RD_DUMMY_S 7
/** BITSCRAMBLER_TX_FIFO_RST : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler tx fifo
*/
#define BITSCRAMBLER_TX_FIFO_RST (BIT(8))
#define BITSCRAMBLER_TX_FIFO_RST_M (BITSCRAMBLER_TX_FIFO_RST_V << BITSCRAMBLER_TX_FIFO_RST_S)
#define BITSCRAMBLER_TX_FIFO_RST_V 0x00000001U
#define BITSCRAMBLER_TX_FIFO_RST_S 8
/** BITSCRAMBLER_RX_CTRL_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x2c)
/** BITSCRAMBLER_RX_ENA : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler rx
*/
#define BITSCRAMBLER_RX_ENA (BIT(0))
#define BITSCRAMBLER_RX_ENA_M (BITSCRAMBLER_RX_ENA_V << BITSCRAMBLER_RX_ENA_S)
#define BITSCRAMBLER_RX_ENA_V 0x00000001U
#define BITSCRAMBLER_RX_ENA_S 0
/** BITSCRAMBLER_RX_PAUSE : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler rx core
*/
#define BITSCRAMBLER_RX_PAUSE (BIT(1))
#define BITSCRAMBLER_RX_PAUSE_M (BITSCRAMBLER_RX_PAUSE_V << BITSCRAMBLER_RX_PAUSE_S)
#define BITSCRAMBLER_RX_PAUSE_V 0x00000001U
#define BITSCRAMBLER_RX_PAUSE_S 1
/** BITSCRAMBLER_RX_HALT : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler rx core
*/
#define BITSCRAMBLER_RX_HALT (BIT(2))
#define BITSCRAMBLER_RX_HALT_M (BITSCRAMBLER_RX_HALT_V << BITSCRAMBLER_RX_HALT_S)
#define BITSCRAMBLER_RX_HALT_V 0x00000001U
#define BITSCRAMBLER_RX_HALT_S 2
/** BITSCRAMBLER_RX_EOF_MODE : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler rx core EOF signal generating mode which is
* combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
* buffer, 0 counter by write dma fifo
*/
#define BITSCRAMBLER_RX_EOF_MODE (BIT(3))
#define BITSCRAMBLER_RX_EOF_MODE_M (BITSCRAMBLER_RX_EOF_MODE_V << BITSCRAMBLER_RX_EOF_MODE_S)
#define BITSCRAMBLER_RX_EOF_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_EOF_MODE_S 3
/** BITSCRAMBLER_RX_COND_MODE : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler rx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
#define BITSCRAMBLER_RX_COND_MODE (BIT(4))
#define BITSCRAMBLER_RX_COND_MODE_M (BITSCRAMBLER_RX_COND_MODE_V << BITSCRAMBLER_RX_COND_MODE_S)
#define BITSCRAMBLER_RX_COND_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_COND_MODE_S 4
/** BITSCRAMBLER_RX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instructions
*/
#define BITSCRAMBLER_RX_FETCH_MODE (BIT(5))
#define BITSCRAMBLER_RX_FETCH_MODE_M (BITSCRAMBLER_RX_FETCH_MODE_V << BITSCRAMBLER_RX_FETCH_MODE_S)
#define BITSCRAMBLER_RX_FETCH_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_FETCH_MODE_S 5
/** BITSCRAMBLER_RX_HALT_MODE : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
#define BITSCRAMBLER_RX_HALT_MODE (BIT(6))
#define BITSCRAMBLER_RX_HALT_MODE_M (BITSCRAMBLER_RX_HALT_MODE_V << BITSCRAMBLER_RX_HALT_MODE_S)
#define BITSCRAMBLER_RX_HALT_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_HALT_MODE_S 6
/** BITSCRAMBLER_RX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler rx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
#define BITSCRAMBLER_RX_RD_DUMMY (BIT(7))
#define BITSCRAMBLER_RX_RD_DUMMY_M (BITSCRAMBLER_RX_RD_DUMMY_V << BITSCRAMBLER_RX_RD_DUMMY_S)
#define BITSCRAMBLER_RX_RD_DUMMY_V 0x00000001U
#define BITSCRAMBLER_RX_RD_DUMMY_S 7
/** BITSCRAMBLER_RX_FIFO_RST : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler rx fifo
*/
#define BITSCRAMBLER_RX_FIFO_RST (BIT(8))
#define BITSCRAMBLER_RX_FIFO_RST_M (BITSCRAMBLER_RX_FIFO_RST_V << BITSCRAMBLER_RX_FIFO_RST_S)
#define BITSCRAMBLER_RX_FIFO_RST_V 0x00000001U
#define BITSCRAMBLER_RX_FIFO_RST_S 8
/** BITSCRAMBLER_TX_STATE_REG register
* Status registers
*/
#define BITSCRAMBLER_TX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x30)
/** BITSCRAMBLER_TX_IN_IDLE : RO; bitpos: [0]; default: 1;
* represents the bitscrambler tx core in halt mode
*/
#define BITSCRAMBLER_TX_IN_IDLE (BIT(0))
#define BITSCRAMBLER_TX_IN_IDLE_M (BITSCRAMBLER_TX_IN_IDLE_V << BITSCRAMBLER_TX_IN_IDLE_S)
#define BITSCRAMBLER_TX_IN_IDLE_V 0x00000001U
#define BITSCRAMBLER_TX_IN_IDLE_S 0
/** BITSCRAMBLER_TX_IN_RUN : RO; bitpos: [1]; default: 0;
* represents the bitscrambler tx core in run mode
*/
#define BITSCRAMBLER_TX_IN_RUN (BIT(1))
#define BITSCRAMBLER_TX_IN_RUN_M (BITSCRAMBLER_TX_IN_RUN_V << BITSCRAMBLER_TX_IN_RUN_S)
#define BITSCRAMBLER_TX_IN_RUN_V 0x00000001U
#define BITSCRAMBLER_TX_IN_RUN_S 1
/** BITSCRAMBLER_TX_IN_WAIT : RO; bitpos: [2]; default: 0;
* represents the bitscrambler tx core in wait mode to wait write back done
*/
#define BITSCRAMBLER_TX_IN_WAIT (BIT(2))
#define BITSCRAMBLER_TX_IN_WAIT_M (BITSCRAMBLER_TX_IN_WAIT_V << BITSCRAMBLER_TX_IN_WAIT_S)
#define BITSCRAMBLER_TX_IN_WAIT_V 0x00000001U
#define BITSCRAMBLER_TX_IN_WAIT_S 2
/** BITSCRAMBLER_TX_IN_PAUSE : RO; bitpos: [3]; default: 0;
* represents the bitscrambler tx core in pause mode
*/
#define BITSCRAMBLER_TX_IN_PAUSE (BIT(3))
#define BITSCRAMBLER_TX_IN_PAUSE_M (BITSCRAMBLER_TX_IN_PAUSE_V << BITSCRAMBLER_TX_IN_PAUSE_S)
#define BITSCRAMBLER_TX_IN_PAUSE_V 0x00000001U
#define BITSCRAMBLER_TX_IN_PAUSE_S 3
/** BITSCRAMBLER_TX_FIFO_EMPTY : RO; bitpos: [4]; default: 0;
* represents the bitscrambler tx fifo in empty state
*/
#define BITSCRAMBLER_TX_FIFO_EMPTY (BIT(4))
#define BITSCRAMBLER_TX_FIFO_EMPTY_M (BITSCRAMBLER_TX_FIFO_EMPTY_V << BITSCRAMBLER_TX_FIFO_EMPTY_S)
#define BITSCRAMBLER_TX_FIFO_EMPTY_V 0x00000001U
#define BITSCRAMBLER_TX_FIFO_EMPTY_S 4
/** BITSCRAMBLER_TX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler tx core when get EOF
*/
#define BITSCRAMBLER_TX_EOF_GET_CNT 0x00003FFFU
#define BITSCRAMBLER_TX_EOF_GET_CNT_M (BITSCRAMBLER_TX_EOF_GET_CNT_V << BITSCRAMBLER_TX_EOF_GET_CNT_S)
#define BITSCRAMBLER_TX_EOF_GET_CNT_V 0x00003FFFU
#define BITSCRAMBLER_TX_EOF_GET_CNT_S 16
/** BITSCRAMBLER_TX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler tx core
*/
#define BITSCRAMBLER_TX_EOF_OVERLOAD (BIT(30))
#define BITSCRAMBLER_TX_EOF_OVERLOAD_M (BITSCRAMBLER_TX_EOF_OVERLOAD_V << BITSCRAMBLER_TX_EOF_OVERLOAD_S)
#define BITSCRAMBLER_TX_EOF_OVERLOAD_V 0x00000001U
#define BITSCRAMBLER_TX_EOF_OVERLOAD_S 30
/** BITSCRAMBLER_TX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_tx_eof_overload and
* reg_bitscrambler_tx_eof_get_cnt registers
*/
#define BITSCRAMBLER_TX_EOF_TRACE_CLR (BIT(31))
#define BITSCRAMBLER_TX_EOF_TRACE_CLR_M (BITSCRAMBLER_TX_EOF_TRACE_CLR_V << BITSCRAMBLER_TX_EOF_TRACE_CLR_S)
#define BITSCRAMBLER_TX_EOF_TRACE_CLR_V 0x00000001U
#define BITSCRAMBLER_TX_EOF_TRACE_CLR_S 31
/** BITSCRAMBLER_RX_STATE_REG register
* Status registers
*/
#define BITSCRAMBLER_RX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x34)
/** BITSCRAMBLER_RX_IN_IDLE : RO; bitpos: [0]; default: 1;
* represents the bitscrambler rx core in halt mode
*/
#define BITSCRAMBLER_RX_IN_IDLE (BIT(0))
#define BITSCRAMBLER_RX_IN_IDLE_M (BITSCRAMBLER_RX_IN_IDLE_V << BITSCRAMBLER_RX_IN_IDLE_S)
#define BITSCRAMBLER_RX_IN_IDLE_V 0x00000001U
#define BITSCRAMBLER_RX_IN_IDLE_S 0
/** BITSCRAMBLER_RX_IN_RUN : RO; bitpos: [1]; default: 0;
* represents the bitscrambler rx core in run mode
*/
#define BITSCRAMBLER_RX_IN_RUN (BIT(1))
#define BITSCRAMBLER_RX_IN_RUN_M (BITSCRAMBLER_RX_IN_RUN_V << BITSCRAMBLER_RX_IN_RUN_S)
#define BITSCRAMBLER_RX_IN_RUN_V 0x00000001U
#define BITSCRAMBLER_RX_IN_RUN_S 1
/** BITSCRAMBLER_RX_IN_WAIT : RO; bitpos: [2]; default: 0;
* represents the bitscrambler rx core in wait mode to wait write back done
*/
#define BITSCRAMBLER_RX_IN_WAIT (BIT(2))
#define BITSCRAMBLER_RX_IN_WAIT_M (BITSCRAMBLER_RX_IN_WAIT_V << BITSCRAMBLER_RX_IN_WAIT_S)
#define BITSCRAMBLER_RX_IN_WAIT_V 0x00000001U
#define BITSCRAMBLER_RX_IN_WAIT_S 2
/** BITSCRAMBLER_RX_IN_PAUSE : RO; bitpos: [3]; default: 0;
* represents the bitscrambler rx core in pause mode
*/
#define BITSCRAMBLER_RX_IN_PAUSE (BIT(3))
#define BITSCRAMBLER_RX_IN_PAUSE_M (BITSCRAMBLER_RX_IN_PAUSE_V << BITSCRAMBLER_RX_IN_PAUSE_S)
#define BITSCRAMBLER_RX_IN_PAUSE_V 0x00000001U
#define BITSCRAMBLER_RX_IN_PAUSE_S 3
/** BITSCRAMBLER_RX_FIFO_FULL : RO; bitpos: [4]; default: 0;
* represents the bitscrambler rx fifo in full state
*/
#define BITSCRAMBLER_RX_FIFO_FULL (BIT(4))
#define BITSCRAMBLER_RX_FIFO_FULL_M (BITSCRAMBLER_RX_FIFO_FULL_V << BITSCRAMBLER_RX_FIFO_FULL_S)
#define BITSCRAMBLER_RX_FIFO_FULL_V 0x00000001U
#define BITSCRAMBLER_RX_FIFO_FULL_S 4
/** BITSCRAMBLER_RX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler rx core when get EOF
*/
#define BITSCRAMBLER_RX_EOF_GET_CNT 0x00003FFFU
#define BITSCRAMBLER_RX_EOF_GET_CNT_M (BITSCRAMBLER_RX_EOF_GET_CNT_V << BITSCRAMBLER_RX_EOF_GET_CNT_S)
#define BITSCRAMBLER_RX_EOF_GET_CNT_V 0x00003FFFU
#define BITSCRAMBLER_RX_EOF_GET_CNT_S 16
/** BITSCRAMBLER_RX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler rx core
*/
#define BITSCRAMBLER_RX_EOF_OVERLOAD (BIT(30))
#define BITSCRAMBLER_RX_EOF_OVERLOAD_M (BITSCRAMBLER_RX_EOF_OVERLOAD_V << BITSCRAMBLER_RX_EOF_OVERLOAD_S)
#define BITSCRAMBLER_RX_EOF_OVERLOAD_V 0x00000001U
#define BITSCRAMBLER_RX_EOF_OVERLOAD_S 30
/** BITSCRAMBLER_RX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_rx_eof_overload and
* reg_bitscrambler_rx_eof_get_cnt registers
*/
#define BITSCRAMBLER_RX_EOF_TRACE_CLR (BIT(31))
#define BITSCRAMBLER_RX_EOF_TRACE_CLR_M (BITSCRAMBLER_RX_EOF_TRACE_CLR_V << BITSCRAMBLER_RX_EOF_TRACE_CLR_S)
#define BITSCRAMBLER_RX_EOF_TRACE_CLR_V 0x00000001U
#define BITSCRAMBLER_RX_EOF_TRACE_CLR_S 31
/** BITSCRAMBLER_SYS_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_SYS_REG (DR_REG_BITSCRAMBLER_BASE + 0xf8)
/** BITSCRAMBLER_LOOP_MODE : R/W; bitpos: [0]; default: 0;
* write this bit to set the bitscrambler tx loop back to DMA rx
*/
#define BITSCRAMBLER_LOOP_MODE (BIT(0))
#define BITSCRAMBLER_LOOP_MODE_M (BITSCRAMBLER_LOOP_MODE_V << BITSCRAMBLER_LOOP_MODE_S)
#define BITSCRAMBLER_LOOP_MODE_V 0x00000001U
#define BITSCRAMBLER_LOOP_MODE_S 0
/** BITSCRAMBLER_CLK_EN : R/W; bitpos: [31]; default: 0;
* Reserved
*/
#define BITSCRAMBLER_CLK_EN (BIT(31))
#define BITSCRAMBLER_CLK_EN_M (BITSCRAMBLER_CLK_EN_V << BITSCRAMBLER_CLK_EN_S)
#define BITSCRAMBLER_CLK_EN_V 0x00000001U
#define BITSCRAMBLER_CLK_EN_S 31
/** BITSCRAMBLER_VERSION_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_VERSION_REG (DR_REG_BITSCRAMBLER_BASE + 0xfc)
/** BITSCRAMBLER_BITSCRAMBLER_VER : R/W; bitpos: [27:0]; default: 36713024;
* Reserved
*/
#define BITSCRAMBLER_BITSCRAMBLER_VER 0x0FFFFFFFU
#define BITSCRAMBLER_BITSCRAMBLER_VER_M (BITSCRAMBLER_BITSCRAMBLER_VER_V << BITSCRAMBLER_BITSCRAMBLER_VER_S)
#define BITSCRAMBLER_BITSCRAMBLER_VER_V 0x0FFFFFFFU
#define BITSCRAMBLER_BITSCRAMBLER_VER_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Control and configuration registers */
/** Type of tx_inst_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_inst_idx : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
uint32_t tx_inst_idx:3;
/** tx_inst_pos : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
uint32_t tx_inst_pos:4;
uint32_t reserved_7:25;
};
uint32_t val;
} bitscrambler_tx_inst_cfg0_reg_t;
/** Type of tx_inst_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_inst : R/W; bitpos: [31:0]; default: 4;
* write this bits to update instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG
*/
uint32_t tx_inst:32;
};
uint32_t val;
} bitscrambler_tx_inst_cfg1_reg_t;
/** Type of rx_inst_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_inst_idx : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
uint32_t rx_inst_idx:3;
/** rx_inst_pos : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
uint32_t rx_inst_pos:4;
uint32_t reserved_7:25;
};
uint32_t val;
} bitscrambler_rx_inst_cfg0_reg_t;
/** Type of rx_inst_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_inst : R/W; bitpos: [31:0]; default: 12;
* write this bits to update instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG
*/
uint32_t rx_inst:32;
};
uint32_t val;
} bitscrambler_rx_inst_cfg1_reg_t;
/** Type of tx_lut_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_lut_idx : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_tx_lut_mode
*/
uint32_t tx_lut_idx:11;
/** tx_lut_mode : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
uint32_t tx_lut_mode:2;
uint32_t reserved_13:19;
};
uint32_t val;
} bitscrambler_tx_lut_cfg0_reg_t;
/** Type of tx_lut_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_lut : R/W; bitpos: [31:0]; default: 20;
* write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
*/
uint32_t tx_lut:32;
};
uint32_t val;
} bitscrambler_tx_lut_cfg1_reg_t;
/** Type of rx_lut_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_lut_idx : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_rx_lut_mode
*/
uint32_t rx_lut_idx:11;
/** rx_lut_mode : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
uint32_t rx_lut_mode:2;
uint32_t reserved_13:19;
};
uint32_t val;
} bitscrambler_rx_lut_cfg0_reg_t;
/** Type of rx_lut_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_lut : R/W; bitpos: [31:0]; default: 28;
* write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
*/
uint32_t rx_lut:32;
};
uint32_t val;
} bitscrambler_rx_lut_cfg1_reg_t;
/** Group: Configuration registers */
/** Type of tx_tailing_bits register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
uint32_t tx_tailing_bits:16;
uint32_t reserved_16:16;
};
uint32_t val;
} bitscrambler_tx_tailing_bits_reg_t;
/** Type of rx_tailing_bits register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
uint32_t rx_tailing_bits:16;
uint32_t reserved_16:16;
};
uint32_t val;
} bitscrambler_rx_tailing_bits_reg_t;
/** Type of tx_ctrl register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_ena : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler tx
*/
uint32_t tx_ena:1;
/** tx_pause : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler tx core
*/
uint32_t tx_pause:1;
/** tx_halt : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler tx core
*/
uint32_t tx_halt:1;
/** tx_eof_mode : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler tx core EOF signal generating mode which is
* combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
* counter by write peripheral buffer
*/
uint32_t tx_eof_mode:1;
/** tx_cond_mode : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler tx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
uint32_t tx_cond_mode:1;
/** tx_fetch_mode : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instructions
*/
uint32_t tx_fetch_mode:1;
/** tx_halt_mode : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
uint32_t tx_halt_mode:1;
/** tx_rd_dummy : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler tx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
uint32_t tx_rd_dummy:1;
/** tx_fifo_rst : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler tx fifo
*/
uint32_t tx_fifo_rst:1;
uint32_t reserved_9:23;
};
uint32_t val;
} bitscrambler_tx_ctrl_reg_t;
/** Type of rx_ctrl register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_ena : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler rx
*/
uint32_t rx_ena:1;
/** rx_pause : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler rx core
*/
uint32_t rx_pause:1;
/** rx_halt : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler rx core
*/
uint32_t rx_halt:1;
/** rx_eof_mode : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler rx core EOF signal generating mode which is
* combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
* buffer, 0 counter by write dma fifo
*/
uint32_t rx_eof_mode:1;
/** rx_cond_mode : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler rx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
uint32_t rx_cond_mode:1;
/** rx_fetch_mode : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instructions
*/
uint32_t rx_fetch_mode:1;
/** rx_halt_mode : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
uint32_t rx_halt_mode:1;
/** rx_rd_dummy : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler rx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
uint32_t rx_rd_dummy:1;
/** rx_fifo_rst : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler rx fifo
*/
uint32_t rx_fifo_rst:1;
uint32_t reserved_9:23;
};
uint32_t val;
} bitscrambler_rx_ctrl_reg_t;
/** Type of sys register
* Control and configuration registers
*/
typedef union {
struct {
/** loop_mode : R/W; bitpos: [0]; default: 0;
* write this bit to set the bitscrambler tx loop back to DMA rx
*/
uint32_t loop_mode:1;
uint32_t reserved_1:30;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Reserved
*/
uint32_t clk_en:1;
};
uint32_t val;
} bitscrambler_sys_reg_t;
/** Group: Status registers */
/** Type of tx_state register
* Status registers
*/
typedef union {
struct {
/** tx_in_idle : RO; bitpos: [0]; default: 1;
* represents the bitscrambler tx core in halt mode
*/
uint32_t tx_in_idle:1;
/** tx_in_run : RO; bitpos: [1]; default: 0;
* represents the bitscrambler tx core in run mode
*/
uint32_t tx_in_run:1;
/** tx_in_wait : RO; bitpos: [2]; default: 0;
* represents the bitscrambler tx core in wait mode to wait write back done
*/
uint32_t tx_in_wait:1;
/** tx_in_pause : RO; bitpos: [3]; default: 0;
* represents the bitscrambler tx core in pause mode
*/
uint32_t tx_in_pause:1;
/** tx_fifo_empty : RO; bitpos: [4]; default: 0;
* represents the bitscrambler tx fifo in empty state
*/
uint32_t tx_fifo_empty:1;
uint32_t reserved_5:11;
/** tx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler tx core when get EOF
*/
uint32_t tx_eof_get_cnt:14;
/** tx_eof_overload : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler tx core
*/
uint32_t tx_eof_overload:1;
/** tx_eof_trace_clr : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_tx_eof_overload and
* reg_bitscrambler_tx_eof_get_cnt registers
*/
uint32_t tx_eof_trace_clr:1;
};
uint32_t val;
} bitscrambler_tx_state_reg_t;
/** Type of rx_state register
* Status registers
*/
typedef union {
struct {
/** rx_in_idle : RO; bitpos: [0]; default: 1;
* represents the bitscrambler rx core in halt mode
*/
uint32_t rx_in_idle:1;
/** rx_in_run : RO; bitpos: [1]; default: 0;
* represents the bitscrambler rx core in run mode
*/
uint32_t rx_in_run:1;
/** rx_in_wait : RO; bitpos: [2]; default: 0;
* represents the bitscrambler rx core in wait mode to wait write back done
*/
uint32_t rx_in_wait:1;
/** rx_in_pause : RO; bitpos: [3]; default: 0;
* represents the bitscrambler rx core in pause mode
*/
uint32_t rx_in_pause:1;
/** rx_fifo_full : RO; bitpos: [4]; default: 0;
* represents the bitscrambler rx fifo in full state
*/
uint32_t rx_fifo_full:1;
uint32_t reserved_5:11;
/** rx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler rx core when get EOF
*/
uint32_t rx_eof_get_cnt:14;
/** rx_eof_overload : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler rx core
*/
uint32_t rx_eof_overload:1;
/** rx_eof_trace_clr : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_rx_eof_overload and
* reg_bitscrambler_rx_eof_get_cnt registers
*/
uint32_t rx_eof_trace_clr:1;
};
uint32_t val;
} bitscrambler_rx_state_reg_t;
/** Group: Version register */
/** Type of version register
* Control and configuration registers
*/
typedef union {
struct {
/** bitscrambler_ver : R/W; bitpos: [27:0]; default: 36713024;
* Reserved
*/
uint32_t bitscrambler_ver:28;
uint32_t reserved_28:4;
};
uint32_t val;
} bitscrambler_version_reg_t;
///////////////////// TX and RX registers are exactly the same //////////////////////////////////
// The following registers are used for both TX and RX, so we can use the same struct for both //
/////////////////////////////////////////////////////////////////////////////////////////////////
/** Type of inst_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** inst_idx : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
uint32_t inst_idx:3;
/** inst_pos : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
uint32_t inst_pos:4;
uint32_t reserved_7:25;
};
uint32_t val;
} bitscrambler_inst_cfg0_reg_t;
/** Type of inst_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** inst : R/W; bitpos: [31:0]; default: 4;
* write this bits to update instruction, Read this bits to get instruction.
*/
uint32_t inst:32;
};
uint32_t val;
} bitscrambler_inst_cfg1_reg_t;
/** Type of lut_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** lut_idx : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on lut_mode
*/
uint32_t lut_idx:11;
/** lut_mode : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
uint32_t lut_mode:2;
uint32_t reserved_13:19;
};
uint32_t val;
} bitscrambler_lut_cfg0_reg_t;
/** Type of lut_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** lut : R/W; bitpos: [31:0]; default: 20;
* write this bits to update LUT, Read this bits to get LUT
*/
uint32_t lut:32;
};
uint32_t val;
} bitscrambler_lut_cfg1_reg_t;
/** Type of tailing_bits register
* Control and configuration registers
*/
typedef union {
struct {
/** tailing_bits : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
uint32_t tailing_bits:16;
uint32_t reserved_16:16;
};
uint32_t val;
} bitscrambler_tailing_bits_reg_t;
/** Type of ctrl register
* Control and configuration registers
*/
typedef union {
struct {
/** ena : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler tx
*/
uint32_t ena:1;
/** pause : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler tx core
*/
uint32_t pause:1;
/** halt : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler tx core
*/
uint32_t halt:1;
/** eof_mode : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler tx core EOF signal generating mode which is
* combined with reg_bitscrambler_tailing_bits, 0: counter by read dma fifo, 0
* counter by write peripheral buffer
*/
uint32_t eof_mode:1;
/** cond_mode : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler tx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
uint32_t cond_mode:1;
/** fetch_mode : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instructions
*/
uint32_t fetch_mode:1;
/** halt_mode : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler tx core halt mode when halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
uint32_t halt_mode:1;
/** rd_dummy : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler tx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
uint32_t rd_dummy:1;
/** fifo_rst : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler tx fifo
*/
uint32_t fifo_rst:1;
uint32_t reserved_9:23;
};
uint32_t val;
} bitscrambler_ctrl_reg_t;
/** Group: Status registers */
/** Type of state register
* Status registers
*/
typedef union {
struct {
/** in_idle : RO; bitpos: [0]; default: 1;
* represents the bitscrambler tx core in halt mode
*/
uint32_t in_idle:1;
/** in_run : RO; bitpos: [1]; default: 0;
* represents the bitscrambler tx core in run mode
*/
uint32_t in_run:1;
/** in_wait : RO; bitpos: [2]; default: 0;
* represents the bitscrambler tx core in wait mode to wait write back done
*/
uint32_t in_wait:1;
/** in_pause : RO; bitpos: [3]; default: 0;
* represents the bitscrambler tx core in pause mode
*/
uint32_t in_pause:1;
/** fifo_empty : RO; bitpos: [4]; default: 0;
* represents the bitscrambler tx fifo in empty state
*/
uint32_t fifo_empty:1;
uint32_t reserved_5:11;
/** eof_get_cnt : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler tx core when get EOF
*/
uint32_t eof_get_cnt:14;
/** eof_overload : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler tx core
*/
uint32_t eof_overload:1;
/** eof_trace_clr : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_eof_overload and
* reg_bitscrambler_eof_get_cnt registers
*/
uint32_t eof_trace_clr:1;
};
uint32_t val;
} bitscrambler_state_reg_t;
typedef struct {
volatile struct {
bitscrambler_inst_cfg0_reg_t cfg0;
bitscrambler_inst_cfg1_reg_t cfg1;
} inst_cfg[2];
volatile struct {
bitscrambler_lut_cfg0_reg_t cfg0;
bitscrambler_lut_cfg1_reg_t cfg1;
} lut_cfg[2];
volatile bitscrambler_tailing_bits_reg_t tail_bits[2];
volatile bitscrambler_ctrl_reg_t ctrl[2];
volatile bitscrambler_state_reg_t state[2];
uint32_t reserved_038[48];
volatile bitscrambler_sys_reg_t sys;
volatile bitscrambler_version_reg_t version;
} bitscrambler_dev_t;
extern bitscrambler_dev_t BITSCRAMBLER;
#ifndef __cplusplus
_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** DS_Y_MEM register
* memory that stores Y
*/
#define DS_Y_MEM (DR_REG_DS_BASE + 0x0)
#define DS_Y_MEM_SIZE_BYTES 512
/** DS_M_MEM register
* memory that stores M
*/
#define DS_M_MEM (DR_REG_DS_BASE + 0x200)
#define DS_M_MEM_SIZE_BYTES 512
/** DS_RB_MEM register
* memory that stores Rb
*/
#define DS_RB_MEM (DR_REG_DS_BASE + 0x400)
#define DS_RB_MEM_SIZE_BYTES 512
/** DS_BOX_MEM register
* memory that stores BOX
*/
#define DS_BOX_MEM (DR_REG_DS_BASE + 0x600)
#define DS_BOX_MEM_SIZE_BYTES 48
/** DS_IV_MEM register
* memory that stores IV
*/
#define DS_IV_MEM (DR_REG_DS_BASE + 0x630)
#define DS_IV_MEM_SIZE_BYTES 16
/** DS_X_MEM register
* memory that stores X
*/
#define DS_X_MEM (DR_REG_DS_BASE + 0x800)
#define DS_X_MEM_SIZE_BYTES 512
/** DS_Z_MEM register
* memory that stores Z
*/
#define DS_Z_MEM (DR_REG_DS_BASE + 0xa00)
#define DS_Z_MEM_SIZE_BYTES 512
/** DS_SET_START_REG register
* Activates the DS module
*/
#define DS_SET_START_REG (DR_REG_DS_BASE + 0xe00)
/** DS_SET_START : WT; bitpos: [0]; default: 0;
* Configures whether or not to activate the DS peripheral.
* 0: Invalid
* 1: Activate the DS peripheral
*/
#define DS_SET_START (BIT(0))
#define DS_SET_START_M (DS_SET_START_V << DS_SET_START_S)
#define DS_SET_START_V 0x00000001U
#define DS_SET_START_S 0
/** DS_SET_CONTINUE_REG register
* DS continue control register
*/
#define DS_SET_CONTINUE_REG (DR_REG_DS_BASE + 0xe04)
/** DS_SET_CONTINUE : WT; bitpos: [0]; default: 0;
* set this bit to continue DS operation.
*/
#define DS_SET_CONTINUE (BIT(0))
#define DS_SET_CONTINUE_M (DS_SET_CONTINUE_V << DS_SET_CONTINUE_S)
#define DS_SET_CONTINUE_V 0x00000001U
#define DS_SET_CONTINUE_S 0
/** DS_SET_FINISH_REG register
* Ends DS operation
*/
#define DS_SET_FINISH_REG (DR_REG_DS_BASE + 0xe08)
/** DS_SET_FINISH : WT; bitpos: [0]; default: 0;
* Configures whether or not to end DS operation.
* 0: Invalid
* 1: End DS operation
*/
#define DS_SET_FINISH (BIT(0))
#define DS_SET_FINISH_M (DS_SET_FINISH_V << DS_SET_FINISH_S)
#define DS_SET_FINISH_V 0x00000001U
#define DS_SET_FINISH_S 0
/** DS_QUERY_BUSY_REG register
* Status of the DS module
*/
#define DS_QUERY_BUSY_REG (DR_REG_DS_BASE + 0xe0c)
/** DS_QUERY_BUSY : RO; bitpos: [0]; default: 0;
* Represents whether or not the DS module is idle.
* 0: The DS module is idle
* 1: The DS module is busy
*/
#define DS_QUERY_BUSY (BIT(0))
#define DS_QUERY_BUSY_M (DS_QUERY_BUSY_V << DS_QUERY_BUSY_S)
#define DS_QUERY_BUSY_V 0x00000001U
#define DS_QUERY_BUSY_S 0
/** DS_QUERY_KEY_WRONG_REG register
* Checks the reason why \begin{math}DS_KEY\end{math} is not ready
*/
#define DS_QUERY_KEY_WRONG_REG (DR_REG_DS_BASE + 0xe10)
/** DS_QUERY_KEY_WRONG : RO; bitpos: [3:0]; default: 0;
* Represents the specific problem with HMAC initialization.
* 0: HMAC is not called
* 1-15: HMAC was activated, but the DS peripheral did not successfully receive the
* \begin{math}DS_KEY\end{math} from the HMAC peripheral. (The biggest value is 15)
*/
#define DS_QUERY_KEY_WRONG 0x0000000FU
#define DS_QUERY_KEY_WRONG_M (DS_QUERY_KEY_WRONG_V << DS_QUERY_KEY_WRONG_S)
#define DS_QUERY_KEY_WRONG_V 0x0000000FU
#define DS_QUERY_KEY_WRONG_S 0
/** DS_QUERY_CHECK_REG register
* Queries DS check result
*/
#define DS_QUERY_CHECK_REG (DR_REG_DS_BASE + 0xe14)
/** DS_MD_ERROR : RO; bitpos: [0]; default: 0;
* Represents whether or not the MD check passes.
* 0: The MD check passes
* 1: The MD check fails
*/
#define DS_MD_ERROR (BIT(0))
#define DS_MD_ERROR_M (DS_MD_ERROR_V << DS_MD_ERROR_S)
#define DS_MD_ERROR_V 0x00000001U
#define DS_MD_ERROR_S 0
/** DS_PADDING_BAD : RO; bitpos: [1]; default: 0;
* Represents whether or not the padding check passes.
* 0: The padding check passes
* 1: The padding check fails
*/
#define DS_PADDING_BAD (BIT(1))
#define DS_PADDING_BAD_M (DS_PADDING_BAD_V << DS_PADDING_BAD_S)
#define DS_PADDING_BAD_V 0x00000001U
#define DS_PADDING_BAD_S 1
/** DS_KEY_SOURCE_REG register
* DS configure key source register
*/
#define DS_KEY_SOURCE_REG (DR_REG_DS_BASE + 0xe18)
/** DS_KEY_SOURCE : R/W; bitpos: [0]; default: 0;
* digital signature key source bit.
* 1'b0: key is from hmac.
* 1'b1: key is from key manager.
*/
#define DS_KEY_SOURCE (BIT(0))
#define DS_KEY_SOURCE_M (DS_KEY_SOURCE_V << DS_KEY_SOURCE_S)
#define DS_KEY_SOURCE_V 0x00000001U
#define DS_KEY_SOURCE_S 0
/** DS_DATE_REG register
* DS version control register
*/
#define DS_DATE_REG (DR_REG_DS_BASE + 0xe20)
/** DS_DATE : R/W; bitpos: [29:0]; default: 539166977;
* ds version information
*/
#define DS_DATE 0x3FFFFFFFU
#define DS_DATE_M (DS_DATE_V << DS_DATE_S)
#define DS_DATE_V 0x3FFFFFFFU
#define DS_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: memory type */
/** Group: Control/Status registers */
/** Type of set_start register
* Activates the DS module
*/
typedef union {
struct {
/** set_start : WT; bitpos: [0]; default: 0;
* Configures whether or not to activate the DS peripheral.
* 0: Invalid
* 1: Activate the DS peripheral
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_start_reg_t;
/** Type of set_continue register
* DS continue control register
*/
typedef union {
struct {
/** set_continue : WT; bitpos: [0]; default: 0;
* set this bit to continue DS operation.
*/
uint32_t set_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_continue_reg_t;
/** Type of set_finish register
* Ends DS operation
*/
typedef union {
struct {
/** set_finish : WT; bitpos: [0]; default: 0;
* Configures whether or not to end DS operation.
* 0: Invalid
* 1: End DS operation
*/
uint32_t set_finish:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_finish_reg_t;
/** Type of query_busy register
* Status of the DS module
*/
typedef union {
struct {
/** query_busy : RO; bitpos: [0]; default: 0;
* Represents whether or not the DS module is idle.
* 0: The DS module is idle
* 1: The DS module is busy
*/
uint32_t query_busy:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_query_busy_reg_t;
/** Type of query_key_wrong register
* Checks the reason why \begin{math}DS_KEY\end{math} is not ready
*/
typedef union {
struct {
/** query_key_wrong : RO; bitpos: [3:0]; default: 0;
* Represents the specific problem with HMAC initialization.
* 0: HMAC is not called
* 1-15: HMAC was activated, but the DS peripheral did not successfully receive the
* \begin{math}DS_KEY\end{math} from the HMAC peripheral. (The biggest value is 15)
*/
uint32_t query_key_wrong:4;
uint32_t reserved_4:28;
};
uint32_t val;
} ds_query_key_wrong_reg_t;
/** Type of query_check register
* Queries DS check result
*/
typedef union {
struct {
/** md_error : RO; bitpos: [0]; default: 0;
* Represents whether or not the MD check passes.
* 0: The MD check passes
* 1: The MD check fails
*/
uint32_t md_error:1;
/** padding_bad : RO; bitpos: [1]; default: 0;
* Represents whether or not the padding check passes.
* 0: The padding check passes
* 1: The padding check fails
*/
uint32_t padding_bad:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ds_query_check_reg_t;
/** Group: Configuration registers */
/** Type of key_source register
* DS configure key source register
*/
typedef union {
struct {
/** key_source : R/W; bitpos: [0]; default: 0;
* digital signature key source bit.
* 1'b0: key is from hmac.
* 1'b1: key is from key manager.
*/
uint32_t key_source:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_key_source_reg_t;
/** Group: version control register */
/** Type of date register
* DS version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 539166977;
* ds version information
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} ds_date_reg_t;
typedef struct {
volatile uint32_t y[128];
volatile uint32_t m[128];
volatile uint32_t rb[128];
volatile uint32_t box[12];
volatile uint32_t iv[4];
uint32_t reserved_640[112];
volatile uint32_t x[128];
volatile uint32_t z[128];
uint32_t reserved_c00[128];
volatile ds_set_start_reg_t set_start;
volatile ds_set_continue_reg_t set_continue;
volatile ds_set_finish_reg_t set_finish;
volatile ds_query_busy_reg_t query_busy;
volatile ds_query_key_wrong_reg_t query_key_wrong;
volatile ds_query_check_reg_t query_check;
volatile ds_key_source_reg_t key_source;
uint32_t reserved_e1c;
volatile ds_date_reg_t date;
} ds_dev_t;
extern ds_dev_t DS;
#ifndef __cplusplus
_Static_assert(sizeof(ds_dev_t) == 0xe24, "Invalid size of ds_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECC_MULT_INT_RAW_REG register
* ECC raw interrupt status register
*/
#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0))
#define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
#define ECC_MULT_CALC_DONE_INT_RAW_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_RAW_S 0
/** ECC_MULT_INT_ST_REG register
* ECC masked interrupt status register
*/
#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_ST (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
#define ECC_MULT_CALC_DONE_INT_ST_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_ST_S 0
/** ECC_MULT_INT_ENA_REG register
* ECC interrupt enable register
*/
#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
#define ECC_MULT_CALC_DONE_INT_ENA_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_ENA_S 0
/** ECC_MULT_INT_CLR_REG register
* ECC interrupt clear register
*/
#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0))
#define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
#define ECC_MULT_CALC_DONE_INT_CLR_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_CLR_S 0
/** ECC_MULT_CONF_REG register
* ECC configuration register
*/
#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
* Configures whether to start calculation of ECC Accelerator. This bit will be
* self-cleared after the calculation is done.
* 0: No effect
* 1: Start calculation of ECC Accelerator
*/
#define ECC_MULT_START (BIT(0))
#define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S)
#define ECC_MULT_START_V 0x00000001U
#define ECC_MULT_START_S 0
/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
* Configures whether to reset ECC Accelerator.
* 0: No effect
* 1: Reset
*/
#define ECC_MULT_RESET (BIT(1))
#define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
#define ECC_MULT_RESET_V 0x00000001U
#define ECC_MULT_RESET_S 1
/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [3:2]; default: 0;
* Configures the key length mode bit of ECC Accelerator.
* 0: P-192
* 1: P-256
* 2: P-384
* 3: Reserved.
*/
#define ECC_MULT_KEY_LENGTH 0x00000003U
#define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
#define ECC_MULT_KEY_LENGTH_V 0x00000003U
#define ECC_MULT_KEY_LENGTH_S 2
/** ECC_MULT_MOD_BASE : R/W; bitpos: [4]; default: 0;
* Configures the mod base of mod operation, only valid in work_mode 8-11.
* 0: n(order of curve)
* 1: p(mod base of curve)
*/
#define ECC_MULT_MOD_BASE (BIT(4))
#define ECC_MULT_MOD_BASE_M (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S)
#define ECC_MULT_MOD_BASE_V 0x00000001U
#define ECC_MULT_MOD_BASE_S 4
/** ECC_MULT_WORK_MODE : R/W; bitpos: [8:5]; default: 0;
* Configures the work mode of ECC Accelerator.
* 0: Point Multi mode
* 1: Reserved
* 2: Point Verif mode
* 3: Point Verif + Multi mode
* 4: Jacobian Point Multi mode
* 5: Reserved
* 6: Jacobian Point Verif mode
* 7: Point Verif + Jacobian Point Multi mode
* 8: Mod Add mode
* 9. Mod Sub mode
* 10: Mod Multi mode
* 11: Mod Div mode
*/
#define ECC_MULT_WORK_MODE 0x0000000FU
#define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
#define ECC_MULT_WORK_MODE_V 0x0000000FU
#define ECC_MULT_WORK_MODE_S 5
/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [9]; default: 0;
* Configures the security mode of ECC Accelerator.
* 0: no secure function enabled.
* 1: enable constant-time calculation in all point multiplication modes.
*/
#define ECC_MULT_SECURITY_MODE (BIT(9))
#define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
#define ECC_MULT_SECURITY_MODE_V 0x00000001U
#define ECC_MULT_SECURITY_MODE_S 9
/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0;
* Represents the verification result of ECC Accelerator, valid only when calculation
* is done.
*/
#define ECC_MULT_VERIFICATION_RESULT (BIT(29))
#define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
#define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U
#define ECC_MULT_VERIFICATION_RESULT_S 29
/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0;
* Configures whether to force on register clock gate.
* 0: No effect
* 1: Force on
*/
#define ECC_MULT_CLK_EN (BIT(30))
#define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
#define ECC_MULT_CLK_EN_V 0x00000001U
#define ECC_MULT_CLK_EN_S 30
/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0;
* Configures whether to force on ECC memory clock gate.
* 0: No effect
* 1: Force on
*/
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON (BIT(31))
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V 0x00000001U
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S 31
/** ECC_MULT_DATE_REG register
* Version control register
*/
#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 37781792;
* ECC mult version control register
*/
#define ECC_MULT_DATE 0x0FFFFFFFU
#define ECC_MULT_DATE_M (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
#define ECC_MULT_DATE_V 0x0FFFFFFFU
#define ECC_MULT_DATE_S 0
/** ECC_MULT_K_MEM register
* The memory that stores k.
*/
#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100)
#define ECC_MULT_K_MEM_SIZE_BYTES 48
/** ECC_MULT_PX_MEM register
* The memory that stores Px.
*/
#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x130)
#define ECC_MULT_PX_MEM_SIZE_BYTES 48
/** ECC_MULT_PY_MEM register
* The memory that stores Py.
*/
#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x160)
#define ECC_MULT_PY_MEM_SIZE_BYTES 48
/** ECC_MULT_QX_MEM register
* The memory that stores Qx.
*/
#define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x190)
#define ECC_MULT_QX_MEM_SIZE_BYTES 48
/** ECC_MULT_QY_MEM register
* The memory that stores Qy.
*/
#define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x1c0)
#define ECC_MULT_QY_MEM_SIZE_BYTES 48
/** ECC_MULT_QZ_MEM register
* The memory that stores Qz.
*/
#define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1f0)
#define ECC_MULT_QZ_MEM_SIZE_BYTES 48
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Interrupt registers */
/** Type of int_raw register
* ECC raw interrupt status register
*/
typedef union {
struct {
/** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
uint32_t calc_done_int_raw:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_raw_reg_t;
/** Type of int_st register
* ECC masked interrupt status register
*/
typedef union {
struct {
/** calc_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
uint32_t calc_done_int_st:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_st_reg_t;
/** Type of int_ena register
* ECC interrupt enable register
*/
typedef union {
struct {
/** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the ECC_CALC_DONE_INT interrupt.
*/
uint32_t calc_done_int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_ena_reg_t;
/** Type of int_clr register
* ECC interrupt clear register
*/
typedef union {
struct {
/** calc_done_int_clr : WT; bitpos: [0]; default: 0;
* Write 1 to clear the ECC_CALC_DONE_INT interrupt.
*/
uint32_t calc_done_int_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_clr_reg_t;
/** Group: RX Control and configuration registers */
/** Type of conf register
* ECC configuration register
*/
typedef union {
struct {
/** start : R/W/SC; bitpos: [0]; default: 0;
* Configures whether to start calculation of ECC Accelerator. This bit will be
* self-cleared after the calculation is done.
* 0: No effect
* 1: Start calculation of ECC Accelerator
*/
uint32_t start:1;
/** reset : WT; bitpos: [1]; default: 0;
* Configures whether to reset ECC Accelerator.
* 0: No effect
* 1: Reset
*/
uint32_t reset:1;
/** key_length : R/W; bitpos: [3:2]; default: 0;
* Configures the key length mode bit of ECC Accelerator.
* 0: P-192
* 1: P-256
* 2: P-384
* 3: Reserved.
*/
uint32_t key_length:2;
/** mod_base : R/W; bitpos: [4]; default: 0;
* Configures the mod base of mod operation, only valid in work_mode 8-11.
* 0: n(order of curve)
* 1: p(mod base of curve)
*/
uint32_t mod_base:1;
/** work_mode : R/W; bitpos: [8:5]; default: 0;
* Configures the work mode of ECC Accelerator.
* 0: Point Multi mode
* 1: Reserved
* 2: Point Verif mode
* 3: Point Verif + Multi mode
* 4: Jacobian Point Multi mode
* 5: Reserved
* 6: Jacobian Point Verif mode
* 7: Point Verif + Jacobian Point Multi mode
* 8: Mod Add mode
* 9. Mod Sub mode
* 10: Mod Multi mode
* 11: Mod Div mode
*/
uint32_t work_mode:4;
/** security_mode : R/W; bitpos: [9]; default: 0;
* Configures the security mode of ECC Accelerator.
* 0: no secure function enabled.
* 1: enable constant-time calculation in all point multiplication modes.
*/
uint32_t security_mode:1;
uint32_t reserved_10:19;
/** verification_result : RO/SS; bitpos: [29]; default: 0;
* Represents the verification result of ECC Accelerator, valid only when calculation
* is done.
*/
uint32_t verification_result:1;
/** clk_en : R/W; bitpos: [30]; default: 0;
* Configures whether to force on register clock gate.
* 0: No effect
* 1: Force on
*/
uint32_t clk_en:1;
/** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0;
* Configures whether to force on ECC memory clock gate.
* 0: No effect
* 1: Force on
*/
uint32_t mem_clock_gate_force_on:1;
};
uint32_t val;
} ecc_mult_conf_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37781792;
* ECC mult version control register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} ecc_mult_date_reg_t;
typedef struct {
uint32_t reserved_000[3];
volatile ecc_mult_int_raw_reg_t int_raw;
volatile ecc_mult_int_st_reg_t int_st;
volatile ecc_mult_int_ena_reg_t int_ena;
volatile ecc_mult_int_clr_reg_t int_clr;
volatile ecc_mult_conf_reg_t conf;
uint32_t reserved_020[55];
volatile ecc_mult_date_reg_t date;
volatile uint32_t k[12];
volatile uint32_t px[12];
volatile uint32_t py[12];
volatile uint32_t qx[12];
volatile uint32_t qy[12];
volatile uint32_t qz[12];
} ecc_mult_dev_t;
extern ecc_mult_dev_t ECC;
#ifndef __cplusplus
_Static_assert(sizeof(ecc_mult_dev_t) == 0x220, "Invalid size of ecc_mult_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECDSA_CONF_REG register
* ECDSA configure register
*/
#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
* Generate Mode. 2: Export Public Key Mode. 3: invalid.
*/
#define ECDSA_WORK_MODE 0x00000003U
#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
#define ECDSA_WORK_MODE_V 0x00000003U
#define ECDSA_WORK_MODE_S 0
/** ECDSA_ECC_CURVE : R/W; bitpos: [3:2]; default: 0;
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384.
*/
#define ECDSA_ECC_CURVE 0x00000003U
#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
#define ECDSA_ECC_CURVE_V 0x00000003U
#define ECDSA_ECC_CURVE_S 2
/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [4]; default: 0;
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
* written by software.
*/
#define ECDSA_SOFTWARE_SET_K (BIT(4))
#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
#define ECDSA_SOFTWARE_SET_K_V 0x00000001U
#define ECDSA_SOFTWARE_SET_K_S 4
/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [5]; default: 0;
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
* software.
*/
#define ECDSA_SOFTWARE_SET_Z (BIT(5))
#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U
#define ECDSA_SOFTWARE_SET_Z_S 5
/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [6]; default: 0;
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
* deterministic derivation algorithm.
*/
#define ECDSA_DETERMINISTIC_K (BIT(6))
#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
#define ECDSA_DETERMINISTIC_K_V 0x00000001U
#define ECDSA_DETERMINISTIC_K_S 6
/** ECDSA_CLK_REG register
* ECDSA clock gate register
*/
#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
* Write 1 to force on register clock gate.
*/
#define ECDSA_CLK_GATE_FORCE_ON (BIT(0))
#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U
#define ECDSA_CLK_GATE_FORCE_ON_S 0
/** ECDSA_INT_RAW_REG register
* ECDSA interrupt raw register, valid in level.
*/
#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_RAW (BIT(0))
#define ECDSA_PREP_DONE_INT_RAW_M (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S)
#define ECDSA_PREP_DONE_INT_RAW_V 0x00000001U
#define ECDSA_PREP_DONE_INT_RAW_S 0
/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_RAW (BIT(1))
#define ECDSA_PROC_DONE_INT_RAW_M (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S)
#define ECDSA_PROC_DONE_INT_RAW_V 0x00000001U
#define ECDSA_PROC_DONE_INT_RAW_S 1
/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_RAW (BIT(2))
#define ECDSA_POST_DONE_INT_RAW_M (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S)
#define ECDSA_POST_DONE_INT_RAW_V 0x00000001U
#define ECDSA_POST_DONE_INT_RAW_S 2
/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_RAW (BIT(3))
#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_RAW_S 3
/** ECDSA_INT_ST_REG register
* ECDSA interrupt status register.
*/
#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
/** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_ST (BIT(0))
#define ECDSA_PREP_DONE_INT_ST_M (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S)
#define ECDSA_PREP_DONE_INT_ST_V 0x00000001U
#define ECDSA_PREP_DONE_INT_ST_S 0
/** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_ST (BIT(1))
#define ECDSA_PROC_DONE_INT_ST_M (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S)
#define ECDSA_PROC_DONE_INT_ST_V 0x00000001U
#define ECDSA_PROC_DONE_INT_ST_S 1
/** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_ST (BIT(2))
#define ECDSA_POST_DONE_INT_ST_M (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S)
#define ECDSA_POST_DONE_INT_ST_V 0x00000001U
#define ECDSA_POST_DONE_INT_ST_S 2
/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_ST (BIT(3))
#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_ST_S 3
/** ECDSA_INT_ENA_REG register
* ECDSA interrupt enable register.
*/
#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
/** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_ENA (BIT(0))
#define ECDSA_PREP_DONE_INT_ENA_M (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S)
#define ECDSA_PREP_DONE_INT_ENA_V 0x00000001U
#define ECDSA_PREP_DONE_INT_ENA_S 0
/** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_ENA (BIT(1))
#define ECDSA_PROC_DONE_INT_ENA_M (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S)
#define ECDSA_PROC_DONE_INT_ENA_V 0x00000001U
#define ECDSA_PROC_DONE_INT_ENA_S 1
/** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_ENA (BIT(2))
#define ECDSA_POST_DONE_INT_ENA_M (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S)
#define ECDSA_POST_DONE_INT_ENA_V 0x00000001U
#define ECDSA_POST_DONE_INT_ENA_S 2
/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_ENA (BIT(3))
#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_ENA_S 3
/** ECDSA_INT_CLR_REG register
* ECDSA interrupt clear register.
*/
#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
/** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_CLR (BIT(0))
#define ECDSA_PREP_DONE_INT_CLR_M (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S)
#define ECDSA_PREP_DONE_INT_CLR_V 0x00000001U
#define ECDSA_PREP_DONE_INT_CLR_S 0
/** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_CLR (BIT(1))
#define ECDSA_PROC_DONE_INT_CLR_M (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S)
#define ECDSA_PROC_DONE_INT_CLR_V 0x00000001U
#define ECDSA_PROC_DONE_INT_CLR_S 1
/** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_CLR (BIT(2))
#define ECDSA_POST_DONE_INT_CLR_M (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S)
#define ECDSA_POST_DONE_INT_CLR_V 0x00000001U
#define ECDSA_POST_DONE_INT_CLR_S 2
/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0;
* Set this bit to clear the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_CLR (BIT(3))
#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_CLR_S 3
/** ECDSA_START_REG register
* ECDSA start register
*/
#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
/** ECDSA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
* after configuration.
*/
#define ECDSA_START (BIT(0))
#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S)
#define ECDSA_START_V 0x00000001U
#define ECDSA_START_S 0
/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
#define ECDSA_LOAD_DONE (BIT(1))
#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
#define ECDSA_LOAD_DONE_V 0x00000001U
#define ECDSA_LOAD_DONE_S 1
/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
#define ECDSA_GET_DONE (BIT(2))
#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
#define ECDSA_GET_DONE_V 0x00000001U
#define ECDSA_GET_DONE_S 2
/** ECDSA_STATE_REG register
* ECDSA status register
*/
#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
* state.
*/
#define ECDSA_BUSY 0x00000003U
#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S)
#define ECDSA_BUSY_V 0x00000003U
#define ECDSA_BUSY_S 0
/** ECDSA_RESULT_REG register
* ECDSA result register
*/
#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
* done.
*/
#define ECDSA_OPERATION_RESULT (BIT(0))
#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
#define ECDSA_OPERATION_RESULT_V 0x00000001U
#define ECDSA_OPERATION_RESULT_S 0
/** ECDSA_DATE_REG register
* Version control register
*/
#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 37785984;
* ECDSA version control register
*/
#define ECDSA_DATE 0x0FFFFFFFU
#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S)
#define ECDSA_DATE_V 0x0FFFFFFFU
#define ECDSA_DATE_S 0
/** ECDSA_SHA_MODE_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
* The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2:
* SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 7: invalid.
*/
#define ECDSA_SHA_MODE 0x00000007U
#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
#define ECDSA_SHA_MODE_V 0x00000007U
#define ECDSA_SHA_MODE_S 0
/** ECDSA_SHA_START_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
#define ECDSA_SHA_START (BIT(0))
#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
#define ECDSA_SHA_START_V 0x00000001U
#define ECDSA_SHA_START_S 0
/** ECDSA_SHA_CONTINUE_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
* Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
#define ECDSA_SHA_CONTINUE (BIT(0))
#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
#define ECDSA_SHA_CONTINUE_V 0x00000001U
#define ECDSA_SHA_CONTINUE_S 0
/** ECDSA_SHA_BUSY_REG register
* ECDSA status register
*/
#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
* calculation. 0: SHA is idle.
*/
#define ECDSA_SHA_BUSY (BIT(0))
#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
#define ECDSA_SHA_BUSY_V 0x00000001U
#define ECDSA_SHA_BUSY_S 0
/** ECDSA_MESSAGE_MEM register
* The memory that stores message.
*/
#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
#define ECDSA_MESSAGE_MEM_SIZE_BYTES 64
/** ECDSA_R_MEM register
* The memory that stores r.
*/
#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x3e0)
#define ECDSA_R_MEM_SIZE_BYTES 48
/** ECDSA_S_MEM register
* The memory that stores s.
*/
#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x410)
#define ECDSA_S_MEM_SIZE_BYTES 48
/** ECDSA_Z_MEM register
* The memory that stores software written z.
*/
#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x440)
#define ECDSA_Z_MEM_SIZE_BYTES 48
/** ECDSA_QAX_MEM register
* The memory that stores x coordinates of QA or software written k.
*/
#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x470)
#define ECDSA_QAX_MEM_SIZE_BYTES 48
/** ECDSA_QAY_MEM register
* The memory that stores y coordinates of QA.
*/
#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x4a0)
#define ECDSA_QAY_MEM_SIZE_BYTES 48
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECDSA_CONF_REG register
* ECDSA configure register
*/
#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
* Generate Mode. 2: Export Public Key Mode. 3: invalid.
*/
#define ECDSA_WORK_MODE 0x00000003U
#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
#define ECDSA_WORK_MODE_V 0x00000003U
#define ECDSA_WORK_MODE_S 0
/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0;
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256.
*/
#define ECDSA_ECC_CURVE (BIT(2))
#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
#define ECDSA_ECC_CURVE_V 0x00000001U
#define ECDSA_ECC_CURVE_S 2
/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0;
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
* written by software.
*/
#define ECDSA_SOFTWARE_SET_K (BIT(3))
#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
#define ECDSA_SOFTWARE_SET_K_V 0x00000001U
#define ECDSA_SOFTWARE_SET_K_S 3
/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0;
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
* software.
*/
#define ECDSA_SOFTWARE_SET_Z (BIT(4))
#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U
#define ECDSA_SOFTWARE_SET_Z_S 4
/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0;
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
* deterministic derivation algorithm.
*/
#define ECDSA_DETERMINISTIC_K (BIT(5))
#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
#define ECDSA_DETERMINISTIC_K_V 0x00000001U
#define ECDSA_DETERMINISTIC_K_S 5
/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0;
* The (loop number - 1) value in the deterministic derivation algorithm to derive k.
*/
#define ECDSA_DETERMINISTIC_LOOP 0x0000FFFFU
#define ECDSA_DETERMINISTIC_LOOP_M (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S)
#define ECDSA_DETERMINISTIC_LOOP_V 0x0000FFFFU
#define ECDSA_DETERMINISTIC_LOOP_S 6
/** ECDSA_CLK_REG register
* ECDSA clock gate register
*/
#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
* Write 1 to force on register clock gate.
*/
#define ECDSA_CLK_GATE_FORCE_ON (BIT(0))
#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U
#define ECDSA_CLK_GATE_FORCE_ON_S 0
/** ECDSA_INT_RAW_REG register
* ECDSA interrupt raw register, valid in level.
*/
#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
/** ECDSA_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecdsa_calc_done_int interrupt
*/
#define ECDSA_CALC_DONE_INT_RAW (BIT(0))
#define ECDSA_CALC_DONE_INT_RAW_M (ECDSA_CALC_DONE_INT_RAW_V << ECDSA_CALC_DONE_INT_RAW_S)
#define ECDSA_CALC_DONE_INT_RAW_V 0x00000001U
#define ECDSA_CALC_DONE_INT_RAW_S 0
/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_RAW (BIT(1))
#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_RAW_S 1
/** ECDSA_INT_ST_REG register
* ECDSA interrupt status register.
*/
#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
/** ECDSA_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecdsa_calc_done_int interrupt
*/
#define ECDSA_CALC_DONE_INT_ST (BIT(0))
#define ECDSA_CALC_DONE_INT_ST_M (ECDSA_CALC_DONE_INT_ST_V << ECDSA_CALC_DONE_INT_ST_S)
#define ECDSA_CALC_DONE_INT_ST_V 0x00000001U
#define ECDSA_CALC_DONE_INT_ST_S 0
/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_ST (BIT(1))
#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_ST_S 1
/** ECDSA_INT_ENA_REG register
* ECDSA interrupt enable register.
*/
#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
/** ECDSA_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecdsa_calc_done_int interrupt
*/
#define ECDSA_CALC_DONE_INT_ENA (BIT(0))
#define ECDSA_CALC_DONE_INT_ENA_M (ECDSA_CALC_DONE_INT_ENA_V << ECDSA_CALC_DONE_INT_ENA_S)
#define ECDSA_CALC_DONE_INT_ENA_V 0x00000001U
#define ECDSA_CALC_DONE_INT_ENA_S 0
/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_ENA (BIT(1))
#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_ENA_S 1
/** ECDSA_INT_CLR_REG register
* ECDSA interrupt clear register.
*/
#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
/** ECDSA_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecdsa_calc_done_int interrupt
*/
#define ECDSA_CALC_DONE_INT_CLR (BIT(0))
#define ECDSA_CALC_DONE_INT_CLR_M (ECDSA_CALC_DONE_INT_CLR_V << ECDSA_CALC_DONE_INT_CLR_S)
#define ECDSA_CALC_DONE_INT_CLR_V 0x00000001U
#define ECDSA_CALC_DONE_INT_CLR_S 0
/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_CLR (BIT(1))
#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_CLR_S 1
/** ECDSA_START_REG register
* ECDSA start register
*/
#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
/** ECDSA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
* after configuration.
*/
#define ECDSA_START (BIT(0))
#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S)
#define ECDSA_START_V 0x00000001U
#define ECDSA_START_S 0
/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
#define ECDSA_LOAD_DONE (BIT(1))
#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
#define ECDSA_LOAD_DONE_V 0x00000001U
#define ECDSA_LOAD_DONE_S 1
/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
#define ECDSA_GET_DONE (BIT(2))
#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
#define ECDSA_GET_DONE_V 0x00000001U
#define ECDSA_GET_DONE_S 2
/** ECDSA_STATE_REG register
* ECDSA status register
*/
#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
* state.
*/
#define ECDSA_BUSY 0x00000003U
#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S)
#define ECDSA_BUSY_V 0x00000003U
#define ECDSA_BUSY_S 0
/** ECDSA_RESULT_REG register
* ECDSA result register
*/
#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
* done.
*/
#define ECDSA_OPERATION_RESULT (BIT(0))
#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
#define ECDSA_OPERATION_RESULT_V 0x00000001U
#define ECDSA_OPERATION_RESULT_S 0
/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0;
* The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
* curve order, then actually taken k = k mod n.
*/
#define ECDSA_K_VALUE_WARNING (BIT(1))
#define ECDSA_K_VALUE_WARNING_M (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S)
#define ECDSA_K_VALUE_WARNING_V 0x00000001U
#define ECDSA_K_VALUE_WARNING_S 1
/** ECDSA_DATE_REG register
* Version control register
*/
#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 36716656;
* ECDSA version control register
*/
#define ECDSA_DATE 0x0FFFFFFFU
#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S)
#define ECDSA_DATE_V 0x0FFFFFFFU
#define ECDSA_DATE_S 0
/** ECDSA_SHA_MODE_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
* Others: invalid.
*/
#define ECDSA_SHA_MODE 0x00000007U
#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
#define ECDSA_SHA_MODE_V 0x00000007U
#define ECDSA_SHA_MODE_S 0
/** ECDSA_SHA_START_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
#define ECDSA_SHA_START (BIT(0))
#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
#define ECDSA_SHA_START_V 0x00000001U
#define ECDSA_SHA_START_S 0
/** ECDSA_SHA_CONTINUE_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
* Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
#define ECDSA_SHA_CONTINUE (BIT(0))
#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
#define ECDSA_SHA_CONTINUE_V 0x00000001U
#define ECDSA_SHA_CONTINUE_S 0
/** ECDSA_SHA_BUSY_REG register
* ECDSA status register
*/
#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
* calculation. 0: SHA is idle.
*/
#define ECDSA_SHA_BUSY (BIT(0))
#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
#define ECDSA_SHA_BUSY_V 0x00000001U
#define ECDSA_SHA_BUSY_S 0
/** ECDSA_MESSAGE_MEM register
* The memory that stores message.
*/
#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32
/** ECDSA_R_MEM register
* The memory that stores r.
*/
#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0xa00)
#define ECDSA_R_MEM_SIZE_BYTES 32
/** ECDSA_S_MEM register
* The memory that stores s.
*/
#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0xa20)
#define ECDSA_S_MEM_SIZE_BYTES 32
/** ECDSA_Z_MEM register
* The memory that stores software written z.
*/
#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0xa40)
#define ECDSA_Z_MEM_SIZE_BYTES 32
/** ECDSA_QAX_MEM register
* The memory that stores x coordinates of QA or software written k.
*/
#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0xa60)
#define ECDSA_QAX_MEM_SIZE_BYTES 32
/** ECDSA_QAY_MEM register
* The memory that stores y coordinates of QA.
*/
#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0xa80)
#define ECDSA_QAY_MEM_SIZE_BYTES 32
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Data Memory */
/** Group: Configuration registers */
/** Type of conf register
* ECDSA configure register
*/
typedef union {
struct {
/** work_mode : R/W; bitpos: [1:0]; default: 0;
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
* Generate Mode. 2: Export Public Key Mode. 3: invalid.
*/
uint32_t work_mode:2;
/** ecc_curve : R/W; bitpos: [3:2]; default: 0;
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384.
*/
uint32_t ecc_curve:2;
/** software_set_k : R/W; bitpos: [4]; default: 0;
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
* written by software.
*/
uint32_t software_set_k:1;
/** software_set_z : R/W; bitpos: [5]; default: 0;
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
* software.
*/
uint32_t software_set_z:1;
/** deterministic_k : R/W; bitpos: [6]; default: 0;
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
* deterministic derivation algorithm.
*/
uint32_t deterministic_k:1;
uint32_t reserved_7:25;
};
uint32_t val;
} ecdsa_conf_reg_t;
/** Type of start register
* ECDSA start register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
* after configuration.
*/
uint32_t start:1;
/** load_done : WT; bitpos: [1]; default: 0;
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
uint32_t load_done:1;
/** get_done : WT; bitpos: [2]; default: 0;
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
uint32_t get_done:1;
uint32_t reserved_3:29;
};
uint32_t val;
} ecdsa_start_reg_t;
/** Group: Clock and reset registers */
/** Type of clk register
* ECDSA clock gate register
*/
typedef union {
struct {
/** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
* Write 1 to force on register clock gate.
*/
uint32_t clk_gate_force_on:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* ECDSA interrupt raw register, valid in level.
*/
typedef union {
struct {
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_raw:1;
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_raw:1;
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_raw:1;
/** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_raw:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_raw_reg_t;
/** Type of int_st register
* ECDSA interrupt status register.
*/
typedef union {
struct {
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_st:1;
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_st:1;
/** post_done_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_st:1;
/** sha_release_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_st:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_st_reg_t;
/** Type of int_ena register
* ECDSA interrupt enable register.
*/
typedef union {
struct {
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_ena:1;
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_ena:1;
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_ena:1;
/** sha_release_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_ena:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_ena_reg_t;
/** Type of int_clr register
* ECDSA interrupt clear register.
*/
typedef union {
struct {
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_clr:1;
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_clr:1;
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_clr:1;
/** sha_release_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_clr:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_clr_reg_t;
/** Group: Status registers */
/** Type of state register
* ECDSA status register
*/
typedef union {
struct {
/** busy : RO; bitpos: [1:0]; default: 0;
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
* state.
*/
uint32_t busy:2;
uint32_t reserved_2:30;
};
uint32_t val;
} ecdsa_state_reg_t;
/** Group: Result registers */
/** Type of result register
* ECDSA result register
*/
typedef union {
struct {
/** operation_result : RO/SS; bitpos: [0]; default: 0;
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
* done.
*/
uint32_t operation_result:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_result_reg_t;
/** Group: SHA register */
/** Type of sha_mode register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_mode : R/W; bitpos: [2:0]; default: 0;
* The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2:
* SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 7: invalid.
*/
uint32_t sha_mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} ecdsa_sha_mode_reg_t;
/** Type of sha_start register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_start : WT; bitpos: [0]; default: 0;
* Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
uint32_t sha_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_start_reg_t;
/** Type of sha_continue register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_continue : WT; bitpos: [0]; default: 0;
* Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
uint32_t sha_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_continue_reg_t;
/** Type of sha_busy register
* ECDSA status register
*/
typedef union {
struct {
/** sha_busy : RO; bitpos: [0]; default: 0;
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
* calculation. 0: SHA is idle.
*/
uint32_t sha_busy:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_busy_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37785984;
* ECDSA version control register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} ecdsa_date_reg_t;
typedef struct {
uint32_t reserved_000;
volatile ecdsa_conf_reg_t conf;
volatile ecdsa_clk_reg_t clk;
volatile ecdsa_int_raw_reg_t int_raw;
volatile ecdsa_int_st_reg_t int_st;
volatile ecdsa_int_ena_reg_t int_ena;
volatile ecdsa_int_clr_reg_t int_clr;
volatile ecdsa_start_reg_t start;
volatile ecdsa_state_reg_t state;
volatile ecdsa_result_reg_t result;
uint32_t reserved_028[53];
volatile ecdsa_date_reg_t date;
uint32_t reserved_100[64];
volatile ecdsa_sha_mode_reg_t sha_mode;
uint32_t reserved_204[3];
volatile ecdsa_sha_start_reg_t sha_start;
volatile ecdsa_sha_continue_reg_t sha_continue;
volatile ecdsa_sha_busy_reg_t sha_busy;
uint32_t reserved_21c[25];
volatile uint32_t message[16];
uint32_t reserved_2c0[72];
volatile uint32_t r[12];
volatile uint32_t s[12];
volatile uint32_t z[12];
volatile uint32_t qax[12];
volatile uint32_t qay[12];
} ecdsa_dev_t;
extern ecdsa_dev_t ECDSA;
#ifndef __cplusplus
_Static_assert(sizeof(ecdsa_dev_t) == 0x4d0, "Invalid size of ecdsa_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
typedef struct emac_dma_dev_s {
volatile union {
struct {
uint32_t sw_rst : 1; /*When this bit is set the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC clock domains. Before reprogramming any register of the ETH_MAC you should read a zero (0) value in this bit.*/
uint32_t dma_arb_sch : 1; /*This bit specifies the arbitration scheme between the transmit and receive paths.1'b0: weighted round-robin with RX:TX or TX:RX priority specified in PR (bit[15:14]). 1'b1 Fixed priority (Rx priority to Tx).*/
uint32_t desc_skip_len : 5; /*This bit specifies the number of Word to skip between two unchained descriptors.The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL(DESC_SKIP_LEN) value is equal to zero the descriptor table is taken as contiguous by the DMA in Ring mode.*/
uint32_t alt_desc_size : 1; /*When set the size of the alternate descriptor increases to 32 bytes.*/
uint32_t prog_burst_len : 6; /*These bits indicate the maximum number of beats to be transferred in one DMA transaction. If the number of beats to be transferred is more than 32 then perform the following steps: 1. Set the PBLx8 mode 2. Set the PBL(PROG_BURST_LEN).*/
uint32_t pri_ratio : 2; /*These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio Rx:Tx represented by each bit: 2'b00 -- 1: 1 2'b01 -- 2: 0 2'b10 -- 3: 1 2'b11 -- 4: 1*/
uint32_t fixed_burst : 1; /*This bit controls whether the AHB master interface performs fixed burst transfers or not. When set the AHB interface uses only SINGLE INCR4 INCR8 or INCR16 during start of the normal burst transfers. When reset the AHB interface uses SINGLE and INCR burst transfer Operations.*/
uint32_t rx_dma_pbl : 6; /*This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write.The Rx DMA always attempts to burst as specified in the RPBL(RX_DMA_PBL) bit each time it starts a burst transfer on the host bus. You can program RPBL with values of 1 2 4 8 16 and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP(USE_SEP_PBL) is set high.*/
uint32_t use_sep_pbl : 1; /*When set high this bit configures the Rx DMA to use the value configured in Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to the Tx DMA operations. When reset to low the PBL value in Bits[13:8] is applicable for both DMA engines.*/
uint32_t pblx8_mode : 1; /*When set high this bit multiplies the programmed PBL value (Bits[22:17] and Bits[13:8]) eight times. Therefore the DMA transfers the data in 8 16 32 64 128 and 256 beats depending on the PBL value.*/
uint32_t dmaaddralibea : 1; /*When this bit is set high and the FIXED_BURST bit is 1 the AHB interface generates all bursts aligned to the start address LS bits. If the FIXED_BURST bit is 0 the first burst (accessing the start address of data buffer) is not aligned but subsequent bursts are aligned to the address.*/
uint32_t dmamixedburst : 1; /*When this bit is set high and the FIXED_BURST bit is low the AHB master interface starts all bursts of a length more than 16 with INCR (undefined burst) whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less.*/
uint32_t reserved27 : 1;
uint32_t reserved28 : 2;
uint32_t reserved30 : 1;
uint32_t reserved31 : 1;
};
uint32_t val;
} dmabusmode;
uint32_t dmatxpolldemand; /*When these bits are written with any value the DMA reads the current descriptor to which the Register (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host) the transmission returns to the suspend state and Bit[2] (TU) of Status Register is asserted. If the descriptor is available the transmission resumes.*/
uint32_t dmarxpolldemand; /*When these bits are written with any value the DMA reads the current descriptor to which the Current Host Receive Descriptor Register is pointing. If that descriptor is not available (owned by the Host) the reception returns to the Suspended state and Bit[7] (RU) of Status Register is asserted. If the descriptor is available the Rx DMA returns to the active state.*/
uint32_t dmarxbaseaddr; /*This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB Bits[1:0] are ignored and internally taken as all-zero by the DMA. Therefore these LSB bits are read-only.*/
uint32_t dmatxbaseaddr; /*This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB Bits[1:0] are ignored and are internally taken as all-zero by the DMA.Therefore these LSB bits are read-only.*/
volatile union {
struct {
uint32_t trans_int : 1; /*This bit indicates that the frame transmission is complete. When transmission is complete Bit[31] (OWN) of TDES0 is reset and the specific frame status information is updated in the Descriptor.*/
uint32_t trans_proc_stop : 1; /*This bit is set when the transmission is stopped.*/
uint32_t trans_buf_unavail : 1; /*This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand Command.*/
uint32_t trans_jabber_to : 1; /*This bit indicates that the Transmit Jabber Timer expired which happens when the frame size exceeds 2 048 (10 240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert.*/
uint32_t recv_ovflow : 1; /*This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application the overflow status is set in RDES0[11].*/
uint32_t trans_undflow : 1; /*This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set.*/
uint32_t recv_int : 1; /*This bit indicates that the frame reception is complete. When reception is complete the Bit[31] of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor and the specific frame status information is updated in the descriptor. The reception remains in the Running state.*/
uint32_t recv_buf_unavail : 1; /*This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA.*/
uint32_t recv_proc_stop : 1; /*This bit is asserted when the Receive Process enters the Stopped state.*/
uint32_t recv_wdt_to : 1; /*When set this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout.*/
uint32_t early_trans_int : 1; /*This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO.*/
uint32_t reserved11 : 2;
uint32_t fatal_bus_err_int : 1; /*This bit indicates that a bus error occurred as described in Bits [25:23]. When this bit is set the corresponding DMA engine disables all of its bus accesses.*/
uint32_t early_recv_int : 1; /*This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or when Bit[6] (RI) of this register is set (whichever occurs earlier).*/
uint32_t abn_int_summ : 1; /*Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Interrupt Enable Register: Bit[1]: Transmit Process Stopped. Bit[3]: Transmit Jabber Timeout. Bit[4]: Receive FIFO Overflow. Bit[5]: Transmit Underflow. Bit[7]: Receive Buffer Unavailable. Bit[8]: Receive Process Stopped. Bit[9]: Receive Watchdog Timeout. Bit[10]: Early Transmit Interrupt. Bit[13]: Fatal Bus Error. Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit which causes AIS to be set is cleared.*/
uint32_t norm_int_summ : 1; /*Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Interrupt Enable Register: Bit[0]: Transmit Interrupt. Bit[2]: Transmit Buffer Unavailable. Bit[6]: Receive Interrupt. Bit[14]: Early Receive Interrupt. Only unmasked bits affect the Normal Interrupt Summary bit.This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set is cleared.*/
uint32_t recv_proc_state : 3; /*This field indicates the Receive DMA FSM state. This field does not generate an interrupt. 3'b000: Stopped. Reset or Stop Receive Command issued. 3'b001: Running. Fetching Receive Transfer Descriptor. 3'b010: Reserved for future use. 3'b011: Running. Waiting for RX packets. 3'b100: Suspended. Receive Descriptor Unavailable. 3'b101: Running. Closing Receive Descriptor. 3'b110: TIME_STAMP write state. 3'b111: Running. Transferring the TX packets data from receive buffer to host memory.*/
uint32_t trans_proc_state : 3; /*This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. 3'b000: Stopped. Reset or Stop Transmit Command issued. 3'b001: Running. Fetching Transmit Transfer Descriptor. 3'b010: Reserved for future use. 3'b011: Running. Waiting for TX packets. 3'b100: Suspended. Receive Descriptor Unavailable. 3'b101: Running. Closing Transmit Descriptor. 3'b110: TIME_STAMP write state. 3'b111: Running. Transferring the TX packets data from transmit buffer to host memory.*/
uint32_t error_bits : 3; /*This field indicates the type of error that caused a Bus Error for example error response on the AHB interface. This field is valid only when Bit[13] (FBI) is set. This field does not generate an interrupt. 3'b000: Error during Rx DMA Write Data Transfer. 3'b011: Error during Tx DMA Read Data Transfer. 3'b100: Error during Rx DMA Descriptor Write Access. 3'b101: Error during Tx DMA Descriptor Write Access. 3'b110: Error during Rx DMA Descriptor Read Access. 3'b111: Error during Tx DMA Descriptor Read Access.*/
uint32_t reserved26 : 1;
uint32_t reserved27 : 1;
uint32_t pmt_int : 1; /*This bit indicates an interrupt event in the PMT module of the ETH_MAC. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1'b0.*/
uint32_t ts_tri_int : 1; /*This bit indicates an interrupt event in the Timestamp Generator block of the ETH_MAC.The software must read the corresponding registers in the ETH_MAC to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0.*/
uint32_t reserved30 : 1;
uint32_t reserved31 : 1;
};
uint32_t val;
} dmastatus;
volatile union {
struct {
uint32_t reserved0 : 1;
uint32_t start_stop_rx : 1; /*When this bit is set the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames.When this bit is cleared the Rx DMA operation is stopped after the transfer of the current frame.*/
uint32_t opt_second_frame : 1; /*When this bit is set it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained.*/
uint32_t rx_thresh_ctrl : 2; /*These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. 2'b00: 64， 2'b01: 32， 2'b10: 96， 2'b11: 128 .*/
uint32_t drop_gfrm : 1; /*When set the MAC drops the received giant frames in the Rx FIFO that is frames that are larger than the computed giant frame limit.*/
uint32_t fwd_under_gf : 1; /*When set the Rx FIFO forwards Undersized frames (that is frames with no Error and length less than 64 bytes) including pad-bytes and CRC.*/
uint32_t fwd_err_frame : 1; /*When this bit is reset the Rx FIFO drops frames with error status (CRC error collision error giant frame watchdog timeout or overflow).*/
uint32_t reserved8 : 1;
uint32_t reserved9 : 2;
uint32_t reserved11 : 2;
uint32_t start_stop_transmission_command : 1; /*When this bit is set transmission is placed in the Running state and the DMA checks the Transmit List at the current position for a frame to be transmitted.When this bit is reset the transmission process is placed in the Stopped state after completing the transmission of the current frame.*/
uint32_t tx_thresh_ctrl : 3; /*These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition full frames with a length less than the threshold are also transmitted. These bits are used only when Tx_Str_fwd is reset. 3'b000: 64 3'b001: 128 3'b010: 192 3'b011: 256 3'b100: 40 3'b101: 32 3'b110: 24 3'b111: 16 .*/
uint32_t reserved17 : 3;
uint32_t flush_tx_fifo : 1; /*When this bit is set the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete.*/
uint32_t tx_str_fwd : 1; /*When this bit is set transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set the Tx_Thresh_Ctrl values specified in Tx_Thresh_Ctrl are ignored.*/
uint32_t reserved22 : 1;
uint32_t reserved23 : 1;
uint32_t dis_flush_recv_frames : 1; /*When this bit is set the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers.*/
uint32_t rx_store_forward : 1; /*When this bit is set the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it.*/
uint32_t dis_drop_tcpip_err_fram : 1; /*When this bit is set the MAC does not drop the frames which only have errors detected by the Receive Checksum engine.When this bit is reset all error frames are dropped if the Fwd_Err_Frame bit is reset.*/
uint32_t reserved27 : 5;
};
uint32_t val;
} dmaoperation_mode;
volatile union {
struct {
uint32_t dmain_tie : 1; /*When this bit is set with Normal Interrupt Summary Enable (Bit[16]) the Transmit Interrupt is enabled. When this bit is reset the Transmit Interrupt is disabled.*/
uint32_t dmain_tse : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Transmission Stopped Interrupt is enabled. When this bit is reset the Transmission Stopped Interrupt is disabled.*/
uint32_t dmain_tbue : 1; /*When this bit is set with Normal Interrupt Summary Enable (Bit 16) the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset the Transmit Buffer Unavailable Interrupt is Disabled.*/
uint32_t dmain_tjte : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset the Transmit Jabber Timeout Interrupt is disabled.*/
uint32_t dmain_oie : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Receive Overflow Interrupt is enabled. When this bit is reset the Overflow Interrupt is disabled.*/
uint32_t dmain_uie : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Transmit Underflow Interrupt is enabled. When this bit is reset the Underflow Interrupt is disabled.*/
uint32_t dmain_rie : 1; /*When this bit is set with Normal Interrupt Summary Enable (Bit[16]) the Receive Interrupt is enabled. When this bit is reset the Receive Interrupt is disabled.*/
uint32_t dmain_rbue : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset the Receive Buffer Unavailable Interrupt is disabled.*/
uint32_t dmain_rse : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Receive Stopped Interrupt is enabled. When this bit is reset the Receive Stopped Interrupt is disabled.*/
uint32_t dmain_rwte : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset the Receive Watchdog Timeout Interrupt is disabled.*/
uint32_t dmain_etie : 1; /*When this bit is set with an Abnormal Interrupt Summary Enable (Bit[15]) the Early Transmit Interrupt is enabled. When this bit is reset the Early Transmit Interrupt is disabled.*/
uint32_t reserved11 : 2;
uint32_t dmain_fbee : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Fatal Bus Error Interrupt is enabled. When this bit is reset the Fatal Bus Error Enable Interrupt is disabled.*/
uint32_t dmain_erie : 1; /*When this bit is set with Normal Interrupt Summary Enable (Bit[16]) the Early Receive Interrupt is enabled. When this bit is reset the Early Receive Interrupt is disabled.*/
uint32_t dmain_aise : 1; /*When this bit is set abnormal interrupt summary is enabled. When this bit is reset the abnormal interrupt summary is disabled. This bit enables the following interrupts in Status Register: Bit[1]: Transmit Process Stopped. Bit[3]: Transmit Jabber Timeout. Bit[4]: Receive Overflow. Bit[5]: Transmit Underflow. Bit[7]: Receive Buffer Unavailable. Bit[8]: Receive Process Stopped. Bit[9]: Receive Watchdog Timeout. Bit[10]: Early Transmit Interrupt. Bit[13]: Fatal Bus Error.*/
uint32_t dmain_nise : 1; /*When this bit is set normal interrupt summary is enabled. When this bit is reset normal interrupt summary is disabled. This bit enables the following interrupts in Status Register: Bit[0]: Transmit Interrupt. Bit[2]: Transmit Buffer Unavailable. Bit[6]: Receive Interrupt. Bit[14]: Early Receive Interrupt.*/
uint32_t reserved17 : 15;
};
uint32_t val;
} dmain_en;
volatile union {
struct {
uint32_t missed_fc : 16; /*This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read.*/
uint32_t overflow_bmfc : 1; /*This bit is set every time Missed Frame Counter (Bits[15:0]) overflows that is the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened.*/
uint32_t overflow_fc : 11; /*This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read.*/
uint32_t overflow_bfoc : 1; /*This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows that is the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened.*/
uint32_t reserved29 : 3;
};
uint32_t val;
} dmamissedfr;
volatile union {
struct {
uint32_t riwtc : 8; /*This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI(RECV_INT) status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame.*/
uint32_t reserved8 : 24;
};
uint32_t val;
} dmarintwdtimer;
uint32_t reserved_28;
uint32_t reserved_2c;
uint32_t reserved_30;
uint32_t reserved_34;
uint32_t reserved_38;
uint32_t reserved_3c;
uint32_t reserved_40;
uint32_t reserved_44;
uint32_t dmatxcurrdesc; /*The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.*/
uint32_t dmarxcurrdesc; /*The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.*/
uint32_t dmatxcurraddr_buf; /*The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.*/
uint32_t dmarxcurraddr_buf; /*The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.*/
} emac_dma_dev_t;
extern emac_dma_dev_t EMAC_DMA;
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/register/hw_ver2/soc/emac_mac_struct.h Normal file
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
typedef struct {
volatile union {
struct {
uint32_t mac_address_hi : 16; /*This field contains the upper 16 bits Bits[47:32] of the eighth 6-byte MAC Address.*/
uint32_t reserved16 : 8;
uint32_t mask_byte_control : 6; /*These bits are mask control bits for comparison of each of the EMAC_ADDR bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMAC_ADDR registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMAC_ADDR High [15:8]. Bit[28]: EMAC_ADDR High [7:0]. Bit[27]: EMAC_ADDR Low [31:24]. Bit[24]: EMAC_ADDR Low [7:0]. You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
uint32_t source_address : 1; /*When this bit is set the EMAC_ADDR[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMAC_ADDR[47:0] is used to compare with the DA fields of the received frame.*/
uint32_t address_enable : 1; /*When this bit is set the address filter module uses the eighth MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering.*/
};
uint32_t val;
} emacaddrhigh;
uint32_t emacaddrlow; /*This field contains the lower 32 bits of the eighth 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process.*/
} emac_mac_addr_t;
typedef struct emac_mac_dev_s {
volatile union {
struct {
uint32_t pltf : 2; /*These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.2'b00: 7 bytes of preamble. 2'b01: 5 bytes of preamble. 2'b10: 3 bytes of preamble.*/
uint32_t rx : 1; /*When this bit is set the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset the MAC receive state machine is disabled after the completion of the reception of the current frame and does not receive any further frames from the MII.*/
uint32_t tx : 1; /*When this bit is set the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset the MAC transmit state machine is disabled after the completion of the transmission of the current frame and does not transmit any further frames.*/
uint32_t deferralcheck : 1; /*Deferral Check.*/
uint32_t backofflimit : 2; /*The Back-Off limit determines the random integer number (r) of slot time delays (512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode. 00: k= min (n 10). 01: k = min (n 8). 10: k = min (n 4). 11: k = min (n 1) n = retransmission attempt. The random integer r takes the value in the Range 0 ~ 2000.*/
uint32_t padcrcstrip : 1; /*When this bit is set the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1 536 bytes. All received frames with length field greater than or equal to 1 536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset the MAC passes all incoming frames without modifying them to the Host.*/
uint32_t reserved8 : 1;
uint32_t retry : 1; /*When this bit is set the MAC attempts only one transmission. When a collision occurs on the MII interface the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset the MAC attempts retries based on the settings of the BL field (Bits [6:5]). This bit is applicable only in the half-duplex Mode.*/
uint32_t rxipcoffload : 1; /*When this bit is set the MAC calculates the 16-bit one's complement of the one's complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25/26 or 29/30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset this function is disabled.*/
uint32_t duplex : 1; /*When this bit is set the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. This bit is read only with default value of 1'b1 in the full-duplex-mode.*/
uint32_t loopback : 1; /*When this bit is set the MAC operates in the loopback mode MII. The MII Receive clock input (CLK_RX) is required for the loopback to work properly because the transmit clock is not looped-back internally.*/
uint32_t rxown : 1; /*When this bit is set the MAC disables the reception of frames when the TX_EN is asserted in the half-duplex mode. When this bit is reset the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full duplex mode.*/
uint32_t fespeed : 1; /*This bit selects the speed in the MII RMII interface. 0: 10 Mbps. 1: 100 Mbps.*/
uint32_t mii : 1; /*This bit selects the Ethernet line speed. It should be set to 1 for 10 or 100 Mbps operations.In 10 or 100 Mbps operations this bit along with FES(EMACFESPEED) bit it selects the exact linespeed. In the 10/100 Mbps-only operations the bit is always 1.*/
uint32_t disablecrs : 1; /*When set high this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions.*/
uint32_t interframegap : 3; /*These bits control the minimum IFG between frames during transmission. 3'b000: 96 bit times. 3'b001: 88 bit times. 3'b010: 80 bit times. 3'b111: 40 bit times. In the half-duplex mode the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered.*/
uint32_t jumboframe : 1; /*When this bit is set the MAC allows Jumbo frames of 9 018 bytes (9 022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status.*/
uint32_t reserved21 : 1;
uint32_t jabber : 1; /*When this bit is set the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16 383 bytes. When this bit is reset the MAC cuts off the transmitter if the application sends out more than 2 048 bytes of data (10 240 if JE is set high) during Transmission.*/
uint32_t watchdog : 1; /*When this bit is set the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16 383 bytes. When this bit is reset the MAC does not allow a receive frame which more than 2 048 bytes (10 240 if JE is set high) or the value programmed in Register (Watchdog Timeout Register). The MAC cuts off any bytes received after the watchdog limit number of bytes.*/
uint32_t reserved24 : 1;
uint32_t reserved25 : 1;
uint32_t reserved26 : 1;
uint32_t ass2kp : 1; /*When set the MAC considers all frames with up to 2 000 bytes length as normal packets.When Bit[20] (JE) is not set the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit[20] (JE) is not set the MAC considers all received frames of size more than 1 518 bytes (1 522 bytes for tagged) as Giant frames. When Bit[20] is set setting this bit has no effect on Giant Frame status.*/
uint32_t sairc : 3; /*This field controls the source address insertion or replacement for all transmitted frames.Bit[30] specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. 2'b10: If Bit[30] is set to 0 the MAC inserts the content of the MAC Address 0 registers in the SA field of all transmitted frames. If Bit[30] is set to 1 the MAC inserts the content of the MAC Address 1 registers in the SA field of all transmitted frames. 2'b11: If Bit[30] is set to 0 the MAC replaces the content of the MAC Address 0 registers in the SA field of all transmitted frames. If Bit[30] is set to 1 the MAC replaces the content of the MAC Address 1 registers in the SA field of all transmitted frames.*/
uint32_t reserved31 : 1;
};
uint32_t val;
} gmacconfig;
volatile union {
struct {
uint32_t pmode : 1; /*When this bit is set the Address Filter module passes all incoming frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR(PRI_RATIO) is set.*/
uint32_t reserved1 : 1;
uint32_t reserved2 : 1;
uint32_t daif : 1; /*When this bit is set the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset normal filtering of frames is performed.*/
uint32_t pam : 1; /*When set this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed.*/
uint32_t dbf : 1; /*When this bit is set the AFM(Address Filtering Module) module blocks all incoming broadcast frames. In addition it overrides all other filter settings. When this bit is reset the AFM module passes all received broadcast Frames.*/
uint32_t pcf : 2; /*These bits control the forwarding of all control frames (including unicast and multicast Pause frames). 2'b00: MAC filters all control frames from reaching the application. 2'b01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. 2'b10: MAC forwards all control frames to application even if they fail the Address Filter. 2'b11: MAC forwards control frames that pass the Address Filter.The following conditions should be true for the Pause frames processing: Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register (Flow Control Register) to 1. Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register(Flow Control Register) is set. Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001.*/
uint32_t saif : 1; /*When this bit is set the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset frames whose SA does not match the SA registers are marked as failing the SA Address filter.*/
uint32_t safe : 1; /*When this bit is set the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails the MAC drops the frame. When this bit is reset the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison.*/
uint32_t reserved10 : 1;
uint32_t reserved11 : 5;
uint32_t reserved16 : 1;
uint32_t reserved17 : 3;
uint32_t reserved20 : 1;
uint32_t reserved21 : 1;
uint32_t reserved22 : 9;
uint32_t receive_all : 1; /*When this bit is set the MAC Receiver module passes all received frames irrespective of whether they pass the address filter or not to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset the Receiver module passes only those frames to the Application that pass the SA or DA address Filter.*/
};
uint32_t val;
} gmacff;
uint32_t reserved_1008;
uint32_t reserved_100c;
volatile union {
struct {
uint32_t miibusy : 1; /*This bit should read logic 0 before writing to PHY Addr Register and PHY data Register.During a PHY register access the software sets this bit to 1'b1 to indicate that a Read or Write access is in progress. PHY data Register is invalid until this bit is cleared by the MAC. Therefore PHY data Register (MII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed there is no change in the functionality of this bit even when the PHY is not Present.*/
uint32_t miiwrite : 1; /*When set this bit indicates to the PHY that this is a Write operation using the MII Data register. If this bit is not set it indicates that this is a Read operation that is placing the data in the MII Data register.*/
uint32_t miicsrclk : 4; /*CSR clock range: 1.0 MHz ~ 2.5 MHz. 4'b0000: When the APB clock frequency is 80 MHz the MDC clock frequency is APB CLK/42 4'b0011: When the APB clock frequency is 40 MHz the MDC clock frequency is APB CLK/26.*/
uint32_t miireg : 5; /*These bits select the desired MII register in the selected PHY device.*/
uint32_t miidev : 5; /*This field indicates which of the 32 possible PHY devices are being accessed.*/
uint32_t reserved16 : 16;
};
uint32_t val;
} emacgmiiaddr;
volatile union {
struct {
uint32_t mii_data : 16; /*This field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation.*/
uint32_t reserved16 : 16;
};
uint32_t val;
} emacmiidata;
volatile union {
struct {
uint32_t fcbba : 1; /*This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFCE bit is set. In the full-duplex mode this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame the Application must set this bit to 1'b1. During a transfer of the Control Frame this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode when this bit is set (and TFCE is set) then backpressure is asserted by the MAC. During backpressure when the MAC receives a new frame the transmitter starts sending a JAM pattern resulting in a collision. When the MAC is configured for the full-duplex mode the BPA(backpressure activate) is automatically disabled.*/
uint32_t tfce : 1; /*In the full-duplex mode when this bit is set the MAC enables the flow control operation to transmit Pause frames. When this bit is reset the flow control operation in the MAC is disabled and the MAC does not transmit any Pause frames. In the half-duplex mode when this bit is set the MAC enables the backpressure operation. When this bit is reset the backpressure feature is Disabled.*/
uint32_t rfce : 1; /*When this bit is set the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset the decode function of the Pause frame is disabled.*/
uint32_t upfd : 1; /*A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. When this bit is set the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the EMACADDR0 High Register and EMACADDR0 Low Register. When this bit is reset the MAC only detects Pause frames with unique multicast address.*/
uint32_t plt : 2; /*This field configures the threshold of the Pause timer automatic retransmission of the Pause frame.The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example if PT = 100H (256 slot-times) and PLT = 01 then a second Pause frame is automatically transmitted at 228 (256-28) slot times after the first Pause frame is transmitted. The following list provides the threshold values for different values: 2'b00: The threshold is Pause time minus 4 slot times (PT-4 slot times). 2'b01: The threshold is Pause time minus 28 slot times (PT-28 slot times). 2'b10: The threshold is Pause time minus 144 slot times (PT-144 slot times). 2'b11: The threshold is Pause time minus 256 slot times (PT-256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the MII interface.*/
uint32_t reserved6 : 1;
uint32_t dzpq : 1; /*When this bit is set it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of the flow-control signal from the FIFO layer. When this bit is reset normal operation with automatic Zero-Quanta Pause frame generation is enabled.*/
uint32_t reserved8 : 8;
uint32_t pause_time : 16; /*This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain.*/
};
uint32_t val;
} gmacfc;
uint32_t reserved_101c;
uint32_t reserved_1020;
volatile union {
struct {
uint32_t macrpes : 1; /*When high this bit indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state.*/
uint32_t macrffcs : 2; /*When high this field indicates the active state of the FIFO Read and Write controllers of the MAC Receive Frame Controller Module. MACRFFCS[1] represents the status of FIFO Read controller. MACRFFCS[0] represents the status of small FIFO Write controller.*/
uint32_t reserved3 : 1;
uint32_t mtlrfwcas : 1; /*When high this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO.*/
uint32_t mtlrfrcs : 2; /*This field gives the state of the Rx FIFO read Controller: 2'b00: IDLE state.2'b01: Reading frame data.2'b10: Reading frame status (or timestamp).2'b11: Flushing the frame data and status.*/
uint32_t reserved7 : 1;
uint32_t mtlrffls : 2; /*This field gives the status of the fill-level of the Rx FIFO: 2'b00: Rx FIFO Empty. 2'b01: Rx FIFO fill-level below flow-control deactivate threshold. 2'b10: Rx FIFO fill-level above flow-control activate threshold. 2'b11: Rx FIFO Full.*/
uint32_t reserved10 : 6;
uint32_t mactpes : 1; /*When high this bit indicates that the MAC MII transmit protocol engine is actively transmitting data and is not in the IDLE state.*/
uint32_t mactfcs : 2; /*This field indicates the state of the MAC Transmit Frame Controller module: 2'b00: IDLE state. 2'b01: Waiting for status of previous frame or IFG or backoff period to be over. 2'b10: Generating and transmitting a Pause frame (in the full-duplex mode). 2'b11: Transferring input frame for transmission.*/
uint32_t mactp : 1; /*When high this bit indicates that the MAC transmitter is in the Pause condition (in the full-duplex-mode) and hence does not schedule any frame for transmission.*/
uint32_t mtltfrcs : 2; /*This field indicates the state of the Tx FIFO Read Controller: 2'b00: IDLE state. 2'b01: READ state (transferring data to the MAC transmitter). 2'b10: Waiting for TxStatus from the MAC transmitter. 2'b11: Writing the received TxStatus or flushing the Tx FIFO.*/
uint32_t mtltfwcs : 1; /*When high this bit indicates that the MTL Tx FIFO Write Controller is active and is transferring data to the Tx FIFO.*/
uint32_t reserved23 : 1;
uint32_t mtltfnes : 1; /*When high this bit indicates that the MTL Tx FIFO is not empty and some data is left for Transmission.*/
uint32_t mtltsffs : 1; /*When high this bit indicates that the MTL TxStatus FIFO is full. Therefore the MTL cannot accept any more frames for transmission.*/
uint32_t reserved26 : 6;
};
uint32_t val;
} emacdebug;
uint32_t pmt_rwuffr; /*The MSB (31st bit) must be zero.Bit j[30:0] is the byte mask. If Bit 1/2/3/4 (byte number) of the byte mask is set the CRC block processes the Filter 1/2/3/4 Offset + j of the incoming packet(PWKPTR is 0/1/2/3).RWKPTR is 0:Filter 0 Byte Mask .RWKPTR is 1:Filter 1 Byte Mask RWKPTR is 2:Filter 2 Byte Mask RWKPTR is 3:Filter 3 Byte Mask RWKPTR is 4:Bit 3/11/19/27 specifies the address type defining the destination address type of the pattern.When the bit is set the pattern applies to only multicast packets*/
volatile union {
struct {
uint32_t pwrdwn : 1; /*When set the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame.This bit must only be set when MGKPKTEN GLBLUCAST or RWKPKTEN bit is set high.*/
uint32_t mgkpkten : 1; /*When set enables generation of a power management event because of magic packet reception.*/
uint32_t rwkpkten : 1; /*When set enables generation of a power management event because of remote wake-up frame reception*/
uint32_t reserved3 : 2;
uint32_t mgkprcvd : 1; /*When set this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register.*/
uint32_t rwkprcvd : 1; /*When set this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register.*/
uint32_t reserved7 : 2;
uint32_t glblucast : 1; /*When set enables any unicast packet filtered by the MAC (DAFilter) address recognition to be a remote wake-up frame.*/
uint32_t reserved10 : 14;
uint32_t rwkptr : 5; /*The maximum value of the pointer is 7 the detail information please refer to PMT_RWUFFR.*/
uint32_t reserved29 : 2;
uint32_t rwkfiltrst : 1; /*When this bit is set it resets the RWKPTR register to 3’b000.*/
};
uint32_t val;
} pmt_csr;
volatile union {
struct {
uint32_t tlpien : 1; /*When set this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register.*/
uint32_t tlpiex : 1; /*When set this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI_TW_Timer has expired.This bit is cleared by a read into this register.*/
uint32_t rlpien : 1; /*When set this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register.*/
uint32_t rlpiex : 1; /*When set this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the MII interface exited the LPI state and resumed the normal reception. This bit is cleared by a read into this register.*/
uint32_t reserved4 : 4;
uint32_t tlpist : 1; /*When set this bit indicates that the MAC is transmitting the LPI pattern on the MII interface.*/
uint32_t rlpist : 1; /*When set this bit indicates that the MAC is receiving the LPI pattern on the MII interface.*/
uint32_t reserved10 : 6;
uint32_t lpien : 1; /*When set this bit instructs the MAC Transmitter to enter the LPI state. When reset this bit instructs the MAC to exit the LPI state and resume normal transmission.This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission.*/
uint32_t pls : 1; /*This bit indicates the link status of the PHY.When set the link is considered to be okay (up) and when reset the link is considered to be down.*/
uint32_t reserved18 : 1;
uint32_t lpitxa : 1; /*This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side.If the LPITXA and LPIEN bits are set to 1 the MAC enters the LPI mode only after all outstanding frames and pending frames have been transmitted. The MAC comes out of the LPI mode when the application sends any frame.When this bit is 0 the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode.*/
uint32_t reserved20 : 12;
};
uint32_t val;
} gmaclpi_crs;
volatile union {
struct {
uint32_t lpi_tw_timer : 16; /*This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer.*/
uint32_t lpi_ls_timer : 10; /*This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI_LS_Timer reaches the programmed terminal count. The default value of the LPI_LS_Timer is 1000 (1 sec) as defined in the IEEE standard.*/
uint32_t reserved26 : 6;
};
uint32_t val;
} gmaclpitimerscontrol;
volatile union {
struct {
uint32_t reserved0 : 1;
uint32_t reserved1 : 1;
uint32_t reserved2 : 1;
uint32_t pmtints : 1; /*This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bit[5] and Bit[6] in the PMT Control and Status Register). This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. This bit is valid only when you select the optional PMT module during core configuration.*/
uint32_t reserved4 : 1;
uint32_t reserved5 : 1;
uint32_t reserved6 : 1;
uint32_t reserved7 : 1;
uint32_t reserved8 : 1;
uint32_t reserved9 : 1;
uint32_t lpiis : 1; /*When the Energy Efficient Ethernet feature is enabled this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit[0] of Register (LPI Control and Status Register).*/
uint32_t reserved11 : 1;
uint32_t reserved12 : 20;
};
uint32_t val;
} emacints;
volatile union {
struct {
uint32_t reserved0 : 1;
uint32_t reserved1 : 1;
uint32_t reserved2 : 1;
uint32_t pmtintmask : 1; /*When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Interrupt Status Register.*/
uint32_t reserved4 : 5;
uint32_t tsintmask : 1; /*When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Interrupt Status Register. */
uint32_t lpiintmask : 1; /*When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Interrupt Status Register.*/
uint32_t reserved11 : 21;
};
uint32_t val;
} emacintmask;
volatile union {
struct {
uint32_t address0_hi : 16; /*This field contains the upper 16 bits (47:32) of the first 6-byte MAC address.The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames.*/
uint32_t reserved16 : 15;
uint32_t address_enable0 : 1; /*This bit is always set to 1.*/
};
uint32_t val;
} emacaddr0high;
uint32_t emacaddr0low; /*This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames.*/
emac_mac_addr_t emacaddr[15]; /*Offset: 0x40-0xC0. MAC Address1-15 registers. Each MAC address register contains the high and low 32-bit fields for MAC addresses 1-15.*/
uint32_t reserved_10c4; // AN control register
uint32_t reserved_10c8;
uint32_t reserved_10cc;
uint32_t reserved_10d0;
uint32_t reserved_10d4;
volatile union {
struct {
uint32_t link_mode : 1; /*This bit indicates the current mode of operation of the link: 1'b0: Half-duplex mode. 1'b1: Full-duplex mode.*/
uint32_t link_speed : 2; /*This bit indicates the current speed of the link: 2'b00: 2.5 MHz. 2'b01: 25 MHz. 2'b10: 125 MHz.*/
uint32_t reserved3 : 1;
uint32_t jabber_timeout : 1; /*This bit indicates whether there is jabber timeout error (1'b1) in the received Frame.*/
uint32_t reserved5 : 1;
uint32_t reserved6 : 10;
uint32_t reserved16 : 1;
uint32_t reserved17 : 15;
};
uint32_t val;
} emaccstatus;
volatile union {
struct {
uint32_t wdogto : 14; /*When Bit[16] (PWE) is set and Bit[23] (WD) of EMACCONFIG_REG is reset this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field such frame is terminated and declared as an error frame.*/
uint32_t reserved14 : 2;
uint32_t pwdogen : 1; /*When this bit is set and Bit[23] (WD) of EMACCONFIG_REG is reset the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared the watchdog timeout for a received frame is controlled by the setting of Bit[23] (WD) and Bit[20] (JE) in EMACCONFIG_REG.*/
uint32_t reserved17 : 15;
};
uint32_t val;
} emacwdogto;
} emac_mac_dev_t;
extern emac_mac_dev_t EMAC_MAC;
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/register/hw_ver2/soc/emac_ptp_struct.h Normal file
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct emac_ptp_dev_s {
volatile union {
struct {
uint32_t en_timestamp : 1; /* Timestamp Enable */
uint32_t ts_fine_coarse_update : 1; /* Timestamp Fine or Coarse Update */
uint32_t ts_initialize : 1; /* Timestamp Initialize */
uint32_t ts_update : 1; /* Timestamp Update */
uint32_t en_ts_int_trig : 1; /* Timestamp Interrupt Trigger Enable */
uint32_t addend_reg_update : 1; /* Addend Reg Update */
uint32_t reserved1 : 2; /* Reserved */
uint32_t en_ts4all : 1; /* Enable Timestamp for All Frames */
uint32_t ts_digit_bin_roll_ctrl : 1; /* Timestamp Digital or Binary Rollover Control */
uint32_t en_ptp_pkg_proc_ver2_fmt : 1; /* Enable PTP packet Processing for Version 2 Format */
uint32_t en_proc_ptp_ether_frm : 1; /* Enable Processing of PTP over Ethernet Frames */
uint32_t en_proc_ptp_ipv6_udp : 1; /* Enable Processing of PTP Frames Sent over IPv6-UDP */
uint32_t en_proc_ptp_ipv4_udp : 1; /* Enable Processing of PTP Frames Sent over IPv4-UDP */
uint32_t en_ts_snap_event_msg : 1; /* Enable Timestamp Snapshot for Event Messages */
uint32_t en_snap_msg_relevant_master : 1; /* Enable Snapshot for Messages Relevant to Master */
uint32_t sel_snap_type : 2; /* Select PTP packets for Taking Snapshots */
uint32_t en_mac_addr_filter : 1; /* Enable MAC address for PTP Frame Filtering */
uint32_t reserved2 : 5; /* Reserved */
uint32_t aux_snap_fifo_clear : 1; /* Auxiliary Snapshot FIFO Clear */
uint32_t en_aux_snap0 : 1; /* Auxiliary Snapshot 0 Enable */
uint32_t en_aux_snap1 : 1; /* Auxiliary Snapshot 1 Enable */
uint32_t en_aux_snap2 : 1; /* Auxiliary Snapshot 2 Enable */
uint32_t en_aux_snap3 : 1; /* Auxiliary Snapshot 3 Enable */
uint32_t reserved3 : 3; /* Reserved */
};
uint32_t val;
} timestamp_ctrl;
volatile union {
struct {
uint32_t sub_second_incre_value : 8; /* Sub-second Increment Value */
uint32_t reserved : 24; /* Reserved */
};
uint32_t val;
} sub_sec_incre;
volatile union {
struct {
uint32_t ts_second : 32; /* Timestamp Second */
};
uint32_t val;
} sys_seconds;
volatile union {
struct {
uint32_t ts_sub_seconds : 31; /* Timestamp Sub Seconds */
uint32_t reserved: 1; /* Reserved */
};
uint32_t val;
} sys_nanosec;
volatile union {
struct {
uint32_t ts_second : 32; /* Timestamp Second */
};
uint32_t val;
} sys_seconds_update;
volatile union {
struct {
uint32_t ts_sub_seconds : 31; /* Timestamp Sub Seconds */
uint32_t add_sub : 1; /* Add or Subtract Time */
};
uint32_t val;
} sys_nanosec_update;
volatile union {
struct {
uint32_t ts_addend_val: 32; /* Timestamp Addend Register */
};
uint32_t val;
} timestamp_addend;
volatile union {
struct {
uint32_t tgt_time_second_val : 32; /* Target Time Seconds Register */
};
uint32_t val;
} tgt_seconds;
volatile union {
struct {
uint32_t tgt_ts_low_reg : 31; /* Target Timestamp Low Register */
uint32_t tgt_time_reg_busy : 1; /* Target Time Register Busy */
};
uint32_t val;
} tgt_nanosec;
volatile union {
struct {
uint32_t ts_higher_word : 16; /* Timestamp Higher Word Register */
uint32_t reserved : 16; /* Reserved */
};
uint32_t val;
} sys_seconds_high;
volatile union {
struct {
uint32_t ts_secons_ovf : 1; /* Timestamp Seconds Overflow */
uint32_t ts_tgt_time_reach : 1; /* Timestamp Target Time Reached */
uint32_t aux_ts_trig_snap : 1; /* Auxiliary Timestamp Trigger Snapshot */
uint32_t ts_tgt_time_err : 1; /* Timestamp Target Time Error */
uint32_t ts_tgt_time_reach_pps1 : 1; /* Timestamp Target Time Reached for Target Time PPS1 */
uint32_t ts_tgt_time_err1 : 1; /* Timestamp Target Time Error */
uint32_t ts_tgt_time_reach_pps2 : 1; /* Timestamp Target Time Reached for Target Time PPS2 */
uint32_t ts_tgt_time_err2 : 1; /* Timestamp Target Time Error */
uint32_t ts_tgt_time_reach_pps3 : 1; /* Timestamp Target Time Reached for Target Time PPS3 */
uint32_t ts_tgt_time_err3 : 1; /* Timestamp Target Time Error */
uint32_t reserved1 : 6; /* Reserved */
uint32_t aux_ts_snap_trig_identify : 4; /* Auxiliary Timestamp Snapshot Trigger Identifier */
uint32_t reserved2 : 4; /* Reserved */
uint32_t aux_tx_snap_trig_miss : 1; /* Auxiliary Timestamp Snapshot Trigger Missed */
uint32_t aux_ts_snap_num : 5; /* Number of Auxiliary Timestamp Snapshots */
uint32_t reserved : 2; /* Reserved */
};
uint32_t val;
} status;
volatile union {
struct {
uint32_t pps_cmd0 : 4; /* Flexible PPS0 Output Control */
uint32_t en_pps0 : 1; /* Flexible PPS Output Mode Enable */
uint32_t tgt_mode_sel0 : 2; /* Target Time Register Mode for PPS0 Output */
uint32_t reserved1 : 1; /* Reserved */
uint32_t pps_cmd1 : 3; /* Flexible PPS1 Output Control */
uint32_t reserved2 : 2; /* Reserved */
uint32_t tgt_mode_sel1 : 2; /* Target Time Register Mode for PPS1 Output */
uint32_t reserved3 : 1; /* Reserved */
uint32_t pps_cmd2 : 3; /* Flexible PPS2 Output Control */
uint32_t reserved4 : 2; /* Reserved */
uint32_t tgt_mode_sel2 : 2; /* Target Time Register Mode for PPS2 Output */
uint32_t reserved5 : 1; /* Reserved */
uint32_t pps_cmd3 : 3; /* Flexible PPS3 Output Control */
uint32_t reserved6 : 2; /* Reserved */
uint32_t tgt_mode_sel3 : 2; /* Target Time Register Mode for PPS3 Output */
uint32_t reserved7 : 1; /* Reserved */
};
uint32_t val;
} pps_ctrl;
volatile union {
struct {
uint32_t aux_ts_low : 31; /* Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. */
uint32_t reserved : 1; /* Reserved */
};
uint32_t val;
} aux_nanosec;
volatile union {
struct {
uint32_t aux_tx_high : 32; /* Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. */
};
uint32_t val;
} aux_seconds;
volatile union {
struct {
uint32_t av_ethertype_val : 16; /* AV EtherType Value */
uint32_t ac_queue_pri : 3; /* AV Priority for Queuing */
uint32_t en_queue_non_av_pkt : 1; /* VLAN Tagged Non-AV Packets Queueing Enable */
uint32_t dis_av_chann : 1; /* AV Channel Disable */
uint32_t queue_av_ctrl_pkt_chann : 2; /* Channel for Queuing the AV Control Packets */
uint32_t reserved1 : 1; /* Reserved */
uint32_t queue_ptp_pkt_chann : 2; /* Channel for Queuing the PTP Packets */
uint32_t reserved2 : 6; /* Reserved */
};
uint32_t val;
} av_mac_ctrl;
uint32_t reserved1[9]; /* Reserved */
volatile union {
struct {
uint32_t pps0_interval : 32; /* PPS0 Output Signal Interval */
};
uint32_t val;
} pps0_interval;
volatile union {
struct {
uint32_t pps0_width : 32; /* PPS0 Output Signal Width */
};
uint32_t val;
} pps0_width;
uint32_t reserved2[6]; /* Reserved */
volatile union {
struct {
uint32_t pps1_tgt_seconds : 32; /* PPS1 Target Time Seconds Register */
};
uint32_t val;
} pps1_tgt_seconds;
volatile union {
struct {
uint32_t pps1_tgt_nanosec : 31; /* Target Time Low for PPS1 Register */
uint32_t pps1_tgt_time_busy : 1; /* PPS1 Target Time Register Busy */
};
uint32_t val;
} pps1_tgt_nanosec;
volatile union {
struct {
uint32_t pps1_interval : 32; /* PPS1 Output Signal Interval */
};
uint32_t val;
} pps1_interval;
volatile union {
struct {
uint32_t pps1_width : 32; /* PPS1 Output Signal Width */
};
uint32_t val;
} pps1_width;
uint32_t reserved3[4]; /* Reserved */
volatile union {
struct {
uint32_t pps2_tgt_seconds : 32; /* PPS2 Target Time Seconds Register */
};
uint32_t val;
} pps2_tgt_seconds;
volatile union {
struct {
uint32_t pps2_tgt_nanosec : 31; /* Target Time Low for PPS2 Register */
uint32_t pps2_tgt_time_busy : 1; /* PPS2 Target Time Register Busy */
};
uint32_t val;
} pps2_tgt_nanosec;
volatile union {
struct {
uint32_t pps2_interval : 32; /* PPS2 Output Signal Interval */
};
uint32_t val;
} pps2_interval;
volatile union {
struct {
uint32_t pps2_width : 32; /* PPS2 Output Signal Width */
};
uint32_t val;
} pps2_width;
uint32_t reserved4[4]; /* Reserved */
volatile union {
struct {
uint32_t pps3_tgt_seconds : 32; /* PPS3 Target Time Seconds Register */
};
uint32_t val;
} pps3_tgt_seconds;
volatile union {
struct {
uint32_t pps3_tgt_nanosec : 31; /* Target Time Low for PPS3 Register */
uint32_t pps3_tgt_time_busy : 1; /* PPS3 Target Time Register Busy */
};
uint32_t val;
} pps3_tgt_nanosec;
volatile union {
struct {
uint32_t pps3_interval : 32; /* PPS3 Output Signal Interval */
};
uint32_t val;
} pps3_interval;
volatile union {
struct {
uint32_t pps3_width : 32; /* PPS3 Output Signal Width */
};
uint32_t val;
} pps3_width;
} emac_ptp_dev_t;
extern emac_ptp_dev_t EMAC_PTP;
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/register/hw_ver2/soc/gpio_ext_eco5_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: SDM Configure Registers */
/** Type of sigmadeltan register
* Duty Cycle Configure Register of SDMn
*/
typedef union {
struct {
/** sdn_in : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output.
*/
uint32_t sdn_in:8;
/** sdn_prescale : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
uint32_t sdn_prescale:8;
uint32_t reserved_16:16;
};
uint32_t val;
} gpiosd_sigmadeltan_reg_t;
/** Type of sigmadelta_misc register
* MISC Register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** function_clk_en : R/W; bitpos: [30]; default: 0;
* Clock enable bit of sigma delta modulation.
*/
uint32_t function_clk_en:1;
/** spi_swap : R/W; bitpos: [31]; default: 0;
* Reserved.
*/
uint32_t spi_swap:1;
};
uint32_t val;
} gpiosd_sigmadelta_misc_reg_t;
/** Group: Glitch filter Configure Registers */
/** Type of glitch_filter_chn register
* Glitch Filter Configure Register of Channeln
*/
typedef union {
struct {
/** filter_ch0_en : R/W; bitpos: [0]; default: 0;
* Glitch Filter channel enable bit.
*/
uint32_t filter_ch0_en:1;
/** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0;
* Glitch Filter input io number.
*/
uint32_t filter_ch0_input_io_num:6;
/** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0;
* Glitch Filter window threshold.
*/
uint32_t filter_ch0_window_thres:6;
/** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0;
* Glitch Filter window width.
*/
uint32_t filter_ch0_window_width:6;
uint32_t reserved_19:13;
};
uint32_t val;
} gpiosd_glitch_filter_chn_reg_t;
/** Group: Etm Configure Registers */
/** Type of etm_event_chn_cfg register
* Etm Config register of Channeln
*/
typedef union {
struct {
/** etm_ch0_event_sel : R/W; bitpos: [5:0]; default: 0;
* Etm event channel select gpio.
*/
uint32_t etm_ch0_event_sel:6;
uint32_t reserved_6:1;
/** etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
* Etm event send enable bit.
*/
uint32_t etm_ch0_event_en:1;
uint32_t reserved_8:24;
};
uint32_t val;
} gpiosd_etm_event_chn_cfg_reg_t;
/** Type of etm_task_p0_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio0_en:1;
/** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio0_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio1_en:1;
/** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio1_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio2_en:1;
/** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio2_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio3_en:1;
/** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio3_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p0_cfg_reg_t;
/** Type of etm_task_p1_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio4_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio4_en:1;
/** etm_task_gpio4_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio4_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio5_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio5_en:1;
/** etm_task_gpio5_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio5_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio6_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio6_en:1;
/** etm_task_gpio6_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio6_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio7_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio7_en:1;
/** etm_task_gpio7_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio7_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p1_cfg_reg_t;
/** Type of etm_task_p2_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio8_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio8_en:1;
/** etm_task_gpio8_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio8_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio9_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio9_en:1;
/** etm_task_gpio9_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio9_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio10_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio10_en:1;
/** etm_task_gpio10_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio10_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio11_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio11_en:1;
/** etm_task_gpio11_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio11_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p2_cfg_reg_t;
/** Type of etm_task_p3_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio12_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio12_en:1;
/** etm_task_gpio12_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio12_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio13_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio13_en:1;
/** etm_task_gpio13_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio13_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio14_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio14_en:1;
/** etm_task_gpio14_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio14_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio15_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio15_en:1;
/** etm_task_gpio15_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio15_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p3_cfg_reg_t;
/** Type of etm_task_p4_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio16_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio16_en:1;
/** etm_task_gpio16_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio16_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio17_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio17_en:1;
/** etm_task_gpio17_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio17_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio18_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio18_en:1;
/** etm_task_gpio18_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio18_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio19_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio19_en:1;
/** etm_task_gpio19_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio19_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p4_cfg_reg_t;
/** Type of etm_task_p5_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio20_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio20_en:1;
/** etm_task_gpio20_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio20_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio21_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio21_en:1;
/** etm_task_gpio21_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio21_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio22_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio22_en:1;
/** etm_task_gpio22_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio22_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio23_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio23_en:1;
/** etm_task_gpio23_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio23_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p5_cfg_reg_t;
/** Type of etm_task_p6_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio24_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio24_en:1;
/** etm_task_gpio24_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio24_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio25_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio25_en:1;
/** etm_task_gpio25_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio25_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio26_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio26_en:1;
/** etm_task_gpio26_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio26_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio27_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio27_en:1;
/** etm_task_gpio27_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio27_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p6_cfg_reg_t;
/** Type of etm_task_p7_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio28_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio28_en:1;
/** etm_task_gpio28_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio28_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio29_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio29_en:1;
/** etm_task_gpio29_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio29_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio30_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio30_en:1;
/** etm_task_gpio30_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio30_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio31_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio31_en:1;
/** etm_task_gpio31_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio31_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p7_cfg_reg_t;
/** Type of etm_task_p8_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio32_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio32_en:1;
/** etm_task_gpio32_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio32_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio33_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio33_en:1;
/** etm_task_gpio33_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio33_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio34_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio34_en:1;
/** etm_task_gpio34_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio34_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio35_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio35_en:1;
/** etm_task_gpio35_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio35_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p8_cfg_reg_t;
/** Type of etm_task_p9_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio36_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio36_en:1;
/** etm_task_gpio36_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio36_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio37_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio37_en:1;
/** etm_task_gpio37_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio37_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio38_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio38_en:1;
/** etm_task_gpio38_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio38_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio39_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio39_en:1;
/** etm_task_gpio39_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio39_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p9_cfg_reg_t;
/** Type of etm_task_p10_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio40_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio40_en:1;
/** etm_task_gpio40_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio40_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio41_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio41_en:1;
/** etm_task_gpio41_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio41_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio42_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio42_en:1;
/** etm_task_gpio42_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio42_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio43_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio43_en:1;
/** etm_task_gpio43_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio43_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p10_cfg_reg_t;
/** Type of etm_task_p11_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio44_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio44_en:1;
/** etm_task_gpio44_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio44_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio45_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio45_en:1;
/** etm_task_gpio45_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio45_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio46_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio46_en:1;
/** etm_task_gpio46_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio46_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio47_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio47_en:1;
/** etm_task_gpio47_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio47_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p11_cfg_reg_t;
/** Type of etm_task_p12_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio48_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio48_en:1;
/** etm_task_gpio48_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio48_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio49_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio49_en:1;
/** etm_task_gpio49_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio49_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio50_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio50_en:1;
/** etm_task_gpio50_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio50_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio51_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio51_en:1;
/** etm_task_gpio51_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio51_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p12_cfg_reg_t;
/** Type of etm_task_p13_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio52_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio52_en:1;
/** etm_task_gpio52_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio52_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio53_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio53_en:1;
/** etm_task_gpio53_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio53_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio54_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio54_en:1;
/** etm_task_gpio54_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio54_sel:3;
uint32_t reserved_20:12;
};
uint32_t val;
} gpiosd_etm_task_p13_cfg_reg_t;
/** Group: Version Register */
/** Type of version register
* Version Control Register
*/
typedef union {
struct {
/** gpio_sd_date : R/W; bitpos: [27:0]; default: 35663952;
* Version control register.
*/
uint32_t gpio_sd_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_version_reg_t;
typedef struct {
volatile gpiosd_sigmadeltan_reg_t sigmadeltan[8];
uint32_t reserved_020;
volatile gpiosd_sigmadelta_misc_reg_t sigmadelta_misc;
uint32_t reserved_028[2];
volatile gpiosd_glitch_filter_chn_reg_t glitch_filter_chn[8];
uint32_t reserved_050[4];
volatile gpiosd_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
uint32_t reserved_080[8];
volatile gpiosd_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
volatile gpiosd_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
volatile gpiosd_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
volatile gpiosd_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
volatile gpiosd_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
volatile gpiosd_etm_task_p5_cfg_reg_t etm_task_p5_cfg;
volatile gpiosd_etm_task_p6_cfg_reg_t etm_task_p6_cfg;
volatile gpiosd_etm_task_p7_cfg_reg_t etm_task_p7_cfg;
volatile gpiosd_etm_task_p8_cfg_reg_t etm_task_p8_cfg;
volatile gpiosd_etm_task_p9_cfg_reg_t etm_task_p9_cfg;
volatile gpiosd_etm_task_p10_cfg_reg_t etm_task_p10_cfg;
volatile gpiosd_etm_task_p11_cfg_reg_t etm_task_p11_cfg;
volatile gpiosd_etm_task_p12_cfg_reg_t etm_task_p12_cfg;
volatile gpiosd_etm_task_p13_cfg_reg_t etm_task_p13_cfg;
uint32_t reserved_0d8[9];
volatile gpiosd_version_reg_t version;
} gpiosd_dev_t;
extern gpiosd_dev_t GPIO;
#ifndef __cplusplus
_Static_assert(sizeof(gpiosd_dev_t) == 0x100, "Invalid size of gpiosd_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/register/hw_ver2/soc/gpio_ext_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: SDM Configure Registers */
/** Type of sigmadeltan register
* Duty Cycle Configure Register of SDMn
*/
typedef union {
struct {
/** duty : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output.
*/
uint32_t duty: 8;
/** prescale : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
uint32_t prescale: 8;
uint32_t reserved_16: 16;
};
uint32_t val;
} gpio_sigmadelta_chn_reg_t;
/** Type of sigmadelta_misc register
* MISC Register
*/
typedef union {
struct {
uint32_t reserved_0: 30;
/** function_clk_en : R/W; bitpos: [30]; default: 0;
* Clock enable bit of sigma delta modulation.
*/
uint32_t function_clk_en: 1;
/** spi_swap : R/W; bitpos: [31]; default: 0;
* Reserved.
*/
uint32_t spi_swap: 1;
};
uint32_t val;
} gpio_sigmadelta_misc_reg_t;
/** Group: Glitch filter Configure Registers */
/** Type of glitch_filter_chn register
* Glitch Filter Configure Register of Channeln
*/
typedef union {
struct {
/** filter_chn_en : R/W; bitpos: [0]; default: 0;
* Glitch Filter channel enable bit.
*/
uint32_t filter_chn_en: 1;
/** filter_chn_input_io_num : R/W; bitpos: [6:1]; default: 0;
* Glitch Filter input io number.
*/
uint32_t filter_chn_input_io_num: 6;
/** filter_chn_window_thres : R/W; bitpos: [12:7]; default: 0;
* Glitch Filter window threshold.
*/
uint32_t filter_chn_window_thres: 6;
/** filter_chn_window_width : R/W; bitpos: [18:13]; default: 0;
* Glitch Filter window width.
*/
uint32_t filter_chn_window_width: 6;
uint32_t reserved_19: 13;
};
uint32_t val;
} gpio_glitch_filter_chn_reg_t;
/** Group: Etm Configure Registers */
/** Type of etm_event_chn_cfg register
* Etm Config register of Channeln
*/
typedef union {
struct {
/** etm_chn_event_sel : R/W; bitpos: [5:0]; default: 0;
* Etm event channel select gpio.
*/
uint32_t etm_chn_event_sel: 6;
uint32_t reserved_6: 1;
/** etm_chn_event_en : R/W; bitpos: [7]; default: 0;
* Etm event send enable bit.
*/
uint32_t etm_chn_event_en: 1;
uint32_t reserved_8: 24;
};
uint32_t val;
} gpio_etm_event_chn_cfg_reg_t;
/** Type of etm_task_p0_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio0_en: 1;
/** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio0_sel: 3;
uint32_t reserved_4: 4;
/** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio1_en: 1;
/** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio1_sel: 3;
uint32_t reserved_12: 4;
/** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio2_en: 1;
/** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio2_sel: 3;
uint32_t reserved_20: 4;
/** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio3_en: 1;
/** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio3_sel: 3;
uint32_t reserved_28: 4;
};
uint32_t val;
} gpio_etm_task_pn_cfg_reg_t;
/** Group: Version Register */
/** Type of version register
* Version Control Register
*/
typedef union {
struct {
/** gpio_ext_date : R/W; bitpos: [27:0]; default: 35663952;
* Version control register.
*/
uint32_t gpio_ext_date: 28;
uint32_t reserved_28: 4;
};
uint32_t val;
} gpio_ext_version_reg_t;
typedef struct gpio_sd_dev_t {
volatile gpio_sigmadelta_chn_reg_t channel[8];
uint32_t reserved_020;
volatile gpio_sigmadelta_misc_reg_t misc;
} gpio_sd_dev_t;
typedef struct gpio_glitch_filter_dev_t {
volatile gpio_glitch_filter_chn_reg_t glitch_filter_chn[8];
} gpio_glitch_filter_dev_t;
typedef struct gpio_etm_dev_t {
volatile gpio_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
uint32_t reserved_080[8];
volatile gpio_etm_task_pn_cfg_reg_t etm_task_pn_cfg[14];
} gpio_etm_dev_t;
typedef struct {
volatile gpio_sd_dev_t sigma_delta;
uint32_t reserved_028[2];
volatile gpio_glitch_filter_dev_t glitch_filter;
uint32_t reserved_050[4];
volatile gpio_etm_dev_t etm;
uint32_t reserved_0d8[9];
volatile gpio_ext_version_reg_t version;
} gpio_ext_dev_t;
extern gpio_sd_dev_t SDM;
extern gpio_glitch_filter_dev_t GLITCH_FILTER;
extern gpio_etm_dev_t GPIO_ETM;
extern gpio_ext_dev_t GPIO_EXT;
#ifndef __cplusplus
_Static_assert(sizeof(gpio_ext_dev_t) == 0x100, "Invalid size of gpio_ext_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/register/hw_ver2/soc/gpio_reg.h Normal file
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components/soc/esp32p4/register/hw_ver2/soc/gpio_sig_map.h Normal file
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define SD_CARD_CCLK_2_PAD_OUT_IDX 0
#define SD_CARD_CCMD_2_PAD_IN_IDX 1
#define SD_CARD_CCMD_2_PAD_OUT_IDX 1
#define SD_CARD_CDATA0_2_PAD_IN_IDX 2
#define SD_CARD_CDATA0_2_PAD_OUT_IDX 2
#define SD_CARD_CDATA1_2_PAD_IN_IDX 3
#define SD_CARD_CDATA1_2_PAD_OUT_IDX 3
#define SD_CARD_CDATA2_2_PAD_IN_IDX 4
#define SD_CARD_CDATA2_2_PAD_OUT_IDX 4
#define SD_CARD_CDATA3_2_PAD_IN_IDX 5
#define SD_CARD_CDATA3_2_PAD_OUT_IDX 5
#define SD_CARD_CDATA4_2_PAD_IN_IDX 6
#define SD_CARD_CDATA4_2_PAD_OUT_IDX 6
#define SD_CARD_CDATA5_2_PAD_IN_IDX 7
#define SD_CARD_CDATA5_2_PAD_OUT_IDX 7
#define SD_CARD_CDATA6_2_PAD_IN_IDX 8
#define SD_CARD_CDATA6_2_PAD_OUT_IDX 8
#define SD_CARD_CDATA7_2_PAD_IN_IDX 9
#define SD_CARD_CDATA7_2_PAD_OUT_IDX 9
#define UART0_RXD_PAD_IN_IDX 10
#define UART0_TXD_PAD_OUT_IDX 10
#define UART0_CTS_PAD_IN_IDX 11
#define UART0_RTS_PAD_OUT_IDX 11
#define UART0_DSR_PAD_IN_IDX 12
#define UART0_DTR_PAD_OUT_IDX 12
#define UART1_RXD_PAD_IN_IDX 13
#define UART1_TXD_PAD_OUT_IDX 13
#define UART1_CTS_PAD_IN_IDX 14
#define UART1_RTS_PAD_OUT_IDX 14
#define UART1_DSR_PAD_IN_IDX 15
#define UART1_DTR_PAD_OUT_IDX 15
#define UART2_RXD_PAD_IN_IDX 16
#define UART2_TXD_PAD_OUT_IDX 16
#define UART2_CTS_PAD_IN_IDX 17
#define UART2_RTS_PAD_OUT_IDX 17
#define UART2_DSR_PAD_IN_IDX 18
#define UART2_DTR_PAD_OUT_IDX 18
#define UART3_RXD_PAD_IN_IDX 19
#define UART3_TXD_PAD_OUT_IDX 19
#define UART3_CTS_PAD_IN_IDX 20
#define UART3_RTS_PAD_OUT_IDX 20
#define UART3_DSR_PAD_IN_IDX 21
#define UART3_DTR_PAD_OUT_IDX 21
#define UART4_RXD_PAD_IN_IDX 22
#define UART4_TXD_PAD_OUT_IDX 22
#define UART4_CTS_PAD_IN_IDX 23
#define UART4_RTS_PAD_OUT_IDX 23
#define UART4_DSR_PAD_IN_IDX 24
#define UART4_DTR_PAD_OUT_IDX 24
#define I2S0_O_BCK_PAD_IN_IDX 25
#define I2S0_O_BCK_PAD_OUT_IDX 25
#define I2S0_MCLK_PAD_IN_IDX 26
#define I2S0_MCLK_PAD_OUT_IDX 26
#define I2S0_O_WS_PAD_IN_IDX 27
#define I2S0_O_WS_PAD_OUT_IDX 27
#define I2S0_I_SD_PAD_IN_IDX 28
#define I2S0_O_SD_PAD_OUT_IDX 28
#define I2S0_I_BCK_PAD_IN_IDX 29
#define I2S0_I_BCK_PAD_OUT_IDX 29
#define I2S0_I_WS_PAD_IN_IDX 30
#define I2S0_I_WS_PAD_OUT_IDX 30
#define I2S1_O_BCK_PAD_IN_IDX 31
#define I2S1_O_BCK_PAD_OUT_IDX 31
#define I2S1_MCLK_PAD_IN_IDX 32
#define I2S1_MCLK_PAD_OUT_IDX 32
#define I2S1_O_WS_PAD_IN_IDX 33
#define I2S1_O_WS_PAD_OUT_IDX 33
#define I2S1_I_SD_PAD_IN_IDX 34
#define I2S1_O_SD_PAD_OUT_IDX 34
#define I2S1_I_BCK_PAD_IN_IDX 35
#define I2S1_I_BCK_PAD_OUT_IDX 35
#define I2S1_I_WS_PAD_IN_IDX 36
#define I2S1_I_WS_PAD_OUT_IDX 36
#define I2S2_O_BCK_PAD_IN_IDX 37
#define I2S2_O_BCK_PAD_OUT_IDX 37
#define I2S2_MCLK_PAD_IN_IDX 38
#define I2S2_MCLK_PAD_OUT_IDX 38
#define I2S2_O_WS_PAD_IN_IDX 39
#define I2S2_O_WS_PAD_OUT_IDX 39
#define I2S2_I_SD_PAD_IN_IDX 40
#define I2S2_O_SD_PAD_OUT_IDX 40
#define I2S2_I_BCK_PAD_IN_IDX 41
#define I2S2_I_BCK_PAD_OUT_IDX 41
#define I2S2_I_WS_PAD_IN_IDX 42
#define I2S2_I_WS_PAD_OUT_IDX 42
#define I2S0_I_SD1_PAD_IN_IDX 43
#define I2S0_O_SD1_PAD_OUT_IDX 43
#define I2S0_I_SD2_PAD_IN_IDX 44
#define SPI2_DQS_PAD_OUT_IDX 44
#define I2S0_I_SD3_PAD_IN_IDX 45
#define SPI3_CS2_PAD_OUT_IDX 45
#define SPI3_CS1_PAD_OUT_IDX 46
#define SPI3_CK_PAD_IN_IDX 47
#define SPI3_CK_PAD_OUT_IDX 47
#define SPI3_Q_PAD_IN_IDX 48
#define SPI3_QO_PAD_OUT_IDX 48
#define SPI3_D_PAD_IN_IDX 49
#define SPI3_D_PAD_OUT_IDX 49
#define SPI3_HOLD_PAD_IN_IDX 50
#define SPI3_HOLD_PAD_OUT_IDX 50
#define SPI3_WP_PAD_IN_IDX 51
#define SPI3_WP_PAD_OUT_IDX 51
#define SPI3_CS_PAD_IN_IDX 52
#define SPI3_CS_PAD_OUT_IDX 52
#define SPI2_CK_PAD_IN_IDX 53
#define SPI2_CK_PAD_OUT_IDX 53
#define SPI2_Q_PAD_IN_IDX 54
#define SPI2_Q_PAD_OUT_IDX 54
#define SPI2_D_PAD_IN_IDX 55
#define SPI2_D_PAD_OUT_IDX 55
#define SPI2_HOLD_PAD_IN_IDX 56
#define SPI2_HOLD_PAD_OUT_IDX 56
#define SPI2_WP_PAD_IN_IDX 57
#define SPI2_WP_PAD_OUT_IDX 57
#define SPI2_IO4_PAD_IN_IDX 58
#define SPI2_IO4_PAD_OUT_IDX 58
#define SPI2_IO5_PAD_IN_IDX 59
#define SPI2_IO5_PAD_OUT_IDX 59
#define SPI2_IO6_PAD_IN_IDX 60
#define SPI2_IO6_PAD_OUT_IDX 60
#define SPI2_IO7_PAD_IN_IDX 61
#define SPI2_IO7_PAD_OUT_IDX 61
#define SPI2_CS_PAD_IN_IDX 62
#define SPI2_CS_PAD_OUT_IDX 62
#define PCNT_RST_PAD_IN0_IDX 63
#define SPI2_CS1_PAD_OUT_IDX 63
#define PCNT_RST_PAD_IN1_IDX 64
#define SPI2_CS2_PAD_OUT_IDX 64
#define PCNT_RST_PAD_IN2_IDX 65
#define SPI2_CS3_PAD_OUT_IDX 65
#define PCNT_RST_PAD_IN3_IDX 66
#define SPI2_CS4_PAD_OUT_IDX 66
#define SPI2_CS5_PAD_OUT_IDX 67
#define I2C0_SCL_PAD_IN_IDX 68
#define I2C0_SCL_PAD_OUT_IDX 68
#define I2C0_SDA_PAD_IN_IDX 69
#define I2C0_SDA_PAD_OUT_IDX 69
#define I2C1_SCL_PAD_IN_IDX 70
#define I2C1_SCL_PAD_OUT_IDX 70
#define I2C1_SDA_PAD_IN_IDX 71
#define I2C1_SDA_PAD_OUT_IDX 71
#define GPIO_SD0_OUT_IDX 72
#define GPIO_SD1_OUT_IDX 73
#define UART0_SLP_CLK_PAD_IN_IDX 74
#define GPIO_SD2_OUT_IDX 74
#define UART1_SLP_CLK_PAD_IN_IDX 75
#define GPIO_SD3_OUT_IDX 75
#define UART2_SLP_CLK_PAD_IN_IDX 76
#define GPIO_SD4_OUT_IDX 76
#define UART3_SLP_CLK_PAD_IN_IDX 77
#define GPIO_SD5_OUT_IDX 77
#define UART4_SLP_CLK_PAD_IN_IDX 78
#define GPIO_SD6_OUT_IDX 78
#define GPIO_SD7_OUT_IDX 79
#define TWAI0_RX_PAD_IN_IDX 80
#define TWAI0_TX_PAD_OUT_IDX 80
#define TWAI0_BUS_OFF_ON_PAD_OUT_IDX 81
#define TWAI0_CLKOUT_PAD_OUT_IDX 82
#define TWAI1_RX_PAD_IN_IDX 83
#define TWAI1_TX_PAD_OUT_IDX 83
#define TWAI1_BUS_OFF_ON_PAD_OUT_IDX 84
#define TWAI1_CLKOUT_PAD_OUT_IDX 85
#define TWAI2_RX_PAD_IN_IDX 86
#define TWAI2_TX_PAD_OUT_IDX 86
#define TWAI2_BUS_OFF_ON_PAD_OUT_IDX 87
#define TWAI2_CLKOUT_PAD_OUT_IDX 88
#define PWM0_SYNC0_PAD_IN_IDX 89
#define PWM0_CH0_A_PAD_OUT_IDX 89
#define PWM0_SYNC1_PAD_IN_IDX 90
#define PWM0_CH0_B_PAD_OUT_IDX 90
#define PWM0_SYNC2_PAD_IN_IDX 91
#define PWM0_CH1_A_PAD_OUT_IDX 91
#define PWM0_F0_PAD_IN_IDX 92
#define PWM0_CH1_B_PAD_OUT_IDX 92
#define PWM0_F1_PAD_IN_IDX 93
#define PWM0_CH2_A_PAD_OUT_IDX 93
#define PWM0_F2_PAD_IN_IDX 94
#define PWM0_CH2_B_PAD_OUT_IDX 94
#define PWM0_CAP0_PAD_IN_IDX 95
#define PWM1_CH0_A_PAD_OUT_IDX 95
#define PWM0_CAP1_PAD_IN_IDX 96
#define PWM1_CH0_B_PAD_OUT_IDX 96
#define PWM0_CAP2_PAD_IN_IDX 97
#define PWM1_CH1_A_PAD_OUT_IDX 97
#define PWM1_SYNC0_PAD_IN_IDX 98
#define PWM1_CH1_B_PAD_OUT_IDX 98
#define PWM1_SYNC1_PAD_IN_IDX 99
#define PWM1_CH2_A_PAD_OUT_IDX 99
#define PWM1_SYNC2_PAD_IN_IDX 100
#define PWM1_CH2_B_PAD_OUT_IDX 100
#define PWM1_F0_PAD_IN_IDX 101
#define PWM1_F1_PAD_IN_IDX 102
#define PWM1_F2_PAD_IN_IDX 103
#define PWM1_CAP0_PAD_IN_IDX 104
#define PWM1_CAP1_PAD_IN_IDX 105
#define TWAI0_STANDBY_PAD_OUT_IDX 105
#define PWM1_CAP2_PAD_IN_IDX 106
#define TWAI1_STANDBY_PAD_OUT_IDX 106
#define GMII_MDI_PAD_IN_IDX 107
#define TWAI2_STANDBY_PAD_OUT_IDX 107
#define GMAC_PHY_COL_PAD_IN_IDX 108
#define GMII_MDC_PAD_OUT_IDX 108
#define GMAC_PHY_CRS_PAD_IN_IDX 109
#define GMII_MDO_PAD_OUT_IDX 109
#define USB_OTG11_IDDIG_PAD_IN_IDX 110
#define USB_SRP_DISCHRGVBUS_PAD_OUT_IDX 110
#define USB_OTG11_AVALID_PAD_IN_IDX 111
#define USB_OTG11_IDPULLUP_PAD_OUT_IDX 111
#define USB_SRP_BVALID_PAD_IN_IDX 112
#define USB_OTG11_DPPULLDOWN_PAD_OUT_IDX 112
#define USB_OTG11_VBUSVALID_PAD_IN_IDX 113
#define USB_OTG11_DMPULLDOWN_PAD_OUT_IDX 113
#define USB_SRP_SESSEND_PAD_IN_IDX 114
#define USB_OTG11_DRVVBUS_PAD_OUT_IDX 114
#define USB_SRP_CHRGVBUS_PAD_OUT_IDX 115
#define ULPI_CLK_PAD_IN_IDX 117
#define RNG_CHAIN_CLK_PAD_OUT_IDX 117
#define USB_HSPHY_REFCLK_IN_IDX 118
#define HP_PROBE_TOP_OUT0_IDX 118
#define HP_PROBE_TOP_OUT1_IDX 119
#define HP_PROBE_TOP_OUT2_IDX 120
#define HP_PROBE_TOP_OUT3_IDX 121
#define HP_PROBE_TOP_OUT4_IDX 122
#define HP_PROBE_TOP_OUT5_IDX 123
#define HP_PROBE_TOP_OUT6_IDX 124
#define HP_PROBE_TOP_OUT7_IDX 125
#define SD_CARD_DETECT_N_1_PAD_IN_IDX 126
#define LEDC_LS_SIG_OUT_PAD_OUT0_IDX 126
#define SD_CARD_DETECT_N_2_PAD_IN_IDX 127
#define LEDC_LS_SIG_OUT_PAD_OUT1_IDX 127
#define SD_CARD_INT_N_1_PAD_IN_IDX 128
#define LEDC_LS_SIG_OUT_PAD_OUT2_IDX 128
#define SD_CARD_INT_N_2_PAD_IN_IDX 129
#define LEDC_LS_SIG_OUT_PAD_OUT3_IDX 129
#define SD_CARD_WRITE_PRT_1_PAD_IN_IDX 130
#define LEDC_LS_SIG_OUT_PAD_OUT4_IDX 130
#define SD_CARD_WRITE_PRT_2_PAD_IN_IDX 131
#define LEDC_LS_SIG_OUT_PAD_OUT5_IDX 131
#define SD_DATA_STROBE_1_PAD_IN_IDX 132
#define LEDC_LS_SIG_OUT_PAD_OUT6_IDX 132
#define SD_DATA_STROBE_2_PAD_IN_IDX 133
#define LEDC_LS_SIG_OUT_PAD_OUT7_IDX 133
#define I3C_MST_SCL_PAD_IN_IDX 134
#define I3C_MST_SCL_PAD_OUT_IDX 134
#define I3C_MST_SDA_PAD_IN_IDX 135
#define I3C_MST_SDA_PAD_OUT_IDX 135
#define I3C_SLV_SCL_PAD_IN_IDX 136
#define I3C_SLV_SCL_PAD_OUT_IDX 136
#define I3C_SLV_SDA_PAD_IN_IDX 137
#define I3C_SLV_SDA_PAD_OUT_IDX 137
#define I3C_MST_SCL_PULLUP_EN_PAD_OUT_IDX 138
#define I3C_MST_SDA_PULLUP_EN_PAD_OUT_IDX 139
#define USB_JTAG_TDO_BRIDGE_PAD_IN_IDX 140
#define USB_JTAG_TDI_BRIDGE_PAD_OUT_IDX 140
#define PCNT_SIG_CH0_PAD_IN0_IDX 141
#define USB_JTAG_TMS_BRIDGE_PAD_OUT_IDX 141
#define PCNT_SIG_CH0_PAD_IN1_IDX 142
#define USB_JTAG_TCK_BRIDGE_PAD_OUT_IDX 142
#define PCNT_SIG_CH0_PAD_IN2_IDX 143
#define USB_JTAG_TRST_BRIDGE_PAD_OUT_IDX 143
#define PCNT_SIG_CH0_PAD_IN3_IDX 144
#define LCD_CS_PAD_OUT_IDX 144
#define PCNT_SIG_CH1_PAD_IN0_IDX 145
#define LCD_DC_PAD_OUT_IDX 145
#define PCNT_SIG_CH1_PAD_IN1_IDX 146
#define SD_RST_N_1_PAD_OUT_IDX 146
#define PCNT_SIG_CH1_PAD_IN2_IDX 147
#define SD_RST_N_2_PAD_OUT_IDX 147
#define PCNT_SIG_CH1_PAD_IN3_IDX 148
#define SD_CCMD_OD_PULLUP_EN_N_PAD_OUT_IDX 148
#define PCNT_CTRL_CH0_PAD_IN0_IDX 149
#define LCD_PCLK_PAD_OUT_IDX 149
#define PCNT_CTRL_CH0_PAD_IN1_IDX 150
#define CAM_CLK_PAD_OUT_IDX 150
#define PCNT_CTRL_CH0_PAD_IN2_IDX 151
#define LCD_H_ENABLE_PAD_OUT_IDX 151
#define PCNT_CTRL_CH0_PAD_IN3_IDX 152
#define LCD_H_SYNC_PAD_OUT_IDX 152
#define PCNT_CTRL_CH1_PAD_IN0_IDX 153
#define LCD_V_SYNC_PAD_OUT_IDX 153
#define PCNT_CTRL_CH1_PAD_IN1_IDX 154
#define LCD_DATA_OUT_PAD_OUT0_IDX 154
#define PCNT_CTRL_CH1_PAD_IN2_IDX 155
#define LCD_DATA_OUT_PAD_OUT1_IDX 155
#define PCNT_CTRL_CH1_PAD_IN3_IDX 156
#define LCD_DATA_OUT_PAD_OUT2_IDX 156
#define LCD_DATA_OUT_PAD_OUT3_IDX 157
#define CAM_PCLK_PAD_IN_IDX 158
#define LCD_DATA_OUT_PAD_OUT4_IDX 158
#define CAM_H_ENABLE_PAD_IN_IDX 159
#define LCD_DATA_OUT_PAD_OUT5_IDX 159
#define CAM_H_SYNC_PAD_IN_IDX 160
#define LCD_DATA_OUT_PAD_OUT6_IDX 160
#define CAM_V_SYNC_PAD_IN_IDX 161
#define LCD_DATA_OUT_PAD_OUT7_IDX 161
#define CAM_DATA_IN_PAD_IN0_IDX 162
#define LCD_DATA_OUT_PAD_OUT8_IDX 162
#define CAM_DATA_IN_PAD_IN1_IDX 163
#define LCD_DATA_OUT_PAD_OUT9_IDX 163
#define CAM_DATA_IN_PAD_IN2_IDX 164
#define LCD_DATA_OUT_PAD_OUT10_IDX 164
#define CAM_DATA_IN_PAD_IN3_IDX 165
#define LCD_DATA_OUT_PAD_OUT11_IDX 165
#define CAM_DATA_IN_PAD_IN4_IDX 166
#define LCD_DATA_OUT_PAD_OUT12_IDX 166
#define CAM_DATA_IN_PAD_IN5_IDX 167
#define LCD_DATA_OUT_PAD_OUT13_IDX 167
#define CAM_DATA_IN_PAD_IN6_IDX 168
#define LCD_DATA_OUT_PAD_OUT14_IDX 168
#define CAM_DATA_IN_PAD_IN7_IDX 169
#define LCD_DATA_OUT_PAD_OUT15_IDX 169
#define CAM_DATA_IN_PAD_IN8_IDX 170
#define LCD_DATA_OUT_PAD_OUT16_IDX 170
#define CAM_DATA_IN_PAD_IN9_IDX 171
#define LCD_DATA_OUT_PAD_OUT17_IDX 171
#define CAM_DATA_IN_PAD_IN10_IDX 172
#define LCD_DATA_OUT_PAD_OUT18_IDX 172
#define CAM_DATA_IN_PAD_IN11_IDX 173
#define LCD_DATA_OUT_PAD_OUT19_IDX 173
#define CAM_DATA_IN_PAD_IN12_IDX 174
#define LCD_DATA_OUT_PAD_OUT20_IDX 174
#define CAM_DATA_IN_PAD_IN13_IDX 175
#define LCD_DATA_OUT_PAD_OUT21_IDX 175
#define CAM_DATA_IN_PAD_IN14_IDX 176
#define LCD_DATA_OUT_PAD_OUT22_IDX 176
#define CAM_DATA_IN_PAD_IN15_IDX 177
#define LCD_DATA_OUT_PAD_OUT23_IDX 177
#define GMAC_PHY_RXDV_PAD_IN_IDX 178
#define GMAC_PHY_TXEN_PAD_OUT_IDX 178
#define GMAC_PHY_RXD0_PAD_IN_IDX 179
#define GMAC_PHY_TXD0_PAD_OUT_IDX 179
#define GMAC_PHY_RXD1_PAD_IN_IDX 180
#define GMAC_PHY_TXD1_PAD_OUT_IDX 180
#define GMAC_PHY_RXD2_PAD_IN_IDX 181
#define GMAC_PHY_TXD2_PAD_OUT_IDX 181
#define GMAC_PHY_RXD3_PAD_IN_IDX 182
#define GMAC_PHY_TXD3_PAD_OUT_IDX 182
#define GMAC_PHY_RXER_PAD_IN_IDX 183
#define GMAC_PHY_TXER_PAD_OUT_IDX 183
#define GMAC_RX_CLK_PAD_IN_IDX 184
#define DBG_CH0_CLK_IDX 184
#define GMAC_TX_CLK_PAD_IN_IDX 185
#define DBG_CH1_CLK_IDX 185
#define PARLIO_RX_CLK_PAD_IN_IDX 186
#define PARLIO_RX_CLK_PAD_OUT_IDX 186
#define PARLIO_TX_CLK_PAD_IN_IDX 187
#define PARLIO_TX_CLK_PAD_OUT_IDX 187
#define PARLIO_RX_DATA0_PAD_IN_IDX 188
#define PARLIO_TX_DATA0_PAD_OUT_IDX 188
#define PARLIO_RX_DATA1_PAD_IN_IDX 189
#define PARLIO_TX_DATA1_PAD_OUT_IDX 189
#define PARLIO_RX_DATA2_PAD_IN_IDX 190
#define PARLIO_TX_DATA2_PAD_OUT_IDX 190
#define PARLIO_RX_DATA3_PAD_IN_IDX 191
#define PARLIO_TX_DATA3_PAD_OUT_IDX 191
#define PARLIO_RX_DATA4_PAD_IN_IDX 192
#define PARLIO_TX_DATA4_PAD_OUT_IDX 192
#define PARLIO_RX_DATA5_PAD_IN_IDX 193
#define PARLIO_TX_DATA5_PAD_OUT_IDX 193
#define PARLIO_RX_DATA6_PAD_IN_IDX 194
#define PARLIO_TX_DATA6_PAD_OUT_IDX 194
#define PARLIO_RX_DATA7_PAD_IN_IDX 195
#define PARLIO_TX_DATA7_PAD_OUT_IDX 195
#define PARLIO_RX_DATA8_PAD_IN_IDX 196
#define PARLIO_TX_DATA8_PAD_OUT_IDX 196
#define PARLIO_RX_DATA9_PAD_IN_IDX 197
#define PARLIO_TX_DATA9_PAD_OUT_IDX 197
#define PARLIO_RX_DATA10_PAD_IN_IDX 198
#define PARLIO_TX_DATA10_PAD_OUT_IDX 198
#define PARLIO_RX_DATA11_PAD_IN_IDX 199
#define PARLIO_TX_DATA11_PAD_OUT_IDX 199
#define PARLIO_RX_DATA12_PAD_IN_IDX 200
#define PARLIO_TX_DATA12_PAD_OUT_IDX 200
#define PARLIO_RX_DATA13_PAD_IN_IDX 201
#define PARLIO_TX_DATA13_PAD_OUT_IDX 201
#define PARLIO_RX_DATA14_PAD_IN_IDX 202
#define PARLIO_TX_DATA14_PAD_OUT_IDX 202
#define PARLIO_RX_DATA15_PAD_IN_IDX 203
#define PARLIO_TX_DATA15_PAD_OUT_IDX 203
#define HP_PROBE_TOP_OUT8_IDX 204
#define HP_PROBE_TOP_OUT9_IDX 205
#define HP_PROBE_TOP_OUT10_IDX 206
#define HP_PROBE_TOP_OUT11_IDX 207
#define HP_PROBE_TOP_OUT12_IDX 208
#define HP_PROBE_TOP_OUT13_IDX 209
#define HP_PROBE_TOP_OUT14_IDX 210
#define HP_PROBE_TOP_OUT15_IDX 211
#define CONSTANT0_PAD_OUT_IDX 212
#define CONSTANT1_PAD_OUT_IDX 213
#define CORE_GPIO_IN_PAD_IN0_IDX 214
#define CORE_GPIO_OUT_PAD_OUT0_IDX 214
#define CORE_GPIO_IN_PAD_IN1_IDX 215
#define CORE_GPIO_OUT_PAD_OUT1_IDX 215
#define CORE_GPIO_IN_PAD_IN2_IDX 216
#define CORE_GPIO_OUT_PAD_OUT2_IDX 216
#define CORE_GPIO_IN_PAD_IN3_IDX 217
#define CORE_GPIO_OUT_PAD_OUT3_IDX 217
#define CORE_GPIO_IN_PAD_IN4_IDX 218
#define CORE_GPIO_OUT_PAD_OUT4_IDX 218
#define CORE_GPIO_IN_PAD_IN5_IDX 219
#define CORE_GPIO_OUT_PAD_OUT5_IDX 219
#define CORE_GPIO_IN_PAD_IN6_IDX 220
#define CORE_GPIO_OUT_PAD_OUT6_IDX 220
#define CORE_GPIO_IN_PAD_IN7_IDX 221
#define CORE_GPIO_OUT_PAD_OUT7_IDX 221
#define CORE_GPIO_IN_PAD_IN8_IDX 222
#define CORE_GPIO_OUT_PAD_OUT8_IDX 222
#define CORE_GPIO_IN_PAD_IN9_IDX 223
#define CORE_GPIO_OUT_PAD_OUT9_IDX 223
#define CORE_GPIO_IN_PAD_IN10_IDX 224
#define CORE_GPIO_OUT_PAD_OUT10_IDX 224
#define CORE_GPIO_IN_PAD_IN11_IDX 225
#define CORE_GPIO_OUT_PAD_OUT11_IDX 225
#define CORE_GPIO_IN_PAD_IN12_IDX 226
#define CORE_GPIO_OUT_PAD_OUT12_IDX 226
#define CORE_GPIO_IN_PAD_IN13_IDX 227
#define CORE_GPIO_OUT_PAD_OUT13_IDX 227
#define CORE_GPIO_IN_PAD_IN14_IDX 228
#define CORE_GPIO_OUT_PAD_OUT14_IDX 228
#define CORE_GPIO_IN_PAD_IN15_IDX 229
#define CORE_GPIO_OUT_PAD_OUT15_IDX 229
#define CORE_GPIO_IN_PAD_IN16_IDX 230
#define CORE_GPIO_OUT_PAD_OUT16_IDX 230
#define CORE_GPIO_IN_PAD_IN17_IDX 231
#define CORE_GPIO_OUT_PAD_OUT17_IDX 231
#define CORE_GPIO_IN_PAD_IN18_IDX 232
#define CORE_GPIO_OUT_PAD_OUT18_IDX 232
#define CORE_GPIO_IN_PAD_IN19_IDX 233
#define CORE_GPIO_OUT_PAD_OUT19_IDX 233
#define CORE_GPIO_IN_PAD_IN20_IDX 234
#define CORE_GPIO_OUT_PAD_OUT20_IDX 234
#define CORE_GPIO_IN_PAD_IN21_IDX 235
#define CORE_GPIO_OUT_PAD_OUT21_IDX 235
#define CORE_GPIO_IN_PAD_IN22_IDX 236
#define CORE_GPIO_OUT_PAD_OUT22_IDX 236
#define CORE_GPIO_IN_PAD_IN23_IDX 237
#define CORE_GPIO_OUT_PAD_OUT23_IDX 237
#define CORE_GPIO_IN_PAD_IN24_IDX 238
#define CORE_GPIO_OUT_PAD_OUT24_IDX 238
#define CORE_GPIO_IN_PAD_IN25_IDX 239
#define CORE_GPIO_OUT_PAD_OUT25_IDX 239
#define CORE_GPIO_IN_PAD_IN26_IDX 240
#define CORE_GPIO_OUT_PAD_OUT26_IDX 240
#define CORE_GPIO_IN_PAD_IN27_IDX 241
#define CORE_GPIO_OUT_PAD_OUT27_IDX 241
#define CORE_GPIO_IN_PAD_IN28_IDX 242
#define PARLIO_TX_CS_PAD_OUT_IDX 242
#define CORE_GPIO_IN_PAD_IN29_IDX 243
#define EMAC_PTP_PPS_PAD_OUT_IDX 243
#define CORE_GPIO_IN_PAD_IN30_IDX 244
#define ANA_COMP0_OUT_IDX 244
#define CORE_GPIO_IN_PAD_IN31_IDX 245
#define ANA_COMP1_OUT_IDX 245
#define RMT_SIG_PAD_IN0_IDX 246
#define RMT_SIG_PAD_OUT0_IDX 246
#define RMT_SIG_PAD_IN1_IDX 247
#define RMT_SIG_PAD_OUT1_IDX 247
#define RMT_SIG_PAD_IN2_IDX 248
#define RMT_SIG_PAD_OUT2_IDX 248
#define RMT_SIG_PAD_IN3_IDX 249
#define RMT_SIG_PAD_OUT3_IDX 249
#define SIG_IN_FUNC250_IDX 250
#define SIG_IN_FUNC250_IDX 250
#define SIG_IN_FUNC251_IDX 251
#define SIG_IN_FUNC251_IDX 251
#define SIG_IN_FUNC252_IDX 252
#define SIG_IN_FUNC252_IDX 252
#define SIG_IN_FUNC253_IDX 253
#define SIG_IN_FUNC253_IDX 253
#define SIG_IN_FUNC254_IDX 254
#define SIG_IN_FUNC254_IDX 254
#define SIG_IN_FUNC255_IDX 255
#define SIG_IN_FUNC255_IDX 255
// version date 230403
#define SIG_GPIO_OUT_IDX 256

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components/soc/esp32p4/register/hw_ver2/soc/gpio_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration register */
/** Type of bt_select register
* GPIO bit select register
*/
typedef union {
struct {
/** bt_sel : R/W; bitpos: [31:0]; default: 0;
* GPIO bit select register
*/
uint32_t bt_sel:32;
};
uint32_t val;
} gpio_bt_select_reg_t;
/** Type of out register
* GPIO output register for GPIO0-31
*/
typedef union {
struct {
/** out_data_orig : R/W/SC/WTC; bitpos: [31:0]; default: 0;
* GPIO output register for GPIO0-31
*/
uint32_t out_data_orig:32;
};
uint32_t val;
} gpio_out_reg_t;
/** Type of out_w1ts register
* GPIO output set register for GPIO0-31
*/
typedef union {
struct {
/** out_w1ts : WT; bitpos: [31:0]; default: 0;
* GPIO output set register for GPIO0-31
*/
uint32_t out_w1ts:32;
};
uint32_t val;
} gpio_out_w1ts_reg_t;
/** Type of out_w1tc register
* GPIO output clear register for GPIO0-31
*/
typedef union {
struct {
/** out_w1tc : WT; bitpos: [31:0]; default: 0;
* GPIO output clear register for GPIO0-31
*/
uint32_t out_w1tc:32;
};
uint32_t val;
} gpio_out_w1tc_reg_t;
/** Type of out1 register
* GPIO output register for GPIO32-56
*/
typedef union {
struct {
/** out1_data_orig : R/W/SC/WTC; bitpos: [24:0]; default: 0;
* GPIO output register for GPIO32-56
*/
uint32_t out1_data_orig:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_out1_reg_t;
/** Type of out1_w1ts register
* GPIO output set register for GPIO32-56
*/
typedef union {
struct {
/** out1_w1ts : WT; bitpos: [24:0]; default: 0;
* GPIO output set register for GPIO32-56
*/
uint32_t out1_w1ts:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_out1_w1ts_reg_t;
/** Type of out1_w1tc register
* GPIO output clear register for GPIO32-56
*/
typedef union {
struct {
/** out1_w1tc : WT; bitpos: [24:0]; default: 0;
* GPIO output clear register for GPIO32-56
*/
uint32_t out1_w1tc:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_out1_w1tc_reg_t;
/** Type of enable register
* GPIO output enable register for GPIO0-31
*/
typedef union {
struct {
/** enable_data : R/W/WTC; bitpos: [31:0]; default: 0;
* GPIO output enable register for GPIO0-31
*/
uint32_t enable_data:32;
};
uint32_t val;
} gpio_enable_reg_t;
/** Type of enable_w1ts register
* GPIO output enable set register for GPIO0-31
*/
typedef union {
struct {
/** enable_w1ts : WT; bitpos: [31:0]; default: 0;
* GPIO output enable set register for GPIO0-31
*/
uint32_t enable_w1ts:32;
};
uint32_t val;
} gpio_enable_w1ts_reg_t;
/** Type of enable_w1tc register
* GPIO output enable clear register for GPIO0-31
*/
typedef union {
struct {
/** enable_w1tc : WT; bitpos: [31:0]; default: 0;
* GPIO output enable clear register for GPIO0-31
*/
uint32_t enable_w1tc:32;
};
uint32_t val;
} gpio_enable_w1tc_reg_t;
/** Type of enable1 register
* GPIO output enable register for GPIO32-56
*/
typedef union {
struct {
/** enable1_data : R/W/WTC; bitpos: [24:0]; default: 0;
* GPIO output enable register for GPIO32-56
*/
uint32_t enable1_data:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_enable1_reg_t;
/** Type of enable1_w1ts register
* GPIO output enable set register for GPIO32-56
*/
typedef union {
struct {
/** enable1_w1ts : WT; bitpos: [24:0]; default: 0;
* GPIO output enable set register for GPIO32-56
*/
uint32_t enable1_w1ts:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_enable1_w1ts_reg_t;
/** Type of enable1_w1tc register
* GPIO output enable clear register for GPIO32-56
*/
typedef union {
struct {
/** enable1_w1tc : WT; bitpos: [24:0]; default: 0;
* GPIO output enable clear register for GPIO32-56
*/
uint32_t enable1_w1tc:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_enable1_w1tc_reg_t;
/** Type of strap register
* pad strapping register
*/
typedef union {
struct {
/** strapping : RO; bitpos: [15:0]; default: 0;
* pad strapping register
*/
uint32_t strapping:16;
uint32_t reserved_16:16;
};
uint32_t val;
} gpio_strap_reg_t;
/** Type of in register
* GPIO input register for GPIO0-31
*/
typedef union {
struct {
/** in_data_next : RO; bitpos: [31:0]; default: 0;
* GPIO input register for GPIO0-31
*/
uint32_t in_data_next:32;
};
uint32_t val;
} gpio_in_reg_t;
/** Type of in1 register
* GPIO input register for GPIO32-56
*/
typedef union {
struct {
/** in1_data_next : RO; bitpos: [24:0]; default: 0;
* GPIO input register for GPIO32-56
*/
uint32_t in1_data_next:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_in1_reg_t;
/** Type of status register
* GPIO interrupt status register for GPIO0-31
*/
typedef union {
struct {
/** status_interrupt : R/W/WTC; bitpos: [31:0]; default: 0;
* GPIO interrupt status register for GPIO0-31
*/
uint32_t status_interrupt:32;
};
uint32_t val;
} gpio_status_reg_t;
/** Type of status_w1ts register
* GPIO interrupt status set register for GPIO0-31
*/
typedef union {
struct {
/** status_w1ts : WT; bitpos: [31:0]; default: 0;
* GPIO interrupt status set register for GPIO0-31
*/
uint32_t status_w1ts:32;
};
uint32_t val;
} gpio_status_w1ts_reg_t;
/** Type of status_w1tc register
* GPIO interrupt status clear register for GPIO0-31
*/
typedef union {
struct {
/** status_w1tc : WT; bitpos: [31:0]; default: 0;
* GPIO interrupt status clear register for GPIO0-31
*/
uint32_t status_w1tc:32;
};
uint32_t val;
} gpio_status_w1tc_reg_t;
/** Type of status1 register
* GPIO interrupt status register for GPIO32-56
*/
typedef union {
struct {
/** status1_interrupt : R/W/WTC; bitpos: [24:0]; default: 0;
* GPIO interrupt status register for GPIO32-56
*/
uint32_t status1_interrupt:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_status1_reg_t;
/** Type of status1_w1ts register
* GPIO interrupt status set register for GPIO32-56
*/
typedef union {
struct {
/** status1_w1ts : WT; bitpos: [24:0]; default: 0;
* GPIO interrupt status set register for GPIO32-56
*/
uint32_t status1_w1ts:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_status1_w1ts_reg_t;
/** Type of status1_w1tc register
* GPIO interrupt status clear register for GPIO32-56
*/
typedef union {
struct {
/** status1_w1tc : WT; bitpos: [24:0]; default: 0;
* GPIO interrupt status clear register for GPIO32-56
*/
uint32_t status1_w1tc:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_status1_w1tc_reg_t;
/** Type of intr_0 register
* GPIO interrupt 0 status register for GPIO0-31
*/
typedef union {
struct {
/** int_0 : RO; bitpos: [31:0]; default: 0;
* GPIO interrupt 0 status register for GPIO0-31
*/
uint32_t int_0:32;
};
uint32_t val;
} gpio_intr_0_reg_t;
/** Type of intr1_0 register
* GPIO interrupt 0 status register for GPIO32-56
*/
typedef union {
struct {
/** int1_0 : RO; bitpos: [24:0]; default: 0;
* GPIO interrupt 0 status register for GPIO32-56
*/
uint32_t int1_0:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_intr1_0_reg_t;
/** Type of intr_1 register
* GPIO interrupt 1 status register for GPIO0-31
*/
typedef union {
struct {
/** int_1 : RO; bitpos: [31:0]; default: 0;
* GPIO interrupt 1 status register for GPIO0-31
*/
uint32_t int_1:32;
};
uint32_t val;
} gpio_intr_1_reg_t;
/** Type of intr1_1 register
* GPIO interrupt 1 status register for GPIO32-56
*/
typedef union {
struct {
/** int1_1 : RO; bitpos: [24:0]; default: 0;
* GPIO interrupt 1 status register for GPIO32-56
*/
uint32_t int1_1:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_intr1_1_reg_t;
/** Type of status_next register
* GPIO interrupt source register for GPIO0-31
*/
typedef union {
struct {
/** status_interrupt_next : RO; bitpos: [31:0]; default: 0;
* GPIO interrupt source register for GPIO0-31
*/
uint32_t status_interrupt_next:32;
};
uint32_t val;
} gpio_status_next_reg_t;
/** Type of status_next1 register
* GPIO interrupt source register for GPIO32-56
*/
typedef union {
struct {
/** status_interrupt_next1 : RO; bitpos: [24:0]; default: 0;
* GPIO interrupt source register for GPIO32-56
*/
uint32_t status_interrupt_next1:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_status_next1_reg_t;
/** Type of pin register
* GPIO pin configuration register
*/
typedef union {
struct {
/** sync2_bypass : R/W; bitpos: [1:0]; default: 0;
* set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
* posedge.
*/
uint32_t sync2_bypass:2;
/** pad_driver : R/W; bitpos: [2]; default: 0;
* set this bit to select pad driver. 1:open-drain. 0:normal.
*/
uint32_t pad_driver:1;
/** sync1_bypass : R/W; bitpos: [4:3]; default: 0;
* set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
* posedge.
*/
uint32_t sync1_bypass:2;
uint32_t reserved_5:2;
/** int_type : R/W; bitpos: [9:7]; default: 0;
* set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
* posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
* at high level
*/
uint32_t int_type:3;
/** wakeup_enable : R/W; bitpos: [10]; default: 0;
* set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
*/
uint32_t wakeup_enable:1;
/** config : R/W; bitpos: [12:11]; default: 0;
* reserved
*/
uint32_t config:2;
/** int_ena : R/W; bitpos: [17:13]; default: 0;
* set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
* interrupt.
*/
uint32_t int_ena:5;
uint32_t reserved_18:14;
};
uint32_t val;
} gpio_pin_reg_t;
/** Type of func_in_sel_cfg register
* GPIO input function configuration register
*/
typedef union {
struct {
/** in_sel : R/W; bitpos: [5:0]; default: 63;
* set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
* high level. s=0x3E: set this port always low level.
*/
uint32_t in_sel:6;
/** in_inv_sel : R/W; bitpos: [6]; default: 0;
* set this bit to invert input signal. 1:invert. 0:not invert.
*/
uint32_t in_inv_sel:1;
/** sig_in_sel : R/W; bitpos: [7]; default: 0;
* set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
*/
uint32_t sig_in_sel:1;
uint32_t reserved_8:24;
};
uint32_t val;
} gpio_func_in_sel_cfg_reg_t;
/** Type of func_out_sel_cfg register
* GPIO output function select register
*/
typedef union {
struct {
/** out_sel : R/W/SC; bitpos: [8:0]; default: 256;
* The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
* output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
* GPIO_OUT_REG[n].
*/
uint32_t out_sel:9;
/** out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
* set this bit to invert output signal.1:invert.0:not invert.
*/
uint32_t out_inv_sel:1;
/** oen_sel : R/W; bitpos: [10]; default: 0;
* set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
* enable signal.0:use peripheral output enable signal.
*/
uint32_t oen_sel:1;
/** oen_inv_sel : R/W; bitpos: [11]; default: 0;
* set this bit to invert output enable signal.1:invert.0:not invert.
*/
uint32_t oen_inv_sel:1;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_func_out_sel_cfg_reg_t;
/** Type of intr_2 register
* GPIO interrupt 2 status register for GPIO0-31
*/
typedef union {
struct {
/** int_2 : RO; bitpos: [31:0]; default: 0;
* GPIO interrupt 2 status register for GPIO0-31
*/
uint32_t int_2:32;
};
uint32_t val;
} gpio_intr_2_reg_t;
/** Type of intr1_2 register
* GPIO interrupt 2 status register for GPIO32-56
*/
typedef union {
struct {
/** int1_2 : RO; bitpos: [24:0]; default: 0;
* GPIO interrupt 2 status register for GPIO32-56
*/
uint32_t int1_2:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_intr1_2_reg_t;
/** Type of intr_3 register
* GPIO interrupt 3 status register for GPIO0-31
*/
typedef union {
struct {
/** int_3 : RO; bitpos: [31:0]; default: 0;
* GPIO interrupt 3 status register for GPIO0-31
*/
uint32_t int_3:32;
};
uint32_t val;
} gpio_intr_3_reg_t;
/** Type of intr1_3 register
* GPIO interrupt 3 status register for GPIO32-56
*/
typedef union {
struct {
/** int1_3 : RO; bitpos: [24:0]; default: 0;
* GPIO interrupt 3 status register for GPIO32-56
*/
uint32_t int1_3:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_intr1_3_reg_t;
/** Type of clock_gate register
* GPIO clock gate register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* set this bit to enable GPIO clock gate
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} gpio_clock_gate_reg_t;
/** Type of zero_det_filter_cnt register
* GPIO analog comparator zero detect filter count
*/
typedef union {
struct {
/** zero_det_filter_cnt : R/W; bitpos: [31:0]; default: 4294967295;
* GPIO analog comparator zero detect filter count
*/
uint32_t zero_det_filter_cnt:32;
};
uint32_t val;
} gpio_zero_det_filter_cnt_reg_t;
/** Type of send_seq register
* High speed sdio pad bist send sequence
*/
typedef union {
struct {
/** send_seq : R/W; bitpos: [31:0]; default: 305419896;
* High speed sdio pad bist send sequence
*/
uint32_t send_seq:32;
};
uint32_t val;
} gpio_send_seq_reg_t;
/** Type of recive_seq register
* High speed sdio pad bist receive sequence
*/
typedef union {
struct {
/** recive_seq : RO; bitpos: [31:0]; default: 0;
* High speed sdio pad bist receive sequence
*/
uint32_t recive_seq:32;
};
uint32_t val;
} gpio_recive_seq_reg_t;
/** Type of bistin_sel register
* High speed sdio pad bist in pad sel
*/
typedef union {
struct {
/** bistin_sel : R/W; bitpos: [3:0]; default: 15;
* High speed sdio pad bist in pad sel 0:pad39, 1: pad40...
*/
uint32_t bistin_sel:4;
uint32_t reserved_4:28;
};
uint32_t val;
} gpio_bistin_sel_reg_t;
/** Type of bist_ctrl register
* High speed sdio pad bist control
*/
typedef union {
struct {
/** bist_pad_oe : R/W; bitpos: [0]; default: 1;
* High speed sdio pad bist out pad oe
*/
uint32_t bist_pad_oe:1;
/** bist_start : WT; bitpos: [1]; default: 0;
* High speed sdio pad bist start
*/
uint32_t bist_start:1;
uint32_t reserved_2:30;
};
uint32_t val;
} gpio_bist_ctrl_reg_t;
/** Type of date register
* GPIO version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 2294787;
* version register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} gpio_date_reg_t;
/** Group: GPIO INT RAW REG */
/** Type of int_raw register
* analog comparator interrupt raw
*/
typedef union {
struct {
/** comp0_neg_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* analog comparator pos edge interrupt raw
*/
uint32_t comp0_neg_int_raw:1;
/** comp0_pos_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* analog comparator neg edge interrupt raw
*/
uint32_t comp0_pos_int_raw:1;
/** comp0_all_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* analog comparator neg or pos edge interrupt raw
*/
uint32_t comp0_all_int_raw:1;
/** comp1_neg_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* analog comparator pos edge interrupt raw
*/
uint32_t comp1_neg_int_raw:1;
/** comp1_pos_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* analog comparator neg edge interrupt raw
*/
uint32_t comp1_pos_int_raw:1;
/** comp1_all_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* analog comparator neg or pos edge interrupt raw
*/
uint32_t comp1_all_int_raw:1;
/** bistok_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
* pad bistok interrupt raw
*/
uint32_t bistok_int_raw:1;
/** bistfail_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
* pad bistfail interrupt raw
*/
uint32_t bistfail_int_raw:1;
uint32_t reserved_8:24;
};
uint32_t val;
} gpio_int_raw_reg_t;
/** Group: GPIO INT ST REG */
/** Type of int_st register
* analog comparator interrupt status
*/
typedef union {
struct {
/** comp0_neg_int_st : RO; bitpos: [0]; default: 0;
* analog comparator pos edge interrupt status
*/
uint32_t comp0_neg_int_st:1;
/** comp0_pos_int_st : RO; bitpos: [1]; default: 0;
* analog comparator neg edge interrupt status
*/
uint32_t comp0_pos_int_st:1;
/** comp0_all_int_st : RO; bitpos: [2]; default: 0;
* analog comparator neg or pos edge interrupt status
*/
uint32_t comp0_all_int_st:1;
/** comp1_neg_int_st : RO; bitpos: [3]; default: 0;
* analog comparator pos edge interrupt status
*/
uint32_t comp1_neg_int_st:1;
/** comp1_pos_int_st : RO; bitpos: [4]; default: 0;
* analog comparator neg edge interrupt status
*/
uint32_t comp1_pos_int_st:1;
/** comp1_all_int_st : RO; bitpos: [5]; default: 0;
* analog comparator neg or pos edge interrupt status
*/
uint32_t comp1_all_int_st:1;
/** bistok_int_st : RO; bitpos: [6]; default: 0;
* pad bistok interrupt status
*/
uint32_t bistok_int_st:1;
/** bistfail_int_st : RO; bitpos: [7]; default: 0;
* pad bistfail interrupt status
*/
uint32_t bistfail_int_st:1;
uint32_t reserved_8:24;
};
uint32_t val;
} gpio_int_st_reg_t;
/** Group: GPIO INT ENA REG */
/** Type of int_ena register
* analog comparator interrupt enable
*/
typedef union {
struct {
/** comp0_neg_int_ena : R/W; bitpos: [0]; default: 1;
* analog comparator pos edge interrupt enable
*/
uint32_t comp0_neg_int_ena:1;
/** comp0_pos_int_ena : R/W; bitpos: [1]; default: 1;
* analog comparator neg edge interrupt enable
*/
uint32_t comp0_pos_int_ena:1;
/** comp0_all_int_ena : R/W; bitpos: [2]; default: 1;
* analog comparator neg or pos edge interrupt enable
*/
uint32_t comp0_all_int_ena:1;
/** comp1_neg_int_ena : R/W; bitpos: [3]; default: 1;
* analog comparator pos edge interrupt enable
*/
uint32_t comp1_neg_int_ena:1;
/** comp1_pos_int_ena : R/W; bitpos: [4]; default: 1;
* analog comparator neg edge interrupt enable
*/
uint32_t comp1_pos_int_ena:1;
/** comp1_all_int_ena : R/W; bitpos: [5]; default: 1;
* analog comparator neg or pos edge interrupt enable
*/
uint32_t comp1_all_int_ena:1;
/** bistok_int_ena : R/W; bitpos: [6]; default: 1;
* pad bistok interrupt enable
*/
uint32_t bistok_int_ena:1;
/** bistfail_int_ena : R/W; bitpos: [7]; default: 1;
* pad bistfail interrupt enable
*/
uint32_t bistfail_int_ena:1;
uint32_t reserved_8:24;
};
uint32_t val;
} gpio_int_ena_reg_t;
/** Group: GPIO INT CLR REG */
/** Type of int_clr register
* analog comparator interrupt clear
*/
typedef union {
struct {
/** comp0_neg_int_clr : WT; bitpos: [0]; default: 0;
* analog comparator pos edge interrupt clear
*/
uint32_t comp0_neg_int_clr:1;
/** comp0_pos_int_clr : WT; bitpos: [1]; default: 0;
* analog comparator neg edge interrupt clear
*/
uint32_t comp0_pos_int_clr:1;
/** comp0_all_int_clr : WT; bitpos: [2]; default: 0;
* analog comparator neg or pos edge interrupt clear
*/
uint32_t comp0_all_int_clr:1;
/** comp1_neg_int_clr : WT; bitpos: [3]; default: 0;
* analog comparator pos edge interrupt clear
*/
uint32_t comp1_neg_int_clr:1;
/** comp1_pos_int_clr : WT; bitpos: [4]; default: 0;
* analog comparator neg edge interrupt clear
*/
uint32_t comp1_pos_int_clr:1;
/** comp1_all_int_clr : WT; bitpos: [5]; default: 0;
* analog comparator neg or pos edge interrupt clear
*/
uint32_t comp1_all_int_clr:1;
/** bistok_int_clr : WT; bitpos: [6]; default: 0;
* pad bistok interrupt enable
*/
uint32_t bistok_int_clr:1;
/** bistfail_int_clr : WT; bitpos: [7]; default: 0;
* pad bistfail interrupt enable
*/
uint32_t bistfail_int_clr:1;
uint32_t reserved_8:24;
};
uint32_t val;
} gpio_int_clr_reg_t;
typedef struct gpio_dev_t {
volatile gpio_bt_select_reg_t bt_select;
volatile gpio_out_reg_t out;
volatile gpio_out_w1ts_reg_t out_w1ts;
volatile gpio_out_w1tc_reg_t out_w1tc;
volatile gpio_out1_reg_t out1;
volatile gpio_out1_w1ts_reg_t out1_w1ts;
volatile gpio_out1_w1tc_reg_t out1_w1tc;
uint32_t reserved_01c;
volatile gpio_enable_reg_t enable;
volatile gpio_enable_w1ts_reg_t enable_w1ts;
volatile gpio_enable_w1tc_reg_t enable_w1tc;
volatile gpio_enable1_reg_t enable1;
volatile gpio_enable1_w1ts_reg_t enable1_w1ts;
volatile gpio_enable1_w1tc_reg_t enable1_w1tc;
volatile gpio_strap_reg_t strap;
volatile gpio_in_reg_t in;
volatile gpio_in1_reg_t in1;
volatile gpio_status_reg_t status;
volatile gpio_status_w1ts_reg_t status_w1ts;
volatile gpio_status_w1tc_reg_t status_w1tc;
volatile gpio_status1_reg_t status1;
volatile gpio_status1_w1ts_reg_t status1_w1ts;
volatile gpio_status1_w1tc_reg_t status1_w1tc;
volatile gpio_intr_0_reg_t intr_0;
volatile gpio_intr1_0_reg_t intr1_0;
volatile gpio_intr_1_reg_t intr_1;
volatile gpio_intr1_1_reg_t intr1_1;
volatile gpio_status_next_reg_t status_next;
volatile gpio_status_next1_reg_t status_next1;
volatile gpio_pin_reg_t pin[57];
volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; /* func0-func255: reserved for func0, 46, 67, 72, 73, 79, 81, 82, 84, 85, 87, 88, 115, 116, 119-125, 157, 204-213 */
volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[57];
volatile gpio_intr_2_reg_t intr_2;
volatile gpio_intr1_2_reg_t intr1_2;
volatile gpio_intr_3_reg_t intr_3;
volatile gpio_intr1_3_reg_t intr1_3;
volatile gpio_clock_gate_reg_t clock_gate;
uint32_t reserved_650[44];
volatile gpio_int_raw_reg_t int_raw;
volatile gpio_int_st_reg_t int_st;
volatile gpio_int_ena_reg_t int_ena;
volatile gpio_int_clr_reg_t int_clr;
volatile gpio_zero_det_filter_cnt_reg_t zero_det_filter_cnt[2];
volatile gpio_send_seq_reg_t send_seq;
volatile gpio_recive_seq_reg_t recive_seq;
volatile gpio_bistin_sel_reg_t bistin_sel;
volatile gpio_bist_ctrl_reg_t bist_ctrl;
uint32_t reserved_728[53];
volatile gpio_date_reg_t date;
} gpio_dev_t;
extern gpio_dev_t GPIO;
#ifndef __cplusplus
_Static_assert(sizeof(gpio_dev_t) == 0x800, "Invalid size of gpio_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HMAC_SET_START_REG register
* HMAC start control register
*/
#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40)
/** HMAC_SET_START : WS; bitpos: [0]; default: 0;
* Configures whether or not to enable HMAC.
*
* 0: Disable HMAC
*
* 1: Enable HMAC
*/
#define HMAC_SET_START (BIT(0))
#define HMAC_SET_START_M (HMAC_SET_START_V << HMAC_SET_START_S)
#define HMAC_SET_START_V 0x00000001U
#define HMAC_SET_START_S 0
/** HMAC_SET_PARA_PURPOSE_REG register
* HMAC parameter configuration register
*/
#define HMAC_SET_PARA_PURPOSE_REG (DR_REG_HMAC_BASE + 0x44)
/** HMAC_PURPOSE_SET : WO; bitpos: [3:0]; default: 0;
* Configures the HMAC purpose, refer to the Table . "
*/
#define HMAC_PURPOSE_SET 0x0000000FU
#define HMAC_PURPOSE_SET_M (HMAC_PURPOSE_SET_V << HMAC_PURPOSE_SET_S)
#define HMAC_PURPOSE_SET_V 0x0000000FU
#define HMAC_PURPOSE_SET_S 0
/** HMAC_SET_PARA_KEY_REG register
* HMAC parameters configuration register
*/
#define HMAC_SET_PARA_KEY_REG (DR_REG_HMAC_BASE + 0x48)
/** HMAC_KEY_SET : WO; bitpos: [2:0]; default: 0;
* Configures HMAC key. There are six keys with index 0~5. Write the index of the
* selected key to this field.
*/
#define HMAC_KEY_SET 0x00000007U
#define HMAC_KEY_SET_M (HMAC_KEY_SET_V << HMAC_KEY_SET_S)
#define HMAC_KEY_SET_V 0x00000007U
#define HMAC_KEY_SET_S 0
/** HMAC_SET_PARA_FINISH_REG register
* HMAC configuration completion register
*/
#define HMAC_SET_PARA_FINISH_REG (DR_REG_HMAC_BASE + 0x4c)
/** HMAC_SET_PARA_END : WS; bitpos: [0]; default: 0;
* Configures whether to finish HMAC configuration.
*
* 0: No effect
*
* 1: Finish configuration
*/
#define HMAC_SET_PARA_END (BIT(0))
#define HMAC_SET_PARA_END_M (HMAC_SET_PARA_END_V << HMAC_SET_PARA_END_S)
#define HMAC_SET_PARA_END_V 0x00000001U
#define HMAC_SET_PARA_END_S 0
/** HMAC_SET_MESSAGE_ONE_REG register
* HMAC message control register
*/
#define HMAC_SET_MESSAGE_ONE_REG (DR_REG_HMAC_BASE + 0x50)
/** HMAC_SET_TEXT_ONE : WS; bitpos: [0]; default: 0;
* Calls SHA to calculate one message block.
*/
#define HMAC_SET_TEXT_ONE (BIT(0))
#define HMAC_SET_TEXT_ONE_M (HMAC_SET_TEXT_ONE_V << HMAC_SET_TEXT_ONE_S)
#define HMAC_SET_TEXT_ONE_V 0x00000001U
#define HMAC_SET_TEXT_ONE_S 0
/** HMAC_SET_MESSAGE_ING_REG register
* HMAC message continue register
*/
#define HMAC_SET_MESSAGE_ING_REG (DR_REG_HMAC_BASE + 0x54)
/** HMAC_SET_TEXT_ING : WS; bitpos: [0]; default: 0;
* Configures whether or not there are unprocessed message blocks.
*
* 0: No unprocessed message block
*
* 1: There are still some message blocks to be processed.
*/
#define HMAC_SET_TEXT_ING (BIT(0))
#define HMAC_SET_TEXT_ING_M (HMAC_SET_TEXT_ING_V << HMAC_SET_TEXT_ING_S)
#define HMAC_SET_TEXT_ING_V 0x00000001U
#define HMAC_SET_TEXT_ING_S 0
/** HMAC_SET_MESSAGE_END_REG register
* HMAC message end register
*/
#define HMAC_SET_MESSAGE_END_REG (DR_REG_HMAC_BASE + 0x58)
/** HMAC_SET_TEXT_END : WS; bitpos: [0]; default: 0;
* Configures whether to start hardware padding.
*
* 0: No effect
*
* 1: Start hardware padding
*/
#define HMAC_SET_TEXT_END (BIT(0))
#define HMAC_SET_TEXT_END_M (HMAC_SET_TEXT_END_V << HMAC_SET_TEXT_END_S)
#define HMAC_SET_TEXT_END_V 0x00000001U
#define HMAC_SET_TEXT_END_S 0
/** HMAC_SET_RESULT_FINISH_REG register
* HMAC result reading finish register
*/
#define HMAC_SET_RESULT_FINISH_REG (DR_REG_HMAC_BASE + 0x5c)
/** HMAC_SET_RESULT_END : WS; bitpos: [0]; default: 0;
* Configures whether to exit upstream mode and clear calculation results.
*
* 0: Not exit
*
* 1: Exit upstream mode and clear calculation results.
*/
#define HMAC_SET_RESULT_END (BIT(0))
#define HMAC_SET_RESULT_END_M (HMAC_SET_RESULT_END_V << HMAC_SET_RESULT_END_S)
#define HMAC_SET_RESULT_END_V 0x00000001U
#define HMAC_SET_RESULT_END_S 0
/** HMAC_SET_INVALIDATE_JTAG_REG register
* Invalidate JTAG result register
*/
#define HMAC_SET_INVALIDATE_JTAG_REG (DR_REG_HMAC_BASE + 0x60)
/** HMAC_SET_INVALIDATE_JTAG : WS; bitpos: [0]; default: 0;
* Configures whether or not to clear calculation results when re-enabling JTAG in
* downstream mode.
*
* 0: Not clear
*
* 1: Clear calculation results
*/
#define HMAC_SET_INVALIDATE_JTAG (BIT(0))
#define HMAC_SET_INVALIDATE_JTAG_M (HMAC_SET_INVALIDATE_JTAG_V << HMAC_SET_INVALIDATE_JTAG_S)
#define HMAC_SET_INVALIDATE_JTAG_V 0x00000001U
#define HMAC_SET_INVALIDATE_JTAG_S 0
/** HMAC_SET_INVALIDATE_DS_REG register
* Invalidate digital signature result register
*/
#define HMAC_SET_INVALIDATE_DS_REG (DR_REG_HMAC_BASE + 0x64)
/** HMAC_SET_INVALIDATE_DS : WS; bitpos: [0]; default: 0;
* Configures whether or not to clear calculation results of the DS module in
* downstream mode.
*
* 0: Not clear
*
* 1: Clear calculation results
*/
#define HMAC_SET_INVALIDATE_DS (BIT(0))
#define HMAC_SET_INVALIDATE_DS_M (HMAC_SET_INVALIDATE_DS_V << HMAC_SET_INVALIDATE_DS_S)
#define HMAC_SET_INVALIDATE_DS_V 0x00000001U
#define HMAC_SET_INVALIDATE_DS_S 0
/** HMAC_QUERY_ERROR_REG register
* Stores matching results between keys generated by users and corresponding purposes
*/
#define HMAC_QUERY_ERROR_REG (DR_REG_HMAC_BASE + 0x68)
/** HMAC_QUREY_CHECK : RO; bitpos: [0]; default: 0;
* Represents whether or not an HMAC key matches the purpose.
*
* 0: Match
*
* 1: Error
*/
#define HMAC_QUREY_CHECK (BIT(0))
#define HMAC_QUREY_CHECK_M (HMAC_QUREY_CHECK_V << HMAC_QUREY_CHECK_S)
#define HMAC_QUREY_CHECK_V 0x00000001U
#define HMAC_QUREY_CHECK_S 0
/** HMAC_QUERY_BUSY_REG register
* Busy state of HMAC module
*/
#define HMAC_QUERY_BUSY_REG (DR_REG_HMAC_BASE + 0x6c)
/** HMAC_BUSY_STATE : RO; bitpos: [0]; default: 0;
* Represents whether or not HMAC is in a busy state. Before configuring HMAC, please
* make sure HMAC is in an IDLE state.
*
* 0: Idle
*
* 1: HMAC is still working on the calculation
*/
#define HMAC_BUSY_STATE (BIT(0))
#define HMAC_BUSY_STATE_M (HMAC_BUSY_STATE_V << HMAC_BUSY_STATE_S)
#define HMAC_BUSY_STATE_V 0x00000001U
#define HMAC_BUSY_STATE_S 0
/** HMAC_WR_MESSAGE_MEM register
* Message block memory.
*/
#define HMAC_WR_MESSAGE_MEM (DR_REG_HMAC_BASE + 0x80)
#define HMAC_WR_MESSAGE_MEM_SIZE_BYTES 64
/** HMAC_RD_RESULT_MEM register
* Result from upstream.
*/
#define HMAC_RD_RESULT_MEM (DR_REG_HMAC_BASE + 0xc0)
#define HMAC_RD_RESULT_MEM_SIZE_BYTES 32
/** HMAC_SET_MESSAGE_PAD_REG register
* Software padding register
*/
#define HMAC_SET_MESSAGE_PAD_REG (DR_REG_HMAC_BASE + 0xf0)
/** HMAC_SET_TEXT_PAD : WO; bitpos: [0]; default: 0;
* Configures whether or not the padding is applied by software.
*
* 0: Not applied by software
*
* 1: Applied by software
*/
#define HMAC_SET_TEXT_PAD (BIT(0))
#define HMAC_SET_TEXT_PAD_M (HMAC_SET_TEXT_PAD_V << HMAC_SET_TEXT_PAD_S)
#define HMAC_SET_TEXT_PAD_V 0x00000001U
#define HMAC_SET_TEXT_PAD_S 0
/** HMAC_ONE_BLOCK_REG register
* One block message register
*/
#define HMAC_ONE_BLOCK_REG (DR_REG_HMAC_BASE + 0xf4)
/** HMAC_SET_ONE_BLOCK : WS; bitpos: [0]; default: 0;
* Write 1 to indicate there is only one block which already contains padding bits and
* there is no need for padding.
*/
#define HMAC_SET_ONE_BLOCK (BIT(0))
#define HMAC_SET_ONE_BLOCK_M (HMAC_SET_ONE_BLOCK_V << HMAC_SET_ONE_BLOCK_S)
#define HMAC_SET_ONE_BLOCK_V 0x00000001U
#define HMAC_SET_ONE_BLOCK_S 0
/** HMAC_SOFT_JTAG_CTRL_REG register
* Jtag register 0.
*/
#define HMAC_SOFT_JTAG_CTRL_REG (DR_REG_HMAC_BASE + 0xf8)
/** HMAC_SOFT_JTAG_CTRL : WS; bitpos: [0]; default: 0;
* Configures whether or not to enable JTAG authentication mode.
*
* 0: Disable
*
* 1: Enable
*
*/
#define HMAC_SOFT_JTAG_CTRL (BIT(0))
#define HMAC_SOFT_JTAG_CTRL_M (HMAC_SOFT_JTAG_CTRL_V << HMAC_SOFT_JTAG_CTRL_S)
#define HMAC_SOFT_JTAG_CTRL_V 0x00000001U
#define HMAC_SOFT_JTAG_CTRL_S 0
/** HMAC_WR_JTAG_REG register
* Re-enable JTAG register 1
*/
#define HMAC_WR_JTAG_REG (DR_REG_HMAC_BASE + 0xfc)
/** HMAC_WR_JTAG : WO; bitpos: [31:0]; default: 0;
* Writes the comparing input used for re-enabling JTAG.
*/
#define HMAC_WR_JTAG 0xFFFFFFFFU
#define HMAC_WR_JTAG_M (HMAC_WR_JTAG_V << HMAC_WR_JTAG_S)
#define HMAC_WR_JTAG_V 0xFFFFFFFFU
#define HMAC_WR_JTAG_S 0
/** HMAC_DATE_REG register
* Version control register
*/
#define HMAC_DATE_REG (DR_REG_HMAC_BASE + 0x1fc)
/** HMAC_DATE : R/W; bitpos: [29:0]; default: 539166977;
* Hmac date information/ hmac version information.
*/
#define HMAC_DATE 0x3FFFFFFFU
#define HMAC_DATE_M (HMAC_DATE_V << HMAC_DATE_S)
#define HMAC_DATE_V 0x3FFFFFFFU
#define HMAC_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/register/hw_ver2/soc/hmac_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Control/Status Registers */
/** Type of set_start register
* HMAC start control register
*/
typedef union {
struct {
/** set_start : WS; bitpos: [0]; default: 0;
* Configures whether or not to enable HMAC.
*
* 0: Disable HMAC
*
* 1: Enable HMAC
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_start_reg_t;
/** Type of set_para_finish register
* HMAC configuration completion register
*/
typedef union {
struct {
/** set_para_end : WS; bitpos: [0]; default: 0;
* Configures whether to finish HMAC configuration.
*
* 0: No effect
*
* 1: Finish configuration
*/
uint32_t set_para_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_para_finish_reg_t;
/** Type of set_message_one register
* HMAC message control register
*/
typedef union {
struct {
/** set_text_one : WS; bitpos: [0]; default: 0;
* Calls SHA to calculate one message block.
*/
uint32_t set_text_one:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_one_reg_t;
/** Type of set_message_ing register
* HMAC message continue register
*/
typedef union {
struct {
/** set_text_ing : WS; bitpos: [0]; default: 0;
* Configures whether or not there are unprocessed message blocks.
*
* 0: No unprocessed message block
*
* 1: There are still some message blocks to be processed.
*/
uint32_t set_text_ing:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_ing_reg_t;
/** Type of set_message_end register
* HMAC message end register
*/
typedef union {
struct {
/** set_text_end : WS; bitpos: [0]; default: 0;
* Configures whether to start hardware padding.
*
* 0: No effect
*
* 1: Start hardware padding
*/
uint32_t set_text_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_end_reg_t;
/** Type of set_result_finish register
* HMAC result reading finish register
*/
typedef union {
struct {
/** set_result_end : WS; bitpos: [0]; default: 0;
* Configures whether to exit upstream mode and clear calculation results.
*
* 0: Not exit
*
* 1: Exit upstream mode and clear calculation results.
*/
uint32_t set_result_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_result_finish_reg_t;
/** Type of set_invalidate_jtag register
* Invalidate JTAG result register
*/
typedef union {
struct {
/** set_invalidate_jtag : WS; bitpos: [0]; default: 0;
* Configures whether or not to clear calculation results when re-enabling JTAG in
* downstream mode.
*
* 0: Not clear
*
* 1: Clear calculation results
*/
uint32_t set_invalidate_jtag:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_invalidate_jtag_reg_t;
/** Type of set_invalidate_ds register
* Invalidate digital signature result register
*/
typedef union {
struct {
/** set_invalidate_ds : WS; bitpos: [0]; default: 0;
* Configures whether or not to clear calculation results of the DS module in
* downstream mode.
*
* 0: Not clear
*
* 1: Clear calculation results
*/
uint32_t set_invalidate_ds:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_invalidate_ds_reg_t;
/** Type of query_error register
* Stores matching results between keys generated by users and corresponding purposes
*/
typedef union {
struct {
/** qurey_check : RO; bitpos: [0]; default: 0;
* Represents whether or not an HMAC key matches the purpose.
*
* 0: Match
*
* 1: Error
*/
uint32_t qurey_check:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_query_error_reg_t;
/** Type of query_busy register
* Busy state of HMAC module
*/
typedef union {
struct {
/** busy_state : RO; bitpos: [0]; default: 0;
* Represents whether or not HMAC is in a busy state. Before configuring HMAC, please
* make sure HMAC is in an IDLE state.
*
* 0: Idle
*
* 1: HMAC is still working on the calculation
*/
uint32_t busy_state:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_query_busy_reg_t;
/** Type of set_message_pad register
* Software padding register
*/
typedef union {
struct {
/** set_text_pad : WO; bitpos: [0]; default: 0;
* Configures whether or not the padding is applied by software.
*
* 0: Not applied by software
*
* 1: Applied by software
*/
uint32_t set_text_pad:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_pad_reg_t;
/** Type of one_block register
* One block message register
*/
typedef union {
struct {
/** set_one_block : WS; bitpos: [0]; default: 0;
* Write 1 to indicate there is only one block which already contains padding bits and
* there is no need for padding.
*/
uint32_t set_one_block:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_one_block_reg_t;
/** Group: Configuration Registers */
/** Type of set_para_purpose register
* HMAC parameter configuration register
*/
typedef union {
struct {
/** purpose_set : WO; bitpos: [3:0]; default: 0;
* Configures the HMAC purpose, refer to the Table . "
*/
uint32_t purpose_set:4;
uint32_t reserved_4:28;
};
uint32_t val;
} hmac_set_para_purpose_reg_t;
/** Type of set_para_key register
* HMAC parameters configuration register
*/
typedef union {
struct {
/** key_set : WO; bitpos: [2:0]; default: 0;
* Configures HMAC key. There are six keys with index 0~5. Write the index of the
* selected key to this field.
*/
uint32_t key_set:3;
uint32_t reserved_3:29;
};
uint32_t val;
} hmac_set_para_key_reg_t;
/** Type of wr_jtag register
* Re-enable JTAG register 1
*/
typedef union {
struct {
/** wr_jtag : WO; bitpos: [31:0]; default: 0;
* Writes the comparing input used for re-enabling JTAG.
*/
uint32_t wr_jtag:32;
};
uint32_t val;
} hmac_wr_jtag_reg_t;
/** Group: Memory Type */
/** Group: Configuration Register */
/** Type of soft_jtag_ctrl register
* Jtag register 0.
*/
typedef union {
struct {
/** soft_jtag_ctrl : WS; bitpos: [0]; default: 0;
* Configures whether or not to enable JTAG authentication mode.
*
* 0: Disable
*
* 1: Enable
*
*/
uint32_t soft_jtag_ctrl:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_soft_jtag_ctrl_reg_t;
/** Group: Version Register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 539166977;
* Hmac date information/ hmac version information.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} hmac_date_reg_t;
typedef struct {
uint32_t reserved_000[16];
volatile hmac_set_start_reg_t set_start;
volatile hmac_set_para_purpose_reg_t set_para_purpose;
volatile hmac_set_para_key_reg_t set_para_key;
volatile hmac_set_para_finish_reg_t set_para_finish;
volatile hmac_set_message_one_reg_t set_message_one;
volatile hmac_set_message_ing_reg_t set_message_ing;
volatile hmac_set_message_end_reg_t set_message_end;
volatile hmac_set_result_finish_reg_t set_result_finish;
volatile hmac_set_invalidate_jtag_reg_t set_invalidate_jtag;
volatile hmac_set_invalidate_ds_reg_t set_invalidate_ds;
volatile hmac_query_error_reg_t query_error;
volatile hmac_query_busy_reg_t query_busy;
uint32_t reserved_070[4];
volatile uint32_t wr_message[16];
volatile uint32_t rd_result[8];
uint32_t reserved_0e0[4];
volatile hmac_set_message_pad_reg_t set_message_pad;
volatile hmac_one_block_reg_t one_block;
volatile hmac_soft_jtag_ctrl_reg_t soft_jtag_ctrl;
volatile hmac_wr_jtag_reg_t wr_jtag;
uint32_t reserved_100[63];
volatile hmac_date_reg_t date;
} hmac_dev_t;
extern hmac_dev_t HMAC;
#ifndef __cplusplus
_Static_assert(sizeof(hmac_dev_t) == 0x200, "Invalid size of hmac_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

779
components/soc/esp32p4/register/hw_ver2/soc/hp2lp_peri_pms_eco5_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** TEE_HP2LP_TEE_PMS_DATE_REG register
* NA
*/
#define TEE_HP2LP_TEE_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0)
/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2363943;
* NA
*/
#define TEE_TEE_DATE 0xFFFFFFFFU
#define TEE_TEE_DATE_M (TEE_TEE_DATE_V << TEE_TEE_DATE_S)
#define TEE_TEE_DATE_V 0xFFFFFFFFU
#define TEE_TEE_DATE_S 0
/** TEE_PMS_CLK_EN_REG register
* NA
*/
#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4)
/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_CLK_EN (BIT(0))
#define TEE_REG_CLK_EN_M (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S)
#define TEE_REG_CLK_EN_V 0x00000001U
#define TEE_REG_CLK_EN_S 0
/** TEE_HP_CORE0_MM_PMS_REG0_REG register
* NA
*/
#define TEE_HP_CORE0_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8)
/** TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW (BIT(0))
#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_S 0
/** TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW (BIT(1))
#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S 1
/** TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW (BIT(2))
#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_S 2
/** TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW (BIT(3))
#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_S 3
/** TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW (BIT(4))
#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_S 4
/** TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW (BIT(5))
#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_S 5
/** TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW (BIT(6))
#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_S 6
/** TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW (BIT(7))
#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_S 7
/** TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW (BIT(8))
#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S 8
/** TEE_REG_HP_CORE0_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW (BIT(9))
#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_S 9
/** TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW (BIT(10))
#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_S 10
/** TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW (BIT(11))
#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_S 11
/** TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW (BIT(12))
#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_S 12
/** TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW (BIT(13))
#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_S 13
/** TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW (BIT(14))
#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_S 14
/** TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW (BIT(15))
#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_S 15
/** TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW (BIT(16))
#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_S 16
/** TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW (BIT(17))
#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_S 17
/** TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW (BIT(18))
#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_S 18
/** TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW (BIT(19))
#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_S 19
/** TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW (BIT(20))
#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_S 20
/** TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW (BIT(21))
#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_S 21
/** TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW (BIT(22))
#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_S 22
/** TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW (BIT(23))
#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_S 23
/** TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW (BIT(24))
#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_S 24
/** TEE_HP_CORE0_UM_PMS_REG0_REG register
* NA
*/
#define TEE_HP_CORE0_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0xc)
/** TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW (BIT(0))
#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_S 0
/** TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW (BIT(1))
#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S 1
/** TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW (BIT(2))
#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_S 2
/** TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW (BIT(3))
#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_S 3
/** TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW (BIT(4))
#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_S 4
/** TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW (BIT(5))
#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_S 5
/** TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW (BIT(6))
#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_S 6
/** TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW (BIT(7))
#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_S 7
/** TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW (BIT(8))
#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S 8
/** TEE_REG_HP_CORE0_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW (BIT(9))
#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_S 9
/** TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW (BIT(10))
#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_S 10
/** TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW (BIT(11))
#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_S 11
/** TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW (BIT(12))
#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_S 12
/** TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW (BIT(13))
#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_S 13
/** TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW (BIT(14))
#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_S 14
/** TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW (BIT(15))
#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_S 15
/** TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW (BIT(16))
#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_S 16
/** TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW (BIT(17))
#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_S 17
/** TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW (BIT(18))
#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_S 18
/** TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW (BIT(19))
#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_S 19
/** TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW (BIT(20))
#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_S 20
/** TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW (BIT(21))
#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_S 21
/** TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW (BIT(22))
#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_S 22
/** TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW (BIT(23))
#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_S 23
/** TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW (BIT(24))
#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_S 24
/** TEE_HP_CORE1_MM_PMS_REG0_REG register
* NA
*/
#define TEE_HP_CORE1_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x10)
/** TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW (BIT(0))
#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_S 0
/** TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW (BIT(1))
#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S 1
/** TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW (BIT(2))
#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_S 2
/** TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW (BIT(3))
#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_S 3
/** TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW (BIT(4))
#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_S 4
/** TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW (BIT(5))
#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_S 5
/** TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW (BIT(6))
#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_S 6
/** TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW (BIT(7))
#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_S 7
/** TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW (BIT(8))
#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S 8
/** TEE_REG_HP_CORE1_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW (BIT(9))
#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_S 9
/** TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW (BIT(10))
#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_S 10
/** TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW (BIT(11))
#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_S 11
/** TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW (BIT(12))
#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_S 12
/** TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW (BIT(13))
#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_S 13
/** TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW (BIT(14))
#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_S 14
/** TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW (BIT(15))
#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_S 15
/** TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW (BIT(16))
#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_S 16
/** TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW (BIT(17))
#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_S 17
/** TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW (BIT(18))
#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_S 18
/** TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW (BIT(19))
#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_S 19
/** TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW (BIT(20))
#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_S 20
/** TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW (BIT(21))
#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_S 21
/** TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW (BIT(22))
#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_S 22
/** TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW (BIT(23))
#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_S 23
/** TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW (BIT(24))
#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_S 24
/** TEE_HP_CORE1_UM_PMS_REG0_REG register
* NA
*/
#define TEE_HP_CORE1_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x14)
/** TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW (BIT(0))
#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_S 0
/** TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW (BIT(1))
#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S 1
/** TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW (BIT(2))
#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_S 2
/** TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW (BIT(3))
#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_S 3
/** TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW (BIT(4))
#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_S 4
/** TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW (BIT(5))
#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_S 5
/** TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW (BIT(6))
#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_S 6
/** TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW (BIT(7))
#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_S 7
/** TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW (BIT(8))
#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S 8
/** TEE_REG_HP_CORE1_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW (BIT(9))
#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_S 9
/** TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW (BIT(10))
#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_S 10
/** TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW (BIT(11))
#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_S 11
/** TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW (BIT(12))
#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_S 12
/** TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW (BIT(13))
#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_S 13
/** TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW (BIT(14))
#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_S 14
/** TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW (BIT(15))
#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_S 15
/** TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW (BIT(16))
#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_S 16
/** TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW (BIT(17))
#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_S 17
/** TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW (BIT(18))
#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_S 18
/** TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW (BIT(19))
#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_S 19
/** TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW (BIT(20))
#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_S 20
/** TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW (BIT(21))
#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_S 21
/** TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW (BIT(22))
#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_S 22
/** TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW (BIT(23))
#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_S 23
/** TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW (BIT(24))
#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_S 24
/** TEE_REGDMA_PERI_PMS_REG register
* NA
*/
#define TEE_REGDMA_PERI_PMS_REG (DR_REG_TEE_BASE + 0x18)
/** TEE_REG_REGDMA_PERI_LP_RAM_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW (BIT(0))
#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_M (TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_V << TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_S)
#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_V 0x00000001U
#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_S 0
/** TEE_REG_REGDMA_PERI_LP_PERI_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW (BIT(1))
#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_M (TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_V << TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_S)
#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_V 0x00000001U
#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_S 1
#ifdef __cplusplus
}
#endif

969
components/soc/esp32p4/register/hw_ver2/soc/hp2lp_peri_pms_reg.h Normal file
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@@ -0,0 +1,969 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** PMS_HP2LP_PERI_PMS_DATE_REG register
* Version control register
*/
#define PMS_HP2LP_PERI_PMS_DATE_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x0)
/** PMS_HP2LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294790;
* Version control register
*/
#define PMS_HP2LP_PERI_PMS_DATE 0xFFFFFFFFU
#define PMS_HP2LP_PERI_PMS_DATE_M (PMS_HP2LP_PERI_PMS_DATE_V << PMS_HP2LP_PERI_PMS_DATE_S)
#define PMS_HP2LP_PERI_PMS_DATE_V 0xFFFFFFFFU
#define PMS_HP2LP_PERI_PMS_DATE_S 0
/** PMS_HP2LP_PERI_PMS_CLK_EN_REG register
* Clock gating register
*/
#define PMS_HP2LP_PERI_PMS_CLK_EN_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x4)
/** PMS_HP2LP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: Enable automatic clock gating
* 1: Keep the clock always on
*/
#define PMS_HP2LP_PERI_PMS_CLK_EN (BIT(0))
#define PMS_HP2LP_PERI_PMS_CLK_EN_M (PMS_HP2LP_PERI_PMS_CLK_EN_V << PMS_HP2LP_PERI_PMS_CLK_EN_S)
#define PMS_HP2LP_PERI_PMS_CLK_EN_V 0x00000001U
#define PMS_HP2LP_PERI_PMS_CLK_EN_S 0
/** PMS_HP_CORE0_MM_PMS_REG0_REG register
* Permission control register0 for HP CPU0 in machine mode
*/
#define PMS_HP_CORE0_MM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x8)
/** PMS_HP_CORE0_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP System
* Registers.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_SYSREG_ALLOW (BIT(0))
#define PMS_HP_CORE0_MM_LP_SYSREG_ALLOW_M (PMS_HP_CORE0_MM_LP_SYSREG_ALLOW_V << PMS_HP_CORE0_MM_LP_SYSREG_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_SYSREG_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_SYSREG_ALLOW_S 0
/** PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP_AONCLKRST.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW (BIT(1))
#define PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW_M (PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V << PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S 1
/** PMS_HP_CORE0_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP timer.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_TIMER_ALLOW (BIT(2))
#define PMS_HP_CORE0_MM_LP_TIMER_ALLOW_M (PMS_HP_CORE0_MM_LP_TIMER_ALLOW_V << PMS_HP_CORE0_MM_LP_TIMER_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_TIMER_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_TIMER_ALLOW_S 2
/** PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP ANAPERI.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW (BIT(3))
#define PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW_M (PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW_V << PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW_S 3
/** PMS_HP_CORE0_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP PMU.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_PMU_ALLOW (BIT(4))
#define PMS_HP_CORE0_MM_LP_PMU_ALLOW_M (PMS_HP_CORE0_MM_LP_PMU_ALLOW_V << PMS_HP_CORE0_MM_LP_PMU_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_PMU_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_PMU_ALLOW_S 4
/** PMS_HP_CORE0_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP WDT.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_WDT_ALLOW (BIT(5))
#define PMS_HP_CORE0_MM_LP_WDT_ALLOW_M (PMS_HP_CORE0_MM_LP_WDT_ALLOW_V << PMS_HP_CORE0_MM_LP_WDT_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_WDT_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_WDT_ALLOW_S 5
/** PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP Mailbox
* Controller.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW (BIT(6))
#define PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW_M (PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW_V << PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW_S 6
/** PMS_HP_CORE0_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP RTC.
* 0: Not allowed
* 1: Allow
*/
#define PMS_HP_CORE0_MM_LP_RTC_ALLOW (BIT(7))
#define PMS_HP_CORE0_MM_LP_RTC_ALLOW_M (PMS_HP_CORE0_MM_LP_RTC_ALLOW_V << PMS_HP_CORE0_MM_LP_RTC_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_RTC_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_RTC_ALLOW_S 7
/** PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP PERICLKRST.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW (BIT(8))
#define PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW_M (PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V << PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S 8
/** PMS_HP_CORE0_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP UART.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_UART_ALLOW (BIT(9))
#define PMS_HP_CORE0_MM_LP_UART_ALLOW_M (PMS_HP_CORE0_MM_LP_UART_ALLOW_V << PMS_HP_CORE0_MM_LP_UART_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_UART_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_UART_ALLOW_S 9
/** PMS_HP_CORE0_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP I2C.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_I2C_ALLOW (BIT(10))
#define PMS_HP_CORE0_MM_LP_I2C_ALLOW_M (PMS_HP_CORE0_MM_LP_I2C_ALLOW_V << PMS_HP_CORE0_MM_LP_I2C_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_I2C_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_I2C_ALLOW_S 10
/** PMS_HP_CORE0_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP SPI.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_SPI_ALLOW (BIT(11))
#define PMS_HP_CORE0_MM_LP_SPI_ALLOW_M (PMS_HP_CORE0_MM_LP_SPI_ALLOW_V << PMS_HP_CORE0_MM_LP_SPI_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_SPI_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_SPI_ALLOW_S 11
/** PMS_HP_CORE0_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP I2C master.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_I2CMST_ALLOW (BIT(12))
#define PMS_HP_CORE0_MM_LP_I2CMST_ALLOW_M (PMS_HP_CORE0_MM_LP_I2CMST_ALLOW_V << PMS_HP_CORE0_MM_LP_I2CMST_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_I2CMST_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_I2CMST_ALLOW_S 12
/** PMS_HP_CORE0_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP I2S.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_I2S_ALLOW (BIT(13))
#define PMS_HP_CORE0_MM_LP_I2S_ALLOW_M (PMS_HP_CORE0_MM_LP_I2S_ALLOW_V << PMS_HP_CORE0_MM_LP_I2S_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_I2S_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_I2S_ALLOW_S 13
/** PMS_HP_CORE0_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP ADC.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_ADC_ALLOW (BIT(14))
#define PMS_HP_CORE0_MM_LP_ADC_ALLOW_M (PMS_HP_CORE0_MM_LP_ADC_ALLOW_V << PMS_HP_CORE0_MM_LP_ADC_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_ADC_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_ADC_ALLOW_S 14
/** PMS_HP_CORE0_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP touch
* sensor.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_TOUCH_ALLOW (BIT(15))
#define PMS_HP_CORE0_MM_LP_TOUCH_ALLOW_M (PMS_HP_CORE0_MM_LP_TOUCH_ALLOW_V << PMS_HP_CORE0_MM_LP_TOUCH_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_TOUCH_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_TOUCH_ALLOW_S 15
/** PMS_HP_CORE0_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP IO MUX.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_IOMUX_ALLOW (BIT(16))
#define PMS_HP_CORE0_MM_LP_IOMUX_ALLOW_M (PMS_HP_CORE0_MM_LP_IOMUX_ALLOW_V << PMS_HP_CORE0_MM_LP_IOMUX_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_IOMUX_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_IOMUX_ALLOW_S 16
/** PMS_HP_CORE0_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP INTR.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_INTR_ALLOW (BIT(17))
#define PMS_HP_CORE0_MM_LP_INTR_ALLOW_M (PMS_HP_CORE0_MM_LP_INTR_ALLOW_V << PMS_HP_CORE0_MM_LP_INTR_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_INTR_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_INTR_ALLOW_S 17
/** PMS_HP_CORE0_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP eFuse.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_EFUSE_ALLOW (BIT(18))
#define PMS_HP_CORE0_MM_LP_EFUSE_ALLOW_M (PMS_HP_CORE0_MM_LP_EFUSE_ALLOW_V << PMS_HP_CORE0_MM_LP_EFUSE_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_EFUSE_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_EFUSE_ALLOW_S 18
/** PMS_HP_CORE0_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access
* LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_PMS_ALLOW (BIT(19))
#define PMS_HP_CORE0_MM_LP_PMS_ALLOW_M (PMS_HP_CORE0_MM_LP_PMS_ALLOW_V << PMS_HP_CORE0_MM_LP_PMS_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_PMS_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_PMS_ALLOW_S 19
/** PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access
* HP2LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW (BIT(20))
#define PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW_M (PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW_V << PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW_S)
#define PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW_S 20
/** PMS_HP_CORE0_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP temperature
* sensor.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_TSENS_ALLOW (BIT(21))
#define PMS_HP_CORE0_MM_LP_TSENS_ALLOW_M (PMS_HP_CORE0_MM_LP_TSENS_ALLOW_V << PMS_HP_CORE0_MM_LP_TSENS_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_TSENS_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_TSENS_ALLOW_S 21
/** PMS_HP_CORE0_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to LP HUK.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_HUK_ALLOW (BIT(22))
#define PMS_HP_CORE0_MM_LP_HUK_ALLOW_M (PMS_HP_CORE0_MM_LP_HUK_ALLOW_V << PMS_HP_CORE0_MM_LP_HUK_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_HUK_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_HUK_ALLOW_S 22
/** PMS_HP_CORE0_MM_LP_SRAM_ALLOW : R/W; bitpos: [23]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access LP SRAM.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_MM_LP_SRAM_ALLOW (BIT(23))
#define PMS_HP_CORE0_MM_LP_SRAM_ALLOW_M (PMS_HP_CORE0_MM_LP_SRAM_ALLOW_V << PMS_HP_CORE0_MM_LP_SRAM_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_SRAM_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_SRAM_ALLOW_S 23
/** PMS_HP_CORE0_UM_PMS_REG0_REG register
* Permission control register0 for HP CPU0 in user mode
*/
#define PMS_HP_CORE0_UM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0xc)
/** PMS_HP_CORE0_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP System
* Registers.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_SYSREG_ALLOW (BIT(0))
#define PMS_HP_CORE0_UM_LP_SYSREG_ALLOW_M (PMS_HP_CORE0_UM_LP_SYSREG_ALLOW_V << PMS_HP_CORE0_UM_LP_SYSREG_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_SYSREG_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_SYSREG_ALLOW_S 0
/** PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP_AONCLKRST.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW (BIT(1))
#define PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW_M (PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V << PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S 1
/** PMS_HP_CORE0_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP timer.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_TIMER_ALLOW (BIT(2))
#define PMS_HP_CORE0_UM_LP_TIMER_ALLOW_M (PMS_HP_CORE0_UM_LP_TIMER_ALLOW_V << PMS_HP_CORE0_UM_LP_TIMER_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_TIMER_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_TIMER_ALLOW_S 2
/** PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP ANAPERI.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW (BIT(3))
#define PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW_M (PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW_V << PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW_S 3
/** PMS_HP_CORE0_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP PMU.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_PMU_ALLOW (BIT(4))
#define PMS_HP_CORE0_UM_LP_PMU_ALLOW_M (PMS_HP_CORE0_UM_LP_PMU_ALLOW_V << PMS_HP_CORE0_UM_LP_PMU_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_PMU_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_PMU_ALLOW_S 4
/** PMS_HP_CORE0_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP WDT.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_WDT_ALLOW (BIT(5))
#define PMS_HP_CORE0_UM_LP_WDT_ALLOW_M (PMS_HP_CORE0_UM_LP_WDT_ALLOW_V << PMS_HP_CORE0_UM_LP_WDT_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_WDT_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_WDT_ALLOW_S 5
/** PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP Mailbox
* Controller.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW (BIT(6))
#define PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW_M (PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW_V << PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW_S 6
/** PMS_HP_CORE0_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP RTC.
* 0: Not allowed
* 1: Allow
*/
#define PMS_HP_CORE0_UM_LP_RTC_ALLOW (BIT(7))
#define PMS_HP_CORE0_UM_LP_RTC_ALLOW_M (PMS_HP_CORE0_UM_LP_RTC_ALLOW_V << PMS_HP_CORE0_UM_LP_RTC_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_RTC_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_RTC_ALLOW_S 7
/** PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP PERICLKRST.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW (BIT(8))
#define PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW_M (PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V << PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S 8
/** PMS_HP_CORE0_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP UART.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_UART_ALLOW (BIT(9))
#define PMS_HP_CORE0_UM_LP_UART_ALLOW_M (PMS_HP_CORE0_UM_LP_UART_ALLOW_V << PMS_HP_CORE0_UM_LP_UART_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_UART_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_UART_ALLOW_S 9
/** PMS_HP_CORE0_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP I2C.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_I2C_ALLOW (BIT(10))
#define PMS_HP_CORE0_UM_LP_I2C_ALLOW_M (PMS_HP_CORE0_UM_LP_I2C_ALLOW_V << PMS_HP_CORE0_UM_LP_I2C_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_I2C_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_I2C_ALLOW_S 10
/** PMS_HP_CORE0_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP SPI.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_SPI_ALLOW (BIT(11))
#define PMS_HP_CORE0_UM_LP_SPI_ALLOW_M (PMS_HP_CORE0_UM_LP_SPI_ALLOW_V << PMS_HP_CORE0_UM_LP_SPI_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_SPI_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_SPI_ALLOW_S 11
/** PMS_HP_CORE0_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP I2C master.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_I2CMST_ALLOW (BIT(12))
#define PMS_HP_CORE0_UM_LP_I2CMST_ALLOW_M (PMS_HP_CORE0_UM_LP_I2CMST_ALLOW_V << PMS_HP_CORE0_UM_LP_I2CMST_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_I2CMST_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_I2CMST_ALLOW_S 12
/** PMS_HP_CORE0_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP I2S.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_I2S_ALLOW (BIT(13))
#define PMS_HP_CORE0_UM_LP_I2S_ALLOW_M (PMS_HP_CORE0_UM_LP_I2S_ALLOW_V << PMS_HP_CORE0_UM_LP_I2S_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_I2S_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_I2S_ALLOW_S 13
/** PMS_HP_CORE0_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP ADC.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_ADC_ALLOW (BIT(14))
#define PMS_HP_CORE0_UM_LP_ADC_ALLOW_M (PMS_HP_CORE0_UM_LP_ADC_ALLOW_V << PMS_HP_CORE0_UM_LP_ADC_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_ADC_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_ADC_ALLOW_S 14
/** PMS_HP_CORE0_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP touch sensor.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_TOUCH_ALLOW (BIT(15))
#define PMS_HP_CORE0_UM_LP_TOUCH_ALLOW_M (PMS_HP_CORE0_UM_LP_TOUCH_ALLOW_V << PMS_HP_CORE0_UM_LP_TOUCH_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_TOUCH_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_TOUCH_ALLOW_S 15
/** PMS_HP_CORE0_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP IO MUX.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_IOMUX_ALLOW (BIT(16))
#define PMS_HP_CORE0_UM_LP_IOMUX_ALLOW_M (PMS_HP_CORE0_UM_LP_IOMUX_ALLOW_V << PMS_HP_CORE0_UM_LP_IOMUX_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_IOMUX_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_IOMUX_ALLOW_S 16
/** PMS_HP_CORE0_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP INTR.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_INTR_ALLOW (BIT(17))
#define PMS_HP_CORE0_UM_LP_INTR_ALLOW_M (PMS_HP_CORE0_UM_LP_INTR_ALLOW_V << PMS_HP_CORE0_UM_LP_INTR_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_INTR_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_INTR_ALLOW_S 17
/** PMS_HP_CORE0_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP eFuse.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_EFUSE_ALLOW (BIT(18))
#define PMS_HP_CORE0_UM_LP_EFUSE_ALLOW_M (PMS_HP_CORE0_UM_LP_EFUSE_ALLOW_V << PMS_HP_CORE0_UM_LP_EFUSE_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_EFUSE_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_EFUSE_ALLOW_S 18
/** PMS_HP_CORE0_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_PMS_ALLOW (BIT(19))
#define PMS_HP_CORE0_UM_LP_PMS_ALLOW_M (PMS_HP_CORE0_UM_LP_PMS_ALLOW_V << PMS_HP_CORE0_UM_LP_PMS_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_PMS_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_PMS_ALLOW_S 19
/** PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access
* HP2LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW (BIT(20))
#define PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW_M (PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW_V << PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW_S)
#define PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW_S 20
/** PMS_HP_CORE0_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP temperature
* sensor.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_TSENS_ALLOW (BIT(21))
#define PMS_HP_CORE0_UM_LP_TSENS_ALLOW_M (PMS_HP_CORE0_UM_LP_TSENS_ALLOW_V << PMS_HP_CORE0_UM_LP_TSENS_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_TSENS_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_TSENS_ALLOW_S 21
/** PMS_HP_CORE0_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* Configures whether HP CPU0 in user mode has permission to LP HUK.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_HUK_ALLOW (BIT(22))
#define PMS_HP_CORE0_UM_LP_HUK_ALLOW_M (PMS_HP_CORE0_UM_LP_HUK_ALLOW_V << PMS_HP_CORE0_UM_LP_HUK_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_HUK_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_HUK_ALLOW_S 22
/** PMS_HP_CORE0_UM_LP_SRAM_ALLOW : R/W; bitpos: [23]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access LP SRAM.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_SRAM_ALLOW (BIT(23))
#define PMS_HP_CORE0_UM_LP_SRAM_ALLOW_M (PMS_HP_CORE0_UM_LP_SRAM_ALLOW_V << PMS_HP_CORE0_UM_LP_SRAM_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_SRAM_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_SRAM_ALLOW_S 23
/** PMS_HP_CORE1_MM_PMS_REG0_REG register
* Permission control register0 for HP CPU1 in machine mode
*/
#define PMS_HP_CORE1_MM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x10)
/** PMS_HP_CORE1_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP System
* Registers.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_SYSREG_ALLOW (BIT(0))
#define PMS_HP_CORE1_MM_LP_SYSREG_ALLOW_M (PMS_HP_CORE1_MM_LP_SYSREG_ALLOW_V << PMS_HP_CORE1_MM_LP_SYSREG_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_SYSREG_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_SYSREG_ALLOW_S 0
/** PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP_AONCLKRST.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW (BIT(1))
#define PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW_M (PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V << PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S 1
/** PMS_HP_CORE1_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP timer.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_TIMER_ALLOW (BIT(2))
#define PMS_HP_CORE1_MM_LP_TIMER_ALLOW_M (PMS_HP_CORE1_MM_LP_TIMER_ALLOW_V << PMS_HP_CORE1_MM_LP_TIMER_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_TIMER_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_TIMER_ALLOW_S 2
/** PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP ANAPERI.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW (BIT(3))
#define PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW_M (PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW_V << PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW_S 3
/** PMS_HP_CORE1_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP PMU.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_PMU_ALLOW (BIT(4))
#define PMS_HP_CORE1_MM_LP_PMU_ALLOW_M (PMS_HP_CORE1_MM_LP_PMU_ALLOW_V << PMS_HP_CORE1_MM_LP_PMU_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_PMU_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_PMU_ALLOW_S 4
/** PMS_HP_CORE1_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP WDT.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_WDT_ALLOW (BIT(5))
#define PMS_HP_CORE1_MM_LP_WDT_ALLOW_M (PMS_HP_CORE1_MM_LP_WDT_ALLOW_V << PMS_HP_CORE1_MM_LP_WDT_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_WDT_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_WDT_ALLOW_S 5
/** PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP Mailbox
* Controller.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW (BIT(6))
#define PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW_M (PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW_V << PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW_S 6
/** PMS_HP_CORE1_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP RTC.
* 0: Not allowed
* 1: Allow
*/
#define PMS_HP_CORE1_MM_LP_RTC_ALLOW (BIT(7))
#define PMS_HP_CORE1_MM_LP_RTC_ALLOW_M (PMS_HP_CORE1_MM_LP_RTC_ALLOW_V << PMS_HP_CORE1_MM_LP_RTC_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_RTC_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_RTC_ALLOW_S 7
/** PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP PERICLKRST.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW (BIT(8))
#define PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW_M (PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V << PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S 8
/** PMS_HP_CORE1_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP UART.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_UART_ALLOW (BIT(9))
#define PMS_HP_CORE1_MM_LP_UART_ALLOW_M (PMS_HP_CORE1_MM_LP_UART_ALLOW_V << PMS_HP_CORE1_MM_LP_UART_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_UART_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_UART_ALLOW_S 9
/** PMS_HP_CORE1_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP I2C.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_I2C_ALLOW (BIT(10))
#define PMS_HP_CORE1_MM_LP_I2C_ALLOW_M (PMS_HP_CORE1_MM_LP_I2C_ALLOW_V << PMS_HP_CORE1_MM_LP_I2C_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_I2C_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_I2C_ALLOW_S 10
/** PMS_HP_CORE1_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP SPI.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_SPI_ALLOW (BIT(11))
#define PMS_HP_CORE1_MM_LP_SPI_ALLOW_M (PMS_HP_CORE1_MM_LP_SPI_ALLOW_V << PMS_HP_CORE1_MM_LP_SPI_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_SPI_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_SPI_ALLOW_S 11
/** PMS_HP_CORE1_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP I2C master.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_I2CMST_ALLOW (BIT(12))
#define PMS_HP_CORE1_MM_LP_I2CMST_ALLOW_M (PMS_HP_CORE1_MM_LP_I2CMST_ALLOW_V << PMS_HP_CORE1_MM_LP_I2CMST_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_I2CMST_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_I2CMST_ALLOW_S 12
/** PMS_HP_CORE1_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP I2S.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_I2S_ALLOW (BIT(13))
#define PMS_HP_CORE1_MM_LP_I2S_ALLOW_M (PMS_HP_CORE1_MM_LP_I2S_ALLOW_V << PMS_HP_CORE1_MM_LP_I2S_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_I2S_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_I2S_ALLOW_S 13
/** PMS_HP_CORE1_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP ADC.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_ADC_ALLOW (BIT(14))
#define PMS_HP_CORE1_MM_LP_ADC_ALLOW_M (PMS_HP_CORE1_MM_LP_ADC_ALLOW_V << PMS_HP_CORE1_MM_LP_ADC_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_ADC_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_ADC_ALLOW_S 14
/** PMS_HP_CORE1_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP touch
* sensor.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_TOUCH_ALLOW (BIT(15))
#define PMS_HP_CORE1_MM_LP_TOUCH_ALLOW_M (PMS_HP_CORE1_MM_LP_TOUCH_ALLOW_V << PMS_HP_CORE1_MM_LP_TOUCH_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_TOUCH_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_TOUCH_ALLOW_S 15
/** PMS_HP_CORE1_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP IO MUX.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_IOMUX_ALLOW (BIT(16))
#define PMS_HP_CORE1_MM_LP_IOMUX_ALLOW_M (PMS_HP_CORE1_MM_LP_IOMUX_ALLOW_V << PMS_HP_CORE1_MM_LP_IOMUX_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_IOMUX_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_IOMUX_ALLOW_S 16
/** PMS_HP_CORE1_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP INTR.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_INTR_ALLOW (BIT(17))
#define PMS_HP_CORE1_MM_LP_INTR_ALLOW_M (PMS_HP_CORE1_MM_LP_INTR_ALLOW_V << PMS_HP_CORE1_MM_LP_INTR_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_INTR_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_INTR_ALLOW_S 17
/** PMS_HP_CORE1_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP eFuse.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_EFUSE_ALLOW (BIT(18))
#define PMS_HP_CORE1_MM_LP_EFUSE_ALLOW_M (PMS_HP_CORE1_MM_LP_EFUSE_ALLOW_V << PMS_HP_CORE1_MM_LP_EFUSE_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_EFUSE_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_EFUSE_ALLOW_S 18
/** PMS_HP_CORE1_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access
* LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_PMS_ALLOW (BIT(19))
#define PMS_HP_CORE1_MM_LP_PMS_ALLOW_M (PMS_HP_CORE1_MM_LP_PMS_ALLOW_V << PMS_HP_CORE1_MM_LP_PMS_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_PMS_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_PMS_ALLOW_S 19
/** PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access
* HP2LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW (BIT(20))
#define PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW_M (PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW_V << PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW_S)
#define PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW_S 20
/** PMS_HP_CORE1_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP temperature
* sensor.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_TSENS_ALLOW (BIT(21))
#define PMS_HP_CORE1_MM_LP_TSENS_ALLOW_M (PMS_HP_CORE1_MM_LP_TSENS_ALLOW_V << PMS_HP_CORE1_MM_LP_TSENS_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_TSENS_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_TSENS_ALLOW_S 21
/** PMS_HP_CORE1_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to LP HUK.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_HUK_ALLOW (BIT(22))
#define PMS_HP_CORE1_MM_LP_HUK_ALLOW_M (PMS_HP_CORE1_MM_LP_HUK_ALLOW_V << PMS_HP_CORE1_MM_LP_HUK_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_HUK_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_HUK_ALLOW_S 22
/** PMS_HP_CORE1_MM_LP_SRAM_ALLOW : R/W; bitpos: [23]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access LP SRAM.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_SRAM_ALLOW (BIT(23))
#define PMS_HP_CORE1_MM_LP_SRAM_ALLOW_M (PMS_HP_CORE1_MM_LP_SRAM_ALLOW_V << PMS_HP_CORE1_MM_LP_SRAM_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_SRAM_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_SRAM_ALLOW_S 23
/** PMS_HP_CORE1_UM_PMS_REG0_REG register
* Permission control register0 for HP CPU1 in user mode
*/
#define PMS_HP_CORE1_UM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x14)
/** PMS_HP_CORE1_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP System
* Registers.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_SYSREG_ALLOW (BIT(0))
#define PMS_HP_CORE1_UM_LP_SYSREG_ALLOW_M (PMS_HP_CORE1_UM_LP_SYSREG_ALLOW_V << PMS_HP_CORE1_UM_LP_SYSREG_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_SYSREG_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_SYSREG_ALLOW_S 0
/** PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP_AONCLKRST.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW (BIT(1))
#define PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW_M (PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V << PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S 1
/** PMS_HP_CORE1_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP timer.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_TIMER_ALLOW (BIT(2))
#define PMS_HP_CORE1_UM_LP_TIMER_ALLOW_M (PMS_HP_CORE1_UM_LP_TIMER_ALLOW_V << PMS_HP_CORE1_UM_LP_TIMER_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_TIMER_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_TIMER_ALLOW_S 2
/** PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP ANAPERI.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW (BIT(3))
#define PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW_M (PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW_V << PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW_S 3
/** PMS_HP_CORE1_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP PMU.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_PMU_ALLOW (BIT(4))
#define PMS_HP_CORE1_UM_LP_PMU_ALLOW_M (PMS_HP_CORE1_UM_LP_PMU_ALLOW_V << PMS_HP_CORE1_UM_LP_PMU_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_PMU_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_PMU_ALLOW_S 4
/** PMS_HP_CORE1_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP WDT.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_WDT_ALLOW (BIT(5))
#define PMS_HP_CORE1_UM_LP_WDT_ALLOW_M (PMS_HP_CORE1_UM_LP_WDT_ALLOW_V << PMS_HP_CORE1_UM_LP_WDT_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_WDT_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_WDT_ALLOW_S 5
/** PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP Mailbox
* Controller.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW (BIT(6))
#define PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW_M (PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW_V << PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW_S 6
/** PMS_HP_CORE1_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP RTC.
* 0: Not allowed
* 1: Allow
*/
#define PMS_HP_CORE1_UM_LP_RTC_ALLOW (BIT(7))
#define PMS_HP_CORE1_UM_LP_RTC_ALLOW_M (PMS_HP_CORE1_UM_LP_RTC_ALLOW_V << PMS_HP_CORE1_UM_LP_RTC_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_RTC_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_RTC_ALLOW_S 7
/** PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP PERICLKRST.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW (BIT(8))
#define PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW_M (PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V << PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S 8
/** PMS_HP_CORE1_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP UART.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_UART_ALLOW (BIT(9))
#define PMS_HP_CORE1_UM_LP_UART_ALLOW_M (PMS_HP_CORE1_UM_LP_UART_ALLOW_V << PMS_HP_CORE1_UM_LP_UART_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_UART_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_UART_ALLOW_S 9
/** PMS_HP_CORE1_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP I2C.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_I2C_ALLOW (BIT(10))
#define PMS_HP_CORE1_UM_LP_I2C_ALLOW_M (PMS_HP_CORE1_UM_LP_I2C_ALLOW_V << PMS_HP_CORE1_UM_LP_I2C_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_I2C_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_I2C_ALLOW_S 10
/** PMS_HP_CORE1_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP SPI.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_SPI_ALLOW (BIT(11))
#define PMS_HP_CORE1_UM_LP_SPI_ALLOW_M (PMS_HP_CORE1_UM_LP_SPI_ALLOW_V << PMS_HP_CORE1_UM_LP_SPI_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_SPI_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_SPI_ALLOW_S 11
/** PMS_HP_CORE1_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP I2C master.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_I2CMST_ALLOW (BIT(12))
#define PMS_HP_CORE1_UM_LP_I2CMST_ALLOW_M (PMS_HP_CORE1_UM_LP_I2CMST_ALLOW_V << PMS_HP_CORE1_UM_LP_I2CMST_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_I2CMST_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_I2CMST_ALLOW_S 12
/** PMS_HP_CORE1_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP I2S.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_I2S_ALLOW (BIT(13))
#define PMS_HP_CORE1_UM_LP_I2S_ALLOW_M (PMS_HP_CORE1_UM_LP_I2S_ALLOW_V << PMS_HP_CORE1_UM_LP_I2S_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_I2S_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_I2S_ALLOW_S 13
/** PMS_HP_CORE1_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP ADC.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_ADC_ALLOW (BIT(14))
#define PMS_HP_CORE1_UM_LP_ADC_ALLOW_M (PMS_HP_CORE1_UM_LP_ADC_ALLOW_V << PMS_HP_CORE1_UM_LP_ADC_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_ADC_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_ADC_ALLOW_S 14
/** PMS_HP_CORE1_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP touch sensor.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_TOUCH_ALLOW (BIT(15))
#define PMS_HP_CORE1_UM_LP_TOUCH_ALLOW_M (PMS_HP_CORE1_UM_LP_TOUCH_ALLOW_V << PMS_HP_CORE1_UM_LP_TOUCH_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_TOUCH_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_TOUCH_ALLOW_S 15
/** PMS_HP_CORE1_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP IO MUX.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_IOMUX_ALLOW (BIT(16))
#define PMS_HP_CORE1_UM_LP_IOMUX_ALLOW_M (PMS_HP_CORE1_UM_LP_IOMUX_ALLOW_V << PMS_HP_CORE1_UM_LP_IOMUX_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_IOMUX_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_IOMUX_ALLOW_S 16
/** PMS_HP_CORE1_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP INTR.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_INTR_ALLOW (BIT(17))
#define PMS_HP_CORE1_UM_LP_INTR_ALLOW_M (PMS_HP_CORE1_UM_LP_INTR_ALLOW_V << PMS_HP_CORE1_UM_LP_INTR_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_INTR_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_INTR_ALLOW_S 17
/** PMS_HP_CORE1_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP eFuse.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_EFUSE_ALLOW (BIT(18))
#define PMS_HP_CORE1_UM_LP_EFUSE_ALLOW_M (PMS_HP_CORE1_UM_LP_EFUSE_ALLOW_V << PMS_HP_CORE1_UM_LP_EFUSE_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_EFUSE_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_EFUSE_ALLOW_S 18
/** PMS_HP_CORE1_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_PMS_ALLOW (BIT(19))
#define PMS_HP_CORE1_UM_LP_PMS_ALLOW_M (PMS_HP_CORE1_UM_LP_PMS_ALLOW_V << PMS_HP_CORE1_UM_LP_PMS_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_PMS_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_PMS_ALLOW_S 19
/** PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access
* HP2LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW (BIT(20))
#define PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW_M (PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW_V << PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW_S)
#define PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW_S 20
/** PMS_HP_CORE1_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP temperature
* sensor.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_TSENS_ALLOW (BIT(21))
#define PMS_HP_CORE1_UM_LP_TSENS_ALLOW_M (PMS_HP_CORE1_UM_LP_TSENS_ALLOW_V << PMS_HP_CORE1_UM_LP_TSENS_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_TSENS_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_TSENS_ALLOW_S 21
/** PMS_HP_CORE1_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* Configures whether HP CPU1 in user mode has permission to LP HUK.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_HUK_ALLOW (BIT(22))
#define PMS_HP_CORE1_UM_LP_HUK_ALLOW_M (PMS_HP_CORE1_UM_LP_HUK_ALLOW_V << PMS_HP_CORE1_UM_LP_HUK_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_HUK_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_HUK_ALLOW_S 22
/** PMS_HP_CORE1_UM_LP_SRAM_ALLOW : R/W; bitpos: [23]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access LP SRAM.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_SRAM_ALLOW (BIT(23))
#define PMS_HP_CORE1_UM_LP_SRAM_ALLOW_M (PMS_HP_CORE1_UM_LP_SRAM_ALLOW_V << PMS_HP_CORE1_UM_LP_SRAM_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_SRAM_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_SRAM_ALLOW_S 23
/** PMS_REGDMA_LP_PERI_PMS_REG register
* LP Peripheral Permission register for REGDMA
*/
#define PMS_REGDMA_LP_PERI_PMS_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x18)
/** PMS_REGDMA_PERI_LP_SRAM_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether REGDMA has permission to access LP SRAM.
* 0: Not allowed
* 1: Allow
*/
#define PMS_REGDMA_PERI_LP_SRAM_ALLOW (BIT(0))
#define PMS_REGDMA_PERI_LP_SRAM_ALLOW_M (PMS_REGDMA_PERI_LP_SRAM_ALLOW_V << PMS_REGDMA_PERI_LP_SRAM_ALLOW_S)
#define PMS_REGDMA_PERI_LP_SRAM_ALLOW_V 0x00000001U
#define PMS_REGDMA_PERI_LP_SRAM_ALLOW_S 0
/** PMS_REGDMA_PERI_LP_PERI_ALLOW : R/W; bitpos: [1]; default: 1;
* Configures whether REGDMA has permission to access all LP peripherals.
* 0: Not allowed
* 1: Allow
*/
#define PMS_REGDMA_PERI_LP_PERI_ALLOW (BIT(1))
#define PMS_REGDMA_PERI_LP_PERI_ALLOW_M (PMS_REGDMA_PERI_LP_PERI_ALLOW_V << PMS_REGDMA_PERI_LP_PERI_ALLOW_S)
#define PMS_REGDMA_PERI_LP_PERI_ALLOW_V 0x00000001U
#define PMS_REGDMA_PERI_LP_PERI_ALLOW_S 1
#ifdef __cplusplus
}
#endif

530
components/soc/esp32p4/register/hw_ver2/soc/hp2lp_peri_pms_struct.h Normal file
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@@ -0,0 +1,530 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: TEE HP2LP TEE PMS DATE REG */
/** Type of hp2lp_tee_pms_date register
* NA
*/
typedef union {
struct {
/** tee_date : R/W; bitpos: [31:0]; default: 2363943;
* NA
*/
uint32_t tee_date:32;
};
uint32_t val;
} tee_hp2lp_tee_pms_date_reg_t;
/** Group: TEE PMS CLK EN REG */
/** Type of pms_clk_en register
* NA
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} tee_pms_clk_en_reg_t;
/** Group: TEE HP CORE0 MM PMS REG0 REG */
/** Type of hp_core0_mm_pms_reg0 register
* NA
*/
typedef union {
struct {
/** reg_hp_core0_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_sysreg_allow:1;
/** reg_hp_core0_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_aonclkrst_allow:1;
/** reg_hp_core0_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_timer_allow:1;
/** reg_hp_core0_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_anaperi_allow:1;
/** reg_hp_core0_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_pmu_allow:1;
/** reg_hp_core0_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_wdt_allow:1;
/** reg_hp_core0_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_mailbox_allow:1;
/** reg_hp_core0_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_rtc_allow:1;
/** reg_hp_core0_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_periclkrst_allow:1;
/** reg_hp_core0_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_uart_allow:1;
/** reg_hp_core0_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_i2c_allow:1;
/** reg_hp_core0_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_spi_allow:1;
/** reg_hp_core0_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_i2cmst_allow:1;
/** reg_hp_core0_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_i2s_allow:1;
/** reg_hp_core0_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_adc_allow:1;
/** reg_hp_core0_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_touch_allow:1;
/** reg_hp_core0_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_iomux_allow:1;
/** reg_hp_core0_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_intr_allow:1;
/** reg_hp_core0_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_efuse_allow:1;
/** reg_hp_core0_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_pms_allow:1;
/** reg_hp_core0_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_hp2lp_pms_allow:1;
/** reg_hp_core0_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_tsens_allow:1;
/** reg_hp_core0_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_huk_allow:1;
/** reg_hp_core0_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_tcm_ram_allow:1;
/** reg_hp_core0_mm_lp_trng_allow : R/W; bitpos: [24]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_trng_allow:1;
uint32_t reserved_25:7;
};
uint32_t val;
} tee_hp_core0_mm_pms_reg0_reg_t;
/** Group: TEE HP CORE0 UM PMS REG0 REG */
/** Type of hp_core0_um_pms_reg0 register
* NA
*/
typedef union {
struct {
/** reg_hp_core0_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_sysreg_allow:1;
/** reg_hp_core0_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_aonclkrst_allow:1;
/** reg_hp_core0_um_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_timer_allow:1;
/** reg_hp_core0_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_anaperi_allow:1;
/** reg_hp_core0_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_pmu_allow:1;
/** reg_hp_core0_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_wdt_allow:1;
/** reg_hp_core0_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_mailbox_allow:1;
/** reg_hp_core0_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_rtc_allow:1;
/** reg_hp_core0_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_periclkrst_allow:1;
/** reg_hp_core0_um_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_uart_allow:1;
/** reg_hp_core0_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_i2c_allow:1;
/** reg_hp_core0_um_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_spi_allow:1;
/** reg_hp_core0_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_i2cmst_allow:1;
/** reg_hp_core0_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_i2s_allow:1;
/** reg_hp_core0_um_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_adc_allow:1;
/** reg_hp_core0_um_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_touch_allow:1;
/** reg_hp_core0_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_iomux_allow:1;
/** reg_hp_core0_um_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_intr_allow:1;
/** reg_hp_core0_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_efuse_allow:1;
/** reg_hp_core0_um_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_pms_allow:1;
/** reg_hp_core0_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_hp2lp_pms_allow:1;
/** reg_hp_core0_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_tsens_allow:1;
/** reg_hp_core0_um_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_huk_allow:1;
/** reg_hp_core0_um_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_tcm_ram_allow:1;
/** reg_hp_core0_um_lp_trng_allow : R/W; bitpos: [24]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_trng_allow:1;
uint32_t reserved_25:7;
};
uint32_t val;
} tee_hp_core0_um_pms_reg0_reg_t;
/** Group: TEE HP CORE1 MM PMS REG0 REG */
/** Type of hp_core1_mm_pms_reg0 register
* NA
*/
typedef union {
struct {
/** reg_hp_core1_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_sysreg_allow:1;
/** reg_hp_core1_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_aonclkrst_allow:1;
/** reg_hp_core1_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_timer_allow:1;
/** reg_hp_core1_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_anaperi_allow:1;
/** reg_hp_core1_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_pmu_allow:1;
/** reg_hp_core1_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_wdt_allow:1;
/** reg_hp_core1_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_mailbox_allow:1;
/** reg_hp_core1_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_rtc_allow:1;
/** reg_hp_core1_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_periclkrst_allow:1;
/** reg_hp_core1_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_uart_allow:1;
/** reg_hp_core1_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_i2c_allow:1;
/** reg_hp_core1_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_spi_allow:1;
/** reg_hp_core1_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_i2cmst_allow:1;
/** reg_hp_core1_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_i2s_allow:1;
/** reg_hp_core1_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_adc_allow:1;
/** reg_hp_core1_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_touch_allow:1;
/** reg_hp_core1_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_iomux_allow:1;
/** reg_hp_core1_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_intr_allow:1;
/** reg_hp_core1_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_efuse_allow:1;
/** reg_hp_core1_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_pms_allow:1;
/** reg_hp_core1_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_hp2lp_pms_allow:1;
/** reg_hp_core1_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_tsens_allow:1;
/** reg_hp_core1_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_huk_allow:1;
/** reg_hp_core1_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_tcm_ram_allow:1;
/** reg_hp_core1_mm_lp_trng_allow : R/W; bitpos: [24]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_trng_allow:1;
uint32_t reserved_25:7;
};
uint32_t val;
} tee_hp_core1_mm_pms_reg0_reg_t;
/** Group: TEE HP CORE1 UM PMS REG0 REG */
/** Type of hp_core1_um_pms_reg0 register
* NA
*/
typedef union {
struct {
/** reg_hp_core1_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_sysreg_allow:1;
/** reg_hp_core1_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_aonclkrst_allow:1;
/** reg_hp_core1_um_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_timer_allow:1;
/** reg_hp_core1_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_anaperi_allow:1;
/** reg_hp_core1_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_pmu_allow:1;
/** reg_hp_core1_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_wdt_allow:1;
/** reg_hp_core1_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_mailbox_allow:1;
/** reg_hp_core1_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_rtc_allow:1;
/** reg_hp_core1_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_periclkrst_allow:1;
/** reg_hp_core1_um_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_uart_allow:1;
/** reg_hp_core1_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_i2c_allow:1;
/** reg_hp_core1_um_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_spi_allow:1;
/** reg_hp_core1_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_i2cmst_allow:1;
/** reg_hp_core1_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_i2s_allow:1;
/** reg_hp_core1_um_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_adc_allow:1;
/** reg_hp_core1_um_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_touch_allow:1;
/** reg_hp_core1_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_iomux_allow:1;
/** reg_hp_core1_um_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_intr_allow:1;
/** reg_hp_core1_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_efuse_allow:1;
/** reg_hp_core1_um_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_pms_allow:1;
/** reg_hp_core1_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_hp2lp_pms_allow:1;
/** reg_hp_core1_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_tsens_allow:1;
/** reg_hp_core1_um_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_huk_allow:1;
/** reg_hp_core1_um_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_tcm_ram_allow:1;
/** reg_hp_core1_um_lp_trng_allow : R/W; bitpos: [24]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_trng_allow:1;
uint32_t reserved_25:7;
};
uint32_t val;
} tee_hp_core1_um_pms_reg0_reg_t;
/** Group: TEE REGDMA PERI PMS REG */
/** Type of regdma_peri_pms register
* NA
*/
typedef union {
struct {
/** reg_regdma_peri_lp_ram_allow : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_regdma_peri_lp_ram_allow:1;
/** reg_regdma_peri_lp_peri_allow : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_regdma_peri_lp_peri_allow:1;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_regdma_peri_pms_reg_t;
typedef struct {
volatile tee_hp2lp_tee_pms_date_reg_t hp2lp_tee_pms_date;
volatile tee_pms_clk_en_reg_t pms_clk_en;
volatile tee_hp_core0_mm_pms_reg0_reg_t hp_core0_mm_pms_reg0;
volatile tee_hp_core0_um_pms_reg0_reg_t hp_core0_um_pms_reg0;
volatile tee_hp_core1_mm_pms_reg0_reg_t hp_core1_mm_pms_reg0;
volatile tee_hp_core1_um_pms_reg0_reg_t hp_core1_um_pms_reg0;
volatile tee_regdma_peri_pms_reg_t regdma_peri_pms;
} tee_dev_t;
extern tee_dev_t HP2LP_PERI_PMS;
#ifndef __cplusplus
_Static_assert(sizeof(tee_dev_t) == 0x1c, "Invalid size of tee_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HUK_CLK_REG register
* HUK Generator clock gate control register
*/
#define HUK_CLK_REG (DR_REG_HUK_BASE + 0x4)
/** HUK_CLK_EN : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
#define HUK_CLK_EN (BIT(0))
#define HUK_CLK_EN_M (HUK_CLK_EN_V << HUK_CLK_EN_S)
#define HUK_CLK_EN_V 0x00000001U
#define HUK_CLK_EN_S 0
/** HUK_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
#define HUK_MEM_CG_FORCE_ON (BIT(1))
#define HUK_MEM_CG_FORCE_ON_M (HUK_MEM_CG_FORCE_ON_V << HUK_MEM_CG_FORCE_ON_S)
#define HUK_MEM_CG_FORCE_ON_V 0x00000001U
#define HUK_MEM_CG_FORCE_ON_S 1
/** HUK_INT_RAW_REG register
* HUK Generator interrupt raw register, valid in level.
*/
#define HUK_INT_RAW_REG (DR_REG_HUK_BASE + 0x8)
/** HUK_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_RAW (BIT(0))
#define HUK_PREP_DONE_INT_RAW_M (HUK_PREP_DONE_INT_RAW_V << HUK_PREP_DONE_INT_RAW_S)
#define HUK_PREP_DONE_INT_RAW_V 0x00000001U
#define HUK_PREP_DONE_INT_RAW_S 0
/** HUK_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_RAW (BIT(1))
#define HUK_PROC_DONE_INT_RAW_M (HUK_PROC_DONE_INT_RAW_V << HUK_PROC_DONE_INT_RAW_S)
#define HUK_PROC_DONE_INT_RAW_V 0x00000001U
#define HUK_PROC_DONE_INT_RAW_S 1
/** HUK_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_RAW (BIT(2))
#define HUK_POST_DONE_INT_RAW_M (HUK_POST_DONE_INT_RAW_V << HUK_POST_DONE_INT_RAW_S)
#define HUK_POST_DONE_INT_RAW_V 0x00000001U
#define HUK_POST_DONE_INT_RAW_S 2
/** HUK_INT_ST_REG register
* HUK Generator interrupt status register.
*/
#define HUK_INT_ST_REG (DR_REG_HUK_BASE + 0xc)
/** HUK_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_ST (BIT(0))
#define HUK_PREP_DONE_INT_ST_M (HUK_PREP_DONE_INT_ST_V << HUK_PREP_DONE_INT_ST_S)
#define HUK_PREP_DONE_INT_ST_V 0x00000001U
#define HUK_PREP_DONE_INT_ST_S 0
/** HUK_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_ST (BIT(1))
#define HUK_PROC_DONE_INT_ST_M (HUK_PROC_DONE_INT_ST_V << HUK_PROC_DONE_INT_ST_S)
#define HUK_PROC_DONE_INT_ST_V 0x00000001U
#define HUK_PROC_DONE_INT_ST_S 1
/** HUK_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_ST (BIT(2))
#define HUK_POST_DONE_INT_ST_M (HUK_POST_DONE_INT_ST_V << HUK_POST_DONE_INT_ST_S)
#define HUK_POST_DONE_INT_ST_V 0x00000001U
#define HUK_POST_DONE_INT_ST_S 2
/** HUK_INT_ENA_REG register
* HUK Generator interrupt enable register.
*/
#define HUK_INT_ENA_REG (DR_REG_HUK_BASE + 0x10)
/** HUK_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_ENA (BIT(0))
#define HUK_PREP_DONE_INT_ENA_M (HUK_PREP_DONE_INT_ENA_V << HUK_PREP_DONE_INT_ENA_S)
#define HUK_PREP_DONE_INT_ENA_V 0x00000001U
#define HUK_PREP_DONE_INT_ENA_S 0
/** HUK_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_ENA (BIT(1))
#define HUK_PROC_DONE_INT_ENA_M (HUK_PROC_DONE_INT_ENA_V << HUK_PROC_DONE_INT_ENA_S)
#define HUK_PROC_DONE_INT_ENA_V 0x00000001U
#define HUK_PROC_DONE_INT_ENA_S 1
/** HUK_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_ENA (BIT(2))
#define HUK_POST_DONE_INT_ENA_M (HUK_POST_DONE_INT_ENA_V << HUK_POST_DONE_INT_ENA_S)
#define HUK_POST_DONE_INT_ENA_V 0x00000001U
#define HUK_POST_DONE_INT_ENA_S 2
/** HUK_INT_CLR_REG register
* HUK Generator interrupt clear register.
*/
#define HUK_INT_CLR_REG (DR_REG_HUK_BASE + 0x14)
/** HUK_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_CLR (BIT(0))
#define HUK_PREP_DONE_INT_CLR_M (HUK_PREP_DONE_INT_CLR_V << HUK_PREP_DONE_INT_CLR_S)
#define HUK_PREP_DONE_INT_CLR_V 0x00000001U
#define HUK_PREP_DONE_INT_CLR_S 0
/** HUK_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_CLR (BIT(1))
#define HUK_PROC_DONE_INT_CLR_M (HUK_PROC_DONE_INT_CLR_V << HUK_PROC_DONE_INT_CLR_S)
#define HUK_PROC_DONE_INT_CLR_V 0x00000001U
#define HUK_PROC_DONE_INT_CLR_S 1
/** HUK_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_CLR (BIT(2))
#define HUK_POST_DONE_INT_CLR_M (HUK_POST_DONE_INT_CLR_V << HUK_POST_DONE_INT_CLR_S)
#define HUK_POST_DONE_INT_CLR_V 0x00000001U
#define HUK_POST_DONE_INT_CLR_S 2
/** HUK_CONF_REG register
* HUK Generator configuration register
*/
#define HUK_CONF_REG (DR_REG_HUK_BASE + 0x20)
/** HUK_MODE : R/W; bitpos: [0]; default: 0;
* Set this field to choose the huk process. 1: process huk generate mode. 0: process
* huk recovery mode.
*/
#define HUK_MODE (BIT(0))
#define HUK_MODE_M (HUK_MODE_V << HUK_MODE_S)
#define HUK_MODE_V 0x00000001U
#define HUK_MODE_S 0
/** HUK_START_REG register
* HUK Generator control register
*/
#define HUK_START_REG (DR_REG_HUK_BASE + 0x24)
/** HUK_START : WT; bitpos: [0]; default: 0;
* Write 1 to continue HUK Generator operation at LOAD/GAIN state.
*/
#define HUK_START (BIT(0))
#define HUK_START_M (HUK_START_V << HUK_START_S)
#define HUK_START_V 0x00000001U
#define HUK_START_S 0
/** HUK_CONTINUE : WT; bitpos: [1]; default: 0;
* Write 1 to start HUK Generator at IDLE state.
*/
#define HUK_CONTINUE (BIT(1))
#define HUK_CONTINUE_M (HUK_CONTINUE_V << HUK_CONTINUE_S)
#define HUK_CONTINUE_V 0x00000001U
#define HUK_CONTINUE_S 1
/** HUK_STATE_REG register
* HUK Generator state register
*/
#define HUK_STATE_REG (DR_REG_HUK_BASE + 0x28)
/** HUK_STATE : RO; bitpos: [1:0]; default: 0;
* The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
#define HUK_STATE 0x00000003U
#define HUK_STATE_M (HUK_STATE_V << HUK_STATE_S)
#define HUK_STATE_V 0x00000003U
#define HUK_STATE_S 0
/** HUK_STATUS_REG register
* HUK Generator HUK status register
*/
#define HUK_STATUS_REG (DR_REG_HUK_BASE + 0x34)
/** HUK_STATUS : RO; bitpos: [1:0]; default: 0;
* The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
* 2: HUK is generated but invalid. 3: reserved.
*/
#define HUK_STATUS 0x00000003U
#define HUK_STATUS_M (HUK_STATUS_V << HUK_STATUS_S)
#define HUK_STATUS_V 0x00000003U
#define HUK_STATUS_S 0
/** HUK_RISK_LEVEL : RO; bitpos: [4:2]; default: 0;
* The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
* are in the PUF SRAM. 7: Error Level, HUK is invalid.
*/
#define HUK_RISK_LEVEL 0x00000007U
#define HUK_RISK_LEVEL_M (HUK_RISK_LEVEL_V << HUK_RISK_LEVEL_S)
#define HUK_RISK_LEVEL_V 0x00000007U
#define HUK_RISK_LEVEL_S 2
/** HUK_UPDATE_REQ : RO; bitpos: [5]; default: 0;
* The update request of HUK info. 0: User can update HUK info according to the risk
* level. 1: The HUK info is expired, and user need to update it.
*/
#define HUK_UPDATE_REQ (BIT(5))
#define HUK_UPDATE_REQ_M (HUK_UPDATE_REQ_V << HUK_UPDATE_REQ_S)
#define HUK_UPDATE_REQ_V 0x00000001U
#define HUK_UPDATE_REQ_S 5
/** HUK_DATE_REG register
* Version control register
*/
#define HUK_DATE_REG (DR_REG_HUK_BASE + 0xfc)
/** HUK_DATE : R/W; bitpos: [27:0]; default: 37765232;
* HUK Generator version control register.
*/
#define HUK_DATE 0x0FFFFFFFU
#define HUK_DATE_M (HUK_DATE_V << HUK_DATE_S)
#define HUK_DATE_V 0x0FFFFFFFU
#define HUK_DATE_S 0
/** HUK_INFO_MEM register
* The memory that stores HUK info.
*/
#define HUK_INFO_MEM (DR_REG_HUK_BASE + 0x100)
#define HUK_INFO_MEM_SIZE_BYTES 384
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Clock gate register */
/** Type of clk register
* HUK Generator clock gate control register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
uint32_t clk_en:1;
/** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
uint32_t mem_cg_force_on:1;
uint32_t reserved_2:30;
};
uint32_t val;
} huk_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* HUK Generator interrupt raw register, valid in level.
*/
typedef union {
struct {
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_raw:1;
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_raw:1;
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the huk_post_done_int interrupt
*/
uint32_t post_done_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_raw_reg_t;
/** Type of int_st register
* HUK Generator interrupt status register.
*/
typedef union {
struct {
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_st:1;
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_st:1;
/** post_done_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the huk_post_done_int interrupt
*/
uint32_t post_done_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_st_reg_t;
/** Type of int_ena register
* HUK Generator interrupt enable register.
*/
typedef union {
struct {
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_ena:1;
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_ena:1;
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the huk_post_done_int interrupt
*/
uint32_t post_done_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_ena_reg_t;
/** Type of int_clr register
* HUK Generator interrupt clear register.
*/
typedef union {
struct {
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_clr:1;
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_clr:1;
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the huk_post_done_int interrupt
*/
uint32_t post_done_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_clr_reg_t;
/** Group: Configuration registers */
/** Type of conf register
* HUK Generator configuration register
*/
typedef union {
struct {
/** mode : R/W; bitpos: [0]; default: 0;
* Set this field to choose the huk process. 1: process huk generate mode. 0: process
* huk recovery mode.
*/
uint32_t mode:1;
uint32_t reserved_1:31;
};
uint32_t val;
} huk_conf_reg_t;
/** Group: Control registers */
/** Type of start register
* HUK Generator control register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to continue HUK Generator operation at LOAD/GAIN state.
*/
uint32_t start:1;
/** continue : WT; bitpos: [1]; default: 0;
* Write 1 to start HUK Generator at IDLE state.
*/
uint32_t conti:1;
uint32_t reserved_2:30;
};
uint32_t val;
} huk_start_reg_t;
/** Group: State registers */
/** Type of state register
* HUK Generator state register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} huk_state_reg_t;
/** Group: Result registers */
/** Type of status register
* HUK Generator HUK status register
*/
typedef union {
struct {
/** status : RO; bitpos: [1:0]; default: 0;
* The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
* 2: HUK is generated but invalid. 3: reserved.
*/
uint32_t status:2;
/** risk_level : RO; bitpos: [4:2]; default: 0;
* The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
* are in the PUF SRAM. 7: Error Level, HUK is invalid.
*/
uint32_t risk_level:3;
/** update_req : RO; bitpos: [5]; default: 0;
* The update request of HUK info. 0: User can update HUK info according to the risk
* level. 1: The HUK info is expired, and user need to update it.
*/
uint32_t update_req:1;
uint32_t reserved_6:26;
};
uint32_t val;
} huk_status_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37765232;
* HUK Generator version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} huk_date_reg_t;
typedef struct {
uint32_t reserved_000;
volatile huk_clk_reg_t clk;
volatile huk_int_raw_reg_t int_raw;
volatile huk_int_st_reg_t int_st;
volatile huk_int_ena_reg_t int_ena;
volatile huk_int_clr_reg_t int_clr;
uint32_t reserved_018[2];
volatile huk_conf_reg_t conf;
volatile huk_start_reg_t start;
volatile huk_state_reg_t state;
uint32_t reserved_02c[2];
volatile huk_status_reg_t status;
uint32_t reserved_038[49];
volatile huk_date_reg_t date;
volatile uint32_t info[96];
} huk_dev_t;
extern huk_dev_t HUK;
#ifndef __cplusplus
_Static_assert(sizeof(huk_dev_t) == 0x280, "Invalid size of huk_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** I2C_ANA_MST_I2C0_CTRL_REG register
* need des
*/
#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0)
/** I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFFU
#define I2C_ANA_MST_I2C0_CTRL_M (I2C_ANA_MST_I2C0_CTRL_V << I2C_ANA_MST_I2C0_CTRL_S)
#define I2C_ANA_MST_I2C0_CTRL_V 0x01FFFFFFU
#define I2C_ANA_MST_I2C0_CTRL_S 0
/** I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C0_BUSY (BIT(25))
#define I2C_ANA_MST_I2C0_BUSY_M (I2C_ANA_MST_I2C0_BUSY_V << I2C_ANA_MST_I2C0_BUSY_S)
#define I2C_ANA_MST_I2C0_BUSY_V 0x00000001U
#define I2C_ANA_MST_I2C0_BUSY_S 25
/** I2C_ANA_MST_I2C1_CTRL_REG register
* need des
*/
#define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4)
/** I2C_ANA_MST_I2C1_CTRL : R/W; bitpos: [24:0]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFFU
#define I2C_ANA_MST_I2C1_CTRL_M (I2C_ANA_MST_I2C1_CTRL_V << I2C_ANA_MST_I2C1_CTRL_S)
#define I2C_ANA_MST_I2C1_CTRL_V 0x01FFFFFFU
#define I2C_ANA_MST_I2C1_CTRL_S 0
/** I2C_ANA_MST_I2C1_BUSY : RO; bitpos: [25]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C1_BUSY (BIT(25))
#define I2C_ANA_MST_I2C1_BUSY_M (I2C_ANA_MST_I2C1_BUSY_V << I2C_ANA_MST_I2C1_BUSY_S)
#define I2C_ANA_MST_I2C1_BUSY_V 0x00000001U
#define I2C_ANA_MST_I2C1_BUSY_S 25
/** I2C_ANA_MST_I2C0_CONF_REG register
* need des
*/
#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8)
/** I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C0_CONF 0x00FFFFFFU
#define I2C_ANA_MST_I2C0_CONF_M (I2C_ANA_MST_I2C0_CONF_V << I2C_ANA_MST_I2C0_CONF_S)
#define I2C_ANA_MST_I2C0_CONF_V 0x00FFFFFFU
#define I2C_ANA_MST_I2C0_CONF_S 0
/** I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C0_STATUS 0x000000FFU
#define I2C_ANA_MST_I2C0_STATUS_M (I2C_ANA_MST_I2C0_STATUS_V << I2C_ANA_MST_I2C0_STATUS_S)
#define I2C_ANA_MST_I2C0_STATUS_V 0x000000FFU
#define I2C_ANA_MST_I2C0_STATUS_S 24
/** I2C_ANA_MST_I2C1_CONF_REG register
* need des
*/
#define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xc)
/** I2C_ANA_MST_I2C1_CONF : R/W; bitpos: [23:0]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C1_CONF 0x00FFFFFFU
#define I2C_ANA_MST_I2C1_CONF_M (I2C_ANA_MST_I2C1_CONF_V << I2C_ANA_MST_I2C1_CONF_S)
#define I2C_ANA_MST_I2C1_CONF_V 0x00FFFFFFU
#define I2C_ANA_MST_I2C1_CONF_S 0
/** I2C_ANA_MST_I2C1_STATUS : RO; bitpos: [31:24]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C1_STATUS 0x000000FFU
#define I2C_ANA_MST_I2C1_STATUS_M (I2C_ANA_MST_I2C1_STATUS_V << I2C_ANA_MST_I2C1_STATUS_S)
#define I2C_ANA_MST_I2C1_STATUS_V 0x000000FFU
#define I2C_ANA_MST_I2C1_STATUS_S 24
/** I2C_ANA_MST_I2C_BURST_CONF_REG register
* need des
*/
#define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10)
/** I2C_ANA_MST_I2C_MST_BURST_CTRL : R/W; bitpos: [31:0]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C_MST_BURST_CTRL 0xFFFFFFFFU
#define I2C_ANA_MST_I2C_MST_BURST_CTRL_M (I2C_ANA_MST_I2C_MST_BURST_CTRL_V << I2C_ANA_MST_I2C_MST_BURST_CTRL_S)
#define I2C_ANA_MST_I2C_MST_BURST_CTRL_V 0xFFFFFFFFU
#define I2C_ANA_MST_I2C_MST_BURST_CTRL_S 0
/** I2C_ANA_MST_I2C_BURST_STATUS_REG register
* need des
*/
#define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14)
/** I2C_ANA_MST_I2C_MST_BURST_DONE : RO; bitpos: [0]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C_MST_BURST_DONE (BIT(0))
#define I2C_ANA_MST_I2C_MST_BURST_DONE_M (I2C_ANA_MST_I2C_MST_BURST_DONE_V << I2C_ANA_MST_I2C_MST_BURST_DONE_S)
#define I2C_ANA_MST_I2C_MST_BURST_DONE_V 0x00000001U
#define I2C_ANA_MST_I2C_MST_BURST_DONE_S 0
/** I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG : RO; bitpos: [1]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1))
#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_M (I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V << I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S)
#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V 0x00000001U
#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S 1
/** I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG : RO; bitpos: [2]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG (BIT(2))
#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_M (I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V << I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S)
#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V 0x00000001U
#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S 2
/** I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT : R/W; bitpos: [31:20]; default: 1024;
* need des
*/
#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT 0x00000FFFU
#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_M (I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V << I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S)
#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V 0x00000FFFU
#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S 20
/** I2C_ANA_MST_ANA_CONF0_REG register
* need des
*/
#define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18)
/** I2C_ANA_MST_ANA_CONF0 : R/W; bitpos: [23:0]; default: 0;
* need des
*/
#define I2C_ANA_MST_ANA_CONF0 0x00FFFFFFU
#define I2C_ANA_MST_ANA_CONF0_M (I2C_ANA_MST_ANA_CONF0_V << I2C_ANA_MST_ANA_CONF0_S)
#define I2C_ANA_MST_ANA_CONF0_V 0x00FFFFFFU
#define I2C_ANA_MST_ANA_CONF0_S 0
/** I2C_ANA_MST_ANA_STATUS0 : RO; bitpos: [31:24]; default: 0;
* need des
*/
#define I2C_ANA_MST_ANA_STATUS0 0x000000FFU
#define I2C_ANA_MST_ANA_STATUS0_M (I2C_ANA_MST_ANA_STATUS0_V << I2C_ANA_MST_ANA_STATUS0_S)
#define I2C_ANA_MST_ANA_STATUS0_V 0x000000FFU
#define I2C_ANA_MST_ANA_STATUS0_S 24
/** I2C_ANA_MST_ANA_CONF1_REG register
* need des
*/
#define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1c)
/** I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0;
* need des
*/
#define I2C_ANA_MST_ANA_CONF1 0x00FFFFFFU
#define I2C_ANA_MST_ANA_CONF1_M (I2C_ANA_MST_ANA_CONF1_V << I2C_ANA_MST_ANA_CONF1_S)
#define I2C_ANA_MST_ANA_CONF1_V 0x00FFFFFFU
#define I2C_ANA_MST_ANA_CONF1_S 0
/** I2C_ANA_MST_ANA_STATUS1 : RO; bitpos: [31:24]; default: 0;
* need des
*/
#define I2C_ANA_MST_ANA_STATUS1 0x000000FFU
#define I2C_ANA_MST_ANA_STATUS1_M (I2C_ANA_MST_ANA_STATUS1_V << I2C_ANA_MST_ANA_STATUS1_S)
#define I2C_ANA_MST_ANA_STATUS1_V 0x000000FFU
#define I2C_ANA_MST_ANA_STATUS1_S 24
/** I2C_ANA_MST_ANA_CONF2_REG register
* need des
*/
#define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20)
/** I2C_ANA_MST_ANA_CONF2 : R/W; bitpos: [23:0]; default: 0;
* need des
*/
#define I2C_ANA_MST_ANA_CONF2 0x00FFFFFFU
#define I2C_ANA_MST_ANA_CONF2_M (I2C_ANA_MST_ANA_CONF2_V << I2C_ANA_MST_ANA_CONF2_S)
#define I2C_ANA_MST_ANA_CONF2_V 0x00FFFFFFU
#define I2C_ANA_MST_ANA_CONF2_S 0
/** I2C_ANA_MST_ANA_STATUS2 : RO; bitpos: [31:24]; default: 0;
* need des
*/
#define I2C_ANA_MST_ANA_STATUS2 0x000000FFU
#define I2C_ANA_MST_ANA_STATUS2_M (I2C_ANA_MST_ANA_STATUS2_V << I2C_ANA_MST_ANA_STATUS2_S)
#define I2C_ANA_MST_ANA_STATUS2_V 0x000000FFU
#define I2C_ANA_MST_ANA_STATUS2_S 24
/** I2C_ANA_MST_I2C0_CTRL1_REG register
* need des
*/
#define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24)
/** I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;
* need des
*/
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003FU
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M (I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V << I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S)
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x0000003FU
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0
/** I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;
* need des
*/
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001FU
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M (I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V << I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S)
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x0000001FU
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6
/** I2C_ANA_MST_I2C1_CTRL1_REG register
* need des
*/
#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28)
/** I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;
* need des
*/
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003FU
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M (I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V << I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S)
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x0000003FU
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0
/** I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;
* need des
*/
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001FU
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M (I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V << I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S)
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x0000001FU
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6
/** I2C_ANA_MST_HW_I2C_CTRL_REG register
* need des
*/
#define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2c)
/** I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;
* need des
*/
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003FU
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M (I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V << I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S)
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x0000003FU
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0
/** I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;
* need des
*/
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001FU
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M (I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V << I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S)
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x0000001FU
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6
/** I2C_ANA_MST_ARBITER_DIS : R/W; bitpos: [11]; default: 0;
* need des
*/
#define I2C_ANA_MST_ARBITER_DIS (BIT(11))
#define I2C_ANA_MST_ARBITER_DIS_M (I2C_ANA_MST_ARBITER_DIS_V << I2C_ANA_MST_ARBITER_DIS_S)
#define I2C_ANA_MST_ARBITER_DIS_V 0x00000001U
#define I2C_ANA_MST_ARBITER_DIS_S 11
/** I2C_ANA_MST_NOUSE_REG register
* need des
*/
#define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30)
/** I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFFU
#define I2C_ANA_MST_I2C_MST_NOUSE_M (I2C_ANA_MST_I2C_MST_NOUSE_V << I2C_ANA_MST_I2C_MST_NOUSE_S)
#define I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFFU
#define I2C_ANA_MST_I2C_MST_NOUSE_S 0
/** I2C_ANA_MST_CLK160M_REG register
* need des
*/
#define I2C_ANA_MST_CLK160M_REG (DR_REG_I2C_ANA_MST_BASE + 0x34)
/** I2C_ANA_MST_CLK_I2C_MST_SEL_160M : R/W; bitpos: [0]; default: 0;
* need des
*/
#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M (BIT(0))
#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_M (I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V << I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S)
#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V 0x00000001U
#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S 0
/** I2C_ANA_MST_DATE_REG register
* need des
*/
#define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x38)
/** I2C_ANA_MST_DATE : R/W; bitpos: [27:0]; default: 36717104;
* need des
*/
#define I2C_ANA_MST_DATE 0x0FFFFFFFU
#define I2C_ANA_MST_DATE_M (I2C_ANA_MST_DATE_V << I2C_ANA_MST_DATE_S)
#define I2C_ANA_MST_DATE_V 0x0FFFFFFFU
#define I2C_ANA_MST_DATE_S 0
/** I2C_ANA_MST_I2C_MST_CLK_EN : R/W; bitpos: [28]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C_MST_CLK_EN (BIT(28))
#define I2C_ANA_MST_I2C_MST_CLK_EN_M (I2C_ANA_MST_I2C_MST_CLK_EN_V << I2C_ANA_MST_I2C_MST_CLK_EN_S)
#define I2C_ANA_MST_I2C_MST_CLK_EN_V 0x00000001U
#define I2C_ANA_MST_I2C_MST_CLK_EN_S 28
#ifdef __cplusplus
}
#endif

304
components/soc/esp32p4/register/hw_ver2/soc/i2c_ana_mst_struct.h Normal file
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@@ -0,0 +1,304 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configure Register */
/** Type of i2c0_ctrl register
* need des
*/
typedef union {
struct {
/** i2c0_ctrl : R/W; bitpos: [24:0]; default: 0;
* need des
*/
uint32_t i2c0_ctrl:25;
/** i2c0_busy : RO; bitpos: [25]; default: 0;
* need des
*/
uint32_t i2c0_busy:1;
uint32_t reserved_26:6;
};
uint32_t val;
} i2c_ana_mst_i2c0_ctrl_reg_t;
/** Type of i2c1_ctrl register
* need des
*/
typedef union {
struct {
/** i2c1_ctrl : R/W; bitpos: [24:0]; default: 0;
* need des
*/
uint32_t i2c1_ctrl:25;
/** i2c1_busy : RO; bitpos: [25]; default: 0;
* need des
*/
uint32_t i2c1_busy:1;
uint32_t reserved_26:6;
};
uint32_t val;
} i2c_ana_mst_i2c1_ctrl_reg_t;
/** Type of i2c0_conf register
* need des
*/
typedef union {
struct {
/** i2c0_conf : R/W; bitpos: [23:0]; default: 0;
* need des
*/
uint32_t i2c0_conf:24;
/** i2c0_status : RO; bitpos: [31:24]; default: 0;
* need des
*/
uint32_t i2c0_status:8;
};
uint32_t val;
} i2c_ana_mst_i2c0_conf_reg_t;
/** Type of i2c1_conf register
* need des
*/
typedef union {
struct {
/** i2c1_conf : R/W; bitpos: [23:0]; default: 0;
* need des
*/
uint32_t i2c1_conf:24;
/** i2c1_status : RO; bitpos: [31:24]; default: 0;
* need des
*/
uint32_t i2c1_status:8;
};
uint32_t val;
} i2c_ana_mst_i2c1_conf_reg_t;
/** Type of i2c_burst_conf register
* need des
*/
typedef union {
struct {
/** i2c_mst_burst_ctrl : R/W; bitpos: [31:0]; default: 0;
* need des
*/
uint32_t i2c_mst_burst_ctrl:32;
};
uint32_t val;
} i2c_ana_mst_i2c_burst_conf_reg_t;
/** Type of i2c_burst_status register
* need des
*/
typedef union {
struct {
/** i2c_mst_burst_done : RO; bitpos: [0]; default: 0;
* need des
*/
uint32_t i2c_mst_burst_done:1;
/** i2c_mst0_burst_err_flag : RO; bitpos: [1]; default: 0;
* need des
*/
uint32_t i2c_mst0_burst_err_flag:1;
/** i2c_mst1_burst_err_flag : RO; bitpos: [2]; default: 0;
* need des
*/
uint32_t i2c_mst1_burst_err_flag:1;
uint32_t reserved_3:17;
/** i2c_mst_burst_timeout_cnt : R/W; bitpos: [31:20]; default: 1024;
* need des
*/
uint32_t i2c_mst_burst_timeout_cnt:12;
};
uint32_t val;
} i2c_ana_mst_i2c_burst_status_reg_t;
/** Type of ana_conf0 register
* need des
*/
typedef union {
struct {
/** ana_conf0 : R/W; bitpos: [23:0]; default: 0;
* need des
*/
uint32_t ana_conf0:24;
/** ana_status0 : RO; bitpos: [31:24]; default: 0;
* need des
*/
uint32_t ana_status0:8;
};
uint32_t val;
} i2c_ana_mst_ana_conf0_reg_t;
/** Type of ana_conf1 register
* need des
*/
typedef union {
struct {
/** ana_conf1 : R/W; bitpos: [23:0]; default: 0;
* need des
*/
uint32_t ana_conf1:24;
/** ana_status1 : RO; bitpos: [31:24]; default: 0;
* need des
*/
uint32_t ana_status1:8;
};
uint32_t val;
} i2c_ana_mst_ana_conf1_reg_t;
/** Type of ana_conf2 register
* need des
*/
typedef union {
struct {
/** ana_conf2 : R/W; bitpos: [23:0]; default: 0;
* need des
*/
uint32_t ana_conf2:24;
/** ana_status2 : RO; bitpos: [31:24]; default: 0;
* need des
*/
uint32_t ana_status2:8;
};
uint32_t val;
} i2c_ana_mst_ana_conf2_reg_t;
/** Type of i2c0_ctrl1 register
* need des
*/
typedef union {
struct {
/** i2c0_scl_pulse_dur : R/W; bitpos: [5:0]; default: 2;
* need des
*/
uint32_t i2c0_scl_pulse_dur:6;
/** i2c0_sda_side_guard : R/W; bitpos: [10:6]; default: 1;
* need des
*/
uint32_t i2c0_sda_side_guard:5;
uint32_t reserved_11:21;
};
uint32_t val;
} i2c_ana_mst_i2c0_ctrl1_reg_t;
/** Type of i2c1_ctrl1 register
* need des
*/
typedef union {
struct {
/** i2c1_scl_pulse_dur : R/W; bitpos: [5:0]; default: 2;
* need des
*/
uint32_t i2c1_scl_pulse_dur:6;
/** i2c1_sda_side_guard : R/W; bitpos: [10:6]; default: 1;
* need des
*/
uint32_t i2c1_sda_side_guard:5;
uint32_t reserved_11:21;
};
uint32_t val;
} i2c_ana_mst_i2c1_ctrl1_reg_t;
/** Type of hw_i2c_ctrl register
* need des
*/
typedef union {
struct {
/** hw_i2c_scl_pulse_dur : R/W; bitpos: [5:0]; default: 2;
* need des
*/
uint32_t hw_i2c_scl_pulse_dur:6;
/** hw_i2c_sda_side_guard : R/W; bitpos: [10:6]; default: 1;
* need des
*/
uint32_t hw_i2c_sda_side_guard:5;
/** arbiter_dis : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t arbiter_dis:1;
uint32_t reserved_12:20;
};
uint32_t val;
} i2c_ana_mst_hw_i2c_ctrl_reg_t;
/** Type of nouse register
* need des
*/
typedef union {
struct {
/** i2c_mst_nouse : R/W; bitpos: [31:0]; default: 0;
* need des
*/
uint32_t i2c_mst_nouse:32;
};
uint32_t val;
} i2c_ana_mst_nouse_reg_t;
/** Type of clk160m register
* need des
*/
typedef union {
struct {
/** clk_i2c_mst_sel_160m : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t clk_i2c_mst_sel_160m:1;
uint32_t reserved_1:31;
};
uint32_t val;
} i2c_ana_mst_clk160m_reg_t;
/** Type of date register
* need des
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36717104;
* need des
*/
uint32_t date:28;
/** i2c_mst_clk_en : R/W; bitpos: [28]; default: 0;
* need des
*/
uint32_t i2c_mst_clk_en:1;
uint32_t reserved_29:3;
};
uint32_t val;
} i2c_ana_mst_date_reg_t;
typedef struct {
volatile i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl;
volatile i2c_ana_mst_i2c1_ctrl_reg_t i2c1_ctrl;
volatile i2c_ana_mst_i2c0_conf_reg_t i2c0_conf;
volatile i2c_ana_mst_i2c1_conf_reg_t i2c1_conf;
volatile i2c_ana_mst_i2c_burst_conf_reg_t i2c_burst_conf;
volatile i2c_ana_mst_i2c_burst_status_reg_t i2c_burst_status;
volatile i2c_ana_mst_ana_conf0_reg_t ana_conf0;
volatile i2c_ana_mst_ana_conf1_reg_t ana_conf1;
volatile i2c_ana_mst_ana_conf2_reg_t ana_conf2;
volatile i2c_ana_mst_i2c0_ctrl1_reg_t i2c0_ctrl1;
volatile i2c_ana_mst_i2c1_ctrl1_reg_t i2c1_ctrl1;
volatile i2c_ana_mst_hw_i2c_ctrl_reg_t hw_i2c_ctrl;
volatile i2c_ana_mst_nouse_reg_t nouse;
volatile i2c_ana_mst_clk160m_reg_t clk160m;
volatile i2c_ana_mst_date_reg_t date;
} i2c_ana_mst_dev_t;
extern i2c_ana_mst_dev_t I2C_ANA_MST;
#ifndef __cplusplus
_Static_assert(sizeof(i2c_ana_mst_dev_t) == 0x3c, "Invalid size of i2c_ana_mst_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: I3C COMMAND BUF PORT REG */
/** Type of command_buf_port register
* NA
*/
typedef union {
struct {
/** reg_command : R/W; bitpos: [31:0]; default: 0;
* Contains a Command Descriptor structure that depends on the requested transfer
* type. Command Descriptor structure is used to schedule the transfers to devices on
* I3C bus.
*/
uint32_t reg_command:32;
};
uint32_t val;
} i3c_mst_mem_command_buf_port_reg_t;
/** Group: I3C RESPONSE BUF PORT REG */
/** Type of response_buf_port register
* NA
*/
typedef union {
struct {
/** response : RO; bitpos: [31:0]; default: 0;
* The Response Buffer can be read through this register. The response status for each
* Command is written into the Response Buffer by the controller if ROC (Response On
* Completion) bit is set or if transfer error has occurred. The response buffer can
* be read through this register.
*/
uint32_t response:32;
};
uint32_t val;
} i3c_mst_mem_response_buf_port_reg_t;
/** Group: I3C RX DATA PORT REG */
/** Type of rx_data_port register
* NA
*/
typedef union {
struct {
/** rx_data_port : RO; bitpos: [31:0]; default: 0;
* Receive Data Port. Receive data is mapped to the Rx-data buffer and receive data is
* always packed in 4-byte aligned data words. If the length of data transfer is not
* aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional
* data bytes have to be ignored) at the end of the transferred data. The valid data
* must be identified using the DATA_LENGTH filed in the Response Descriptor.
*/
uint32_t rx_data_port:32;
};
uint32_t val;
} i3c_mst_mem_rx_data_port_reg_t;
/** Group: I3C TX DATA PORT REG */
/** Type of tx_data_port register
* NA
*/
typedef union {
struct {
/** reg_tx_data_port : R/W; bitpos: [31:0]; default: 0;
* Transmit Data Port. Transmit data is mapped to the Tx-data buffer and transmit
* data is always packed in 4-byte aligned data words. If the length of data transfer
* is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the
* additional data bytes have to be ignored) at the end of the transferred data. The
* valid data must be identified using the DATA_LENGTH filed in the Response
* Descriptor.
*/
uint32_t reg_tx_data_port:32;
};
uint32_t val;
} i3c_mst_mem_tx_data_port_reg_t;
/** Group: I3C IBI STATUS BUF REG */
/** Type of ibi_status_buf register
* In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is
* used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data)
*/
typedef union {
struct {
/** data_length : RO; bitpos: [7:0]; default: 0;
* This field represents the length of data received along with IBI, in bytes.
*/
uint32_t data_length:8;
/** ibi_id : RO; bitpos: [15:8]; default: 0;
* IBI Identifier. The byte received after START which includes the address the R/W
* bit: Device address and R/W bit in case of Slave Interrupt or Master Request.
*/
uint32_t ibi_id:8;
uint32_t reserved_16:12;
/** ibi_sts : RO; bitpos: [28]; default: 0;
* IBI received data/status. IBI Data register is mapped to the IBI Buffer. The IBI
* Data is always packed in4-byte aligned and put to the IBI Buffer. This register
* When read from, reads the data from the IBI buffer. IBI Status register when read
* from, returns the data from the IBI Buffer and indicates how the controller
* responded to incoming IBI(SIR, MR and HJ).
*/
uint32_t ibi_sts:1;
uint32_t reserved_29:3;
};
uint32_t val;
} i3c_mst_mem_ibi_status_buf_reg_t;
/** Group: I3C IBI DATA BUF REG */
/** Type of ibi_data_buf register
* NA
*/
typedef union {
struct {
/** ibi_data : RO; bitpos: [31:0]; default: 0;
* NA
*/
uint32_t ibi_data:32;
};
uint32_t val;
} i3c_mst_mem_ibi_data_buf_reg_t;
/** Group: I3C DEV ADDR TABLEn LOC REG */
/** Type of dev_addr_tablen_loc register
* NA
*/
typedef union {
struct {
/** reg_dat_devn_static_addr : R/W; bitpos: [6:0]; default: 0;
* NA
*/
uint32_t reg_dat_devn_static_addr:7;
uint32_t reserved_7:9;
/** reg_dat_dev12_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
* Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
* parity of dynamic address.
*/
uint32_t reg_dat_devn_dynamic_addr:8;
uint32_t reserved_24:5;
/** reg_dat_dev12_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
* This field is used to set the Device NACK Retry count for the particular device. If
* the Device NACK's for the device address, the controller automatically retries the
* same device until this count expires. If the Slave does not ACK for the mentioned
* number of retries, then controller generates an error response and move to the Halt
* state.
*/
uint32_t reg_dat_devn_nack_retry_cnt:2;
/** reg_dat_dev12_i2c : R/W; bitpos: [31]; default: 0;
* Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
* device.
*/
uint32_t reg_dat_devn_i2c:1;
};
uint32_t val;
} i3c_mst_mem_dev_addr_tablen_loc_reg_t;
typedef struct {
volatile uint32_t loc1;
volatile uint32_t loc2;
volatile uint32_t loc3;
volatile uint32_t loc4;
} i3c_mst_mem_dev_char_tablen_reg_t;
typedef struct {
uint32_t reserved_000[2];
volatile i3c_mst_mem_command_buf_port_reg_t command_buf_port;
volatile i3c_mst_mem_response_buf_port_reg_t response_buf_port;
volatile i3c_mst_mem_rx_data_port_reg_t rx_data_port;
volatile i3c_mst_mem_tx_data_port_reg_t tx_data_port;
volatile i3c_mst_mem_ibi_status_buf_reg_t ibi_status_buf;
uint32_t reserved_01c[9];
volatile i3c_mst_mem_ibi_data_buf_reg_t ibi_data_buf;
uint32_t reserved_044[31];
volatile i3c_mst_mem_dev_addr_tablen_loc_reg_t dev_addr_table[12];
uint32_t reserved_0f0[4];
volatile i3c_mst_mem_dev_char_tablen_reg_t dev_char_table[12];
} i3c_mst_mem_dev_t;
extern i3c_mst_mem_dev_t I3C_MST_MEM;
#ifndef __cplusplus
_Static_assert(sizeof(i3c_mst_mem_dev_t) == 0x1c0, "Invalid size of i3c_mst_mem_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** I3C_SLV_CONFIG_REG register
* NA
*/
#define I3C_SLV_CONFIG_REG (DR_REG_I3C_SLV_BASE + 0x4)
/** I3C_SLV_SLVENA : R/W; bitpos: [0]; default: 1;
* 1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus.
* This should be not set until registers such as PARTNO, IDEXT and the like are set
* 1st -if used- since they impact data to the master
*/
#define I3C_SLV_SLVENA (BIT(0))
#define I3C_SLV_SLVENA_M (I3C_SLV_SLVENA_V << I3C_SLV_SLVENA_S)
#define I3C_SLV_SLVENA_V 0x00000001U
#define I3C_SLV_SLVENA_S 0
/** I3C_SLV_NACK : R/W; bitpos: [1]; default: 0;
* 1:the slave will NACK all requests to it except CCC broadcast. This should be used
* with caution as the Master may determine the slave is missing if overused.
*/
#define I3C_SLV_NACK (BIT(1))
#define I3C_SLV_NACK_M (I3C_SLV_NACK_V << I3C_SLV_NACK_S)
#define I3C_SLV_NACK_V 0x00000001U
#define I3C_SLV_NACK_S 1
/** I3C_SLV_MATCHSS : R/W; bitpos: [2]; default: 0;
* 1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This
* allows START and STOP to be used to detect end of a message to /from this slave.
*/
#define I3C_SLV_MATCHSS (BIT(2))
#define I3C_SLV_MATCHSS_M (I3C_SLV_MATCHSS_V << I3C_SLV_MATCHSS_S)
#define I3C_SLV_MATCHSS_V 0x00000001U
#define I3C_SLV_MATCHSS_S 2
/** I3C_SLV_S0IGNORE : R/W; bitpos: [3]; default: 0;
* If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an
* Exit Pattern. This should only be used when the bus will not use HDR.
*/
#define I3C_SLV_S0IGNORE (BIT(3))
#define I3C_SLV_S0IGNORE_M (I3C_SLV_S0IGNORE_V << I3C_SLV_S0IGNORE_S)
#define I3C_SLV_S0IGNORE_V 0x00000001U
#define I3C_SLV_S0IGNORE_S 3
/** I3C_SLV_DDROK : R/W; bitpos: [4]; default: 0;
* NA
*/
#define I3C_SLV_DDROK (BIT(4))
#define I3C_SLV_DDROK_M (I3C_SLV_DDROK_V << I3C_SLV_DDROK_S)
#define I3C_SLV_DDROK_V 0x00000001U
#define I3C_SLV_DDROK_S 4
/** I3C_SLV_IDRAND : R/W; bitpos: [8]; default: 0;
* NA
*/
#define I3C_SLV_IDRAND (BIT(8))
#define I3C_SLV_IDRAND_M (I3C_SLV_IDRAND_V << I3C_SLV_IDRAND_S)
#define I3C_SLV_IDRAND_V 0x00000001U
#define I3C_SLV_IDRAND_S 8
/** I3C_SLV_OFFLINE : R/W; bitpos: [9]; default: 0;
* NA
*/
#define I3C_SLV_OFFLINE (BIT(9))
#define I3C_SLV_OFFLINE_M (I3C_SLV_OFFLINE_V << I3C_SLV_OFFLINE_S)
#define I3C_SLV_OFFLINE_V 0x00000001U
#define I3C_SLV_OFFLINE_S 9
/** I3C_SLV_BAMATCH : R/W; bitpos: [23:16]; default: 47;
* Bus Available condition match value for current ???Slow clock???. This provides the
* count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low
* when the Master is not doing so. The max width , and so max value, is controlled by
* the block. Only if enabled for events such IBI or MR or HJ, and if enabled to
* provide this as a register. With is limited to CLK_SLOW_BITS
*/
#define I3C_SLV_BAMATCH 0x000000FFU
#define I3C_SLV_BAMATCH_M (I3C_SLV_BAMATCH_V << I3C_SLV_BAMATCH_S)
#define I3C_SLV_BAMATCH_V 0x000000FFU
#define I3C_SLV_BAMATCH_S 16
/** I3C_SLV_SADDR : R/W; bitpos: [31:25]; default: 0;
* If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled
* to use one and to be provided by SW. Block may provide in HW as well.
*/
#define I3C_SLV_SADDR 0x0000007FU
#define I3C_SLV_SADDR_M (I3C_SLV_SADDR_V << I3C_SLV_SADDR_S)
#define I3C_SLV_SADDR_V 0x0000007FU
#define I3C_SLV_SADDR_S 25
/** I3C_SLV_STATUS_REG register
* NA
*/
#define I3C_SLV_STATUS_REG (DR_REG_I3C_SLV_BASE + 0x8)
/** I3C_SLV_STNOTSTOP : RO; bitpos: [0]; default: 0;
* Is 1 if bus is busy(activity) and 0 when in a STOP condition. Other bits may also
* set when busy. Note that this can also be true from an S0 or S1 error, which waits
* for an Exit Pattern.
*/
#define I3C_SLV_STNOTSTOP (BIT(0))
#define I3C_SLV_STNOTSTOP_M (I3C_SLV_STNOTSTOP_V << I3C_SLV_STNOTSTOP_S)
#define I3C_SLV_STNOTSTOP_V 0x00000001U
#define I3C_SLV_STNOTSTOP_S 0
/** I3C_SLV_STMSG : RO; bitpos: [1]; default: 0;
* Is 1 if this bus Slave is listening to the bus traffic or responding, If
* STNOSTOP=1, then this will be 0 when a non-matching address seen until next
* respeated START it STOP.
*/
#define I3C_SLV_STMSG (BIT(1))
#define I3C_SLV_STMSG_M (I3C_SLV_STMSG_V << I3C_SLV_STMSG_S)
#define I3C_SLV_STMSG_V 0x00000001U
#define I3C_SLV_STMSG_S 1
/** I3C_SLV_STCCCH : RO; bitpos: [2]; default: 0;
* Is 1 if a CCC message is being handled automatically.
*/
#define I3C_SLV_STCCCH (BIT(2))
#define I3C_SLV_STCCCH_M (I3C_SLV_STCCCH_V << I3C_SLV_STCCCH_S)
#define I3C_SLV_STCCCH_V 0x00000001U
#define I3C_SLV_STCCCH_S 2
/** I3C_SLV_STREQRD : RO; bitpos: [3]; default: 0;
* 1 if the req in process is an sdr read from this slave or an IBI is being pushed
* out,
*/
#define I3C_SLV_STREQRD (BIT(3))
#define I3C_SLV_STREQRD_M (I3C_SLV_STREQRD_V << I3C_SLV_STREQRD_S)
#define I3C_SLV_STREQRD_V 0x00000001U
#define I3C_SLV_STREQRD_S 3
/** I3C_SLV_STREQWR : RO; bitpos: [4]; default: 0;
* NA
*/
#define I3C_SLV_STREQWR (BIT(4))
#define I3C_SLV_STREQWR_M (I3C_SLV_STREQWR_V << I3C_SLV_STREQWR_S)
#define I3C_SLV_STREQWR_V 0x00000001U
#define I3C_SLV_STREQWR_S 4
/** I3C_SLV_STDAA : RO; bitpos: [5]; default: 0;
* NA
*/
#define I3C_SLV_STDAA (BIT(5))
#define I3C_SLV_STDAA_M (I3C_SLV_STDAA_V << I3C_SLV_STDAA_S)
#define I3C_SLV_STDAA_V 0x00000001U
#define I3C_SLV_STDAA_S 5
/** I3C_SLV_STHDR : RO; bitpos: [6]; default: 0;
* NA
*/
#define I3C_SLV_STHDR (BIT(6))
#define I3C_SLV_STHDR_M (I3C_SLV_STHDR_V << I3C_SLV_STHDR_S)
#define I3C_SLV_STHDR_V 0x00000001U
#define I3C_SLV_STHDR_S 6
/** I3C_SLV_START : R/W; bitpos: [8]; default: 0;
* NA
*/
#define I3C_SLV_START (BIT(8))
#define I3C_SLV_START_M (I3C_SLV_START_V << I3C_SLV_START_S)
#define I3C_SLV_START_V 0x00000001U
#define I3C_SLV_START_S 8
/** I3C_SLV_MATCHED : R/W; bitpos: [9]; default: 0;
* NA
*/
#define I3C_SLV_MATCHED (BIT(9))
#define I3C_SLV_MATCHED_M (I3C_SLV_MATCHED_V << I3C_SLV_MATCHED_S)
#define I3C_SLV_MATCHED_V 0x00000001U
#define I3C_SLV_MATCHED_S 9
/** I3C_SLV_STOP : R/W; bitpos: [10]; default: 0;
* NA
*/
#define I3C_SLV_STOP (BIT(10))
#define I3C_SLV_STOP_M (I3C_SLV_STOP_V << I3C_SLV_STOP_S)
#define I3C_SLV_STOP_V 0x00000001U
#define I3C_SLV_STOP_S 10
/** I3C_SLV_RXPEND : RO; bitpos: [11]; default: 0;
* Receiving a message from master,which is not being handled by block(not a CCC
* internally processed). For all but External FIFO, this uses DATACTRL RXTRIG, which
* defaults to not-empty. If DMA is enabled for RX, DMA will be signaled as well. Will
* self-clear if data is read(FIFO and non-FIFO)
*/
#define I3C_SLV_RXPEND (BIT(11))
#define I3C_SLV_RXPEND_M (I3C_SLV_RXPEND_V << I3C_SLV_RXPEND_S)
#define I3C_SLV_RXPEND_V 0x00000001U
#define I3C_SLV_RXPEND_S 11
/** I3C_SLV_TXNOTFULL : RO; bitpos: [12]; default: 0;
* Is 1 when the To-bus buffer/FIFO can accept more data to go out. Defau:1. For all
* but External FIFO, this uses DATACTRL TXTRIG,which defaults to not-full. If DMA is
* enabled for TX, it will also be signaled to provide more.
*/
#define I3C_SLV_TXNOTFULL (BIT(12))
#define I3C_SLV_TXNOTFULL_M (I3C_SLV_TXNOTFULL_V << I3C_SLV_TXNOTFULL_S)
#define I3C_SLV_TXNOTFULL_V 0x00000001U
#define I3C_SLV_TXNOTFULL_S 12
/** I3C_SLV_DACHG : R/W; bitpos: [13]; default: 0;
* The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in
* that state of being valid or none. Actual DA can be seen in the DYNADDR register.
* Note that this will also be used when MAP Auto feature is configured. This will be
* changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main
* DA(0) will indicate if last change was due to Auto MAP.
*/
#define I3C_SLV_DACHG (BIT(13))
#define I3C_SLV_DACHG_M (I3C_SLV_DACHG_V << I3C_SLV_DACHG_S)
#define I3C_SLV_DACHG_V 0x00000001U
#define I3C_SLV_DACHG_S 13
/** I3C_SLV_CCC : R/W; bitpos: [14]; default: 0;
* A common -command-code(CCC), not handled by block, has been received. This acts
* differently between: *Broadcasted ones, which will then also correspond with RXPEND
* and the 1st byte will be the CCC(command) . *Direct ones, which may never be
* directed to this device. If it is, then the TXSEND or RXPEND will be triggered
* with this end the RXPEND will contain the command.
*/
#define I3C_SLV_CCC (BIT(14))
#define I3C_SLV_CCC_M (I3C_SLV_CCC_V << I3C_SLV_CCC_S)
#define I3C_SLV_CCC_V 0x00000001U
#define I3C_SLV_CCC_S 14
/** I3C_SLV_ERRWARN : RO; bitpos: [15]; default: 0;
* NA
*/
#define I3C_SLV_ERRWARN (BIT(15))
#define I3C_SLV_ERRWARN_M (I3C_SLV_ERRWARN_V << I3C_SLV_ERRWARN_S)
#define I3C_SLV_ERRWARN_V 0x00000001U
#define I3C_SLV_ERRWARN_S 15
/** I3C_SLV_HDRMATCH : R/W; bitpos: [16]; default: 0;
* NA
*/
#define I3C_SLV_HDRMATCH (BIT(16))
#define I3C_SLV_HDRMATCH_M (I3C_SLV_HDRMATCH_V << I3C_SLV_HDRMATCH_S)
#define I3C_SLV_HDRMATCH_V 0x00000001U
#define I3C_SLV_HDRMATCH_S 16
/** I3C_SLV_CTRL_REG register
* NA
*/
#define I3C_SLV_CTRL_REG (DR_REG_I3C_SLV_BASE + 0xc)
/** I3C_SLV_SLV_EVENT : R/W; bitpos: [1:0]; default: 0;
* If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will
* show the status as it progresses. Once completed, the field will automatically
* return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal
* mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1:
* start an IBI. This will try to push through an IBI on the bus. If data associate
* with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is
* enabled, this will include anytime control related bytes further, the IBIDATA byte
* will have bit7 set to 1.
*/
#define I3C_SLV_SLV_EVENT 0x00000003U
#define I3C_SLV_SLV_EVENT_M (I3C_SLV_SLV_EVENT_V << I3C_SLV_SLV_EVENT_S)
#define I3C_SLV_SLV_EVENT_V 0x00000003U
#define I3C_SLV_SLV_EVENT_S 0
/** I3C_SLV_EXTDATA : R/W; bitpos: [3]; default: 0;
* reserved
*/
#define I3C_SLV_EXTDATA (BIT(3))
#define I3C_SLV_EXTDATA_M (I3C_SLV_EXTDATA_V << I3C_SLV_EXTDATA_S)
#define I3C_SLV_EXTDATA_V 0x00000001U
#define I3C_SLV_EXTDATA_S 3
/** I3C_SLV_MAPIDX : R/W; bitpos: [7:4]; default: 0;
* Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic
* Address, or can be any valid index.
*/
#define I3C_SLV_MAPIDX 0x0000000FU
#define I3C_SLV_MAPIDX_M (I3C_SLV_MAPIDX_V << I3C_SLV_MAPIDX_S)
#define I3C_SLV_MAPIDX_V 0x0000000FU
#define I3C_SLV_MAPIDX_S 4
/** I3C_SLV_IBIDATA : R/W; bitpos: [15:8]; default: 0;
* Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is
* required.
*/
#define I3C_SLV_IBIDATA 0x000000FFU
#define I3C_SLV_IBIDATA_M (I3C_SLV_IBIDATA_V << I3C_SLV_IBIDATA_S)
#define I3C_SLV_IBIDATA_V 0x000000FFU
#define I3C_SLV_IBIDATA_S 8
/** I3C_SLV_PENDINT : R/W; bitpos: [19:16]; default: 0;
* Should be set to the pending interrupt that GETSTATUS CCC will return. This should
* be maintained by the application if used and configured, as the Master will read
* this. If not configured, the GETSTATUS field will return 1 if an IBI is pending,
* and 0 otherwise.
*/
#define I3C_SLV_PENDINT 0x0000000FU
#define I3C_SLV_PENDINT_M (I3C_SLV_PENDINT_V << I3C_SLV_PENDINT_S)
#define I3C_SLV_PENDINT_V 0x0000000FU
#define I3C_SLV_PENDINT_S 16
/** I3C_SLV_ACTSTATE : R/W; bitpos: [21:20]; default: 0;
* NA
*/
#define I3C_SLV_ACTSTATE 0x00000003U
#define I3C_SLV_ACTSTATE_M (I3C_SLV_ACTSTATE_V << I3C_SLV_ACTSTATE_S)
#define I3C_SLV_ACTSTATE_V 0x00000003U
#define I3C_SLV_ACTSTATE_S 20
/** I3C_SLV_VENDINFO : R/W; bitpos: [31:24]; default: 0;
* NA
*/
#define I3C_SLV_VENDINFO 0x000000FFU
#define I3C_SLV_VENDINFO_M (I3C_SLV_VENDINFO_V << I3C_SLV_VENDINFO_S)
#define I3C_SLV_VENDINFO_V 0x000000FFU
#define I3C_SLV_VENDINFO_S 24
/** I3C_SLV_INTSET_REG register
* INSET allows setting enables for interrupts(connecting the corresponding STATUS
* source to causing an IRQ to the processor)
*/
#define I3C_SLV_INTSET_REG (DR_REG_I3C_SLV_BASE + 0x10)
/** I3C_SLV_STOP_ENA : R/W; bitpos: [10]; default: 0;
* Interrupt on STOP state on the bus. See Start as the preferred interrupt when
* needed. This interrupt may not trigger for quick STOP/START combination, as it
* relates to the state of being stopped.
*/
#define I3C_SLV_STOP_ENA (BIT(10))
#define I3C_SLV_STOP_ENA_M (I3C_SLV_STOP_ENA_V << I3C_SLV_STOP_ENA_S)
#define I3C_SLV_STOP_ENA_V 0x00000001U
#define I3C_SLV_STOP_ENA_S 10
/** I3C_SLV_RXPEND_ENA : R/W; bitpos: [11]; default: 0;
* Interrupt when receiving a message from Master, which is not being handled by the
* block (excludes CCCs being handled automatically). If FIFO, then RX fullness
* trigger. If DMA, then message end.
*/
#define I3C_SLV_RXPEND_ENA (BIT(11))
#define I3C_SLV_RXPEND_ENA_M (I3C_SLV_RXPEND_ENA_V << I3C_SLV_RXPEND_ENA_S)
#define I3C_SLV_RXPEND_ENA_V 0x00000001U
#define I3C_SLV_RXPEND_ENA_S 11
/** I3C_SLV_TXSEND_ENA : R/W; bitpos: [12]; default: 0;
* NA
*/
#define I3C_SLV_TXSEND_ENA (BIT(12))
#define I3C_SLV_TXSEND_ENA_M (I3C_SLV_TXSEND_ENA_V << I3C_SLV_TXSEND_ENA_S)
#define I3C_SLV_TXSEND_ENA_V 0x00000001U
#define I3C_SLV_TXSEND_ENA_S 12
/** I3C_SLV_INTCLR_REG register
* NA
*/
#define I3C_SLV_INTCLR_REG (DR_REG_I3C_SLV_BASE + 0x14)
/** I3C_SLV_STOP_CLR : WO; bitpos: [10]; default: 0;
* Interrupt on STOP state on the bus. See Start as the preferred interrupt when
* needed. This interrupt may not trigger for quick STOP/START combination, as it
* relates to the state of being stopped.
*/
#define I3C_SLV_STOP_CLR (BIT(10))
#define I3C_SLV_STOP_CLR_M (I3C_SLV_STOP_CLR_V << I3C_SLV_STOP_CLR_S)
#define I3C_SLV_STOP_CLR_V 0x00000001U
#define I3C_SLV_STOP_CLR_S 10
/** I3C_SLV_RXPEND_CLR : WO; bitpos: [11]; default: 0;
* Interrupt when receiving a message from Master, which is not being handled by the
* block (excludes CCCs being handled automatically). If FIFO, then RX fullness
* trigger. If DMA, then message end.
*/
#define I3C_SLV_RXPEND_CLR (BIT(11))
#define I3C_SLV_RXPEND_CLR_M (I3C_SLV_RXPEND_CLR_V << I3C_SLV_RXPEND_CLR_S)
#define I3C_SLV_RXPEND_CLR_V 0x00000001U
#define I3C_SLV_RXPEND_CLR_S 11
/** I3C_SLV_TXSEND_CLR : WO; bitpos: [12]; default: 0;
* NA
*/
#define I3C_SLV_TXSEND_CLR (BIT(12))
#define I3C_SLV_TXSEND_CLR_M (I3C_SLV_TXSEND_CLR_V << I3C_SLV_TXSEND_CLR_S)
#define I3C_SLV_TXSEND_CLR_V 0x00000001U
#define I3C_SLV_TXSEND_CLR_S 12
/** I3C_SLV_INTMASKED_REG register
* NA
*/
#define I3C_SLV_INTMASKED_REG (DR_REG_I3C_SLV_BASE + 0x18)
/** I3C_SLV_STOP_MASK : RO; bitpos: [10]; default: 0;
* Interrupt on STOP state on the bus. See Start as the preferred interrupt when
* needed. This interrupt may not trigger for quick STOP/START combination, as it
* relates to the state of being stopped.
*/
#define I3C_SLV_STOP_MASK (BIT(10))
#define I3C_SLV_STOP_MASK_M (I3C_SLV_STOP_MASK_V << I3C_SLV_STOP_MASK_S)
#define I3C_SLV_STOP_MASK_V 0x00000001U
#define I3C_SLV_STOP_MASK_S 10
/** I3C_SLV_RXPEND_MASK : RO; bitpos: [11]; default: 0;
* Interrupt when receiving a message from Master, which is not being handled by the
* block (excludes CCCs being handled automatically). If FIFO, then RX fullness
* trigger. If DMA, then message end.
*/
#define I3C_SLV_RXPEND_MASK (BIT(11))
#define I3C_SLV_RXPEND_MASK_M (I3C_SLV_RXPEND_MASK_V << I3C_SLV_RXPEND_MASK_S)
#define I3C_SLV_RXPEND_MASK_V 0x00000001U
#define I3C_SLV_RXPEND_MASK_S 11
/** I3C_SLV_TXSEND_MASK : RO; bitpos: [12]; default: 0;
* NA
*/
#define I3C_SLV_TXSEND_MASK (BIT(12))
#define I3C_SLV_TXSEND_MASK_M (I3C_SLV_TXSEND_MASK_V << I3C_SLV_TXSEND_MASK_S)
#define I3C_SLV_TXSEND_MASK_V 0x00000001U
#define I3C_SLV_TXSEND_MASK_S 12
/** I3C_SLV_DATACTRL_REG register
* NA
*/
#define I3C_SLV_DATACTRL_REG (DR_REG_I3C_SLV_BASE + 0x2c)
/** I3C_SLV_FLUSHTB : WO; bitpos: [0]; default: 0;
* Flushes the from-bus buffer/FIFO. Not normally used
*/
#define I3C_SLV_FLUSHTB (BIT(0))
#define I3C_SLV_FLUSHTB_M (I3C_SLV_FLUSHTB_V << I3C_SLV_FLUSHTB_S)
#define I3C_SLV_FLUSHTB_V 0x00000001U
#define I3C_SLV_FLUSHTB_S 0
/** I3C_SLV_FLUSHFB : WO; bitpos: [1]; default: 0;
* Flushes the to-bus buffer/FIFO. Used when Master terminates a to-bus (read) message
* prematurely
*/
#define I3C_SLV_FLUSHFB (BIT(1))
#define I3C_SLV_FLUSHFB_M (I3C_SLV_FLUSHFB_V << I3C_SLV_FLUSHFB_S)
#define I3C_SLV_FLUSHFB_V 0x00000001U
#define I3C_SLV_FLUSHFB_S 1
/** I3C_SLV_UNLOCK : WO; bitpos: [3]; default: 0;
* If this bit is not written 1, the register bits from 7 to 4 are not changed on
* write.
*/
#define I3C_SLV_UNLOCK (BIT(3))
#define I3C_SLV_UNLOCK_M (I3C_SLV_UNLOCK_V << I3C_SLV_UNLOCK_S)
#define I3C_SLV_UNLOCK_V 0x00000001U
#define I3C_SLV_UNLOCK_S 3
/** I3C_SLV_TXTRIG : R/W; bitpos: [5:4]; default: 3;
* Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled).
* The defaults is 3
*/
#define I3C_SLV_TXTRIG 0x00000003U
#define I3C_SLV_TXTRIG_M (I3C_SLV_TXTRIG_V << I3C_SLV_TXTRIG_S)
#define I3C_SLV_TXTRIG_V 0x00000003U
#define I3C_SLV_TXTRIG_S 4
/** I3C_SLV_RXTRIG : R/W; bitpos: [7:6]; default: 2;
* Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled).
* The defaults is 3
*/
#define I3C_SLV_RXTRIG 0x00000003U
#define I3C_SLV_RXTRIG_M (I3C_SLV_RXTRIG_V << I3C_SLV_RXTRIG_S)
#define I3C_SLV_RXTRIG_V 0x00000003U
#define I3C_SLV_RXTRIG_S 6
/** I3C_SLV_TXCOUNT : RO; bitpos: [20:16]; default: 0;
* NA
*/
#define I3C_SLV_TXCOUNT 0x0000001FU
#define I3C_SLV_TXCOUNT_M (I3C_SLV_TXCOUNT_V << I3C_SLV_TXCOUNT_S)
#define I3C_SLV_TXCOUNT_V 0x0000001FU
#define I3C_SLV_TXCOUNT_S 16
/** I3C_SLV_RXCOUNT : RO; bitpos: [28:24]; default: 0;
* NA
*/
#define I3C_SLV_RXCOUNT 0x0000001FU
#define I3C_SLV_RXCOUNT_M (I3C_SLV_RXCOUNT_V << I3C_SLV_RXCOUNT_S)
#define I3C_SLV_RXCOUNT_V 0x0000001FU
#define I3C_SLV_RXCOUNT_S 24
/** I3C_SLV_TXFULL : RO; bitpos: [30]; default: 0;
* NA
*/
#define I3C_SLV_TXFULL (BIT(30))
#define I3C_SLV_TXFULL_M (I3C_SLV_TXFULL_V << I3C_SLV_TXFULL_S)
#define I3C_SLV_TXFULL_V 0x00000001U
#define I3C_SLV_TXFULL_S 30
/** I3C_SLV_RXEMPTY : RO; bitpos: [31]; default: 0;
* NA
*/
#define I3C_SLV_RXEMPTY (BIT(31))
#define I3C_SLV_RXEMPTY_M (I3C_SLV_RXEMPTY_V << I3C_SLV_RXEMPTY_S)
#define I3C_SLV_RXEMPTY_V 0x00000001U
#define I3C_SLV_RXEMPTY_S 31
/** I3C_SLV_WDATAB_REG register
* NA
*/
#define I3C_SLV_WDATAB_REG (DR_REG_I3C_SLV_BASE + 0x30)
/** I3C_SLV_WDATAB : WO; bitpos: [7:0]; default: 0;
* NA
*/
#define I3C_SLV_WDATAB 0x000000FFU
#define I3C_SLV_WDATAB_M (I3C_SLV_WDATAB_V << I3C_SLV_WDATAB_S)
#define I3C_SLV_WDATAB_V 0x000000FFU
#define I3C_SLV_WDATAB_S 0
/** I3C_SLV_WDATA_END : WO; bitpos: [8]; default: 0;
* NA
*/
#define I3C_SLV_WDATA_END (BIT(8))
#define I3C_SLV_WDATA_END_M (I3C_SLV_WDATA_END_V << I3C_SLV_WDATA_END_S)
#define I3C_SLV_WDATA_END_V 0x00000001U
#define I3C_SLV_WDATA_END_S 8
/** I3C_SLV_WDATABE_REG register
* NA
*/
#define I3C_SLV_WDATABE_REG (DR_REG_I3C_SLV_BASE + 0x34)
/** I3C_SLV_WDATABE : WO; bitpos: [7:0]; default: 0;
* NA
*/
#define I3C_SLV_WDATABE 0x000000FFU
#define I3C_SLV_WDATABE_M (I3C_SLV_WDATABE_V << I3C_SLV_WDATABE_S)
#define I3C_SLV_WDATABE_V 0x000000FFU
#define I3C_SLV_WDATABE_S 0
/** I3C_SLV_RDARAB_REG register
* Read Byte Data (from-bus) register
*/
#define I3C_SLV_RDARAB_REG (DR_REG_I3C_SLV_BASE + 0x40)
/** I3C_SLV_DATA0 : RO; bitpos: [7:0]; default: 0;
* This register allows reading a byte from the bus unless external FIFO is used. A
* byte should not be read unless there is data waiting, as indicated by the RXPEND
* bit being set in the STATUS register
*/
#define I3C_SLV_DATA0 0x000000FFU
#define I3C_SLV_DATA0_M (I3C_SLV_DATA0_V << I3C_SLV_DATA0_S)
#define I3C_SLV_DATA0_V 0x000000FFU
#define I3C_SLV_DATA0_S 0
/** I3C_SLV_RDATAH_REG register
* Read Half-word Data (from-bus) register
*/
#define I3C_SLV_RDATAH_REG (DR_REG_I3C_SLV_BASE + 0x48)
/** I3C_SLV_DATA_LSB : RO; bitpos: [7:0]; default: 0;
* NA
*/
#define I3C_SLV_DATA_LSB 0x000000FFU
#define I3C_SLV_DATA_LSB_M (I3C_SLV_DATA_LSB_V << I3C_SLV_DATA_LSB_S)
#define I3C_SLV_DATA_LSB_V 0x000000FFU
#define I3C_SLV_DATA_LSB_S 0
/** I3C_SLV_DATA_MSB : RO; bitpos: [15:8]; default: 0;
* This register allows reading a Half-word (byte pair) from the bus unless external
* FIFO is used. A Half-word should not be read unless there is at least 2 bytes of
* data waiting, as indicated by the RX FIFO level trigger or RXCOUNT available space
* in the DATACTRL register
*/
#define I3C_SLV_DATA_MSB 0x000000FFU
#define I3C_SLV_DATA_MSB_M (I3C_SLV_DATA_MSB_V << I3C_SLV_DATA_MSB_S)
#define I3C_SLV_DATA_MSB_V 0x000000FFU
#define I3C_SLV_DATA_MSB_S 8
/** I3C_SLV_CAPABILITIES2_REG register
* NA
*/
#define I3C_SLV_CAPABILITIES2_REG (DR_REG_I3C_SLV_BASE + 0x5c)
/** I3C_SLV_CAPABLITIES2 : RO; bitpos: [31:0]; default: 256;
* NA
*/
#define I3C_SLV_CAPABLITIES2 0xFFFFFFFFU
#define I3C_SLV_CAPABLITIES2_M (I3C_SLV_CAPABLITIES2_V << I3C_SLV_CAPABLITIES2_S)
#define I3C_SLV_CAPABLITIES2_V 0xFFFFFFFFU
#define I3C_SLV_CAPABLITIES2_S 0
/** I3C_SLV_CAPABILITIES_REG register
* NA
*/
#define I3C_SLV_CAPABILITIES_REG (DR_REG_I3C_SLV_BASE + 0x60)
/** I3C_SLV_CAPABLITIES : RO; bitpos: [31:0]; default: 2081684508;
* NA
*/
#define I3C_SLV_CAPABLITIES 0xFFFFFFFFU
#define I3C_SLV_CAPABLITIES_M (I3C_SLV_CAPABLITIES_V << I3C_SLV_CAPABLITIES_S)
#define I3C_SLV_CAPABLITIES_V 0xFFFFFFFFU
#define I3C_SLV_CAPABLITIES_S 0
/** I3C_SLV_IDPARTNO_REG register
* NA
*/
#define I3C_SLV_IDPARTNO_REG (DR_REG_I3C_SLV_BASE + 0x6c)
/** I3C_SLV_PARTNO : R/W; bitpos: [31:0]; default: 0;
* NA
*/
#define I3C_SLV_PARTNO 0xFFFFFFFFU
#define I3C_SLV_PARTNO_M (I3C_SLV_PARTNO_V << I3C_SLV_PARTNO_S)
#define I3C_SLV_PARTNO_V 0xFFFFFFFFU
#define I3C_SLV_PARTNO_S 0
/** I3C_SLV_IDEXT_REG register
* NA
*/
#define I3C_SLV_IDEXT_REG (DR_REG_I3C_SLV_BASE + 0x70)
/** I3C_SLV_IDEXT : R/W; bitpos: [31:0]; default: 0;
* NA
*/
#define I3C_SLV_IDEXT 0xFFFFFFFFU
#define I3C_SLV_IDEXT_M (I3C_SLV_IDEXT_V << I3C_SLV_IDEXT_S)
#define I3C_SLV_IDEXT_V 0xFFFFFFFFU
#define I3C_SLV_IDEXT_S 0
/** I3C_SLV_VENDORID_REG register
* NA
*/
#define I3C_SLV_VENDORID_REG (DR_REG_I3C_SLV_BASE + 0x74)
/** I3C_SLV_VID : R/W; bitpos: [14:0]; default: 21840;
* NA
*/
#define I3C_SLV_VID 0x00007FFFU
#define I3C_SLV_VID_M (I3C_SLV_VID_V << I3C_SLV_VID_S)
#define I3C_SLV_VID_V 0x00007FFFU
#define I3C_SLV_VID_S 0
#ifdef __cplusplus
}
#endif

550
components/soc/esp32p4/register/hw_ver2/soc/i3c_slv_struct.h Normal file
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@@ -0,0 +1,550 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: I3C_SLV CONFIG REG */
/** Type of config register
* NA
*/
typedef union {
struct {
/** slvena : R/W; bitpos: [0]; default: 1;
* 1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus.
* This should be not set until registers such as PARTNO, IDEXT and the like are set
* 1st -if used- since they impact data to the master
*/
uint32_t slvena:1;
/** nack : R/W; bitpos: [1]; default: 0;
* 1:the slave will NACK all requests to it except CCC broadcast. This should be used
* with caution as the Master may determine the slave is missing if overused.
*/
uint32_t nack:1;
/** matchss : R/W; bitpos: [2]; default: 0;
* 1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This
* allows START and STOP to be used to detect end of a message to /from this slave.
*/
uint32_t matchss:1;
/** s0ignore : R/W; bitpos: [3]; default: 0;
* If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an
* Exit Pattern. This should only be used when the bus will not use HDR.
*/
uint32_t s0ignore:1;
/** ddrok : R/W; bitpos: [4]; default: 0;
* NA
*/
uint32_t ddrok:1;
uint32_t reserved_5:3;
/** idrand : R/W; bitpos: [8]; default: 0;
* NA
*/
uint32_t idrand:1;
/** offline : R/W; bitpos: [9]; default: 0;
* NA
*/
uint32_t offline:1;
uint32_t reserved_10:6;
/** bamatch : R/W; bitpos: [23:16]; default: 47;
* Bus Available condition match value for current ???Slow clock???. This provides the
* count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low
* when the Master is not doing so. The max width , and so max value, is controlled by
* the block. Only if enabled for events such IBI or MR or HJ, and if enabled to
* provide this as a register. With is limited to CLK_SLOW_BITS
*/
uint32_t bamatch:8;
uint32_t reserved_24:1;
/** saddr : R/W; bitpos: [31:25]; default: 0;
* If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled
* to use one and to be provided by SW. Block may provide in HW as well.
*/
uint32_t saddr:7;
};
uint32_t val;
} i3c_slv_config_reg_t;
/** Group: I3C_SLV STATUS REG */
/** Type of status register
* NA
*/
typedef union {
struct {
/** stnotstop : RO; bitpos: [0]; default: 0;
* Is 1 if bus is busy(activity) and 0 when in a STOP condition. Other bits may also
* set when busy. Note that this can also be true from an S0 or S1 error, which waits
* for an Exit Pattern.
*/
uint32_t stnotstop:1;
/** stmsg : RO; bitpos: [1]; default: 0;
* Is 1 if this bus Slave is listening to the bus traffic or responding, If
* STNOSTOP=1, then this will be 0 when a non-matching address seen until next
* respeated START it STOP.
*/
uint32_t stmsg:1;
/** stccch : RO; bitpos: [2]; default: 0;
* Is 1 if a CCC message is being handled automatically.
*/
uint32_t stccch:1;
/** streqrd : RO; bitpos: [3]; default: 0;
* 1 if the req in process is an sdr read from this slave or an IBI is being pushed
* out,
*/
uint32_t streqrd:1;
/** streqwr : RO; bitpos: [4]; default: 0;
* NA
*/
uint32_t streqwr:1;
/** stdaa : RO; bitpos: [5]; default: 0;
* NA
*/
uint32_t stdaa:1;
/** sthdr : RO; bitpos: [6]; default: 0;
* NA
*/
uint32_t sthdr:1;
uint32_t reserved_7:1;
/** start : R/W; bitpos: [8]; default: 0;
* NA
*/
uint32_t start:1;
/** matched : R/W; bitpos: [9]; default: 0;
* NA
*/
uint32_t matched:1;
/** stop : R/W; bitpos: [10]; default: 0;
* NA
*/
uint32_t stop:1;
/** rxpend : RO; bitpos: [11]; default: 0;
* Receiving a message from master,which is not being handled by block(not a CCC
* internally processed). For all but External FIFO, this uses DATACTRL RXTRIG, which
* defaults to not-empty. If DMA is enabled for RX, DMA will be signaled as well. Will
* self-clear if data is read(FIFO and non-FIFO)
*/
uint32_t rxpend:1;
/** txnotfull : RO; bitpos: [12]; default: 0;
* Is 1 when the To-bus buffer/FIFO can accept more data to go out. Defau:1. For all
* but External FIFO, this uses DATACTRL TXTRIG,which defaults to not-full. If DMA is
* enabled for TX, it will also be signaled to provide more.
*/
uint32_t txnotfull:1;
/** dachg : R/W; bitpos: [13]; default: 0;
* The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in
* that state of being valid or none. Actual DA can be seen in the DYNADDR register.
* Note that this will also be used when MAP Auto feature is configured. This will be
* changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main
* DA(0) will indicate if last change was due to Auto MAP.
*/
uint32_t dachg:1;
/** ccc : R/W; bitpos: [14]; default: 0;
* A common -command-code(CCC), not handled by block, has been received. This acts
* differently between: *Broadcasted ones, which will then also correspond with RXPEND
* and the 1st byte will be the CCC(command) . *Direct ones, which may never be
* directed to this device. If it is, then the TXSEND or RXPEND will be triggered
* with this end the RXPEND will contain the command.
*/
uint32_t ccc:1;
/** errwarn : RO; bitpos: [15]; default: 0;
* NA
*/
uint32_t errwarn:1;
/** hdrmatch : R/W; bitpos: [16]; default: 0;
* NA
*/
uint32_t hdrmatch:1;
uint32_t reserved_17:15;
};
uint32_t val;
} i3c_slv_status_reg_t;
/** Group: I3C_SLV CTRL REG */
/** Type of ctrl register
* NA
*/
typedef union {
struct {
/** slv_event : R/W; bitpos: [1:0]; default: 0;
* If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will
* show the status as it progresses. Once completed, the field will automatically
* return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal
* mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1:
* start an IBI. This will try to push through an IBI on the bus. If data associate
* with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is
* enabled, this will include anytime control related bytes further, the IBIDATA byte
* will have bit7 set to 1.
*/
uint32_t slv_event:2;
uint32_t reserved_2:1;
/** extdata : R/W; bitpos: [3]; default: 0;
* reserved
*/
uint32_t extdata:1;
/** mapidx : R/W; bitpos: [7:4]; default: 0;
* Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic
* Address, or can be any valid index.
*/
uint32_t mapidx:4;
/** ibidata : R/W; bitpos: [15:8]; default: 0;
* Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is
* required.
*/
uint32_t ibidata:8;
/** pendint : R/W; bitpos: [19:16]; default: 0;
* Should be set to the pending interrupt that GETSTATUS CCC will return. This should
* be maintained by the application if used and configured, as the Master will read
* this. If not configured, the GETSTATUS field will return 1 if an IBI is pending,
* and 0 otherwise.
*/
uint32_t pendint:4;
/** actstate : R/W; bitpos: [21:20]; default: 0;
* NA
*/
uint32_t actstate:2;
uint32_t reserved_22:2;
/** vendinfo : R/W; bitpos: [31:24]; default: 0;
* NA
*/
uint32_t vendinfo:8;
};
uint32_t val;
} i3c_slv_ctrl_reg_t;
/** Group: I3C_SLV INTSET REG */
/** Type of intset register
* INSET allows setting enables for interrupts(connecting the corresponding STATUS
* source to causing an IRQ to the processor)
*/
typedef union {
struct {
uint32_t reserved_0:10;
/** stop_ena : R/W; bitpos: [10]; default: 0;
* Interrupt on STOP state on the bus. See Start as the preferred interrupt when
* needed. This interrupt may not trigger for quick STOP/START combination, as it
* relates to the state of being stopped.
*/
uint32_t stop_ena:1;
/** rxpend_ena : R/W; bitpos: [11]; default: 0;
* Interrupt when receiving a message from Master, which is not being handled by the
* block (excludes CCCs being handled automatically). If FIFO, then RX fullness
* trigger. If DMA, then message end.
*/
uint32_t rxpend_ena:1;
/** txsend_ena : R/W; bitpos: [12]; default: 0;
* NA
*/
uint32_t txsend_ena:1;
uint32_t reserved_13:19;
};
uint32_t val;
} i3c_slv_intset_reg_t;
/** Group: I3C_SLV INTCLR REG */
/** Type of intclr register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:10;
/** stop_clr : WO; bitpos: [10]; default: 0;
* Interrupt on STOP state on the bus. See Start as the preferred interrupt when
* needed. This interrupt may not trigger for quick STOP/START combination, as it
* relates to the state of being stopped.
*/
uint32_t stop_clr:1;
/** rxpend_clr : WO; bitpos: [11]; default: 0;
* Interrupt when receiving a message from Master, which is not being handled by the
* block (excludes CCCs being handled automatically). If FIFO, then RX fullness
* trigger. If DMA, then message end.
*/
uint32_t rxpend_clr:1;
/** txsend_clr : WO; bitpos: [12]; default: 0;
* NA
*/
uint32_t txsend_clr:1;
uint32_t reserved_13:19;
};
uint32_t val;
} i3c_slv_intclr_reg_t;
/** Group: I3C_SLV INTMASKED REG */
/** Type of intmasked register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:10;
/** stop_mask : RO; bitpos: [10]; default: 0;
* Interrupt on STOP state on the bus. See Start as the preferred interrupt when
* needed. This interrupt may not trigger for quick STOP/START combination, as it
* relates to the state of being stopped.
*/
uint32_t stop_mask:1;
/** rxpend_mask : RO; bitpos: [11]; default: 0;
* Interrupt when receiving a message from Master, which is not being handled by the
* block (excludes CCCs being handled automatically). If FIFO, then RX fullness
* trigger. If DMA, then message end.
*/
uint32_t rxpend_mask:1;
/** txsend_mask : RO; bitpos: [12]; default: 0;
* NA
*/
uint32_t txsend_mask:1;
uint32_t reserved_13:19;
};
uint32_t val;
} i3c_slv_intmasked_reg_t;
/** Group: I3C_SLV DATACTRL REG */
/** Type of datactrl register
* NA
*/
typedef union {
struct {
/** flushtb : WO; bitpos: [0]; default: 0;
* Flushes the from-bus buffer/FIFO. Not normally used
*/
uint32_t flushtb:1;
/** flushfb : WO; bitpos: [1]; default: 0;
* Flushes the to-bus buffer/FIFO. Used when Master terminates a to-bus (read) message
* prematurely
*/
uint32_t flushfb:1;
uint32_t reserved_2:1;
/** unlock : WO; bitpos: [3]; default: 0;
* If this bit is not written 1, the register bits from 7 to 4 are not changed on
* write.
*/
uint32_t unlock:1;
/** txtrig : R/W; bitpos: [5:4]; default: 3;
* Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled).
* The defaults is 3
*/
uint32_t txtrig:2;
/** rxtrig : R/W; bitpos: [7:6]; default: 2;
* Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled).
* The defaults is 3
*/
uint32_t rxtrig:2;
uint32_t reserved_8:8;
/** txcount : RO; bitpos: [20:16]; default: 0;
* NA
*/
uint32_t txcount:5;
uint32_t reserved_21:3;
/** rxcount : RO; bitpos: [28:24]; default: 0;
* NA
*/
uint32_t rxcount:5;
uint32_t reserved_29:1;
/** txfull : RO; bitpos: [30]; default: 0;
* NA
*/
uint32_t txfull:1;
/** rxempty : RO; bitpos: [31]; default: 0;
* NA
*/
uint32_t rxempty:1;
};
uint32_t val;
} i3c_slv_datactrl_reg_t;
/** Group: I3C_SLV WDATAB REG */
/** Type of wdatab register
* NA
*/
typedef union {
struct {
/** wdatab : WO; bitpos: [7:0]; default: 0;
* NA
*/
uint32_t wdatab:8;
/** wdata_end : WO; bitpos: [8]; default: 0;
* NA
*/
uint32_t wdata_end:1;
uint32_t reserved_9:23;
};
uint32_t val;
} i3c_slv_wdatab_reg_t;
/** Group: I3C_SLV WDATABE REG */
/** Type of wdatabe register
* NA
*/
typedef union {
struct {
/** wdatabe : WO; bitpos: [7:0]; default: 0;
* NA
*/
uint32_t wdatabe:8;
uint32_t reserved_8:24;
};
uint32_t val;
} i3c_slv_wdatabe_reg_t;
/** Group: I3C_SLV RDARAB REG */
/** Type of rdarab register
* Read Byte Data (from-bus) register
*/
typedef union {
struct {
/** data0 : RO; bitpos: [7:0]; default: 0;
* This register allows reading a byte from the bus unless external FIFO is used. A
* byte should not be read unless there is data waiting, as indicated by the RXPEND
* bit being set in the STATUS register
*/
uint32_t data0:8;
uint32_t reserved_8:24;
};
uint32_t val;
} i3c_slv_rdarab_reg_t;
/** Group: I3C_SLV RDATAH REG */
/** Type of rdatah register
* Read Half-word Data (from-bus) register
*/
typedef union {
struct {
/** data_lsb : RO; bitpos: [7:0]; default: 0;
* NA
*/
uint32_t data_lsb:8;
/** data_msb : RO; bitpos: [15:8]; default: 0;
* This register allows reading a Half-word (byte pair) from the bus unless external
* FIFO is used. A Half-word should not be read unless there is at least 2 bytes of
* data waiting, as indicated by the RX FIFO level trigger or RXCOUNT available space
* in the DATACTRL register
*/
uint32_t data_msb:8;
uint32_t reserved_16:16;
};
uint32_t val;
} i3c_slv_rdatah_reg_t;
/** Group: I3C_SLV CAPABILITIES2 REG */
/** Type of capabilities2 register
* NA
*/
typedef union {
struct {
/** capablities2 : RO; bitpos: [31:0]; default: 256;
* NA
*/
uint32_t capablities2:32;
};
uint32_t val;
} i3c_slv_capabilities2_reg_t;
/** Group: I3C_SLV CAPABILITIES REG */
/** Type of capabilities register
* NA
*/
typedef union {
struct {
/** capabilities : RO; bitpos: [31:0]; default: 2081684508;
* NA
*/
uint32_t capabilities:32;
};
uint32_t val;
} i3c_slv_capabilities_reg_t;
/** Group: I3C_SLV IDPARTNO REG */
/** Type of idpartno register
* NA
*/
typedef union {
struct {
/** partno : R/W; bitpos: [31:0]; default: 0;
* NA
*/
uint32_t partno:32;
};
uint32_t val;
} i3c_slv_idpartno_reg_t;
/** Group: I3C_SLV IDEXT REG */
/** Type of idext register
* NA
*/
typedef union {
struct {
/** idext : R/W; bitpos: [31:0]; default: 0;
* NA
*/
uint32_t idext:32;
};
uint32_t val;
} i3c_slv_idext_reg_t;
/** Group: I3C_SLV VENDORID REG */
/** Type of vendorid register
* NA
*/
typedef union {
struct {
/** vid : R/W; bitpos: [14:0]; default: 21840;
* NA
*/
uint32_t vid:15;
uint32_t reserved_15:17;
};
uint32_t val;
} i3c_slv_vendorid_reg_t;
typedef struct {
uint32_t reserved_000;
volatile i3c_slv_config_reg_t config;
volatile i3c_slv_status_reg_t status;
volatile i3c_slv_ctrl_reg_t ctrl;
volatile i3c_slv_intset_reg_t intset;
volatile i3c_slv_intclr_reg_t intclr;
volatile i3c_slv_intmasked_reg_t intmasked;
uint32_t reserved_01c[4];
volatile i3c_slv_datactrl_reg_t datactrl;
volatile i3c_slv_wdatab_reg_t wdatab;
volatile i3c_slv_wdatabe_reg_t wdatabe;
uint32_t reserved_038[2];
volatile i3c_slv_rdarab_reg_t rdarab;
uint32_t reserved_044;
volatile i3c_slv_rdatah_reg_t rdatah;
uint32_t reserved_04c[4];
volatile i3c_slv_capabilities2_reg_t capabilities2;
volatile i3c_slv_capabilities_reg_t capabilities;
uint32_t reserved_064[2];
volatile i3c_slv_idpartno_reg_t idpartno;
volatile i3c_slv_idext_reg_t idext;
volatile i3c_slv_vendorid_reg_t vendorid;
} i3c_slv_dev_t;
extern i3c_slv_dev_t I3C_SLV;
#ifndef __cplusplus
_Static_assert(sizeof(i3c_slv_dev_t) == 0x78, "Invalid size of i3c_slv_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

176
components/soc/esp32p4/register/hw_ver2/soc/icm_sys_qos_reg.h Normal file
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@@ -0,0 +1,176 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ICM_AXI_VERID_FILEDS_REG register
* NA
*/
#define ICM_AXI_VERID_FILEDS_REG (DR_REG_ICM_AXI_BASE + 0x0)
/** ICM_AXI_REG_VERID : RO; bitpos: [31:0]; default: 875574314;
* NA
*/
#define ICM_AXI_REG_VERID 0xFFFFFFFFU
#define ICM_AXI_REG_VERID_M (ICM_AXI_REG_VERID_V << ICM_AXI_REG_VERID_S)
#define ICM_AXI_REG_VERID_V 0xFFFFFFFFU
#define ICM_AXI_REG_VERID_S 0
/** ICM_AXI_HW_CFG_REG_REG register
* NA
*/
#define ICM_AXI_HW_CFG_REG_REG (DR_REG_ICM_AXI_BASE + 0x4)
/** ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT : RO; bitpos: [0]; default: 1;
* NA
*/
#define ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT (BIT(0))
#define ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT_M (ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT_V << ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT_S)
#define ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT_V 0x00000001U
#define ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT_S 0
/** ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT : RO; bitpos: [1]; default: 0;
* NA
*/
#define ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT (BIT(1))
#define ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT_M (ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT_V << ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT_S)
#define ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT_V 0x00000001U
#define ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT_S 1
/** ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT : RO; bitpos: [2]; default: 0;
* NA
*/
#define ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT (BIT(2))
#define ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT_M (ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT_V << ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT_S)
#define ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT_V 0x00000001U
#define ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT_S 2
/** ICM_AXI_REG_AXI_HWCFG_LOCK_EN : RO; bitpos: [3]; default: 0;
* NA
*/
#define ICM_AXI_REG_AXI_HWCFG_LOCK_EN (BIT(3))
#define ICM_AXI_REG_AXI_HWCFG_LOCK_EN_M (ICM_AXI_REG_AXI_HWCFG_LOCK_EN_V << ICM_AXI_REG_AXI_HWCFG_LOCK_EN_S)
#define ICM_AXI_REG_AXI_HWCFG_LOCK_EN_V 0x00000001U
#define ICM_AXI_REG_AXI_HWCFG_LOCK_EN_S 3
/** ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN : RO; bitpos: [4]; default: 1;
* NA
*/
#define ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN (BIT(4))
#define ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN_M (ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN_V << ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN_S)
#define ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN_V 0x00000001U
#define ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN_S 4
/** ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE : RO; bitpos: [5]; default: 0;
* NA
*/
#define ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE (BIT(5))
#define ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE_M (ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE_V << ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE_S)
#define ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE_V 0x00000001U
#define ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE_S 5
/** ICM_AXI_REG_AXI_HWCFG_REMAP_EN : RO; bitpos: [6]; default: 1;
* NA
*/
#define ICM_AXI_REG_AXI_HWCFG_REMAP_EN (BIT(6))
#define ICM_AXI_REG_AXI_HWCFG_REMAP_EN_M (ICM_AXI_REG_AXI_HWCFG_REMAP_EN_V << ICM_AXI_REG_AXI_HWCFG_REMAP_EN_S)
#define ICM_AXI_REG_AXI_HWCFG_REMAP_EN_V 0x00000001U
#define ICM_AXI_REG_AXI_HWCFG_REMAP_EN_S 6
/** ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN : RO; bitpos: [7]; default: 0;
* NA
*/
#define ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN (BIT(7))
#define ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN_M (ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN_V << ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN_S)
#define ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN_V 0x00000001U
#define ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN_S 7
/** ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN : RO; bitpos: [8]; default: 1;
* NA
*/
#define ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN (BIT(8))
#define ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN_M (ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN_V << ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN_S)
#define ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN_V 0x00000001U
#define ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN_S 8
/** ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS : RO; bitpos: [16:12]; default: 13;
* NA
*/
#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS 0x0000001FU
#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS_M (ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS_V << ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS_S)
#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS_V 0x0000001FU
#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS_S 12
/** ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES : RO; bitpos: [24:20]; default: 7;
* NA
*/
#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES 0x0000001FU
#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES_M (ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES_V << ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES_S)
#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES_V 0x0000001FU
#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES_S 20
/** ICM_AXI_CMD_REG register
* NA
*/
#define ICM_AXI_CMD_REG (DR_REG_ICM_AXI_BASE + 0x8)
/** ICM_AXI_REG_AXI_CMD : R/W; bitpos: [2:0]; default: 0;
* NA
*/
#define ICM_AXI_REG_AXI_CMD 0x00000007U
#define ICM_AXI_REG_AXI_CMD_M (ICM_AXI_REG_AXI_CMD_V << ICM_AXI_REG_AXI_CMD_S)
#define ICM_AXI_REG_AXI_CMD_V 0x00000007U
#define ICM_AXI_REG_AXI_CMD_S 0
/** ICM_AXI_REG_RD_WR_CHAN : R/W; bitpos: [7]; default: 0;
* NA
*/
#define ICM_AXI_REG_RD_WR_CHAN (BIT(7))
#define ICM_AXI_REG_RD_WR_CHAN_M (ICM_AXI_REG_RD_WR_CHAN_V << ICM_AXI_REG_RD_WR_CHAN_S)
#define ICM_AXI_REG_RD_WR_CHAN_V 0x00000001U
#define ICM_AXI_REG_RD_WR_CHAN_S 7
/** ICM_AXI_REG_AXI_MASTER_PORT : R/W; bitpos: [11:8]; default: 0;
* NA
*/
#define ICM_AXI_REG_AXI_MASTER_PORT 0x0000000FU
#define ICM_AXI_REG_AXI_MASTER_PORT_M (ICM_AXI_REG_AXI_MASTER_PORT_V << ICM_AXI_REG_AXI_MASTER_PORT_S)
#define ICM_AXI_REG_AXI_MASTER_PORT_V 0x0000000FU
#define ICM_AXI_REG_AXI_MASTER_PORT_S 8
/** ICM_AXI_REG_AXI_ERR_BIT : RO; bitpos: [28]; default: 0;
* NA
*/
#define ICM_AXI_REG_AXI_ERR_BIT (BIT(28))
#define ICM_AXI_REG_AXI_ERR_BIT_M (ICM_AXI_REG_AXI_ERR_BIT_V << ICM_AXI_REG_AXI_ERR_BIT_S)
#define ICM_AXI_REG_AXI_ERR_BIT_V 0x00000001U
#define ICM_AXI_REG_AXI_ERR_BIT_S 28
/** ICM_AXI_REG_AXI_SOFT_RESET_BIT : R/W; bitpos: [29]; default: 0;
* NA
*/
#define ICM_AXI_REG_AXI_SOFT_RESET_BIT (BIT(29))
#define ICM_AXI_REG_AXI_SOFT_RESET_BIT_M (ICM_AXI_REG_AXI_SOFT_RESET_BIT_V << ICM_AXI_REG_AXI_SOFT_RESET_BIT_S)
#define ICM_AXI_REG_AXI_SOFT_RESET_BIT_V 0x00000001U
#define ICM_AXI_REG_AXI_SOFT_RESET_BIT_S 29
/** ICM_AXI_REG_AXI_RD_WR_CMD : R/W; bitpos: [30]; default: 0;
* NA
*/
#define ICM_AXI_REG_AXI_RD_WR_CMD (BIT(30))
#define ICM_AXI_REG_AXI_RD_WR_CMD_M (ICM_AXI_REG_AXI_RD_WR_CMD_V << ICM_AXI_REG_AXI_RD_WR_CMD_S)
#define ICM_AXI_REG_AXI_RD_WR_CMD_V 0x00000001U
#define ICM_AXI_REG_AXI_RD_WR_CMD_S 30
/** ICM_AXI_REG_AXI_CMD_EN : R/W; bitpos: [31]; default: 0;
* NA
*/
#define ICM_AXI_REG_AXI_CMD_EN (BIT(31))
#define ICM_AXI_REG_AXI_CMD_EN_M (ICM_AXI_REG_AXI_CMD_EN_V << ICM_AXI_REG_AXI_CMD_EN_S)
#define ICM_AXI_REG_AXI_CMD_EN_V 0x00000001U
#define ICM_AXI_REG_AXI_CMD_EN_S 31
/** ICM_AXI_DATA_REG register
* NA
*/
#define ICM_AXI_DATA_REG (DR_REG_ICM_AXI_BASE + 0xc)
/** ICM_AXI_REG_DATA : R/W; bitpos: [31:0]; default: 0;
* NA
*/
#define ICM_AXI_REG_DATA 0xFFFFFFFFU
#define ICM_AXI_REG_DATA_M (ICM_AXI_REG_DATA_V << ICM_AXI_REG_DATA_S)
#define ICM_AXI_REG_DATA_V 0xFFFFFFFFU
#define ICM_AXI_REG_DATA_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/register/hw_ver2/soc/icm_sys_qos_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: ICM AXI VERID FIELDS REG */
/** Type of verid_fileds register
* NA
*/
typedef union {
struct {
/** reg_verid : RO; bitpos: [31:0]; default: 875574314;
* NA
*/
uint32_t reg_verid:32;
};
uint32_t val;
} icm_axi_verid_fileds_reg_t;
/** Group: ICM AXI HW CFG REG REG */
/** Type of hw_cfg_reg register
* NA
*/
typedef union {
struct {
/** reg_axi_hwcfg_qos_support : RO; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_axi_hwcfg_qos_support:1;
/** reg_axi_hwcfg_apb3_support : RO; bitpos: [1]; default: 0;
* NA
*/
uint32_t reg_axi_hwcfg_apb3_support:1;
/** reg_axi_hwcfg_axi4_support : RO; bitpos: [2]; default: 0;
* NA
*/
uint32_t reg_axi_hwcfg_axi4_support:1;
/** reg_axi_hwcfg_lock_en : RO; bitpos: [3]; default: 0;
* NA
*/
uint32_t reg_axi_hwcfg_lock_en:1;
/** reg_axi_hwcfg_trust_zone_en : RO; bitpos: [4]; default: 1;
* NA
*/
uint32_t reg_axi_hwcfg_trust_zone_en:1;
/** reg_axi_hwcfg_decoder_type : RO; bitpos: [5]; default: 0;
* NA
*/
uint32_t reg_axi_hwcfg_decoder_type:1;
/** reg_axi_hwcfg_remap_en : RO; bitpos: [6]; default: 1;
* NA
*/
uint32_t reg_axi_hwcfg_remap_en:1;
/** reg_axi_hwcfg_bi_dir_cmd_en : RO; bitpos: [7]; default: 0;
* NA
*/
uint32_t reg_axi_hwcfg_bi_dir_cmd_en:1;
/** reg_axi_hwcfg_low_power_inf_en : RO; bitpos: [8]; default: 1;
* NA
*/
uint32_t reg_axi_hwcfg_low_power_inf_en:1;
uint32_t reserved_9:3;
/** reg_axi_hwcfg_axi_num_masters : RO; bitpos: [16:12]; default: 13;
* NA
*/
uint32_t reg_axi_hwcfg_axi_num_masters:5;
uint32_t reserved_17:3;
/** reg_axi_hwcfg_axi_num_slaves : RO; bitpos: [24:20]; default: 7;
* NA
*/
uint32_t reg_axi_hwcfg_axi_num_slaves:5;
uint32_t reserved_25:7;
};
uint32_t val;
} icm_axi_hw_cfg_reg_reg_t;
/** Group: ICM AXI CMD REG */
/** Type of cmd register
* NA
*/
typedef union {
struct {
/** reg_axi_cmd : R/W; bitpos: [2:0]; default: 0;
* NA
*/
uint32_t reg_axi_cmd:3;
uint32_t reserved_3:4;
/** reg_rd_wr_chan : R/W; bitpos: [7]; default: 0;
* NA
*/
uint32_t reg_rd_wr_chan:1;
/** reg_axi_master_port : R/W; bitpos: [11:8]; default: 0;
* NA
*/
uint32_t reg_axi_master_port:4;
uint32_t reserved_12:16;
/** reg_axi_err_bit : RO; bitpos: [28]; default: 0;
* NA
*/
uint32_t reg_axi_err_bit:1;
/** reg_axi_soft_reset_bit : R/W; bitpos: [29]; default: 0;
* NA
*/
uint32_t reg_axi_soft_reset_bit:1;
/** reg_axi_rd_wr_cmd : R/W; bitpos: [30]; default: 0;
* NA
*/
uint32_t reg_axi_rd_wr_cmd:1;
/** reg_axi_cmd_en : R/W; bitpos: [31]; default: 0;
* NA
*/
uint32_t reg_axi_cmd_en:1;
};
uint32_t val;
} icm_axi_cmd_reg_t;
/** Group: ICM AXI DATA REG */
/** Type of data register
* NA
*/
typedef union {
struct {
/** reg_data : R/W; bitpos: [31:0]; default: 0;
* NA
*/
uint32_t reg_data:32;
};
uint32_t val;
} icm_axi_data_reg_t;
typedef struct {
volatile icm_axi_verid_fileds_reg_t verid_fileds;
volatile icm_axi_hw_cfg_reg_reg_t hw_cfg_reg;
volatile icm_axi_cmd_reg_t cmd;
volatile icm_axi_data_reg_t data;
} icm_axi_dev_t;
extern icm_axi_dev_t ICM_SYS;
#ifndef __cplusplus
_Static_assert(sizeof(icm_axi_dev_t) == 0x10, "Invalid size of icm_axi_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ICM_VER_DATE_REG register
* NA
*/
#define ICM_VER_DATE_REG (DR_REG_ICM_BASE + 0x0)
/** ICM_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539165204;
* NA
*/
#define ICM_REG_VER_DATE 0xFFFFFFFFU
#define ICM_REG_VER_DATE_M (ICM_REG_VER_DATE_V << ICM_REG_VER_DATE_S)
#define ICM_REG_VER_DATE_V 0xFFFFFFFFU
#define ICM_REG_VER_DATE_S 0
/** ICM_CLK_EN_REG register
* NA
*/
#define ICM_CLK_EN_REG (DR_REG_ICM_BASE + 0x4)
/** ICM_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
* NA
*/
#define ICM_REG_CLK_EN (BIT(0))
#define ICM_REG_CLK_EN_M (ICM_REG_CLK_EN_V << ICM_REG_CLK_EN_S)
#define ICM_REG_CLK_EN_V 0x00000001U
#define ICM_REG_CLK_EN_S 0
/** ICM_DLOCK_STATUS_REG register
* NA
*/
#define ICM_DLOCK_STATUS_REG (DR_REG_ICM_BASE + 0x8)
/** ICM_REG_DLOCK_MST : RO; bitpos: [3:0]; default: 0;
* Lowest numbered deadlocked master
*/
#define ICM_REG_DLOCK_MST 0x0000000FU
#define ICM_REG_DLOCK_MST_M (ICM_REG_DLOCK_MST_V << ICM_REG_DLOCK_MST_S)
#define ICM_REG_DLOCK_MST_V 0x0000000FU
#define ICM_REG_DLOCK_MST_S 0
/** ICM_REG_DLOCK_SLV : RO; bitpos: [6:4]; default: 0;
* Slave with which dlock_mst is deadlocked
*/
#define ICM_REG_DLOCK_SLV 0x00000007U
#define ICM_REG_DLOCK_SLV_M (ICM_REG_DLOCK_SLV_V << ICM_REG_DLOCK_SLV_S)
#define ICM_REG_DLOCK_SLV_V 0x00000007U
#define ICM_REG_DLOCK_SLV_S 4
/** ICM_REG_DLOCK_ID : RO; bitpos: [10:7]; default: 0;
* AXI ID of deadlocked transaction
*/
#define ICM_REG_DLOCK_ID 0x0000000FU
#define ICM_REG_DLOCK_ID_M (ICM_REG_DLOCK_ID_V << ICM_REG_DLOCK_ID_S)
#define ICM_REG_DLOCK_ID_V 0x0000000FU
#define ICM_REG_DLOCK_ID_S 7
/** ICM_REG_DLOCK_WR : RO; bitpos: [11]; default: 0;
* Asserted if deadlocked transaction is a write
*/
#define ICM_REG_DLOCK_WR (BIT(11))
#define ICM_REG_DLOCK_WR_M (ICM_REG_DLOCK_WR_V << ICM_REG_DLOCK_WR_S)
#define ICM_REG_DLOCK_WR_V 0x00000001U
#define ICM_REG_DLOCK_WR_S 11
/** ICM_INT_RAW_REG register
* NA
*/
#define ICM_INT_RAW_REG (DR_REG_ICM_BASE + 0xc)
/** ICM_REG_DLOCK_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* NA
*/
#define ICM_REG_DLOCK_INT_RAW (BIT(0))
#define ICM_REG_DLOCK_INT_RAW_M (ICM_REG_DLOCK_INT_RAW_V << ICM_REG_DLOCK_INT_RAW_S)
#define ICM_REG_DLOCK_INT_RAW_V 0x00000001U
#define ICM_REG_DLOCK_INT_RAW_S 0
/** ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* NA
*/
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW (BIT(1))
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_M (ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_V << ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_S)
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_V 0x00000001U
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_S 1
/** ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* NA
*/
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW (BIT(2))
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_M (ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_V << ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_S)
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_V 0x00000001U
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_S 2
/** ICM_INT_ST_REG register
* NA
*/
#define ICM_INT_ST_REG (DR_REG_ICM_BASE + 0x10)
/** ICM_REG_DLOCK_INT_ST : RO; bitpos: [0]; default: 0;
* NA
*/
#define ICM_REG_DLOCK_INT_ST (BIT(0))
#define ICM_REG_DLOCK_INT_ST_M (ICM_REG_DLOCK_INT_ST_V << ICM_REG_DLOCK_INT_ST_S)
#define ICM_REG_DLOCK_INT_ST_V 0x00000001U
#define ICM_REG_DLOCK_INT_ST_S 0
/** ICM_REG_ICM_SYS_ADDRHOLE_INT_ST : RO; bitpos: [1]; default: 0;
* NA
*/
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ST (BIT(1))
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_M (ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_V << ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_S)
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_V 0x00000001U
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_S 1
/** ICM_REG_ICM_CPU_ADDRHOLE_INT_ST : RO; bitpos: [2]; default: 0;
* NA
*/
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ST (BIT(2))
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_M (ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_V << ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_S)
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_V 0x00000001U
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_S 2
/** ICM_INT_ENA_REG register
* NA
*/
#define ICM_INT_ENA_REG (DR_REG_ICM_BASE + 0x14)
/** ICM_REG_DLOCK_INT_ENA : R/W; bitpos: [0]; default: 1;
* NA
*/
#define ICM_REG_DLOCK_INT_ENA (BIT(0))
#define ICM_REG_DLOCK_INT_ENA_M (ICM_REG_DLOCK_INT_ENA_V << ICM_REG_DLOCK_INT_ENA_S)
#define ICM_REG_DLOCK_INT_ENA_V 0x00000001U
#define ICM_REG_DLOCK_INT_ENA_S 0
/** ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA : R/W; bitpos: [1]; default: 1;
* NA
*/
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA (BIT(1))
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_M (ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_V << ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_S)
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_V 0x00000001U
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_S 1
/** ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA : R/W; bitpos: [2]; default: 1;
* NA
*/
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA (BIT(2))
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_M (ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_V << ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_S)
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_V 0x00000001U
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_S 2
/** ICM_INT_CLR_REG register
* NA
*/
#define ICM_INT_CLR_REG (DR_REG_ICM_BASE + 0x18)
/** ICM_REG_DLOCK_INT_CLR : WT; bitpos: [0]; default: 0;
* NA
*/
#define ICM_REG_DLOCK_INT_CLR (BIT(0))
#define ICM_REG_DLOCK_INT_CLR_M (ICM_REG_DLOCK_INT_CLR_V << ICM_REG_DLOCK_INT_CLR_S)
#define ICM_REG_DLOCK_INT_CLR_V 0x00000001U
#define ICM_REG_DLOCK_INT_CLR_S 0
/** ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR : WT; bitpos: [1]; default: 0;
* NA
*/
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR (BIT(1))
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_M (ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_V << ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_S)
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_V 0x00000001U
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_S 1
/** ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR : WT; bitpos: [2]; default: 0;
* NA
*/
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR (BIT(2))
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_M (ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_V << ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_S)
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_V 0x00000001U
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_S 2
/** ICM_MST_ARB_PRIORITY_REG0_REG register
* NA
*/
#define ICM_MST_ARB_PRIORITY_REG0_REG (DR_REG_ICM_BASE + 0x1c)
/** ICM_REG_CPU_PRIORITY : R/W; bitpos: [3:0]; default: 0;
* CPU arbitration priority for command channels between masters connected to sys_icm
*/
#define ICM_REG_CPU_PRIORITY 0x0000000FU
#define ICM_REG_CPU_PRIORITY_M (ICM_REG_CPU_PRIORITY_V << ICM_REG_CPU_PRIORITY_S)
#define ICM_REG_CPU_PRIORITY_V 0x0000000FU
#define ICM_REG_CPU_PRIORITY_S 0
/** ICM_REG_CACHE_PRIORITY : R/W; bitpos: [7:4]; default: 0;
* CACHE arbitration priority for command channels between masters connected to sys_icm
*/
#define ICM_REG_CACHE_PRIORITY 0x0000000FU
#define ICM_REG_CACHE_PRIORITY_M (ICM_REG_CACHE_PRIORITY_V << ICM_REG_CACHE_PRIORITY_S)
#define ICM_REG_CACHE_PRIORITY_V 0x0000000FU
#define ICM_REG_CACHE_PRIORITY_S 4
/** ICM_REG_DMA2D_PRIORITY : R/W; bitpos: [11:8]; default: 0;
* GFX arbitration priority for command channels between masters connected to sys_icm
*/
#define ICM_REG_DMA2D_PRIORITY 0x0000000FU
#define ICM_REG_DMA2D_PRIORITY_M (ICM_REG_DMA2D_PRIORITY_V << ICM_REG_DMA2D_PRIORITY_S)
#define ICM_REG_DMA2D_PRIORITY_V 0x0000000FU
#define ICM_REG_DMA2D_PRIORITY_S 8
/** ICM_REG_GDMA_MST1_PRIORITY : R/W; bitpos: [15:12]; default: 0;
* GDMA mst1 arbitration priority for command channels between masters connected to
* sys_icm
*/
#define ICM_REG_GDMA_MST1_PRIORITY 0x0000000FU
#define ICM_REG_GDMA_MST1_PRIORITY_M (ICM_REG_GDMA_MST1_PRIORITY_V << ICM_REG_GDMA_MST1_PRIORITY_S)
#define ICM_REG_GDMA_MST1_PRIORITY_V 0x0000000FU
#define ICM_REG_GDMA_MST1_PRIORITY_S 12
/** ICM_REG_GDMA_MST2_PRIORITY : R/W; bitpos: [19:16]; default: 0;
* GDMA mst2 arbitration priority for command channels between masters connected to
* sys_icm
*/
#define ICM_REG_GDMA_MST2_PRIORITY 0x0000000FU
#define ICM_REG_GDMA_MST2_PRIORITY_M (ICM_REG_GDMA_MST2_PRIORITY_V << ICM_REG_GDMA_MST2_PRIORITY_S)
#define ICM_REG_GDMA_MST2_PRIORITY_V 0x0000000FU
#define ICM_REG_GDMA_MST2_PRIORITY_S 16
/** ICM_REG_H264_M1_PRIORITY : R/W; bitpos: [23:20]; default: 0;
* H264 mst1 arbitration priority for command channels between masters connected to
* sys_icm
*/
#define ICM_REG_H264_M1_PRIORITY 0x0000000FU
#define ICM_REG_H264_M1_PRIORITY_M (ICM_REG_H264_M1_PRIORITY_V << ICM_REG_H264_M1_PRIORITY_S)
#define ICM_REG_H264_M1_PRIORITY_V 0x0000000FU
#define ICM_REG_H264_M1_PRIORITY_S 20
/** ICM_REG_H264_M2_PRIORITY : R/W; bitpos: [27:24]; default: 0;
* H264 mst2 arbitration priority for command channels between masters connected to
* sys_icm
*/
#define ICM_REG_H264_M2_PRIORITY 0x0000000FU
#define ICM_REG_H264_M2_PRIORITY_M (ICM_REG_H264_M2_PRIORITY_V << ICM_REG_H264_M2_PRIORITY_S)
#define ICM_REG_H264_M2_PRIORITY_V 0x0000000FU
#define ICM_REG_H264_M2_PRIORITY_S 24
/** ICM_REG_AXI_PDMA_PRIORITY : R/W; bitpos: [31:28]; default: 0;
* AXI PDMA arbitration priority for command channels between masters connected to
* sys_icm
*/
#define ICM_REG_AXI_PDMA_PRIORITY 0x0000000FU
#define ICM_REG_AXI_PDMA_PRIORITY_M (ICM_REG_AXI_PDMA_PRIORITY_V << ICM_REG_AXI_PDMA_PRIORITY_S)
#define ICM_REG_AXI_PDMA_PRIORITY_V 0x0000000FU
#define ICM_REG_AXI_PDMA_PRIORITY_S 28
/** ICM_SLV_ARB_PRIORITY_REG register
* NA
*/
#define ICM_SLV_ARB_PRIORITY_REG (DR_REG_ICM_BASE + 0x24)
/** ICM_REG_L2MEM_PRIORITY : R/W; bitpos: [5:3]; default: 0;
* L2MEM arbitration priority for response channels between slaves connected to sys_icm
*/
#define ICM_REG_L2MEM_PRIORITY 0x00000007U
#define ICM_REG_L2MEM_PRIORITY_M (ICM_REG_L2MEM_PRIORITY_V << ICM_REG_L2MEM_PRIORITY_S)
#define ICM_REG_L2MEM_PRIORITY_V 0x00000007U
#define ICM_REG_L2MEM_PRIORITY_S 3
/** ICM_REG_FLASH_MSPI_PRIORITY : R/W; bitpos: [14:12]; default: 0;
* FLASH MSPI arbitration priority for response channels between slaves connected to
* sys_icm
*/
#define ICM_REG_FLASH_MSPI_PRIORITY 0x00000007U
#define ICM_REG_FLASH_MSPI_PRIORITY_M (ICM_REG_FLASH_MSPI_PRIORITY_V << ICM_REG_FLASH_MSPI_PRIORITY_S)
#define ICM_REG_FLASH_MSPI_PRIORITY_V 0x00000007U
#define ICM_REG_FLASH_MSPI_PRIORITY_S 12
/** ICM_REG_PSRAM_MSPI_PRIORITY : R/W; bitpos: [17:15]; default: 0;
* PSRAM MSPI arbitration priority for response channels between slaves connected to
* sys_icm
*/
#define ICM_REG_PSRAM_MSPI_PRIORITY 0x00000007U
#define ICM_REG_PSRAM_MSPI_PRIORITY_M (ICM_REG_PSRAM_MSPI_PRIORITY_V << ICM_REG_PSRAM_MSPI_PRIORITY_S)
#define ICM_REG_PSRAM_MSPI_PRIORITY_V 0x00000007U
#define ICM_REG_PSRAM_MSPI_PRIORITY_S 15
/** ICM_REG_LCD_PRIORITY : R/W; bitpos: [20:18]; default: 0;
* MIPI_LCD registers arbitration priority for response channels between slaves
* connected to sys_icm
*/
#define ICM_REG_LCD_PRIORITY 0x00000007U
#define ICM_REG_LCD_PRIORITY_M (ICM_REG_LCD_PRIORITY_V << ICM_REG_LCD_PRIORITY_S)
#define ICM_REG_LCD_PRIORITY_V 0x00000007U
#define ICM_REG_LCD_PRIORITY_S 18
/** ICM_REG_CAM_PRIORITY : R/W; bitpos: [23:21]; default: 0;
* MIPI_CAM registers arbitration priority for response channels between slaves
* connected to sys_icm
*/
#define ICM_REG_CAM_PRIORITY 0x00000007U
#define ICM_REG_CAM_PRIORITY_M (ICM_REG_CAM_PRIORITY_V << ICM_REG_CAM_PRIORITY_S)
#define ICM_REG_CAM_PRIORITY_V 0x00000007U
#define ICM_REG_CAM_PRIORITY_S 21
/** ICM_MST_ARQOS_REG0_REG register
* NA
*/
#define ICM_MST_ARQOS_REG0_REG (DR_REG_ICM_BASE + 0x28)
/** ICM_REG_CPU_ARQOS : R/W; bitpos: [3:0]; default: 0;
* NA
*/
#define ICM_REG_CPU_ARQOS 0x0000000FU
#define ICM_REG_CPU_ARQOS_M (ICM_REG_CPU_ARQOS_V << ICM_REG_CPU_ARQOS_S)
#define ICM_REG_CPU_ARQOS_V 0x0000000FU
#define ICM_REG_CPU_ARQOS_S 0
/** ICM_REG_CACHE_ARQOS : R/W; bitpos: [7:4]; default: 0;
* NA
*/
#define ICM_REG_CACHE_ARQOS 0x0000000FU
#define ICM_REG_CACHE_ARQOS_M (ICM_REG_CACHE_ARQOS_V << ICM_REG_CACHE_ARQOS_S)
#define ICM_REG_CACHE_ARQOS_V 0x0000000FU
#define ICM_REG_CACHE_ARQOS_S 4
/** ICM_REG_DMA2D_ARQOS : R/W; bitpos: [11:8]; default: 0;
* NA
*/
#define ICM_REG_DMA2D_ARQOS 0x0000000FU
#define ICM_REG_DMA2D_ARQOS_M (ICM_REG_DMA2D_ARQOS_V << ICM_REG_DMA2D_ARQOS_S)
#define ICM_REG_DMA2D_ARQOS_V 0x0000000FU
#define ICM_REG_DMA2D_ARQOS_S 8
/** ICM_REG_GDMA_MST1_ARQOS : R/W; bitpos: [15:12]; default: 0;
* NA
*/
#define ICM_REG_GDMA_MST1_ARQOS 0x0000000FU
#define ICM_REG_GDMA_MST1_ARQOS_M (ICM_REG_GDMA_MST1_ARQOS_V << ICM_REG_GDMA_MST1_ARQOS_S)
#define ICM_REG_GDMA_MST1_ARQOS_V 0x0000000FU
#define ICM_REG_GDMA_MST1_ARQOS_S 12
/** ICM_REG_GDMA_MST2_ARQOS : R/W; bitpos: [19:16]; default: 0;
* NA
*/
#define ICM_REG_GDMA_MST2_ARQOS 0x0000000FU
#define ICM_REG_GDMA_MST2_ARQOS_M (ICM_REG_GDMA_MST2_ARQOS_V << ICM_REG_GDMA_MST2_ARQOS_S)
#define ICM_REG_GDMA_MST2_ARQOS_V 0x0000000FU
#define ICM_REG_GDMA_MST2_ARQOS_S 16
/** ICM_REG_H264_DMA2D_M1_ARQOS : R/W; bitpos: [23:20]; default: 0;
* NA
*/
#define ICM_REG_H264_DMA2D_M1_ARQOS 0x0000000FU
#define ICM_REG_H264_DMA2D_M1_ARQOS_M (ICM_REG_H264_DMA2D_M1_ARQOS_V << ICM_REG_H264_DMA2D_M1_ARQOS_S)
#define ICM_REG_H264_DMA2D_M1_ARQOS_V 0x0000000FU
#define ICM_REG_H264_DMA2D_M1_ARQOS_S 20
/** ICM_REG_H264_DMA2D_M2_ARQOS : R/W; bitpos: [27:24]; default: 0;
* NA
*/
#define ICM_REG_H264_DMA2D_M2_ARQOS 0x0000000FU
#define ICM_REG_H264_DMA2D_M2_ARQOS_M (ICM_REG_H264_DMA2D_M2_ARQOS_V << ICM_REG_H264_DMA2D_M2_ARQOS_S)
#define ICM_REG_H264_DMA2D_M2_ARQOS_V 0x0000000FU
#define ICM_REG_H264_DMA2D_M2_ARQOS_S 24
/** ICM_REG_AXI_PDMA_INT_ARQOS : R/W; bitpos: [31:28]; default: 0;
* NA
*/
#define ICM_REG_AXI_PDMA_INT_ARQOS 0x0000000FU
#define ICM_REG_AXI_PDMA_INT_ARQOS_M (ICM_REG_AXI_PDMA_INT_ARQOS_V << ICM_REG_AXI_PDMA_INT_ARQOS_S)
#define ICM_REG_AXI_PDMA_INT_ARQOS_V 0x0000000FU
#define ICM_REG_AXI_PDMA_INT_ARQOS_S 28
/** ICM_MST_AWQOS_REG0_REG register
* NA
*/
#define ICM_MST_AWQOS_REG0_REG (DR_REG_ICM_BASE + 0x30)
/** ICM_REG_CPU_AWQOS : R/W; bitpos: [3:0]; default: 0;
* NA
*/
#define ICM_REG_CPU_AWQOS 0x0000000FU
#define ICM_REG_CPU_AWQOS_M (ICM_REG_CPU_AWQOS_V << ICM_REG_CPU_AWQOS_S)
#define ICM_REG_CPU_AWQOS_V 0x0000000FU
#define ICM_REG_CPU_AWQOS_S 0
/** ICM_REG_CACHE_AWQOS : R/W; bitpos: [7:4]; default: 0;
* NA
*/
#define ICM_REG_CACHE_AWQOS 0x0000000FU
#define ICM_REG_CACHE_AWQOS_M (ICM_REG_CACHE_AWQOS_V << ICM_REG_CACHE_AWQOS_S)
#define ICM_REG_CACHE_AWQOS_V 0x0000000FU
#define ICM_REG_CACHE_AWQOS_S 4
/** ICM_REG_DMA2D_AWQOS : R/W; bitpos: [11:8]; default: 0;
* NA
*/
#define ICM_REG_DMA2D_AWQOS 0x0000000FU
#define ICM_REG_DMA2D_AWQOS_M (ICM_REG_DMA2D_AWQOS_V << ICM_REG_DMA2D_AWQOS_S)
#define ICM_REG_DMA2D_AWQOS_V 0x0000000FU
#define ICM_REG_DMA2D_AWQOS_S 8
/** ICM_REG_GDMA_MST1_AWQOS : R/W; bitpos: [15:12]; default: 0;
* NA
*/
#define ICM_REG_GDMA_MST1_AWQOS 0x0000000FU
#define ICM_REG_GDMA_MST1_AWQOS_M (ICM_REG_GDMA_MST1_AWQOS_V << ICM_REG_GDMA_MST1_AWQOS_S)
#define ICM_REG_GDMA_MST1_AWQOS_V 0x0000000FU
#define ICM_REG_GDMA_MST1_AWQOS_S 12
/** ICM_REG_GDMA_MST2_AWQOS : R/W; bitpos: [19:16]; default: 0;
* NA
*/
#define ICM_REG_GDMA_MST2_AWQOS 0x0000000FU
#define ICM_REG_GDMA_MST2_AWQOS_M (ICM_REG_GDMA_MST2_AWQOS_V << ICM_REG_GDMA_MST2_AWQOS_S)
#define ICM_REG_GDMA_MST2_AWQOS_V 0x0000000FU
#define ICM_REG_GDMA_MST2_AWQOS_S 16
/** ICM_REG_H264_DMA2D_M1_AWQOS : R/W; bitpos: [23:20]; default: 0;
* NA
*/
#define ICM_REG_H264_DMA2D_M1_AWQOS 0x0000000FU
#define ICM_REG_H264_DMA2D_M1_AWQOS_M (ICM_REG_H264_DMA2D_M1_AWQOS_V << ICM_REG_H264_DMA2D_M1_AWQOS_S)
#define ICM_REG_H264_DMA2D_M1_AWQOS_V 0x0000000FU
#define ICM_REG_H264_DMA2D_M1_AWQOS_S 20
/** ICM_REG_H264_DMA2D_M2_AWQOS : R/W; bitpos: [27:24]; default: 0;
* NA
*/
#define ICM_REG_H264_DMA2D_M2_AWQOS 0x0000000FU
#define ICM_REG_H264_DMA2D_M2_AWQOS_M (ICM_REG_H264_DMA2D_M2_AWQOS_V << ICM_REG_H264_DMA2D_M2_AWQOS_S)
#define ICM_REG_H264_DMA2D_M2_AWQOS_V 0x0000000FU
#define ICM_REG_H264_DMA2D_M2_AWQOS_S 24
/** ICM_REG_PDMA_INT_AWQOS : R/W; bitpos: [31:28]; default: 0;
* NA
*/
#define ICM_REG_PDMA_INT_AWQOS 0x0000000FU
#define ICM_REG_PDMA_INT_AWQOS_M (ICM_REG_PDMA_INT_AWQOS_V << ICM_REG_PDMA_INT_AWQOS_S)
#define ICM_REG_PDMA_INT_AWQOS_V 0x0000000FU
#define ICM_REG_PDMA_INT_AWQOS_S 28
/** ICM_SYS_ADDRHOLE_ADDR_REG register
* icm sys addr hole address registers
*/
#define ICM_SYS_ADDRHOLE_ADDR_REG (DR_REG_ICM_BASE + 0x38)
/** ICM_REG_ICM_SYS_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
* NA
*/
#define ICM_REG_ICM_SYS_ADDRHOLE_ADDR 0xFFFFFFFFU
#define ICM_REG_ICM_SYS_ADDRHOLE_ADDR_M (ICM_REG_ICM_SYS_ADDRHOLE_ADDR_V << ICM_REG_ICM_SYS_ADDRHOLE_ADDR_S)
#define ICM_REG_ICM_SYS_ADDRHOLE_ADDR_V 0xFFFFFFFFU
#define ICM_REG_ICM_SYS_ADDRHOLE_ADDR_S 0
/** ICM_SYS_ADDRHOLE_INFO_REG register
* NA
*/
#define ICM_SYS_ADDRHOLE_INFO_REG (DR_REG_ICM_BASE + 0x3c)
/** ICM_REG_ICM_SYS_ADDRHOLE_ID : RO; bitpos: [7:0]; default: 0;
* master id = 4-bit CID + 4-bit UID(refer to related IP) . CID is used to verify
* master in icm. CID: 4'h1: cache, 4'h5 gdma mst1, 4'h6: gdma mst2, 4'h8: axi pdma,
* 4'ha: dma2d, 4'hb: h264 mst1, 4'hc: h264 mst2.
*/
#define ICM_REG_ICM_SYS_ADDRHOLE_ID 0x000000FFU
#define ICM_REG_ICM_SYS_ADDRHOLE_ID_M (ICM_REG_ICM_SYS_ADDRHOLE_ID_V << ICM_REG_ICM_SYS_ADDRHOLE_ID_S)
#define ICM_REG_ICM_SYS_ADDRHOLE_ID_V 0x000000FFU
#define ICM_REG_ICM_SYS_ADDRHOLE_ID_S 0
/** ICM_REG_ICM_SYS_ADDRHOLE_WR : RO; bitpos: [8]; default: 0;
* 1: illegal address access, 0: access without permission
*/
#define ICM_REG_ICM_SYS_ADDRHOLE_WR (BIT(8))
#define ICM_REG_ICM_SYS_ADDRHOLE_WR_M (ICM_REG_ICM_SYS_ADDRHOLE_WR_V << ICM_REG_ICM_SYS_ADDRHOLE_WR_S)
#define ICM_REG_ICM_SYS_ADDRHOLE_WR_V 0x00000001U
#define ICM_REG_ICM_SYS_ADDRHOLE_WR_S 8
/** ICM_REG_ICM_SYS_ADDRHOLE_SECURE : RO; bitpos: [9]; default: 0;
* It is illegall access address if reg_icm_cpu_addrhole_secure is 1, Otherwise, it
* the address without permission to access.
*/
#define ICM_REG_ICM_SYS_ADDRHOLE_SECURE (BIT(9))
#define ICM_REG_ICM_SYS_ADDRHOLE_SECURE_M (ICM_REG_ICM_SYS_ADDRHOLE_SECURE_V << ICM_REG_ICM_SYS_ADDRHOLE_SECURE_S)
#define ICM_REG_ICM_SYS_ADDRHOLE_SECURE_V 0x00000001U
#define ICM_REG_ICM_SYS_ADDRHOLE_SECURE_S 9
/** ICM_CPU_ADDRHOLE_ADDR_REG register
* icm cpu addr hole address registers
*/
#define ICM_CPU_ADDRHOLE_ADDR_REG (DR_REG_ICM_BASE + 0x40)
/** ICM_REG_ICM_CPU_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
* It is illegall access address if reg_icm_cpu_addrhole_secure is 1. Otherwise, it
* the address without permission to access.
*/
#define ICM_REG_ICM_CPU_ADDRHOLE_ADDR 0xFFFFFFFFU
#define ICM_REG_ICM_CPU_ADDRHOLE_ADDR_M (ICM_REG_ICM_CPU_ADDRHOLE_ADDR_V << ICM_REG_ICM_CPU_ADDRHOLE_ADDR_S)
#define ICM_REG_ICM_CPU_ADDRHOLE_ADDR_V 0xFFFFFFFFU
#define ICM_REG_ICM_CPU_ADDRHOLE_ADDR_S 0
/** ICM_CPU_ADDRHOLE_INFO_REG register
* NA
*/
#define ICM_CPU_ADDRHOLE_INFO_REG (DR_REG_ICM_BASE + 0x44)
/** ICM_REG_ICM_CPU_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0;
* master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4:
* regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha
* tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma.
*/
#define ICM_REG_ICM_CPU_ADDRHOLE_ID 0x0000001FU
#define ICM_REG_ICM_CPU_ADDRHOLE_ID_M (ICM_REG_ICM_CPU_ADDRHOLE_ID_V << ICM_REG_ICM_CPU_ADDRHOLE_ID_S)
#define ICM_REG_ICM_CPU_ADDRHOLE_ID_V 0x0000001FU
#define ICM_REG_ICM_CPU_ADDRHOLE_ID_S 0
/** ICM_REG_ICM_CPU_ADDRHOLE_WR : RO; bitpos: [8]; default: 0;
* 1:write trans, 0: read trans.
*/
#define ICM_REG_ICM_CPU_ADDRHOLE_WR (BIT(8))
#define ICM_REG_ICM_CPU_ADDRHOLE_WR_M (ICM_REG_ICM_CPU_ADDRHOLE_WR_V << ICM_REG_ICM_CPU_ADDRHOLE_WR_S)
#define ICM_REG_ICM_CPU_ADDRHOLE_WR_V 0x00000001U
#define ICM_REG_ICM_CPU_ADDRHOLE_WR_S 8
/** ICM_REG_ICM_CPU_ADDRHOLE_SECURE : RO; bitpos: [9]; default: 0;
* 1: illegal address access, 0: access without permission
*/
#define ICM_REG_ICM_CPU_ADDRHOLE_SECURE (BIT(9))
#define ICM_REG_ICM_CPU_ADDRHOLE_SECURE_M (ICM_REG_ICM_CPU_ADDRHOLE_SECURE_V << ICM_REG_ICM_CPU_ADDRHOLE_SECURE_S)
#define ICM_REG_ICM_CPU_ADDRHOLE_SECURE_V 0x00000001U
#define ICM_REG_ICM_CPU_ADDRHOLE_SECURE_S 9
/** ICM_DLOCK_TIMEOUT_REG register
* NA
*/
#define ICM_DLOCK_TIMEOUT_REG (DR_REG_ICM_BASE + 0x48)
/** ICM_REG_DLOCK_TIMEOUT : R/W; bitpos: [12:0]; default: 2048;
* if no response until reg_dlock_timeout bus clock cycle, deadlock will happen
*/
#define ICM_REG_DLOCK_TIMEOUT 0x00001FFFU
#define ICM_REG_DLOCK_TIMEOUT_M (ICM_REG_DLOCK_TIMEOUT_V << ICM_REG_DLOCK_TIMEOUT_S)
#define ICM_REG_DLOCK_TIMEOUT_V 0x00001FFFU
#define ICM_REG_DLOCK_TIMEOUT_S 0
/** ICM_RDN_ECO_CS_REG register
* NA
*/
#define ICM_RDN_ECO_CS_REG (DR_REG_ICM_BASE + 0x50)
/** ICM_REG_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
* NA
*/
#define ICM_REG_RDN_ECO_EN (BIT(0))
#define ICM_REG_RDN_ECO_EN_M (ICM_REG_RDN_ECO_EN_V << ICM_REG_RDN_ECO_EN_S)
#define ICM_REG_RDN_ECO_EN_V 0x00000001U
#define ICM_REG_RDN_ECO_EN_S 0
/** ICM_REG_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
* NA
*/
#define ICM_REG_RDN_ECO_RESULT (BIT(1))
#define ICM_REG_RDN_ECO_RESULT_M (ICM_REG_RDN_ECO_RESULT_V << ICM_REG_RDN_ECO_RESULT_S)
#define ICM_REG_RDN_ECO_RESULT_V 0x00000001U
#define ICM_REG_RDN_ECO_RESULT_S 1
/** ICM_RDN_ECO_LOW_REG register
* NA
*/
#define ICM_RDN_ECO_LOW_REG (DR_REG_ICM_BASE + 0x54)
/** ICM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
* NA
*/
#define ICM_RDN_ECO_LOW 0xFFFFFFFFU
#define ICM_RDN_ECO_LOW_M (ICM_RDN_ECO_LOW_V << ICM_RDN_ECO_LOW_S)
#define ICM_RDN_ECO_LOW_V 0xFFFFFFFFU
#define ICM_RDN_ECO_LOW_S 0
/** ICM_RDN_ECO_HIGH_REG register
* NA
*/
#define ICM_RDN_ECO_HIGH_REG (DR_REG_ICM_BASE + 0x58)
/** ICM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
* NA
*/
#define ICM_RDN_ECO_HIGH 0xFFFFFFFFU
#define ICM_RDN_ECO_HIGH_M (ICM_RDN_ECO_HIGH_V << ICM_RDN_ECO_HIGH_S)
#define ICM_RDN_ECO_HIGH_V 0xFFFFFFFFU
#define ICM_RDN_ECO_HIGH_S 0
#ifdef __cplusplus
}
#endif

521
components/soc/esp32p4/register/hw_ver2/soc/icm_sys_struct.h Normal file
View File

@@ -0,0 +1,521 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: ICM VER DATE REG */
/** Type of ver_date register
* NA
*/
typedef union {
struct {
/** reg_ver_date : R/W; bitpos: [31:0]; default: 539165204;
* NA
*/
uint32_t reg_ver_date:32;
};
uint32_t val;
} icm_ver_date_reg_t;
/** Group: ICM CLK EN REG */
/** Type of clk_en register
* NA
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 0;
* NA
*/
uint32_t reg_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} icm_clk_en_reg_t;
/** Group: ICM DLOCK STATUS REG */
/** Type of dlock_status register
* NA
*/
typedef union {
struct {
/** reg_dlock_mst : RO; bitpos: [3:0]; default: 0;
* Lowest numbered deadlocked master
*/
uint32_t reg_dlock_mst:4;
/** reg_dlock_slv : RO; bitpos: [6:4]; default: 0;
* Slave with which dlock_mst is deadlocked
*/
uint32_t reg_dlock_slv:3;
/** reg_dlock_id : RO; bitpos: [10:7]; default: 0;
* AXI ID of deadlocked transaction
*/
uint32_t reg_dlock_id:4;
/** reg_dlock_wr : RO; bitpos: [11]; default: 0;
* Asserted if deadlocked transaction is a write
*/
uint32_t reg_dlock_wr:1;
uint32_t reserved_12:20;
};
uint32_t val;
} icm_dlock_status_reg_t;
/** Group: ICM INT RAW REG */
/** Type of int_raw register
* NA
*/
typedef union {
struct {
/** reg_dlock_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* NA
*/
uint32_t reg_dlock_int_raw:1;
/** reg_icm_sys_addrhole_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* NA
*/
uint32_t reg_icm_sys_addrhole_int_raw:1;
/** reg_icm_cpu_addrhole_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* NA
*/
uint32_t reg_icm_cpu_addrhole_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} icm_int_raw_reg_t;
/** Group: ICM INT ST REG */
/** Type of int_st register
* NA
*/
typedef union {
struct {
/** reg_dlock_int_st : RO; bitpos: [0]; default: 0;
* NA
*/
uint32_t reg_dlock_int_st:1;
/** reg_icm_sys_addrhole_int_st : RO; bitpos: [1]; default: 0;
* NA
*/
uint32_t reg_icm_sys_addrhole_int_st:1;
/** reg_icm_cpu_addrhole_int_st : RO; bitpos: [2]; default: 0;
* NA
*/
uint32_t reg_icm_cpu_addrhole_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} icm_int_st_reg_t;
/** Group: ICM INT ENA REG */
/** Type of int_ena register
* NA
*/
typedef union {
struct {
/** reg_dlock_int_ena : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_dlock_int_ena:1;
/** reg_icm_sys_addrhole_int_ena : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_icm_sys_addrhole_int_ena:1;
/** reg_icm_cpu_addrhole_int_ena : R/W; bitpos: [2]; default: 1;
* NA
*/
uint32_t reg_icm_cpu_addrhole_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} icm_int_ena_reg_t;
/** Group: ICM INT CLR REG */
/** Type of int_clr register
* NA
*/
typedef union {
struct {
/** reg_dlock_int_clr : WT; bitpos: [0]; default: 0;
* NA
*/
uint32_t reg_dlock_int_clr:1;
/** reg_icm_sys_addrhole_int_clr : WT; bitpos: [1]; default: 0;
* NA
*/
uint32_t reg_icm_sys_addrhole_int_clr:1;
/** reg_icm_cpu_addrhole_int_clr : WT; bitpos: [2]; default: 0;
* NA
*/
uint32_t reg_icm_cpu_addrhole_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} icm_int_clr_reg_t;
/** Group: ICM MST ARB PRIORITY REG0 REG */
/** Type of mst_arb_priority_reg0 register
* NA
*/
typedef union {
struct {
/** reg_cpu_priority : R/W; bitpos: [3:0]; default: 0;
* CPU arbitration priority for command channels between masters connected to sys_icm
*/
uint32_t reg_cpu_priority:4;
/** reg_cache_priority : R/W; bitpos: [7:4]; default: 0;
* CACHE arbitration priority for command channels between masters connected to sys_icm
*/
uint32_t reg_cache_priority:4;
/** reg_dma2d_priority : R/W; bitpos: [11:8]; default: 0;
* GFX arbitration priority for command channels between masters connected to sys_icm
*/
uint32_t reg_dma2d_priority:4;
/** reg_gdma_mst1_priority : R/W; bitpos: [15:12]; default: 0;
* GDMA mst1 arbitration priority for command channels between masters connected to
* sys_icm
*/
uint32_t reg_gdma_mst1_priority:4;
/** reg_gdma_mst2_priority : R/W; bitpos: [19:16]; default: 0;
* GDMA mst2 arbitration priority for command channels between masters connected to
* sys_icm
*/
uint32_t reg_gdma_mst2_priority:4;
/** reg_h264_m1_priority : R/W; bitpos: [23:20]; default: 0;
* H264 mst1 arbitration priority for command channels between masters connected to
* sys_icm
*/
uint32_t reg_h264_m1_priority:4;
/** reg_h264_m2_priority : R/W; bitpos: [27:24]; default: 0;
* H264 mst2 arbitration priority for command channels between masters connected to
* sys_icm
*/
uint32_t reg_h264_m2_priority:4;
/** reg_axi_pdma_priority : R/W; bitpos: [31:28]; default: 0;
* AXI PDMA arbitration priority for command channels between masters connected to
* sys_icm
*/
uint32_t reg_axi_pdma_priority:4;
};
uint32_t val;
} icm_mst_arb_priority_reg0_reg_t;
/** Group: ICM SLV ARB PRIORITY REG */
/** Type of slv_arb_priority register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:3;
/** reg_l2mem_priority : R/W; bitpos: [5:3]; default: 0;
* L2MEM arbitration priority for response channels between slaves connected to sys_icm
*/
uint32_t reg_l2mem_priority:3;
uint32_t reserved_6:6;
/** reg_flash_mspi_priority : R/W; bitpos: [14:12]; default: 0;
* FLASH MSPI arbitration priority for response channels between slaves connected to
* sys_icm
*/
uint32_t reg_flash_mspi_priority:3;
/** reg_psram_mspi_priority : R/W; bitpos: [17:15]; default: 0;
* PSRAM MSPI arbitration priority for response channels between slaves connected to
* sys_icm
*/
uint32_t reg_psram_mspi_priority:3;
/** reg_lcd_priority : R/W; bitpos: [20:18]; default: 0;
* MIPI_LCD registers arbitration priority for response channels between slaves
* connected to sys_icm
*/
uint32_t reg_lcd_priority:3;
/** reg_cam_priority : R/W; bitpos: [23:21]; default: 0;
* MIPI_CAM registers arbitration priority for response channels between slaves
* connected to sys_icm
*/
uint32_t reg_cam_priority:3;
uint32_t reserved_24:8;
};
uint32_t val;
} icm_slv_arb_priority_reg_t;
/** Group: ICM MST ARQOS REG0 REG */
/** Type of mst_arqos_reg0 register
* NA
*/
typedef union {
struct {
/** reg_cpu_arqos : R/W; bitpos: [3:0]; default: 0;
* NA
*/
uint32_t reg_cpu_arqos:4;
/** reg_cache_arqos : R/W; bitpos: [7:4]; default: 0;
* NA
*/
uint32_t reg_cache_arqos:4;
/** reg_dma2d_arqos : R/W; bitpos: [11:8]; default: 0;
* NA
*/
uint32_t reg_dma2d_arqos:4;
/** reg_gdma_mst1_arqos : R/W; bitpos: [15:12]; default: 0;
* NA
*/
uint32_t reg_gdma_mst1_arqos:4;
/** reg_gdma_mst2_arqos : R/W; bitpos: [19:16]; default: 0;
* NA
*/
uint32_t reg_gdma_mst2_arqos:4;
/** reg_h264_dma2d_m1_arqos : R/W; bitpos: [23:20]; default: 0;
* NA
*/
uint32_t reg_h264_dma2d_m1_arqos:4;
/** reg_h264_dma2d_m2_arqos : R/W; bitpos: [27:24]; default: 0;
* NA
*/
uint32_t reg_h264_dma2d_m2_arqos:4;
/** reg_axi_pdma_int_arqos : R/W; bitpos: [31:28]; default: 0;
* NA
*/
uint32_t reg_axi_pdma_int_arqos:4;
};
uint32_t val;
} icm_mst_arqos_reg0_reg_t;
/** Group: ICM MST AWQOS REG0 REG */
/** Type of mst_awqos_reg0 register
* NA
*/
typedef union {
struct {
/** reg_cpu_awqos : R/W; bitpos: [3:0]; default: 0;
* NA
*/
uint32_t reg_cpu_awqos:4;
/** reg_cache_awqos : R/W; bitpos: [7:4]; default: 0;
* NA
*/
uint32_t reg_cache_awqos:4;
/** reg_dma2d_awqos : R/W; bitpos: [11:8]; default: 0;
* NA
*/
uint32_t reg_dma2d_awqos:4;
/** reg_gdma_mst1_awqos : R/W; bitpos: [15:12]; default: 0;
* NA
*/
uint32_t reg_gdma_mst1_awqos:4;
/** reg_gdma_mst2_awqos : R/W; bitpos: [19:16]; default: 0;
* NA
*/
uint32_t reg_gdma_mst2_awqos:4;
/** reg_h264_dma2d_m1_awqos : R/W; bitpos: [23:20]; default: 0;
* NA
*/
uint32_t reg_h264_dma2d_m1_awqos:4;
/** reg_h264_dma2d_m2_awqos : R/W; bitpos: [27:24]; default: 0;
* NA
*/
uint32_t reg_h264_dma2d_m2_awqos:4;
/** reg_pdma_int_awqos : R/W; bitpos: [31:28]; default: 0;
* NA
*/
uint32_t reg_pdma_int_awqos:4;
};
uint32_t val;
} icm_mst_awqos_reg0_reg_t;
/** Group: ICM ADDRHOLE ADDR REG */
/** Type of sys_addrhole_addr register
* icm sys addr hole address registers
*/
typedef union {
struct {
/** reg_icm_sys_addrhole_addr : RO; bitpos: [31:0]; default: 0;
* NA
*/
uint32_t reg_icm_sys_addrhole_addr:32;
};
uint32_t val;
} icm_sys_addrhole_addr_reg_t;
/** Type of cpu_addrhole_addr register
* icm cpu addr hole address registers
*/
typedef union {
struct {
/** reg_icm_cpu_addrhole_addr : RO; bitpos: [31:0]; default: 0;
* It is illegall access address if reg_icm_cpu_addrhole_secure is 1. Otherwise, it
* the address without permission to access.
*/
uint32_t reg_icm_cpu_addrhole_addr:32;
};
uint32_t val;
} icm_cpu_addrhole_addr_reg_t;
/** Group: ICM ADDRHOLE INFO REG */
/** Type of sys_addrhole_info register
* NA
*/
typedef union {
struct {
/** reg_icm_sys_addrhole_id : RO; bitpos: [7:0]; default: 0;
* master id = 4-bit CID + 4-bit UID(refer to related IP) . CID is used to verify
* master in icm. CID: 4'h1: cache, 4'h5 gdma mst1, 4'h6: gdma mst2, 4'h8: axi pdma,
* 4'ha: dma2d, 4'hb: h264 mst1, 4'hc: h264 mst2.
*/
uint32_t reg_icm_sys_addrhole_id:8;
/** reg_icm_sys_addrhole_wr : RO; bitpos: [8]; default: 0;
* 1: illegal address access, 0: access without permission
*/
uint32_t reg_icm_sys_addrhole_wr:1;
/** reg_icm_sys_addrhole_secure : RO; bitpos: [9]; default: 0;
* It is illegall access address if reg_icm_cpu_addrhole_secure is 1, Otherwise, it
* the address without permission to access.
*/
uint32_t reg_icm_sys_addrhole_secure:1;
uint32_t reserved_10:22;
};
uint32_t val;
} icm_sys_addrhole_info_reg_t;
/** Type of cpu_addrhole_info register
* NA
*/
typedef union {
struct {
/** reg_icm_cpu_addrhole_id : RO; bitpos: [4:0]; default: 0;
* master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4:
* regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha
* tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma.
*/
uint32_t reg_icm_cpu_addrhole_id:5;
uint32_t reserved_5:3;
/** reg_icm_cpu_addrhole_wr : RO; bitpos: [8]; default: 0;
* 1:write trans, 0: read trans.
*/
uint32_t reg_icm_cpu_addrhole_wr:1;
/** reg_icm_cpu_addrhole_secure : RO; bitpos: [9]; default: 0;
* 1: illegal address access, 0: access without permission
*/
uint32_t reg_icm_cpu_addrhole_secure:1;
uint32_t reserved_10:22;
};
uint32_t val;
} icm_cpu_addrhole_info_reg_t;
/** Group: ICM DLOCK TIMEOUT REG */
/** Type of dlock_timeout register
* NA
*/
typedef union {
struct {
/** reg_dlock_timeout : R/W; bitpos: [12:0]; default: 2048;
* if no response until reg_dlock_timeout bus clock cycle, deadlock will happen
*/
uint32_t reg_dlock_timeout:13;
uint32_t reserved_13:19;
};
uint32_t val;
} icm_dlock_timeout_reg_t;
/** Group: ICM RDN ECO CS REG */
/** Type of rdn_eco_cs register
* NA
*/
typedef union {
struct {
/** reg_rdn_eco_en : R/W; bitpos: [0]; default: 0;
* NA
*/
uint32_t reg_rdn_eco_en:1;
/** reg_rdn_eco_result : RO; bitpos: [1]; default: 0;
* NA
*/
uint32_t reg_rdn_eco_result:1;
uint32_t reserved_2:30;
};
uint32_t val;
} icm_rdn_eco_cs_reg_t;
/** Group: ICM RDN ECO LOW REG */
/** Type of rdn_eco_low register
* NA
*/
typedef union {
struct {
/** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
* NA
*/
uint32_t rdn_eco_low:32;
};
uint32_t val;
} icm_rdn_eco_low_reg_t;
/** Group: ICM RDN ECO HIGH REG */
/** Type of rdn_eco_high register
* NA
*/
typedef union {
struct {
/** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
* NA
*/
uint32_t rdn_eco_high:32;
};
uint32_t val;
} icm_rdn_eco_high_reg_t;
typedef struct {
volatile icm_ver_date_reg_t ver_date;
volatile icm_clk_en_reg_t clk_en;
volatile icm_dlock_status_reg_t dlock_status;
volatile icm_int_raw_reg_t int_raw;
volatile icm_int_st_reg_t int_st;
volatile icm_int_ena_reg_t int_ena;
volatile icm_int_clr_reg_t int_clr;
volatile icm_mst_arb_priority_reg0_reg_t mst_arb_priority_reg0;
uint32_t reserved_020;
volatile icm_slv_arb_priority_reg_t slv_arb_priority;
volatile icm_mst_arqos_reg0_reg_t mst_arqos_reg0;
uint32_t reserved_02c;
volatile icm_mst_awqos_reg0_reg_t mst_awqos_reg0;
uint32_t reserved_034;
volatile icm_sys_addrhole_addr_reg_t sys_addrhole_addr;
volatile icm_sys_addrhole_info_reg_t sys_addrhole_info;
volatile icm_cpu_addrhole_addr_reg_t cpu_addrhole_addr;
volatile icm_cpu_addrhole_info_reg_t cpu_addrhole_info;
volatile icm_dlock_timeout_reg_t dlock_timeout;
uint32_t reserved_04c;
volatile icm_rdn_eco_cs_reg_t rdn_eco_cs;
volatile icm_rdn_eco_low_reg_t rdn_eco_low;
volatile icm_rdn_eco_high_reg_t rdn_eco_high;
} icm_dev_t;
extern icm_dev_t ICM_SYS;
#ifndef __cplusplus
_Static_assert(sizeof(icm_dev_t) == 0x5c, "Invalid size of icm_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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