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Merge branch 'change/support_pm_slp_iram_opt_in_normal_light_sleep_v5.3' into 'release/v5.3'

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change(esp_pm): bypass cache access assertion when using ext0 or ext1(backport v5.3)

See merge request espressif/esp-idf!33142
This commit is contained in:
Jiang Jiang Jian
2024-09-09 11:26:28 +08:00
parent 0593e04dee 4c3f6efbd7
commit b994115eee
2 changed files with 19 additions and 4 deletions
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21
components/esp_hw_support/sleep_modes.c
View File

@@ -1322,8 +1322,21 @@ esp_err_t esp_light_sleep_start(void)
#if CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION && CONFIG_PM_SLP_IRAM_OPT
/* Cache Suspend 0: if CONFIG_PM_SLP_IRAM_OPT is enabled, suspend cache here so that the access to flash
during the sleep process can be explicitly exposed. */
suspend_cache();
* during the sleep process can be explicitly exposed.
*
* If we use EXTx wakeup, we must put related codes in IRAM, but The `rtc_io_desc` table
* consumes a significant amount of memory. For example, on the ESP32, its size is 1008
* bytes. Therefore, when EXTx wakeup is enabled, we do not perform cache access checks here */
uint32_t ignore_check_wakeup_triggers = 0;
#if SOC_PM_SUPPORT_EXT0_WAKEUP
ignore_check_wakeup_triggers |= RTC_EXT0_TRIG_EN;
#endif
#if SOC_PM_SUPPORT_EXT1_WAKEUP
ignore_check_wakeup_triggers |= RTC_EXT1_TRIG_EN;
#endif
if (!(s_config.wakeup_triggers & ignore_check_wakeup_triggers)) {
suspend_cache();
}
#endif
// Decide which power domains can be powered down
@@ -1463,7 +1476,9 @@ esp_err_t esp_light_sleep_start(void)
#if CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION && CONFIG_PM_SLP_IRAM_OPT
/* Cache Resume 0: sleep process done, resume cache for continue running */
resume_cache();
if (!(s_config.wakeup_triggers & ignore_check_wakeup_triggers)) {
resume_cache();
}
#endif
#if !CONFIG_FREERTOS_UNICORE

2
components/esp_pm/Kconfig
View File

@@ -49,7 +49,7 @@ menu "Power Management"
config PM_SLP_IRAM_OPT
bool "Put lightsleep related codes in internal RAM"
depends on FREERTOS_USE_TICKLESS_IDLE
depends on SOC_LIGHT_SLEEP_SUPPORTED
help
If enabled, about 2.1KB of lightsleep related source code would be in IRAM and chip would sleep
longer for 310us at 160MHz CPU frequency most each time.