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refactor(esp32c61): update bus_monitor registers for C61
This commit is contained in:
laokaiyao
File diff suppressed because it is too large
Load Diff
@@ -1,5 +1,5 @@
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/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -10,86 +10,78 @@
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extern "C" {
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#endif
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/** Group: monitor configuration registers */
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/** Group: Monitor configuration registers */
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/** Type of core_0_montr_ena register
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* core0 monitor enable configuration register
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* Configures whether to enable HP CPU monitoring
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*/
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typedef union {
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struct {
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/** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
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* Configures whether to monitor read operations in region 0 by the Data bus. \\
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* 0: Not monitor\\
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* 1: Monitor\\
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* Configures whether to monitor read operations in region 0 by the Data bus.
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* 0: Not monitor
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* 1: Monitor
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*/
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uint32_t core_0_area_dram0_0_rd_ena:1;
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/** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
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* Configures whether to monitor write operations in region 0 by the Data bus.\\
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* 0: Not monitor\\
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* 1: Monitor\\
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* Configures whether to monitor write operations in region 0 by the Data bus.
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* 0: Not monitor
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* 1: Monitor
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*/
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uint32_t core_0_area_dram0_0_wr_ena:1;
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/** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
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* Configures whether to monitor read operations in region 1 by the Data bus.\\
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* 0: Not Monitor\\
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* 1: Monitor\\
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* Configures whether to monitor read operations in region 1 by the Data bus.
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* 0: Not Monitor
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* 1: Monitor
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*/
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uint32_t core_0_area_dram0_1_rd_ena:1;
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/** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
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* Configures whether to monitor write operations in region 1 by the Data bus.\\
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* 0: Not Monitor\\
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* 1: Monitor\\
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* Configures whether to monitor write operations in region 1 by the Data bus.
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* 0: Not Monitor
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* 1: Monitor
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*/
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uint32_t core_0_area_dram0_1_wr_ena:1;
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/** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
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* Configures whether to monitor read operations in region 0 by the Peripheral bus.\\
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* 0: Not Monitor\\
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* 1: Monitor\\
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* Configures whether to monitor read operations in region 0 by the Peripheral bus.
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* 0: Not Monitor
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* 1: Monitor
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*/
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uint32_t core_0_area_pif_0_rd_ena:1;
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/** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
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* Configures whether to monitor write operations in region 0 by the Peripheral bus.\\
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* 0: Not Monitor\\
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* 1: Monitor\\
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* Configures whether to monitor write operations in region 0 by the Peripheral bus.
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* 0: Not Monitor
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* 1: Monitor
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*/
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uint32_t core_0_area_pif_0_wr_ena:1;
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/** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
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* Configures whether to monitor read operations in region 1 by the Peripheral bus.\\
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* 0: Not Monitor\\
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* 1: Monitor\\
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* Configures whether to monitor read operations in region 1 by the Peripheral bus.
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* 0: Not Monitor
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* 1: Monitor
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*/
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uint32_t core_0_area_pif_1_rd_ena:1;
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/** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
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* Configures whether to monitor write operations in region 1 by the Peripheral bus.\\
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* 0: Not Monitor\\
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* 1: Monitor\\
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* Configures whether to monitor write operations in region 1 by the Peripheral bus.
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* 0: Not Monitor
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* 1: Monitor
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*/
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uint32_t core_0_area_pif_1_wr_ena:1;
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/** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
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* Configures whether to monitor SP exceeding the lower bound address of SP monitored
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* region.\\
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* 0: Not Monitor\\
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* 1: Monitor\\
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* region.
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* 0: Not Monitor
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* 1: Monitor
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*/
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uint32_t core_0_sp_spill_min_ena:1;
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/** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
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* Configures whether to monitor SP exceeding the upper bound address of SP monitored
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* region.\\
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* 0: Not Monitor\\
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* 1: Monitor\\
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* region.
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* 0: Not Monitor
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* 1: Monitor
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*/
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uint32_t core_0_sp_spill_max_ena:1;
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/** core_0_iram0_exception_monitor_ena : R/W; bitpos: [10]; default: 0;
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* IBUS busy monitor enable
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*/
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uint32_t core_0_iram0_exception_monitor_ena:1;
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/** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0;
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* DBUS busy monitor enable
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*/
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uint32_t core_0_dram0_exception_monitor_ena:1;
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uint32_t reserved_12:20;
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uint32_t reserved_10:22;
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};
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uint32_t val;
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} assist_debug_core_0_montr_ena_reg_t;
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} bus_monitor_core_0_montr_ena_reg_t;
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/** Type of core_0_area_dram0_0_min register
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* Configures lower boundary address of region 0 monitored on Data bus
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@@ -102,7 +94,7 @@ typedef union {
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uint32_t core_0_area_dram0_0_min:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_dram0_0_min_reg_t;
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} bus_monitor_core_0_area_dram0_0_min_reg_t;
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/** Type of core_0_area_dram0_0_max register
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* Configures upper boundary address of region 0 monitored on Data bus
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@@ -115,7 +107,7 @@ typedef union {
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uint32_t core_0_area_dram0_0_max:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_dram0_0_max_reg_t;
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} bus_monitor_core_0_area_dram0_0_max_reg_t;
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/** Type of core_0_area_dram0_1_min register
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* Configures lower boundary address of region 1 monitored on Data bus
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@@ -128,7 +120,7 @@ typedef union {
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uint32_t core_0_area_dram0_1_min:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_dram0_1_min_reg_t;
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} bus_monitor_core_0_area_dram0_1_min_reg_t;
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/** Type of core_0_area_dram0_1_max register
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* Configures upper boundary address of region 1 monitored on Data bus
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@@ -141,7 +133,7 @@ typedef union {
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uint32_t core_0_area_dram0_1_max:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_dram0_1_max_reg_t;
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} bus_monitor_core_0_area_dram0_1_max_reg_t;
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/** Type of core_0_area_pif_0_min register
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* Configures lower boundary address of region 0 monitored on Peripheral bus
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@@ -154,7 +146,7 @@ typedef union {
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uint32_t core_0_area_pif_0_min:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_pif_0_min_reg_t;
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} bus_monitor_core_0_area_pif_0_min_reg_t;
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/** Type of core_0_area_pif_0_max register
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* Configures upper boundary address of region 0 monitored on Peripheral bus
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@@ -167,7 +159,7 @@ typedef union {
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uint32_t core_0_area_pif_0_max:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_pif_0_max_reg_t;
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} bus_monitor_core_0_area_pif_0_max_reg_t;
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/** Type of core_0_area_pif_1_min register
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* Configures lower boundary address of region 1 monitored on Peripheral bus
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@@ -180,7 +172,7 @@ typedef union {
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uint32_t core_0_area_pif_1_min:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_pif_1_min_reg_t;
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} bus_monitor_core_0_area_pif_1_min_reg_t;
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/** Type of core_0_area_pif_1_max register
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* Configures upper boundary address of region 1 monitored on Peripheral bus
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@@ -193,10 +185,10 @@ typedef union {
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uint32_t core_0_area_pif_1_max:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_pif_1_max_reg_t;
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} bus_monitor_core_0_area_pif_1_max_reg_t;
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/** Type of core_0_area_pc register
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* Region monitoring HP CPU PC status register
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* Represents the PC value when HP CPU region monitor is triggered
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*/
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typedef union {
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struct {
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@@ -206,10 +198,10 @@ typedef union {
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uint32_t core_0_area_pc:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_pc_reg_t;
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} bus_monitor_core_0_area_pc_reg_t;
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/** Type of core_0_area_sp register
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* Region monitoring HP CPU SP status register
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* Represents the SP value when HP CPU region monitor is triggered
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*/
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typedef union {
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struct {
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@@ -219,255 +211,228 @@ typedef union {
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uint32_t core_0_area_sp:32;
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};
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uint32_t val;
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} assist_debug_core_0_area_sp_reg_t;
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} bus_monitor_core_0_area_sp_reg_t;
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/** Type of core_0_sp_min register
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* Configures stack monitoring lower boundary address
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* Configures SP monitoring lower boundary address
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*/
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typedef union {
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struct {
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/** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
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* Configures the lower bound address of SP.
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* Configures the lower bound address of SP monitored region.
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*/
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uint32_t core_0_sp_min:32;
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};
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uint32_t val;
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} assist_debug_core_0_sp_min_reg_t;
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} bus_monitor_core_0_sp_min_reg_t;
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/** Type of core_0_sp_max register
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* Configures stack monitoring upper boundary address
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* Configures SP monitoring upper boundary address
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*/
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typedef union {
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struct {
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/** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
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* Configures the upper bound address of SP.
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* Configures the upper bound address of SP monitored region.
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*/
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uint32_t core_0_sp_max:32;
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};
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uint32_t val;
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} assist_debug_core_0_sp_max_reg_t;
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} bus_monitor_core_0_sp_max_reg_t;
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/** Type of core_0_sp_pc register
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* Stack monitoring HP CPU PC status register
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* Represents the PC value when HP CPU SP monitor is triggered
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*/
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typedef union {
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struct {
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/** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
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* Represents the PC value during stack monitoring.
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* Represents the PC value when SP monitoring is triggered.
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*/
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uint32_t core_0_sp_pc:32;
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};
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uint32_t val;
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} assist_debug_core_0_sp_pc_reg_t;
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} bus_monitor_core_0_sp_pc_reg_t;
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/** Group: interrupt configuration register */
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/** Group: Interrupt configuration registers */
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/** Type of core_0_intr_raw register
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* core0 monitor interrupt status register
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* HP CPU monitor raw interrupt status register
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*/
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typedef union {
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struct {
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/** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
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* The raw interrupt status of read operations in region 0 by Data bus.
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* The raw interrupt status of BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INT.
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*/
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uint32_t core_0_area_dram0_0_rd_raw:1;
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/** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
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* The raw interrupt status of write operations in region 0 by Data bus.
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* The raw interrupt status of BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INT.
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*/
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uint32_t core_0_area_dram0_0_wr_raw:1;
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/** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
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* The raw interrupt status of read operations in region 1 by Data bus.
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* The raw interrupt status of BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INT.
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*/
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uint32_t core_0_area_dram0_1_rd_raw:1;
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/** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
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* The raw interrupt status of write operations in region 1 by Data bus.
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* The raw interrupt status of BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INT.
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*/
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uint32_t core_0_area_dram0_1_wr_raw:1;
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/** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
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* The raw interrupt status of read operations in region 0 by Peripheral bus.
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* The raw interrupt status of BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INT.
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*/
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uint32_t core_0_area_pif_0_rd_raw:1;
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/** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
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* The raw interrupt status of write operations in region 0 by Peripheral bus.
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* The raw interrupt status of BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INT.
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*/
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uint32_t core_0_area_pif_0_wr_raw:1;
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/** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
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* The raw interrupt status of read operations in region 1 by Peripheral bus.
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* The raw interrupt status of BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INT.
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*/
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uint32_t core_0_area_pif_1_rd_raw:1;
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/** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
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* The raw interrupt status of write operations in region 1 by Peripheral bus.
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* The raw interrupt status of BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INT.
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*/
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uint32_t core_0_area_pif_1_wr_raw:1;
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/** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
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* The raw interrupt status of SP exceeding the lower bound address of SP monitored
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* region.
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* The raw interrupt status of BUS_MONITOR_CORE_0_SP_SPILL_MIN_INT.
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*/
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uint32_t core_0_sp_spill_min_raw:1;
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/** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
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* The raw interrupt status of SP exceeding the upper bound address of SP monitored
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* region.
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* The raw interrupt status of BUS_MONITOR_CORE_0_SP_SPILL_MAX_INT.
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*/
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uint32_t core_0_sp_spill_max_raw:1;
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/** core_0_iram0_exception_monitor_raw : RO; bitpos: [10]; default: 0;
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* IBUS busy monitor interrupt status
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*/
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uint32_t core_0_iram0_exception_monitor_raw:1;
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/** core_0_dram0_exception_monitor_raw : RO; bitpos: [11]; default: 0;
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* DBUS busy monitor initerrupt status
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*/
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uint32_t core_0_dram0_exception_monitor_raw:1;
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uint32_t reserved_12:20;
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uint32_t reserved_10:22;
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};
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uint32_t val;
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} assist_debug_core_0_intr_raw_reg_t;
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} bus_monitor_core_0_intr_raw_reg_t;
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/** Type of core_0_intr_ena register
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* core0 monitor interrupt enable register
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* HP CPU monitor interrupt enable register
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*/
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typedef union {
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struct {
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/** core_0_area_dram0_0_rd_intr_ena : R/W; bitpos: [0]; default: 0;
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* Core0 dram0 area0 read monitor interrupt enable
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* Write 1 to enable BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INT.
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*/
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uint32_t core_0_area_dram0_0_rd_intr_ena:1;
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/** core_0_area_dram0_0_wr_intr_ena : R/W; bitpos: [1]; default: 0;
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* Core0 dram0 area0 write monitor interrupt enable
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* Write 1 to enable BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INT.
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*/
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uint32_t core_0_area_dram0_0_wr_intr_ena:1;
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/** core_0_area_dram0_1_rd_intr_ena : R/W; bitpos: [2]; default: 0;
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* Core0 dram0 area1 read monitor interrupt enable
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* Write 1 to enable BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INT.
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*/
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uint32_t core_0_area_dram0_1_rd_intr_ena:1;
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/** core_0_area_dram0_1_wr_intr_ena : R/W; bitpos: [3]; default: 0;
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* Core0 dram0 area1 write monitor interrupt enable
|
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* Write 1 to enable BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INT.
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*/
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uint32_t core_0_area_dram0_1_wr_intr_ena:1;
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/** core_0_area_pif_0_rd_intr_ena : R/W; bitpos: [4]; default: 0;
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* Core0 PIF area0 read monitor interrupt enable
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* Write 1 to enable BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INT.
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*/
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uint32_t core_0_area_pif_0_rd_intr_ena:1;
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/** core_0_area_pif_0_wr_intr_ena : R/W; bitpos: [5]; default: 0;
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* Core0 PIF area0 write monitor interrupt enable
|
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* Write 1 to enable BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INT.
|
||||
*/
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uint32_t core_0_area_pif_0_wr_intr_ena:1;
|
||||
/** core_0_area_pif_1_rd_intr_ena : R/W; bitpos: [6]; default: 0;
|
||||
* Core0 PIF area1 read monitor interrupt enable
|
||||
* Write 1 to enable BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INT.
|
||||
*/
|
||||
uint32_t core_0_area_pif_1_rd_intr_ena:1;
|
||||
/** core_0_area_pif_1_wr_intr_ena : R/W; bitpos: [7]; default: 0;
|
||||
* Core0 PIF area1 write monitor interrupt enable
|
||||
* Write 1 to enable BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INT.
|
||||
*/
|
||||
uint32_t core_0_area_pif_1_wr_intr_ena:1;
|
||||
/** core_0_sp_spill_min_intr_ena : R/W; bitpos: [8]; default: 0;
|
||||
* Core0 stackpoint underflow monitor interrupt enable
|
||||
* Write 1 to enable BUS_MONITOR_CORE_0_SP_SPILL_MIN_INT.
|
||||
*/
|
||||
uint32_t core_0_sp_spill_min_intr_ena:1;
|
||||
/** core_0_sp_spill_max_intr_ena : R/W; bitpos: [9]; default: 0;
|
||||
* Core0 stackpoint overflow monitor interrupt enable
|
||||
* Write 1 to enable BUS_MONITOR_CORE_0_SP_SPILL_MAX_INT.
|
||||
*/
|
||||
uint32_t core_0_sp_spill_max_intr_ena:1;
|
||||
/** core_0_iram0_exception_monitor_intr_ena : R/W; bitpos: [10]; default: 0;
|
||||
* IBUS busy monitor interrupt enable
|
||||
*/
|
||||
uint32_t core_0_iram0_exception_monitor_intr_ena:1;
|
||||
/** core_0_dram0_exception_monitor_intr_ena : R/W; bitpos: [11]; default: 0;
|
||||
* DBUS busy monitor interrupt enable
|
||||
*/
|
||||
uint32_t core_0_dram0_exception_monitor_intr_ena:1;
|
||||
uint32_t reserved_12:20;
|
||||
uint32_t reserved_10:22;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_intr_ena_reg_t;
|
||||
} bus_monitor_core_0_intr_ena_reg_t;
|
||||
|
||||
/** Type of core_0_intr_clr register
|
||||
* core0 monitor interrupt clear register
|
||||
* HP CPU monitor interrupt clear register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to clear the interrupt for read operations in region 0 by Data bus.
|
||||
* Write 1 to clear BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INT.
|
||||
*/
|
||||
uint32_t core_0_area_dram0_0_rd_clr:1;
|
||||
/** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
|
||||
* Write 1 to clear the interrupt for write operations in region 0 by Data bus.
|
||||
* Write 1 to clear BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INT.
|
||||
*/
|
||||
uint32_t core_0_area_dram0_0_wr_clr:1;
|
||||
/** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
|
||||
* Write 1 to clear the interrupt for read operations in region 1 by Data bus.
|
||||
* Write 1 to clear BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INT.
|
||||
*/
|
||||
uint32_t core_0_area_dram0_1_rd_clr:1;
|
||||
/** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
|
||||
* Write 1 to clear the interrupt for write operations in region 1 by Data bus.
|
||||
* Write 1 to clear BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INT.
|
||||
*/
|
||||
uint32_t core_0_area_dram0_1_wr_clr:1;
|
||||
/** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
|
||||
* Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus.
|
||||
* Write 1 to clear BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INT.
|
||||
*/
|
||||
uint32_t core_0_area_pif_0_rd_clr:1;
|
||||
/** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
|
||||
* Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus.
|
||||
* Write 1 to clear BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INT.
|
||||
*/
|
||||
uint32_t core_0_area_pif_0_wr_clr:1;
|
||||
/** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
|
||||
* Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus.
|
||||
* Write 1 to clear BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INT.
|
||||
*/
|
||||
uint32_t core_0_area_pif_1_rd_clr:1;
|
||||
/** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
|
||||
* Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus.
|
||||
* Write 1 to clear BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INT.
|
||||
*/
|
||||
uint32_t core_0_area_pif_1_wr_clr:1;
|
||||
/** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
|
||||
* Write 1 to clear the interrupt for SP exceeding the lower bound address of SP
|
||||
* monitored region.
|
||||
* Write 1 to clear BUS_MONITOR_CORE_0_SP_SPILL_MIN_INT.
|
||||
*/
|
||||
uint32_t core_0_sp_spill_min_clr:1;
|
||||
/** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
|
||||
* Write 1 to clear the interrupt for SP exceeding the upper bound address of SP
|
||||
* monitored region.
|
||||
* Write 1 to clear BUS_MONITOR_CORE_0_SP_SPILL_MAX_INT.
|
||||
*/
|
||||
uint32_t core_0_sp_spill_max_clr:1;
|
||||
/** core_0_iram0_exception_monitor_clr : WT; bitpos: [10]; default: 0;
|
||||
* IBUS busy monitor interrupt clr
|
||||
*/
|
||||
uint32_t core_0_iram0_exception_monitor_clr:1;
|
||||
/** core_0_dram0_exception_monitor_clr : WT; bitpos: [11]; default: 0;
|
||||
* DBUS busy monitor interrupt clr
|
||||
*/
|
||||
uint32_t core_0_dram0_exception_monitor_clr:1;
|
||||
uint32_t reserved_12:20;
|
||||
uint32_t reserved_10:22;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_intr_clr_reg_t;
|
||||
} bus_monitor_core_0_intr_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: pc recording configuration register */
|
||||
/** Group: PC recording configuration register */
|
||||
/** Type of core_0_rcd_en register
|
||||
* HP CPU PC logging enable register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
|
||||
* Configures whether to enable PC logging.\\
|
||||
* 0: Disable\\
|
||||
* 1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time\\
|
||||
* Configures whether to enable PC and SP logging.
|
||||
* 0: Disable
|
||||
* 1: BUS_MONITOR_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time,
|
||||
* BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG starts to record SP in real time
|
||||
*/
|
||||
uint32_t core_0_rcd_recorden:1;
|
||||
/** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
|
||||
* Configures whether to enable HP CPU debugging.\\
|
||||
* 0: Disable\\
|
||||
* 1: HP CPU outputs PC\\
|
||||
* Configures whether to enable HP CPU debugging.
|
||||
* 0: Disable
|
||||
* 1: HP CPU outputs PC
|
||||
*/
|
||||
uint32_t core_0_rcd_pdebugen:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_rcd_en_reg_t;
|
||||
} bus_monitor_core_0_rcd_en_reg_t;
|
||||
|
||||
|
||||
/** Group: pc recording status register */
|
||||
/** Group: PC recording status registers */
|
||||
/** Type of core_0_rcd_pdebugpc register
|
||||
* PC logging register
|
||||
* HP CPU PC logging register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
@@ -477,10 +442,10 @@ typedef union {
|
||||
uint32_t core_0_rcd_pdebugpc:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_rcd_pdebugpc_reg_t;
|
||||
} bus_monitor_core_0_rcd_pdebugpc_reg_t;
|
||||
|
||||
/** Type of core_0_rcd_pdebugsp register
|
||||
* PC logging register
|
||||
* HP CPU SP logging register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
@@ -490,174 +455,12 @@ typedef union {
|
||||
uint32_t core_0_rcd_pdebugsp:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_rcd_pdebugsp_reg_t;
|
||||
} bus_monitor_core_0_rcd_pdebugsp_reg_t;
|
||||
|
||||
|
||||
/** Group: exception monitor register */
|
||||
/** Type of core_0_iram0_exception_monitor_0 register
|
||||
* exception monitor status register0
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_iram0_recording_addr_0 : RO; bitpos: [29:0]; default: 0;
|
||||
* reg_core_0_iram0_recording_addr_0
|
||||
*/
|
||||
uint32_t core_0_iram0_recording_addr_0:30;
|
||||
/** core_0_iram0_recording_wr_0 : RO; bitpos: [30]; default: 0;
|
||||
* reg_core_0_iram0_recording_wr_0
|
||||
*/
|
||||
uint32_t core_0_iram0_recording_wr_0:1;
|
||||
/** core_0_iram0_recording_loadstore_0 : RO; bitpos: [31]; default: 0;
|
||||
* reg_core_0_iram0_recording_loadstore_0
|
||||
*/
|
||||
uint32_t core_0_iram0_recording_loadstore_0:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_iram0_exception_monitor_0_reg_t;
|
||||
|
||||
/** Type of core_0_iram0_exception_monitor_1 register
|
||||
* exception monitor status register1
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_iram0_recording_addr_1 : RO; bitpos: [29:0]; default: 0;
|
||||
* reg_core_0_iram0_recording_addr_1
|
||||
*/
|
||||
uint32_t core_0_iram0_recording_addr_1:30;
|
||||
/** core_0_iram0_recording_wr_1 : RO; bitpos: [30]; default: 0;
|
||||
* reg_core_0_iram0_recording_wr_1
|
||||
*/
|
||||
uint32_t core_0_iram0_recording_wr_1:1;
|
||||
/** core_0_iram0_recording_loadstore_1 : RO; bitpos: [31]; default: 0;
|
||||
* reg_core_0_iram0_recording_loadstore_1
|
||||
*/
|
||||
uint32_t core_0_iram0_recording_loadstore_1:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_iram0_exception_monitor_1_reg_t;
|
||||
|
||||
/** Type of core_0_dram0_exception_monitor_0 register
|
||||
* exception monitor status register2
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_dram0_recording_wr_0 : RO; bitpos: [0]; default: 0;
|
||||
* reg_core_0_dram0_recording_wr_0
|
||||
*/
|
||||
uint32_t core_0_dram0_recording_wr_0:1;
|
||||
/** core_0_dram0_recording_byteen_0 : RO; bitpos: [4:1]; default: 0;
|
||||
* reg_core_0_dram0_recording_byteen_0
|
||||
*/
|
||||
uint32_t core_0_dram0_recording_byteen_0:4;
|
||||
uint32_t reserved_5:27;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_dram0_exception_monitor_0_reg_t;
|
||||
|
||||
/** Type of core_0_dram0_exception_monitor_1 register
|
||||
* exception monitor status register3
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_dram0_recording_addr_0 : RO; bitpos: [29:0]; default: 0;
|
||||
* reg_core_0_dram0_recording_addr_0
|
||||
*/
|
||||
uint32_t core_0_dram0_recording_addr_0:30;
|
||||
uint32_t reserved_30:2;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_dram0_exception_monitor_1_reg_t;
|
||||
|
||||
/** Type of core_0_dram0_exception_monitor_2 register
|
||||
* exception monitor status register4
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
|
||||
* reg_core_0_dram0_recording_pc_0
|
||||
*/
|
||||
uint32_t core_0_dram0_recording_pc_0:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_dram0_exception_monitor_2_reg_t;
|
||||
|
||||
/** Type of core_0_dram0_exception_monitor_3 register
|
||||
* exception monitor status register5
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_dram0_recording_wr_1 : RO; bitpos: [0]; default: 0;
|
||||
* reg_core_0_dram0_recording_wr_1
|
||||
*/
|
||||
uint32_t core_0_dram0_recording_wr_1:1;
|
||||
/** core_0_dram0_recording_byteen_1 : RO; bitpos: [4:1]; default: 0;
|
||||
* reg_core_0_dram0_recording_byteen_1
|
||||
*/
|
||||
uint32_t core_0_dram0_recording_byteen_1:4;
|
||||
uint32_t reserved_5:27;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_dram0_exception_monitor_3_reg_t;
|
||||
|
||||
/** Type of core_0_dram0_exception_monitor_4 register
|
||||
* exception monitor status register6
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_dram0_recording_addr_1 : RO; bitpos: [29:0]; default: 0;
|
||||
* reg_core_0_dram0_recording_addr_1
|
||||
*/
|
||||
uint32_t core_0_dram0_recording_addr_1:30;
|
||||
uint32_t reserved_30:2;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_dram0_exception_monitor_4_reg_t;
|
||||
|
||||
/** Type of core_0_dram0_exception_monitor_5 register
|
||||
* exception monitor status register7
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* reg_core_0_dram0_recording_pc_1
|
||||
*/
|
||||
uint32_t core_0_dram0_recording_pc_1:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_dram0_exception_monitor_5_reg_t;
|
||||
|
||||
/** Type of core_x_iram0_dram0_exception_monitor_0 register
|
||||
* exception monitor status register8
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0;
|
||||
* reg_core_x_iram0_dram0_limit_cycle_0
|
||||
*/
|
||||
uint32_t core_x_iram0_dram0_limit_cycle_0:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t;
|
||||
|
||||
/** Type of core_x_iram0_dram0_exception_monitor_1 register
|
||||
* exception monitor status register9
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0;
|
||||
* reg_core_x_iram0_dram0_limit_cycle_1
|
||||
*/
|
||||
uint32_t core_x_iram0_dram0_limit_cycle_1:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t;
|
||||
|
||||
|
||||
/** Group: cpu status registers */
|
||||
/** Group: CPU status registers */
|
||||
/** Type of core_0_lastpc_before_exception register
|
||||
* cpu status register
|
||||
* PC of the last command before HP CPU enters exception
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
@@ -667,106 +470,99 @@ typedef union {
|
||||
uint32_t core_0_lastpc_before_exc:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_lastpc_before_exception_reg_t;
|
||||
} bus_monitor_core_0_lastpc_before_exception_reg_t;
|
||||
|
||||
/** Type of core_0_debug_mode register
|
||||
* cpu status register
|
||||
* HP CPU debug mode status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** core_0_debug_mode : RO; bitpos: [0]; default: 0;
|
||||
* Represents whether RISC-V CPU (HP CPU) is in debugging mode.\\
|
||||
* 1: In debugging mode\\
|
||||
* 0: Not in debugging mode\\
|
||||
* Represents whether RISC-V CPU (HP CPU) is in debugging mode.
|
||||
* 1: In debugging mode
|
||||
* 0: Not in debugging mode
|
||||
*/
|
||||
uint32_t core_0_debug_mode:1;
|
||||
/** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
|
||||
* Represents the status of the RISC-V CPU (HP CPU) debug module.\\
|
||||
* 1: Active status\\
|
||||
* Other: Inactive status\\
|
||||
* Represents the status of the RISC-V CPU (HP CPU) debug module.
|
||||
* 1: Active status
|
||||
* Other: Inactive status
|
||||
*/
|
||||
uint32_t core_0_debug_module_active:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_core_0_debug_mode_reg_t;
|
||||
} bus_monitor_core_0_debug_mode_reg_t;
|
||||
|
||||
|
||||
/** Group: Configuration Registers */
|
||||
/** Group: Clock control register */
|
||||
/** Type of clock_gate register
|
||||
* Register clock control
|
||||
* Clock control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clk_en : R/W; bitpos: [0]; default: 1;
|
||||
* Configures whether to enable the register clock gating. \\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
* Configures whether to enable the register clock gating.
|
||||
* 0: Disable
|
||||
* 1: Enable
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_clock_gate_reg_t;
|
||||
} bus_monitor_clock_gate_reg_t;
|
||||
|
||||
|
||||
/** Group: Version control register */
|
||||
/** Type of date register
|
||||
* Version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [27:0]; default: 34640176;
|
||||
* version register
|
||||
* Version control register.
|
||||
*/
|
||||
uint32_t date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} assist_debug_date_reg_t;
|
||||
} bus_monitor_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile assist_debug_core_0_montr_ena_reg_t core_0_montr_ena;
|
||||
volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
|
||||
volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
|
||||
volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr;
|
||||
volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
|
||||
volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
|
||||
volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
|
||||
volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
|
||||
volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
|
||||
volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
|
||||
volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
|
||||
volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
|
||||
volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc;
|
||||
volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp;
|
||||
volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min;
|
||||
volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max;
|
||||
volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc;
|
||||
volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en;
|
||||
volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
|
||||
volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
|
||||
volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0;
|
||||
volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1;
|
||||
volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0;
|
||||
volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1;
|
||||
volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2;
|
||||
volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3;
|
||||
volatile assist_debug_core_0_dram0_exception_monitor_4_reg_t core_0_dram0_exception_monitor_4;
|
||||
volatile assist_debug_core_0_dram0_exception_monitor_5_reg_t core_0_dram0_exception_monitor_5;
|
||||
volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
|
||||
volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode;
|
||||
uint32_t reserved_078[34];
|
||||
volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0;
|
||||
volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1;
|
||||
volatile assist_debug_clock_gate_reg_t clock_gate;
|
||||
volatile bus_monitor_core_0_montr_ena_reg_t core_0_montr_ena;
|
||||
volatile bus_monitor_core_0_intr_raw_reg_t core_0_intr_raw;
|
||||
volatile bus_monitor_core_0_intr_ena_reg_t core_0_intr_ena;
|
||||
volatile bus_monitor_core_0_intr_clr_reg_t core_0_intr_clr;
|
||||
volatile bus_monitor_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
|
||||
volatile bus_monitor_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
|
||||
volatile bus_monitor_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
|
||||
volatile bus_monitor_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
|
||||
volatile bus_monitor_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
|
||||
volatile bus_monitor_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
|
||||
volatile bus_monitor_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
|
||||
volatile bus_monitor_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
|
||||
volatile bus_monitor_core_0_area_pc_reg_t core_0_area_pc;
|
||||
volatile bus_monitor_core_0_area_sp_reg_t core_0_area_sp;
|
||||
volatile bus_monitor_core_0_sp_min_reg_t core_0_sp_min;
|
||||
volatile bus_monitor_core_0_sp_max_reg_t core_0_sp_max;
|
||||
volatile bus_monitor_core_0_sp_pc_reg_t core_0_sp_pc;
|
||||
volatile bus_monitor_core_0_rcd_en_reg_t core_0_rcd_en;
|
||||
volatile bus_monitor_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
|
||||
volatile bus_monitor_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
|
||||
uint32_t reserved_050[8];
|
||||
volatile bus_monitor_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
|
||||
volatile bus_monitor_core_0_debug_mode_reg_t core_0_debug_mode;
|
||||
uint32_t reserved_078[36];
|
||||
volatile bus_monitor_clock_gate_reg_t clock_gate;
|
||||
uint32_t reserved_10c[188];
|
||||
volatile assist_debug_date_reg_t date;
|
||||
} assist_debug_dev_t;
|
||||
volatile bus_monitor_date_reg_t date;
|
||||
} bus_monitor_dev_t;
|
||||
|
||||
extern assist_debug_dev_t ASSIST_DEBUG;
|
||||
extern bus_monitor_dev_t ASSIST_DEBUG;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
|
||||
_Static_assert(sizeof(bus_monitor_dev_t) == 0x400, "Invalid size of bus_monitor_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -12,63 +12,55 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
/** MEM_MONITOR_LOG_SETTING_REG register
|
||||
* Bus access logging configuration register
|
||||
* Configures bus access logging
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
|
||||
/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [3:0]; default: 0;
|
||||
* Configures monitoring modes.bit[0]: Configures write monitoring. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* bit[1]: Configures word monitoring. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* bit[2]: Configures halfword monitoring. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* bit[3]: Configures byte monitoring. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Configures monitoring modes.
|
||||
* 1: Enable write monitoring
|
||||
* 2: Enable word monitoring
|
||||
* 4: Enable halfword monitoring
|
||||
* 8: Enable byte monitoring
|
||||
* Other values: Invalid
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MODE 0x0000000FU
|
||||
#define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
|
||||
#define MEM_MONITOR_LOG_MODE_V 0x0000000FU
|
||||
#define MEM_MONITOR_LOG_MODE_S 0
|
||||
/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [4]; default: 1;
|
||||
* Configures the writing mode for recorded data.1: Loop mode\\
|
||||
* 0: Non-loop mode\\
|
||||
* Configures the writing mode for recorded data.
|
||||
* 0: Non-loop mode
|
||||
* 1: Loop mode
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(4))
|
||||
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
|
||||
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x00000001U
|
||||
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 4
|
||||
/** MEM_MONITOR_LOG_CORE_ENA : R/W; bitpos: [15:8]; default: 0;
|
||||
* Configures whether to enable CPU bus access logging.bit[0]: Configures whether to
|
||||
* enable HP CPU bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
* Configures whether to enable HP CPU bus access logging.
|
||||
* 0: Disable
|
||||
* 1: Enable
|
||||
* Other values: Invalid
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_CORE_ENA 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_CORE_ENA_M (MEM_MONITOR_LOG_CORE_ENA_V << MEM_MONITOR_LOG_CORE_ENA_S)
|
||||
#define MEM_MONITOR_LOG_CORE_ENA_V 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_CORE_ENA_S 8
|
||||
/** MEM_MONITOR_LOG_DMA_0_ENA : R/W; bitpos: [23:16]; default: 0;
|
||||
* Configures whether to enable DMA_0 bus access logging.bit[0]: Configures whether
|
||||
* to enable DMA_0 bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
* Configures whether to enable DMA_0 bus access logging.
|
||||
* 0: Disable
|
||||
* 1: Enable
|
||||
* Other values: Invalid
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_DMA_0_ENA 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_DMA_0_ENA_M (MEM_MONITOR_LOG_DMA_0_ENA_V << MEM_MONITOR_LOG_DMA_0_ENA_S)
|
||||
#define MEM_MONITOR_LOG_DMA_0_ENA_V 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_DMA_0_ENA_S 16
|
||||
/** MEM_MONITOR_LOG_DMA_1_ENA : R/W; bitpos: [31:24]; default: 0;
|
||||
* Configures whether to enable DMA_1 bus access logging.bit[0]: Configures whether
|
||||
* to enable DMA_1 bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
* Configures whether to enable DMA_1 bus access logging.
|
||||
* 0: Disable
|
||||
* 1: Enable
|
||||
* Other values: Invalid
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_DMA_1_ENA 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_DMA_1_ENA_M (MEM_MONITOR_LOG_DMA_1_ENA_V << MEM_MONITOR_LOG_DMA_1_ENA_S)
|
||||
@@ -76,26 +68,24 @@ extern "C" {
|
||||
#define MEM_MONITOR_LOG_DMA_1_ENA_S 24
|
||||
|
||||
/** MEM_MONITOR_LOG_SETTING1_REG register
|
||||
* Bus access logging configuration register
|
||||
* Configures bus access logging
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_SETTING1_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
|
||||
/** MEM_MONITOR_LOG_DMA_2_ENA : R/W; bitpos: [7:0]; default: 0;
|
||||
* Configures whether to enable DMA_2 bus access logging.bit[0]: Configures whether
|
||||
* to enable DMA_2 bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
* Configures whether to enable DMA_2 bus access logging.
|
||||
* 0: Disable
|
||||
* 1: Enable
|
||||
* Other values: Invalid
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_DMA_2_ENA 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_DMA_2_ENA_M (MEM_MONITOR_LOG_DMA_2_ENA_V << MEM_MONITOR_LOG_DMA_2_ENA_S)
|
||||
#define MEM_MONITOR_LOG_DMA_2_ENA_V 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_DMA_2_ENA_S 0
|
||||
/** MEM_MONITOR_LOG_DMA_3_ENA : R/W; bitpos: [15:8]; default: 0;
|
||||
* Configures whether to enable DMA_3 bus access logging.bit[0]: Configures whether
|
||||
* to enable DMA_3 bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
* Configures whether to enable DMA_3 bus access logging.
|
||||
* 0: Disable
|
||||
* 1: Enable
|
||||
* Other values: Invalid
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_DMA_3_ENA 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_DMA_3_ENA_M (MEM_MONITOR_LOG_DMA_3_ENA_V << MEM_MONITOR_LOG_DMA_3_ENA_S)
|
||||
@@ -103,7 +93,7 @@ extern "C" {
|
||||
#define MEM_MONITOR_LOG_DMA_3_ENA_S 8
|
||||
|
||||
/** MEM_MONITOR_LOG_CHECK_DATA_REG register
|
||||
* Configures monitored data in Bus access logging
|
||||
* Configures data to be monitored for bus access logging
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
|
||||
/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
|
||||
@@ -115,27 +105,28 @@ extern "C" {
|
||||
#define MEM_MONITOR_LOG_CHECK_DATA_S 0
|
||||
|
||||
/** MEM_MONITOR_LOG_DATA_MASK_REG register
|
||||
* Configures masked data in Bus access logging
|
||||
* Configures data mask for bus access logging
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
|
||||
/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
|
||||
* Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask.bit[0]:
|
||||
* Configures whether to mask the least significant byte of
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG.\\
|
||||
* 0: Not mask \\
|
||||
* 1: Mask\\
|
||||
* Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask. Multiple bytes
|
||||
* can be masked at the same time.
|
||||
* bit[0]: Configures whether to mask the least significant byte of
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG.
|
||||
* 0: Not mask
|
||||
* 1: Mask
|
||||
* bit[1]: Configures whether to mask the second least significant byte of
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
|
||||
* 0: Not mask \\
|
||||
* 1: Mask\\
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG.
|
||||
* 0: Not mask
|
||||
* 1: Mask
|
||||
* bit[2]: Configures whether to mask the second most significant byte of
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
|
||||
* 0: Not mask \\
|
||||
* 1: Mask\\
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG.
|
||||
* 0: Not mask
|
||||
* 1: Mask
|
||||
* bit[3]: Configures whether to mask the most significant byte of
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
|
||||
* 0: Not mask \\
|
||||
* 1: Mask\\
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG.
|
||||
* 0: Not mask
|
||||
* 1: Mask
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU
|
||||
#define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
|
||||
@@ -143,7 +134,7 @@ extern "C" {
|
||||
#define MEM_MONITOR_LOG_DATA_MASK_S 0
|
||||
|
||||
/** MEM_MONITOR_LOG_MIN_REG register
|
||||
* Configures monitored address space in Bus access logging
|
||||
* Configures the monitored lower address for bus access logging
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
|
||||
/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
|
||||
@@ -155,7 +146,7 @@ extern "C" {
|
||||
#define MEM_MONITOR_LOG_MIN_S 0
|
||||
|
||||
/** MEM_MONITOR_LOG_MAX_REG register
|
||||
* Configures monitored address space in Bus access logging
|
||||
* Configures the monitored upper address for bus access logging
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
|
||||
/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
|
||||
@@ -167,25 +158,26 @@ extern "C" {
|
||||
#define MEM_MONITOR_LOG_MAX_S 0
|
||||
|
||||
/** MEM_MONITOR_LOG_MON_ADDR_UPDATE_0_REG register
|
||||
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
|
||||
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
|
||||
* Configures whether to update the monitored address space for HP CPU bus access
|
||||
* logging
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_UPDATE_0_REG (DR_REG_MEM_MONITOR_BASE + 0x18)
|
||||
/** MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE : WT; bitpos: [7:0]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the HP CPU bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
* Configures whether to update the monitored address space of the HP CPU bus as the
|
||||
* address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG.
|
||||
* 0: Not update
|
||||
* 1: Update
|
||||
* Other values: Invalid
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_S)
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_V 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_S 0
|
||||
/** MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE : WT; bitpos: [31]; default: 0;
|
||||
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
|
||||
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Configures whether to update the monitored address space of all masters as the
|
||||
* address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG.
|
||||
* 0: Not update
|
||||
* 1: Update
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE (BIT(31))
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_S)
|
||||
@@ -193,49 +185,49 @@ extern "C" {
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_S 31
|
||||
|
||||
/** MEM_MONITOR_LOG_MON_ADDR_UPDATE_1_REG register
|
||||
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
|
||||
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
|
||||
* Configures whether to update the monitored address space for DMA_0 bus access
|
||||
* logging
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_UPDATE_1_REG (DR_REG_MEM_MONITOR_BASE + 0x1c)
|
||||
/** MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE : WT; bitpos: [7:0]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the DMA_0 bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
* Configures whether to update the monitored address space of the DMA_0 bus as the
|
||||
* address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG.
|
||||
* 0: Not update
|
||||
* 1: Update
|
||||
* Other values: Invalid
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_S)
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_V 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_S 0
|
||||
/** MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE : WT; bitpos: [15:8]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the DMA_1 bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
* Configures whether to update the monitored address space of the DMA_1 bus as the
|
||||
* address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG.
|
||||
* 0: Not update
|
||||
* 1: Update
|
||||
* Other values: Invalid
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_S)
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_V 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_S 8
|
||||
/** MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE : WT; bitpos: [23:16]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the DMA_2 bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
* Configures whether to update the monitored address space of the DMA_2 bus as the
|
||||
* address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG.
|
||||
* 0: Not update
|
||||
* 1: Update
|
||||
* Other values: Invalid
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_S)
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_V 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_S 16
|
||||
/** MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE : WT; bitpos: [31:24]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the DMA_3 bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
* Configures whether to update the monitored address space of the DMA_3 bus as the
|
||||
* address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG.
|
||||
* 0: Not update
|
||||
* 1: Update
|
||||
* Other values: Invalid
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_S)
|
||||
@@ -284,9 +276,10 @@ extern "C" {
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x2c)
|
||||
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
|
||||
* Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to
|
||||
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update \\
|
||||
* 0: Not update (default) \\
|
||||
* Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to the
|
||||
* value of MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.
|
||||
* 0: Not update
|
||||
* 1: Update
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0))
|
||||
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
|
||||
@@ -294,21 +287,22 @@ extern "C" {
|
||||
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0
|
||||
|
||||
/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
|
||||
* Logging overflow status register
|
||||
* Represents logging buffer overflow status register
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x30)
|
||||
/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
|
||||
* Represents whether data overflows the storage space.0: Not Overflow\\
|
||||
* 1: Overflow\\
|
||||
* Represents whether data overflows the storage space.
|
||||
* 0: Not Overflow
|
||||
* 1: Overflow
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0))
|
||||
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
|
||||
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U
|
||||
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0
|
||||
/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
|
||||
* Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not
|
||||
* clear\\
|
||||
* 1: Clear\\
|
||||
* Configures whether to clear theMEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.
|
||||
* 0: Not clear (default)
|
||||
* 1: Clear
|
||||
*/
|
||||
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1))
|
||||
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
|
||||
@@ -316,12 +310,13 @@ extern "C" {
|
||||
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1
|
||||
|
||||
/** MEM_MONITOR_CLOCK_GATE_REG register
|
||||
* Register clock control
|
||||
* Clock gating control register
|
||||
*/
|
||||
#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x34)
|
||||
/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
|
||||
* Configures whether to enable the register clock gating.0: Disable\\
|
||||
* 1: Enable\\
|
||||
* Configures whether to enable the register clock gating.
|
||||
* 0: Disable
|
||||
* 1: Enable
|
||||
*/
|
||||
#define MEM_MONITOR_CLK_EN (BIT(0))
|
||||
#define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -10,55 +10,47 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: configuration registers */
|
||||
/** Group: Bus logging configuration registers */
|
||||
/** Type of log_setting register
|
||||
* Bus access logging configuration register
|
||||
* Configures bus access logging
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_mode : R/W; bitpos: [3:0]; default: 0;
|
||||
* Configures monitoring modes.bit[0]: Configures write monitoring. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* bit[1]: Configures word monitoring. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* bit[2]: Configures halfword monitoring. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* bit[3]: Configures byte monitoring. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Configures monitoring modes.
|
||||
* 1: Enable write monitoring
|
||||
* 2: Enable word monitoring
|
||||
* 4: Enable halfword monitoring
|
||||
* 8: Enable byte monitoring
|
||||
* Other values: Invalid
|
||||
*/
|
||||
uint32_t log_mode:4;
|
||||
/** log_mem_loop_enable : R/W; bitpos: [4]; default: 1;
|
||||
* Configures the writing mode for recorded data.1: Loop mode\\
|
||||
* 0: Non-loop mode\\
|
||||
* Configures the writing mode for recorded data.
|
||||
* 0: Non-loop mode
|
||||
* 1: Loop mode
|
||||
*/
|
||||
uint32_t log_mem_loop_enable:1;
|
||||
uint32_t reserved_5:3;
|
||||
/** log_core_ena : R/W; bitpos: [15:8]; default: 0;
|
||||
* Configures whether to enable CPU bus access logging.bit[0]: Configures whether to
|
||||
* enable HP CPU bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
* Configures whether to enable HP CPU bus access logging.
|
||||
* 0: Disable
|
||||
* 1: Enable
|
||||
* Other values: Invalid
|
||||
*/
|
||||
uint32_t log_core_ena:8;
|
||||
/** log_dma_0_ena : R/W; bitpos: [23:16]; default: 0;
|
||||
* Configures whether to enable DMA_0 bus access logging.bit[0]: Configures whether
|
||||
* to enable DMA_0 bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
* Configures whether to enable DMA_0 bus access logging.
|
||||
* 0: Disable
|
||||
* 1: Enable
|
||||
* Other values: Invalid
|
||||
*/
|
||||
uint32_t log_dma_0_ena:8;
|
||||
/** log_dma_1_ena : R/W; bitpos: [31:24]; default: 0;
|
||||
* Configures whether to enable DMA_1 bus access logging.bit[0]: Configures whether
|
||||
* to enable DMA_1 bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
* Configures whether to enable DMA_1 bus access logging.
|
||||
* 0: Disable
|
||||
* 1: Enable
|
||||
* Other values: Invalid
|
||||
*/
|
||||
uint32_t log_dma_1_ena:8;
|
||||
};
|
||||
@@ -66,24 +58,22 @@ typedef union {
|
||||
} mem_monitor_log_setting_reg_t;
|
||||
|
||||
/** Type of log_setting1 register
|
||||
* Bus access logging configuration register
|
||||
* Configures bus access logging
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_dma_2_ena : R/W; bitpos: [7:0]; default: 0;
|
||||
* Configures whether to enable DMA_2 bus access logging.bit[0]: Configures whether
|
||||
* to enable DMA_2 bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
* Configures whether to enable DMA_2 bus access logging.
|
||||
* 0: Disable
|
||||
* 1: Enable
|
||||
* Other values: Invalid
|
||||
*/
|
||||
uint32_t log_dma_2_ena:8;
|
||||
/** log_dma_3_ena : R/W; bitpos: [15:8]; default: 0;
|
||||
* Configures whether to enable DMA_3 bus access logging.bit[0]: Configures whether
|
||||
* to enable DMA_3 bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
* Configures whether to enable DMA_3 bus access logging.
|
||||
* 0: Disable
|
||||
* 1: Enable
|
||||
* Other values: Invalid
|
||||
*/
|
||||
uint32_t log_dma_3_ena:8;
|
||||
uint32_t reserved_16:16;
|
||||
@@ -92,7 +82,7 @@ typedef union {
|
||||
} mem_monitor_log_setting1_reg_t;
|
||||
|
||||
/** Type of log_check_data register
|
||||
* Configures monitored data in Bus access logging
|
||||
* Configures data to be monitored for bus access logging
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
@@ -105,28 +95,29 @@ typedef union {
|
||||
} mem_monitor_log_check_data_reg_t;
|
||||
|
||||
/** Type of log_data_mask register
|
||||
* Configures masked data in Bus access logging
|
||||
* Configures data mask for bus access logging
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_data_mask : R/W; bitpos: [3:0]; default: 0;
|
||||
* Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask.bit[0]:
|
||||
* Configures whether to mask the least significant byte of
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG.\\
|
||||
* 0: Not mask \\
|
||||
* 1: Mask\\
|
||||
* Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask. Multiple bytes
|
||||
* can be masked at the same time.
|
||||
* bit[0]: Configures whether to mask the least significant byte of
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG.
|
||||
* 0: Not mask
|
||||
* 1: Mask
|
||||
* bit[1]: Configures whether to mask the second least significant byte of
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
|
||||
* 0: Not mask \\
|
||||
* 1: Mask\\
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG.
|
||||
* 0: Not mask
|
||||
* 1: Mask
|
||||
* bit[2]: Configures whether to mask the second most significant byte of
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
|
||||
* 0: Not mask \\
|
||||
* 1: Mask\\
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG.
|
||||
* 0: Not mask
|
||||
* 1: Mask
|
||||
* bit[3]: Configures whether to mask the most significant byte of
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
|
||||
* 0: Not mask \\
|
||||
* 1: Mask\\
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG.
|
||||
* 0: Not mask
|
||||
* 1: Mask
|
||||
*/
|
||||
uint32_t log_data_mask:4;
|
||||
uint32_t reserved_4:28;
|
||||
@@ -135,7 +126,7 @@ typedef union {
|
||||
} mem_monitor_log_data_mask_reg_t;
|
||||
|
||||
/** Type of log_min register
|
||||
* Configures monitored address space in Bus access logging
|
||||
* Configures the monitored lower address for bus access logging
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
@@ -148,7 +139,7 @@ typedef union {
|
||||
} mem_monitor_log_min_reg_t;
|
||||
|
||||
/** Type of log_max register
|
||||
* Configures monitored address space in Bus access logging
|
||||
* Configures the monitored upper address for bus access logging
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
@@ -161,24 +152,25 @@ typedef union {
|
||||
} mem_monitor_log_max_reg_t;
|
||||
|
||||
/** Type of log_mon_addr_update_0 register
|
||||
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
|
||||
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
|
||||
* Configures whether to update the monitored address space for HP CPU bus access
|
||||
* logging
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_mon_addr_core_update : WT; bitpos: [7:0]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the HP CPU bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
* Configures whether to update the monitored address space of the HP CPU bus as the
|
||||
* address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG.
|
||||
* 0: Not update
|
||||
* 1: Update
|
||||
* Other values: Invalid
|
||||
*/
|
||||
uint32_t log_mon_addr_core_update:8;
|
||||
uint32_t reserved_8:23;
|
||||
/** log_mon_addr_all_update : WT; bitpos: [31]; default: 0;
|
||||
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
|
||||
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Configures whether to update the monitored address space of all masters as the
|
||||
* address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG.
|
||||
* 0: Not update
|
||||
* 1: Update
|
||||
*/
|
||||
uint32_t log_mon_addr_all_update:1;
|
||||
};
|
||||
@@ -186,41 +178,41 @@ typedef union {
|
||||
} mem_monitor_log_mon_addr_update_0_reg_t;
|
||||
|
||||
/** Type of log_mon_addr_update_1 register
|
||||
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
|
||||
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
|
||||
* Configures whether to update the monitored address space for DMA_0 bus access
|
||||
* logging
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_mon_addr_dma_0_update : WT; bitpos: [7:0]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the DMA_0 bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
* Configures whether to update the monitored address space of the DMA_0 bus as the
|
||||
* address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG.
|
||||
* 0: Not update
|
||||
* 1: Update
|
||||
* Other values: Invalid
|
||||
*/
|
||||
uint32_t log_mon_addr_dma_0_update:8;
|
||||
/** log_mon_addr_dma_1_update : WT; bitpos: [15:8]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the DMA_1 bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
* Configures whether to update the monitored address space of the DMA_1 bus as the
|
||||
* address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG.
|
||||
* 0: Not update
|
||||
* 1: Update
|
||||
* Other values: Invalid
|
||||
*/
|
||||
uint32_t log_mon_addr_dma_1_update:8;
|
||||
/** log_mon_addr_dma_2_update : WT; bitpos: [23:16]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the DMA_2 bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
* Configures whether to update the monitored address space of the DMA_2 bus as the
|
||||
* address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG.
|
||||
* 0: Not update
|
||||
* 1: Update
|
||||
* Other values: Invalid
|
||||
*/
|
||||
uint32_t log_mon_addr_dma_2_update:8;
|
||||
/** log_mon_addr_dma_3_update : WT; bitpos: [31:24]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the DMA_3 bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
* Configures whether to update the monitored address space of the DMA_3 bus as the
|
||||
* address space from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG.
|
||||
* 0: Not update
|
||||
* 1: Update
|
||||
* Other values: Invalid
|
||||
*/
|
||||
uint32_t log_mon_addr_dma_3_update:8;
|
||||
};
|
||||
@@ -273,9 +265,10 @@ typedef union {
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_mem_addr_update : WT; bitpos: [0]; default: 0;
|
||||
* Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to
|
||||
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update \\
|
||||
* 0: Not update (default) \\
|
||||
* Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to the
|
||||
* value of MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.
|
||||
* 0: Not update
|
||||
* 1: Update
|
||||
*/
|
||||
uint32_t log_mem_addr_update:1;
|
||||
uint32_t reserved_1:31;
|
||||
@@ -284,19 +277,20 @@ typedef union {
|
||||
} mem_monitor_log_mem_addr_update_reg_t;
|
||||
|
||||
/** Type of log_mem_full_flag register
|
||||
* Logging overflow status register
|
||||
* Represents logging buffer overflow status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_mem_full_flag : RO; bitpos: [0]; default: 0;
|
||||
* Represents whether data overflows the storage space.0: Not Overflow\\
|
||||
* 1: Overflow\\
|
||||
* Represents whether data overflows the storage space.
|
||||
* 0: Not Overflow
|
||||
* 1: Overflow
|
||||
*/
|
||||
uint32_t log_mem_full_flag:1;
|
||||
/** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0;
|
||||
* Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not
|
||||
* clear\\
|
||||
* 1: Clear\\
|
||||
* Configures whether to clear theMEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.
|
||||
* 0: Not clear (default)
|
||||
* 1: Clear
|
||||
*/
|
||||
uint32_t clr_log_mem_full_flag:1;
|
||||
uint32_t reserved_2:30;
|
||||
@@ -305,15 +299,16 @@ typedef union {
|
||||
} mem_monitor_log_mem_full_flag_reg_t;
|
||||
|
||||
|
||||
/** Group: clk register */
|
||||
/** Group: Clock gating control register */
|
||||
/** Type of clock_gate register
|
||||
* Register clock control
|
||||
* Clock gating control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clk_en : R/W; bitpos: [0]; default: 0;
|
||||
* Configures whether to enable the register clock gating.0: Disable\\
|
||||
* 1: Enable\\
|
||||
* Configures whether to enable the register clock gating.
|
||||
* 0: Disable
|
||||
* 1: Enable
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
uint32_t reserved_1:31;
|
||||
@@ -322,7 +317,7 @@ typedef union {
|
||||
} mem_monitor_clock_gate_reg_t;
|
||||
|
||||
|
||||
/** Group: version register */
|
||||
/** Group: Version control register */
|
||||
/** Type of date register
|
||||
* Version control register
|
||||
*/
|
||||
|
||||
Reference in New Issue
Block a user