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Merge branch 'feat/kconfig_clk_rm' into 'master'

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feat(esp_eth): removed RMII CLK Kconfig option

Closes IDF-9724

See merge request espressif/esp-idf!41853
This commit is contained in:
Ondrej Kosta
2025-09-19 15:35:50 +08:00
parent 79c69cfa17 5aa97623c1
commit bc421db41b
19 changed files with 102 additions and 224 deletions
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68
components/esp_eth/Kconfig
View File

@@ -13,74 +13,6 @@ menu "Ethernet"
ESP32 integrates a 10/100M Ethernet MAC controller.
if ETH_USE_ESP32_EMAC
choice ETH_PHY_INTERFACE
prompt "PHY interface"
default ETH_PHY_INTERFACE_RMII
help
Select the communication interface between MAC and PHY chip.
config ETH_PHY_INTERFACE_RMII
bool "Reduced Media Independent Interface (RMII)"
endchoice
if ETH_PHY_INTERFACE_RMII
choice ETH_RMII_CLK_MODE # IDF-9724
depends on IDF_TARGET_ESP32
prompt "RMII clock mode"
default ETH_RMII_CLK_INPUT
help
Select external or internal RMII clock.
config ETH_RMII_CLK_INPUT
bool "Input RMII clock from external"
help
MAC will get RMII clock from outside.
Note that ESP32 only supports GPIO0 to input the RMII clock.
config ETH_RMII_CLK_OUTPUT
bool "Output RMII clock from internal"
help
ESP32 can generate RMII clock by internal APLL.
This clock can be routed to the external PHY device.
ESP32 supports to route the RMII clock to GPIO0/16/17.
endchoice
endif # ETH_PHY_INTERFACE_RMII
if ETH_RMII_CLK_INPUT
config ETH_RMII_CLK_IN_GPIO
depends on IDF_TARGET_ESP32
int
range 0 0
default 0
help
ESP32 only supports GPIO0 to input the RMII clock.
endif # ETH_RMII_CLK_INPUT
if ETH_RMII_CLK_OUTPUT
config ETH_RMII_CLK_OUTPUT_GPIO0
depends on IDF_TARGET_ESP32
bool "Output RMII clock from GPIO0 (Experimental!)"
default n
help
GPIO0 can be set to output a pre-divided PLL clock. Enabling this option will configure
GPIO0 to output a 50MHz clock. In fact this clock doesn't have directly relationship with
EMAC peripheral. Sometimes this clock may not work well with your PHY chip.
WARNING: If you want the Ethernet to work with WiFi, don’t select ESP32 as RMII CLK output
as it would result in clock instability!
if !ETH_RMII_CLK_OUTPUT_GPIO0
config ETH_RMII_CLK_OUT_GPIO
depends on IDF_TARGET_ESP32
int "RMII clock GPIO number"
range 16 17
default 17
help
Set the GPIO number to output RMII Clock.
WARNING: If you want the Ethernet to work with WiFi, don’t select ESP32 as RMII CLK output
as it would result in clock instability!
endif # !ETH_RMII_CLK_OUTPUT_GPIO0
endif # ETH_RMII_CLK_OUTPUT
config ETH_DMA_BUFFER_SIZE
int "Ethernet DMA buffer size (Byte)"
range 256 1600

100
components/esp_eth/include/esp_eth_mac_esp.h
View File

@@ -22,20 +22,10 @@ extern "C" {
*
*/
typedef enum {
/**
* @brief Default values configured using Kconfig are going to be used when "Default" selected.
*
* @warning Deprecated option. Clock configuration using Kconfig is limitedly supported only for ESP32 SoC via @c ETH_ESP32_EMAC_DEFAULT_CONFIG
* and is going to be reevaluated in the next major release.
* Clock mode and clock GPIO number is supposed to be defined in `EMAC specific configuration` structure from user's code.
*
*/
EMAC_CLK_DEFAULT __attribute__((deprecated)), // IDF-9724
/**
* @brief Input RMII Clock from external. EMAC Clock GPIO number needs to be configured when this option is selected.
*
* @note MAC will get RMII clock from outside. Note that ESP32 only supports GPIO0 to input the RMII clock.
* @note See components/soc/esp32(*)/emac_periph.c for available GPIO numbers.
*
*/
EMAC_CLK_EXT_IN,
@@ -43,55 +33,15 @@ typedef enum {
/**
* @brief Output RMII Clock from internal (A/M)PLL Clock. EMAC Clock GPIO number needs to be configured when this option is selected.
*
* @warning ESP32 Errata: If you want the Ethernet to work with Wi-Fi or BT, don’t select ESP32 as RMII CLK output as it would result in clock instability.
* Applicable only to ESP32, other ESP32 SoCs are not affected.
*
* @note See components/soc/esp32(*)/emac_periph.c for available GPIO numbers.
*
*/
EMAC_CLK_OUT
} emac_rmii_clock_mode_t;
#if CONFIG_IDF_TARGET_ESP32
/**
* @brief RMII Clock GPIO number Options for ESP32
*
* @warning If you want the Ethernet to work with WiFi, don’t select ESP32 as RMII CLK output as it would result in clock instability.
*
*/
typedef enum {
/**
* @brief MAC will get RMII clock from outside at this GPIO.
*
* @note ESP32 only supports GPIO0 to input the RMII clock.
*
*/
EMAC_CLK_IN_GPIO = 0,
/**
* @brief Output RMII Clock from internal APLL Clock available at GPIO0
*
* @note GPIO0 can be set to output a pre-divided PLL clock. Enabling this option will configure GPIO0 to output a 50MHz clock.
* In fact this clock doesn’t have directly relationship with EMAC peripheral. Sometimes this clock may not work well with your PHY chip.
*
*/
EMAC_APPL_CLK_OUT_GPIO = 0,
/**
* @brief Output RMII Clock from internal APLL Clock available at GPIO16
*
*/
EMAC_CLK_OUT_GPIO = 16,
/**
* @brief Inverted Output RMII Clock from internal APLL Clock available at GPIO17
*
*/
EMAC_CLK_OUT_180_GPIO = 17
} emac_rmii_clock_gpio_t;
#else
/**
* @brief RMII Clock GPIO number
*
*/
typedef int emac_rmii_clock_gpio_t;
#endif // CONFIG_IDF_TARGET_ESP32
/**
* @brief Ethernet MAC Clock Configuration
*
@@ -102,8 +52,8 @@ typedef union {
// Reserved for GPIO number, clock source, etc. in MII mode
} mii; /*!< EMAC MII Clock Configuration */
struct {
emac_rmii_clock_mode_t clock_mode; /*!< RMII Clock Mode Configuration */
emac_rmii_clock_gpio_t clock_gpio; /*!< RMII Clock GPIO Configuration */
emac_rmii_clock_mode_t clock_mode; /*!< RMII Clock Mode Configuration */
int clock_gpio; /*!< RMII Clock GPIO Configuration */
} rmii; /*!< EMAC RMII Clock Configuration */
} eth_mac_clock_config_t;
@@ -165,13 +115,7 @@ typedef union {
*
*/
typedef struct {
union {
emac_esp_smi_gpio_config_t smi_gpio; /*!< SMI GPIO numbers */
struct {
int smi_mdc_gpio_num __attribute__((deprecated("Please use smi_gpio instead"))); /*!< SMI MDC GPIO number, set to -1 could bypass the SMI GPIO configuration */
int smi_mdio_gpio_num __attribute__((deprecated("Please use smi_gpio instead"))); /*!< SMI MDIO GPIO number, set to -1 could bypass the SMI GPIO configuration */
};
};
emac_esp_smi_gpio_config_t smi_gpio; /*!< SMI GPIO numbers */
eth_data_interface_t interface; /*!< EMAC Data interface to PHY (MII/RMII) */
eth_mac_clock_config_t clock_config; /*!< EMAC Interface clock configuration */
eth_mac_dma_burst_len_t dma_burst_len; /*!< EMAC DMA burst length for both Tx and Rx */
@@ -223,24 +167,6 @@ typedef bool (*ts_target_exceed_cb_from_isr_t)(esp_eth_mediator_t *eth, void *us
*
*/
#if CONFIG_IDF_TARGET_ESP32
#if CONFIG_ETH_RMII_CLK_INPUT // IDF-9724
#define DEFAULT_RMII_CLK_MODE EMAC_CLK_EXT_IN
#if CONFIG_ETH_RMII_CLK_IN_GPIO == 0
#define DEFAULT_RMII_CLK_GPIO CONFIG_ETH_RMII_CLK_IN_GPIO
#else
#error "ESP32 EMAC only support input RMII clock to GPIO0"
#endif // CONFIG_ETH_RMII_CLK_IN_GPIO == 0
#elif CONFIG_ETH_RMII_CLK_OUTPUT
#define DEFAULT_RMII_CLK_MODE EMAC_CLK_OUT
#if CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0
#define DEFAULT_RMII_CLK_GPIO EMAC_APPL_CLK_OUT_GPIO
#else
#define DEFAULT_RMII_CLK_GPIO CONFIG_ETH_RMII_CLK_OUT_GPIO
#endif // CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0
#else
#error "Unsupported RMII clock mode"
#endif // CONFIG_ETH_RMII_CLK_INPUT
#define ETH_ESP32_EMAC_DEFAULT_CONFIG() \
{ \
.smi_gpio = \
@@ -253,8 +179,8 @@ typedef bool (*ts_target_exceed_cb_from_isr_t)(esp_eth_mediator_t *eth, void *us
{ \
.rmii = \
{ \
.clock_mode = DEFAULT_RMII_CLK_MODE, \
.clock_gpio = (emac_rmii_clock_gpio_t) DEFAULT_RMII_CLK_GPIO \
.clock_mode = EMAC_CLK_EXT_IN, \
.clock_gpio = 0 \
} \
}, \
.dma_burst_len = ETH_DMA_BURST_LEN_32, \
@@ -274,7 +200,7 @@ typedef bool (*ts_target_exceed_cb_from_isr_t)(esp_eth_mediator_t *eth, void *us
.rmii = \
{ \
.clock_mode = EMAC_CLK_EXT_IN, \
.clock_gpio = (emac_rmii_clock_gpio_t) 50 \
.clock_gpio = 50 \
} \
}, \
.dma_burst_len = ETH_DMA_BURST_LEN_32, \
@@ -296,7 +222,7 @@ typedef bool (*ts_target_exceed_cb_from_isr_t)(esp_eth_mediator_t *eth, void *us
.rmii = \
{ \
.clock_mode = EMAC_CLK_EXT_IN, \
.clock_gpio = (emac_rmii_clock_gpio_t) -1 \
.clock_gpio = -1 \
} \
}, \
}

6
components/esp_eth/src/mac/esp_eth_mac_esp.c
View File

@@ -876,9 +876,9 @@ static esp_err_t emac_esp_config_data_interface(const eth_esp32_emac_config_t *e
emac_hal_clock_enable_rmii_input(&emac->hal);
}
#elif CONFIG_IDF_TARGET_ESP32
// we can also use the IOMUX to route the APLL clock to specific GPIO
if (esp32_emac_config->clock_config.rmii.clock_gpio == EMAC_APPL_CLK_OUT_GPIO) {
ESP_GOTO_ON_ERROR(esp_clock_output_start(CLKOUT_SIG_APLL, EMAC_APPL_CLK_OUT_GPIO, &emac->rmii_clk_hdl),
// we can also use the IOMUX to route the APLL clock to GPIO_0
if (esp32_emac_config->clock_config.rmii.clock_gpio == 0) {
ESP_GOTO_ON_ERROR(esp_clock_output_start(CLKOUT_SIG_APLL, 0, &emac->rmii_clk_hdl),
err, TAG, "start APLL clock output failed");
} else
#endif

2
components/esp_eth/test_apps/main/esp_eth_test_common.c
View File

@@ -42,8 +42,10 @@ esp_eth_mac_t *mac_init(void *vendor_emac_config, eth_mac_config_t *mac_config)
#if CONFIG_TARGET_RMII_CLK_OUT
esp32_emac_config.clock_config.rmii.clock_mode = EMAC_CLK_OUT;
esp32_emac_config.clock_config.rmii.clock_gpio = CONFIG_TARGET_RMII_CLK_OUT_GPIO;
#if !SOC_EMAC_RMII_CLK_OUT_INTERNAL_LOOPBACK
esp32_emac_config.clock_config_out_in.rmii.clock_mode = EMAC_CLK_EXT_IN;
esp32_emac_config.clock_config_out_in.rmii.clock_gpio = CONFIG_TARGET_RMII_CLK_IN_GPIO;
#endif // !SOC_EMAC_RMII_CLK_OUT_INTERNAL_LOOPBACK
#endif // CONFIG_TARGET_TEST_RMII_CLK_OUT
if (vendor_emac_config == NULL) {
vendor_emac_config = &esp32_emac_config;

4
components/esp_eth/test_apps/sdkconfig.ci.default_dp83848
View File

@@ -7,5 +7,5 @@ CONFIG_ESP_TASK_WDT_EN=n
CONFIG_TARGET_USE_INTERNAL_ETHERNET=y
CONFIG_TARGET_ETH_PHY_DEVICE_DP83848=y
CONFIG_ETH_RMII_CLK_OUTPUT=y
CONFIG_ETH_RMII_CLK_OUT_GPIO=17
CONFIG_TARGET_RMII_CLK_OUT=y
CONFIG_TARGET_RMII_CLK_OUT_GPIO=17

4
components/esp_eth/test_apps/sdkconfig.ci.default_lan8720
View File

@@ -7,5 +7,5 @@ CONFIG_ESP_TASK_WDT_EN=n
CONFIG_TARGET_USE_INTERNAL_ETHERNET=y
CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720=y
CONFIG_ETH_RMII_CLK_OUTPUT=y
CONFIG_ETH_RMII_CLK_OUT_GPIO=17
CONFIG_TARGET_RMII_CLK_OUT=y
CONFIG_TARGET_RMII_CLK_OUT_GPIO=17

22
docs/en/api-reference/network/esp_eth.rst
View File

@@ -130,15 +130,8 @@ The Ethernet driver is composed of two parts: MAC and PHY.
One of the obvious differences between MII and RMII is signal consumption. MII usually costs up to 18 signals, while the RMII interface can reduce the consumption to 9.
.. only:: esp32
.. note::
ESP-IDF only supports the RMII interface. Therefore, always set :cpp:member:`eth_esp32_emac_config_t::interface` to :cpp:enumerator:`eth_data_interface_t::EMAC_DATA_INTERFACE_RMII` or always select ``CONFIG_ETH_PHY_INTERFACE_RMII`` in the Kconfig option :ref:`CONFIG_ETH_PHY_INTERFACE`.
.. only:: not esp32
.. note::
ESP-IDF only supports the RMII interface. Therefore, always set :cpp:member:`eth_esp32_emac_config_t::interface` to :cpp:enumerator:`eth_data_interface_t::EMAC_DATA_INTERFACE_RMII`.
.. note::
ESP-IDF only supports the RMII interface. Therefore, always set :cpp:member:`eth_esp32_emac_config_t::interface` to :cpp:enumerator:`eth_data_interface_t::EMAC_DATA_INTERFACE_RMII`.
In RMII mode, both the receiver and transmitter signals are referenced to the ``REF_CLK``. ``REF_CLK`` **must be stable during any access to PHY and MAC**. Generally, there are three ways to generate the ``REF_CLK`` depending on the PHY device in your design:
@@ -150,15 +143,12 @@ The Ethernet driver is composed of two parts: MAC and PHY.
.. only:: esp32
.. note::
The ``REF_CLK`` can be also configured via Project Configuration when :cpp:class:`eth_esp32_emac_config_t` is initialized using :c:macro:`ETH_ESP32_EMAC_DEFAULT_CONFIG` macro. In the Project Configuration, choose appropriately ``CONFIG_ETH_RMII_CLK_INPUT`` or ``CONFIG_ETH_RMII_CLK_OUTPUT`` option under :ref:`CONFIG_ETH_RMII_CLK_MODE` configuration based on your design as discussed above.
.. warning::
If the RMII clock mode is configured to :cpp:enumerator:`emac_rmii_clock_mode_t::EMAC_CLK_OUT` (or ``CONFIG_ETH_RMII_CLK_OUTPUT`` is selected), then ``GPIO0`` can be used to output the ``REF_CLK`` signal. See :cpp:enumerator:`emac_rmii_clock_gpio_t::EMAC_APPL_CLK_OUT_GPIO` or :ref:`CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0` for more information.
If the RMII clock mode is configured to :cpp:enumerator:`emac_rmii_clock_mode_t::EMAC_CLK_OUT`, internal Audio PLL clock is used as a source of 50 MHz clock. Hence be sure it is not in collision with I2S bus configuration.
What is more, if you are not using PSRAM in your design, GPIO16 and GPIO17 are also available to output the reference clock signal. See :cpp:enumerator:`emac_rmii_clock_gpio_t::EMAC_CLK_OUT_GPIO` and :cpp:enumerator:`emac_rmii_clock_gpio_t::EMAC_CLK_OUT_180_GPIO` or :ref:`CONFIG_ETH_RMII_CLK_OUT_GPIO` for more information.
When internal clock is selected, then ``GPIO0`` can be used to output the ``REF_CLK`` signal. However, the clock is outputted directly to the GPIO in this particular case and so it does not have direct relationship with EMAC peripheral. Sometimes this configuration may not work well with your PHY chip. If you are not using PSRAM in your design, GPIO16 and GPIO17 are also available to output the reference clock signal. The source of clock is the same (APLL) but these signals are routed from EMAC peripheral.
If the RMII clock mode is configured to :cpp:enumerator:`emac_rmii_clock_mode_t::EMAC_CLK_EXT_IN` (or ``CONFIG_ETH_RMII_CLK_INPUT`` is selected), then ``GPIO0`` is the only choice to input the ``REF_CLK`` signal. Please note that ``GPIO0`` is also an important strapping GPIO on ESP32. If GPIO0 samples a low level during power-up, ESP32 will go into download mode. The system will get halted until a manually reset. The workaround for this issue is disabling the ``REF_CLK`` in hardware by default so that the strapping pin is not interfered by other signals in the boot stage. Then, re-enable the ``REF_CLK`` in the Ethernet driver installation stage.
If the RMII clock mode is configured to :cpp:enumerator:`emac_rmii_clock_mode_t::EMAC_CLK_EXT_IN`, then ``GPIO0`` is the only choice to input the ``REF_CLK`` signal. Please note that ``GPIO0`` is also an important strapping GPIO on ESP32. If GPIO0 samples a low level during power-up, ESP32 will go into download mode. The system will get halted until a manually reset. The workaround for this issue is disabling the ``REF_CLK`` in hardware by default so that the strapping pin is not interfered by other signals in the boot stage. Then, re-enable the ``REF_CLK`` in the Ethernet driver installation stage.
The ways to disable the ``REF_CLK`` signal can be:
@@ -167,7 +157,7 @@ The Ethernet driver is composed of two parts: MAC and PHY.
* Force the PHY device to reset status (as the case **a** in the picture). **This could fail for some PHY device** (i.e., it still outputs signals to GPIO0 even in reset state).
.. warning::
If you want the **Ethernet to work with Wi-Fi**, don’t select ESP32 as source of ``REF_CLK`` as it would result in ``REF_CLK`` instability. Either disable Wi-Fi or use a PHY or an external oscillator as the ``REF_CLK`` source.
If you want the **Ethernet to work with Wi-Fi or Bluetooth**, don’t select ESP32 as source of ``REF_CLK`` as it would result in ``REF_CLK`` instability. Either disable Wi-Fi or use a PHY or an external oscillator as the ``REF_CLK`` source.
.. only:: not esp32

26
docs/en/migration-guides/release-6.x/6.0/networking.rst
View File

@@ -16,3 +16,29 @@ Usage example:
.. code-block:: c
esp_eth_phy_802_3_reset_hw(phy_802_3);
Removed RMII Clock Kconfig Options
----------------------------------
Removed the following RMII clock Kconfig options from `components/esp_eth`. Clock configuration is now handled exclusively through EMAC config structures.
**Removed Options**:
- `ETH_PHY_INTERFACE_RMII`, `ETH_RMII_CLK_INPUT`, `ETH_RMII_CLK_OUTPUT`
- `ETH_RMII_CLK_IN_GPIO`, `ETH_RMII_CLK_OUTPUT_GPIO0`, `ETH_RMII_CLK_OUT_GPIO`
**Migration**:
.. code-block:: c
// Before: Configuration via Kconfig
// CONFIG_ETH_RMII_CLK_INPUT=y
// After: Explicit configuration in code
eth_esp32_emac_config_t emac_config = ETH_ESP32_EMAC_DEFAULT_CONFIG();
emac_config.clock_config.rmii.clock_mode = EMAC_CLK_OUT; // or EMAC_CLK_EXT_IN
emac_config.clock_config.rmii.clock_gpio = 0; // GPIO0 for ESP32
**Impact**: Applications using ``ETH_ESP32_EMAC_DEFAULT_CONFIG()`` continue to work. Custom clock configurations must be set explicitly in the EMAC config structure or use the `Ethernet Init component <https://components.espressif.com/components/espressif/ethernet_init>`_.

21
docs/zh_CN/api-reference/network/esp_eth.rst
View File

@@ -130,15 +130,8 @@
MII 和 RMII 的一个明显区别在于其所需的信号数。MII 通常需要多达 18 个信号，RMII 接口则仅需要 9 个信号。
.. only:: esp32
.. note::
ESP-IDF 只支持 RMII 接口，所以请将 :cpp:member:`eth_esp32_emac_config_t::interface` 设置为 :cpp:enumerator:`eth_data_interface_t::EMAC_DATA_INTERFACE_RMII` 或在 Kconfig 选项 :ref:`CONFIG_ETH_PHY_INTERFACE` 中选择 ``CONFIG_ETH_PHY_INTERFACE_RMII``。
.. only:: not esp32
.. note::
ESP-IDF 只支持 RMII 接口，所以请将 :cpp:member:`eth_esp32_emac_config_t::interface` 设置为 :cpp:enumerator:`eth_data_interface_t::EMAC_DATA_INTERFACE_RMII`。
.. note::
ESP-IDF 只支持 RMII 接口，所以请将 :cpp:member:`eth_esp32_emac_config_t::interface` 设置为 :cpp:enumerator:`eth_data_interface_t::EMAC_DATA_INTERFACE_RMII`。
在 RMII 模式下，接收器和发射器信号的参考时钟为 ``REF_CLK``。 **在访问 PHY 和 MAC 时，REF_CLK 必须保持稳定**。一般来说，根据设计中 PHY 设备的特征，可通过以下三种方式生成 ``REF_CLK``：
@@ -150,15 +143,13 @@
.. only:: esp32
.. note::
使用 :c:macro:`ETH_ESP32_EMAC_DEFAULT_CONFIG` 宏初始化 :cpp:class:`eth_esp32_emac_config_t` 时，也可以通过项目配置来配置 ``REF_CLK``。在项目配置中，根据上述个人设计，在 :ref:`CONFIG_ETH_RMII_CLK_MODE` 配置下选择适当的选项， ``CONFIG_ETH_RMII_CLK_INPUT`` 或是 ``CONFIG_ETH_RMII_CLK_OUTPUT``。
.. warning::
如果配置 RMII 时钟模式为 :cpp:enumerator:`emac_rmii_clock_mode_t::EMAC_CLK_OUT` （或是选择 ``CONFIG_ETH_RMII_CLK_OUTPUT``，那么就可以使用 ``GPIO0`` 输出 ``REF_CLK`` 信号。更多细节，请参见 :cpp:enumerator:`emac_rmii_clock_gpio_t::EMAC_APPL_CLK_OUT_GPIO` 或是 :ref:`CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0`。
如果将 RMII 时钟模式配置为 :cpp:enumerator:`emac_rmii_clock_mode_t::EMAC_CLK_OUT`，则会使用内部音频 PLL (APLL) 时钟作为 50 MHz 时钟源。因此，请确保该配置不会与 I2S 总线的配置发生冲突。
值得一提的是，如果设计中并未使用 PSRAM，则 GPIO16 和 GPIO17 也可以用来输出参考时钟。更多细节，请参见 :cpp:enumerator:`emac_rmii_clock_gpio_t::EMAC_CLK_OUT_GPIO` 和 :cpp:enumerator:`emac_rmii_clock_gpio_t::EMAC_CLK_OUT_180_GPIO`，或是 :ref:`CONFIG_ETH_RMII_CLK_OUT_GPIO`。
当选择内部时钟时，可以使用 ``GPIO0`` 输出 ``REF_CLK`` 信号。然而，在这种情况下时钟是直接输出到 GPIO 的，因此与 EMAC 外设并没有直接关联。有时这种配置可能无法很好地兼容所使用的 PHY 芯片。如果设计中未使用 PSRAM，则还可以使用 GPIO16 和 GPIO17 来输出参考时钟信号。其时钟源相同（均来自 APLL），但这些信号是通过 EMAC 外设引出的。
如果配置 RMII 时钟模式为 :cpp:enumerator:`emac_rmii_clock_mode_t::EMAC_CLK_EXT_IN` （或是选择 ``CONFIG_ETH_RMII_CLK_INPUT``，那么只能选择 ``GPIO0`` 输入 ``REF_CLK`` 信号。请注意， ``GPIO0`` 同时也是 ESP32 上一个重要的 strapping GPIO 管脚。如果上电时 GPIO0 为低电平，则 ESP32 将进入下载模式，需进行手动复位重启系统。解决这个问题的方法是，在硬件中默认禁用 ``REF_CLK``，从而避免 strapping 管脚在启动阶段受到其他信号的干扰。随后，再在以太网驱动安装阶段重新启用 ``REF_CLK``。
如果配置 RMII 时钟模式为 :cpp:enumerator:`emac_rmii_clock_mode_t::EMAC_CLK_EXT_IN`，那么只能选择 ``GPIO0`` 输入 ``REF_CLK`` 信号。请注意， ``GPIO0`` 同时也是 ESP32 上一个重要的 strapping GPIO 管脚。如果上电时 GPIO0 为低电平，则 ESP32 将进入下载模式，需进行手动复位重启系统。解决这个问题的方法是，在硬件中默认禁用 ``REF_CLK``，从而避免 strapping 管脚在启动阶段受到其他信号的干扰。随后，再在以太网驱动安装阶段重新启用 ``REF_CLK``。
可以通过以下方法禁用 ``REF_CLK`` 信号：

26
docs/zh_CN/migration-guides/release-6.x/6.0/networking.rst
View File

@@ -16,3 +16,29 @@
.. code-block:: c
esp_eth_phy_802_3_reset_hw(phy_802_3);
移除 RMII 时钟 Kconfig 选项
---------------------------
已从 `components/esp_eth` 中移除了以下 RMII 时钟相关的 Kconfig 选项。时钟配置现在仅通过 EMAC 配置结构体进行管理。
**移除的选项**：
- `ETH_PHY_INTERFACE_RMII`、`ETH_RMII_CLK_INPUT`、`ETH_RMII_CLK_OUTPUT`
- `ETH_RMII_CLK_IN_GPIO`、`ETH_RMII_CLK_OUTPUT_GPIO0`、`ETH_RMII_CLK_OUT_GPIO`
**迁移方式**：
.. code-block:: c
// 之前：通过 Kconfig 配置
// CONFIG_ETH_RMII_CLK_INPUT=y
// 之后：在代码中显式配置
eth_esp32_emac_config_t emac_config = ETH_ESP32_EMAC_DEFAULT_CONFIG();
emac_config.clock_config.rmii.clock_mode = EMAC_CLK_OUT; // 或 EMAC_CLK_EXT_IN
emac_config.clock_config.rmii.clock_gpio = 0; // ESP32 使用 GPIO0
**影响**：使用 ``ETH_ESP32_EMAC_DEFAULT_CONFIG()`` 的应用程序可继续正常工作。自定义时钟配置需在 EMAC 配置结构体中显式设置，或使用 `Ethernet Init 组件 <https://components.espressif.com/components/espressif/ethernet_init>`_。

2
examples/ethernet/basic/sdkconfig.ci.default_generic
View File

@@ -7,5 +7,3 @@ CONFIG_EXAMPLE_ETH_PHY_ADDR=1
CONFIG_ETH_ENABLED=y
CONFIG_ETH_USE_ESP32_EMAC=y
CONFIG_ETH_PHY_INTERFACE_RMII=y
CONFIG_ETH_RMII_CLK_INPUT=y

2
examples/ethernet/basic/sdkconfig.ci.default_ip101
View File

@@ -7,5 +7,3 @@ CONFIG_EXAMPLE_ETH_PHY_ADDR=1
CONFIG_ETH_ENABLED=y
CONFIG_ETH_USE_ESP32_EMAC=y
CONFIG_ETH_PHY_INTERFACE_RMII=y
CONFIG_ETH_RMII_CLK_INPUT=y

25
examples/ethernet/iperf/pytest_eth_iperf.py
View File

@@ -1,7 +1,5 @@
# SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: Unlicense OR CC0-1.0
from pytest_embedded_idf.utils import idf_parametrize
"""
Test case for iperf example.
@@ -10,6 +8,7 @@ This test case might have problem running on Windows:
- use `sudo killall iperf` to force kill iperf, didn't implement windows version
"""
import os
import subprocess
@@ -17,9 +16,11 @@ import pytest
from common_test_methods import get_host_ip4_by_dest_ip
from idf_iperf_test_util import IperfUtility
from pytest_embedded import Dut
from pytest_embedded_idf.utils import idf_parametrize
try:
from typing import Any, Callable, Tuple, Optional
from collections.abc import Callable
from typing import Any
except ImportError:
# Only used for type annotations
pass
@@ -37,7 +38,7 @@ class IperfTestUtilityEth(IperfUtility.IperfTestUtility):
self, dut, config_name, 'None', 'None', pc_nic_ip, pc_iperf_log_file, test_result
)
def setup(self) -> Tuple[str, int]:
def setup(self) -> tuple[str, int]:
"""
setup iperf test:
@@ -60,9 +61,9 @@ def test_esp_eth_iperf(
dut: Dut,
log_performance: Callable[[str, object], None],
check_performance: Callable[[str, float, str], None],
udp_tx_bw_lim: Optional[int] = NO_BANDWIDTH_LIMIT,
udp_rx_bw_lim: Optional[int] = NO_BANDWIDTH_LIMIT,
spi_eth: Optional[bool] = False,
udp_tx_bw_lim: int | None = NO_BANDWIDTH_LIMIT,
udp_rx_bw_lim: int | None = NO_BANDWIDTH_LIMIT,
spi_eth: bool | None = False,
) -> None:
"""
steps: |
@@ -94,21 +95,21 @@ def test_esp_eth_iperf(
# 4. log performance and compare with pass standard
for throughput_type in test_result:
log_performance(
'{}_throughput'.format(throughput_type),
'{:.02f} Mbps'.format(test_result[throughput_type].get_best_throughput()),
f'{throughput_type}_throughput',
f'{test_result[throughput_type].get_best_throughput():.02f} Mbps',
)
# do check after logging, otherwise test will exit immediately if check fail, some performance can't be logged.
for throughput_type in test_result:
if spi_eth:
check_performance(
'{}_eth_throughput_spi_eth'.format(throughput_type),
f'{throughput_type}_eth_throughput_spi_eth',
test_result[throughput_type].get_best_throughput(),
dut.target,
)
else:
check_performance(
'{}_eth_throughput'.format(throughput_type),
f'{throughput_type}_eth_throughput',
test_result[throughput_type].get_best_throughput(),
dut.target,
)
@@ -149,6 +150,7 @@ def test_esp_eth_iperf_ip101_esp32p4(
@pytest.mark.eth_lan8720
@pytest.mark.temp_skip_ci(targets=['esp32'], reason='IDF-14059')
@pytest.mark.parametrize(
'config',
[
@@ -183,6 +185,7 @@ def test_esp_eth_iperf_rtl8201(
@pytest.mark.eth_dp83848
@pytest.mark.temp_skip_ci(targets=['esp32'], reason='IDF-14059')
@pytest.mark.parametrize(
'config',
[

4
examples/ethernet/iperf/sdkconfig.ci.default_dp83848
View File

@@ -44,6 +44,4 @@ CONFIG_EXAMPLE_ETH_PHY_ADDR=1
CONFIG_ETH_ENABLED=y
CONFIG_ETH_USE_ESP32_EMAC=y
CONFIG_ETH_PHY_INTERFACE_RMII=y
CONFIG_ETH_RMII_CLK_OUTPUT=y
CONFIG_ETH_RMII_CLK_OUT_GPIO=17
# IDF-14059

2
examples/ethernet/iperf/sdkconfig.ci.default_ip101
View File

@@ -44,5 +44,3 @@ CONFIG_EXAMPLE_ETH_PHY_ADDR=1
CONFIG_ETH_ENABLED=y
CONFIG_ETH_USE_ESP32_EMAC=y
CONFIG_ETH_PHY_INTERFACE_RMII=y
CONFIG_ETH_RMII_CLK_INPUT=y

1
examples/ethernet/iperf/sdkconfig.ci.default_ip101_esp32p4
View File

@@ -46,4 +46,3 @@ CONFIG_EXAMPLE_ETH_PHY_ADDR=1
CONFIG_ETH_ENABLED=y
CONFIG_ETH_USE_ESP32_EMAC=y
CONFIG_ETH_PHY_INTERFACE_RMII=y

3
examples/ethernet/iperf/sdkconfig.ci.default_ksz8041
View File

@@ -44,6 +44,3 @@ CONFIG_EXAMPLE_ETH_PHY_ADDR=1
CONFIG_ETH_ENABLED=y
CONFIG_ETH_USE_ESP32_EMAC=y
CONFIG_ETH_PHY_INTERFACE_RMII=y
CONFIG_ETH_RMII_CLK_INPUT=y
CONFIG_ETH_RMII_CLK_IN_GPIO=0

4
examples/ethernet/iperf/sdkconfig.ci.default_lan8720
View File

@@ -44,6 +44,4 @@ CONFIG_EXAMPLE_ETH_PHY_ADDR=0
CONFIG_ETH_ENABLED=y
CONFIG_ETH_USE_ESP32_EMAC=y
CONFIG_ETH_PHY_INTERFACE_RMII=y
CONFIG_ETH_RMII_CLK_OUTPUT=y
CONFIG_ETH_RMII_CLK_OUT_GPIO=17
# IDF-14059

4
examples/ethernet/iperf/sdkconfig.ci.default_rtl8201
View File

@@ -42,7 +42,3 @@ CONFIG_EXAMPLE_ETH_PHY_ADDR=0
CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET=y
CONFIG_EXAMPLE_ETH_PHY_RTL8201=y
CONFIG_ETH_RMII_CLK_INPUT=y
# CONFIG_ETH_RMII_CLK_OUTPUT is not set
CONFIG_ETH_RMII_CLK_IN_GPIO=0