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1.add ldo parameters in efuse table; 2.set ldo dbias based on pvt-efuse; 3.add pll cali stop function; 4. add efuse_ocode

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zlq
2022-07-27 18:18:03 +08:00
committed by Armando
parent dbb3830c44
commit bd7bcbb03b
1 changed files with 2 additions and 2 deletions
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4
components/esp_hw_support/port/esp32c2/rtc_clk.c
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@@ -28,7 +28,7 @@ static const char *TAG = "rtc_clk";
// Current PLL frequency, in 480MHZ. Zero if PLL is not enabled. // Current PLL frequency, in 480MHZ. Zero if PLL is not enabled.
static int s_cur_pll_freq; static int s_cur_pll_freq;
static void rtc_clk_cpu_freq_to_xtal(int freq, int div); void rtc_clk_cpu_freq_to_xtal(int freq, int div);
static void rtc_clk_cpu_freq_to_8m(void); static void rtc_clk_cpu_freq_to_8m(void);
void rtc_clk_32k_enable_external(void) void rtc_clk_32k_enable_external(void)
@@ -279,7 +279,7 @@ void rtc_clk_cpu_freq_set_xtal(void)
/** /**
* Switch to XTAL frequency. Does not disable the PLL. * Switch to XTAL frequency. Does not disable the PLL.
*/ */
static void rtc_clk_cpu_freq_to_xtal(int freq, int div) void rtc_clk_cpu_freq_to_xtal(int freq, int div)
{ {
ets_update_cpu_frequency(freq); ets_update_cpu_frequency(freq);
/* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */ /* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */