espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-10-03 18:40:59 +02:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'bugfix/wifibug-1373' into 'release/v5.3'

Browse Source 
backport v5.3: add hal interface to configure pau regdma wait timeout parameter

See merge request espressif/esp-idf!41079
This commit is contained in:
Jiang Jiang Jian
2025-08-08 19:48:20 +08:00
parent 24bc87dbba 08c146b2ab
commit bea47a18d7
8 changed files with 64 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
components/esp_hw_support/port/pau_regdma.c
View File

@@ -15,6 +15,9 @@
#include "esp_private/esp_pau.h"
#include "esp_private/periph_ctrl.h"
#define PAU_REGDMA_LINK_WAIT_RETRY_COUNT (1000)
#define PAU_REGDMA_LINK_WAIT_READ_INTERNAL (32)
static __attribute__((unused)) const char *TAG = "pau_regdma";
typedef struct {
@@ -32,6 +35,7 @@ pau_context_t * __attribute__((weak)) IRAM_ATTR PAU_instance(void)
if (pau_hal.dev == NULL) {
pau_hal.dev = &PAU;
pau_hal_enable_bus_clock(true);
pau_hal_set_regdma_wait_timeout(&pau_hal, PAU_REGDMA_LINK_WAIT_RETRY_COUNT, PAU_REGDMA_LINK_WAIT_READ_INTERNAL);
#if SOC_PAU_IN_TOP_DOMAIN
pau_hal_lp_sys_initialize();
#endif

10
components/hal/esp32c6/include/hal/pau_ll.h
View File

@@ -157,6 +157,16 @@ static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev)
dev->int_clr.error_int_clr = 1;
}
static inline void pau_ll_set_regdma_link_wait_retry_count(pau_dev_t *dev, int count)
{
dev->regdma_bkp_conf.link_tout_thres = count;
}
static inline void pau_ll_set_regdma_link_wait_read_interval(pau_dev_t *dev, int interval)
{
dev->regdma_bkp_conf.read_interval = interval;
}
#ifdef __cplusplus
}
#endif

7
components/hal/esp32c6/pau_hal.c
View File

@@ -54,3 +54,10 @@ void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal)
pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
}
void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval)
{
HAL_ASSERT(count > 0 && interval > 0);
pau_ll_set_regdma_link_wait_retry_count(hal->dev, count);
pau_ll_set_regdma_link_wait_read_interval(hal->dev, interval);
}

10
components/hal/esp32h2/include/hal/pau_ll.h
View File

@@ -127,6 +127,16 @@ static inline __attribute__((always_inline)) void pau_ll_clear_regdma_backup_err
dev->int_clr.error_int_clr = 1;
}
static inline void pau_ll_set_regdma_link_wait_retry_count(pau_dev_t *dev, int count)
{
dev->regdma_bkp_conf.link_tout_thres = count;
}
static inline void pau_ll_set_regdma_link_wait_read_interval(pau_dev_t *dev, int interval)
{
dev->regdma_bkp_conf.read_interval = interval;
}
#ifdef __cplusplus
}
#endif

7
components/hal/esp32h2/pau_hal.c
View File

@@ -41,3 +41,10 @@ void IRAM_ATTR pau_hal_regdma_clock_configure(pau_hal_context_t *hal, bool enabl
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.regdma_conf, regdma_rst_en, !enable);
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.regdma_conf, regdma_clk_en, enable);
}
void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval)
{
HAL_ASSERT(count > 0 && interval > 0);
pau_ll_set_regdma_link_wait_retry_count(hal->dev, count);
pau_ll_set_regdma_link_wait_read_interval(hal->dev, interval);
}

10
components/hal/esp32p4/include/hal/pau_ll.h
View File

@@ -158,6 +158,16 @@ static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev)
dev->int_clr.error_int_clr = 1;
}
static inline void pau_ll_set_regdma_link_wait_retry_count(pau_dev_t *dev, int count)
{
dev->regdma_bkp_conf.link_tout_thres = count;
}
static inline void pau_ll_set_regdma_link_wait_read_interval(pau_dev_t *dev, int interval)
{
dev->regdma_bkp_conf.read_interval = interval;
}
#ifdef __cplusplus
}
#endif

7
components/hal/esp32p4/pau_hal.c
View File

@@ -63,6 +63,13 @@ void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal)
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
}
void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval)
{
HAL_ASSERT(count > 0 && interval > 0);
pau_ll_set_regdma_link_wait_retry_count(hal->dev, count);
pau_ll_set_regdma_link_wait_read_interval(hal->dev, interval);
}
#if SOC_PAU_IN_TOP_DOMAIN
void IRAM_ATTR pau_hal_lp_sys_initialize(void)
{

9
components/hal/include/hal/pau_hal.h
View File

@@ -118,6 +118,15 @@ void pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal);
void pau_hal_regdma_clock_configure(pau_hal_context_t *hal, bool enable);
#endif
/**
* @brief Set regdma link wait timeout, include wait retry count and register read interval
*
* @param hal regdma hal context
* @param count the maximum number of regdma wait retry count
* @param interval the interval of regdma wait link to read register
*/
void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval);
#if SOC_PAU_IN_TOP_DOMAIN
/**
* If PAU is in TOP power domain, configuration will be lost after sleep, it is necessary