Power Management: support CPU powered down in light sleep for esp32h2

components/esp_hw_support/CMakeLists.txt

@@ -117,8 +117,7 @@ if(NOT BOOTLOADER_BUILD)
 
     if(CONFIG_IDF_TARGET_ESP32H2)
         list(REMOVE_ITEM srcs
-                "sleep_cpu.c"         # TODO: IDF-6267
-                "sleep_wake_stub.c"   # TODO: IDF-6267
+                "sleep_wake_stub.c"   # TODO: IDF-6268
             )
     endif()
 else()

components/esp_hw_support/sleep_cpu.c

@@ -46,6 +46,14 @@
 #include "soc/plic_reg.h"
 #include "soc/clint_reg.h"
 #include "esp32c6/rom/cache.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/rom/rtc.h"
+#include "riscv/rvsleep-frames.h"
+#include "soc/intpri_reg.h"
+#include "soc/extmem_reg.h"
+#include "soc/plic_reg.h"
+#include "soc/clint_reg.h"
+#include "esp32h2/rom/cache.h"
 #endif
 
 static __attribute__((unused)) const char *TAG = "sleep";
@@ -317,8 +325,13 @@ static inline void * cpu_domain_intpri_sleep_frame_alloc_and_init(void)
 static inline void * cpu_domain_cache_config_sleep_frame_alloc_and_init(void)
 {
     const static cpu_domain_dev_regs_region_t regions[] = {
+#if CONFIG_IDF_TARGET_ESP32C6
         { .start = EXTMEM_L1_CACHE_CTRL_REG, .end = EXTMEM_L1_CACHE_CTRL_REG + 4 },
         { .start = EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_REG, .end = EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_REG + 4 }
+#elif CONFIG_IDF_TARGET_ESP32H2
+        { .start = CACHE_L1_CACHE_CTRL_REG, .end = CACHE_L1_CACHE_CTRL_REG + 4 },
+        { .start = CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG, .end = CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG + 4 }
+#endif
     };
     return cpu_domain_dev_sleep_frame_alloc_and_init(regions, sizeof(regions) / sizeof(regions[0]));
 }

components/esp_hw_support/sleep_cpu_asm.S

@@ -9,7 +9,7 @@
 #include "soc/soc_caps.h"
 #include "sdkconfig.h"
 
-#if !CONFIG_IDF_TARGET_ESP32C6
+#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2
 #include "soc/lp_aon_reg.h"
 #include "soc/extmem_reg.h"
 #endif
@@ -115,7 +115,7 @@ rv_core_critical_regs_save:
     csrr    t0, mscratch
     sw      t0, RV_SLP_CTX_T0(t3)
 
-#if !CONFIG_IDF_TARGET_ESP32C6
+#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2
     /* writeback dcache is required here!!! */
     la      t0, EXTMEM_CACHE_SYNC_MAP_REG
     li      t1, 0x10

components/esp_hw_support/sleep_modes.c

@@ -835,7 +835,6 @@ void IRAM_ATTR esp_deep_sleep_start(void)
 #else
     uint32_t force_pd_flags = RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_VDDSDIO | RTC_SLEEP_PD_INT_8M | RTC_SLEEP_PD_XTAL;
 #endif
-
     /**
      * If all wireless modules share one power domain, we name this power domain "modem".
      * If wireless modules have their own power domain, we give these power domains separate

components/esp_pm/Kconfig

@@ -95,7 +95,7 @@ menu "Power Management"
 
     config PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP
         bool "Power down CPU in light sleep"
-        depends on IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C6
+        depends on SOC_PM_SUPPORT_CPU_PD
         select PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP if ESP32S3_DATA_CACHE_16KB
         default y
         help

components/esp_rom/include/esp32h2/rom/rtc.h

@@ -61,6 +61,7 @@ extern "C" {
 #define RTC_ENTRY_ADDR_REG      LP_AON_STORE6_REG
 #define RTC_RESET_CAUSE_REG     LP_AON_STORE6_REG
 #define RTC_MEMORY_CRC_REG      LP_AON_STORE7_REG
+#define LIGHT_SLEEP_WAKE_STUB_ADDR_REG  LP_AON_STORE8_REG
 
 #define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
 

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -1061,7 +1061,7 @@ config SOC_PM_SUPPORT_BT_WAKEUP
 
 config SOC_PM_SUPPORT_CPU_PD
     bool
-    default n
+    default y
 
 config SOC_PM_SUPPORT_XTAL32K_PD
     bool
@@ -1079,6 +1079,10 @@ config SOC_PM_SUPPORT_VDDSDIO_PD
     bool
     default y
 
+config SOC_PM_CPU_RETENTION_BY_SW
+    bool
+    default y
+
 config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
     bool
     default y

components/soc/esp32h2/include/soc/soc_caps.h

@@ -448,11 +448,12 @@
 // TODO: IDF-6270 (Copy from esp32c6, need check)
 /*-------------------------- Power Management CAPS ----------------------------*/
 #define SOC_PM_SUPPORT_BT_WAKEUP        (1)
-#define SOC_PM_SUPPORT_CPU_PD           (0)
+#define SOC_PM_SUPPORT_CPU_PD           (1)
 #define SOC_PM_SUPPORT_XTAL32K_PD       (1)
 #define SOC_PM_SUPPORT_RC32K_PD         (1)
 #define SOC_PM_SUPPORT_RC_FAST_PD       (1)
 #define SOC_PM_SUPPORT_VDDSDIO_PD       (1)
+#define SOC_PM_CPU_RETENTION_BY_SW      (1)
 #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY   (1) /*!<Supports CRC only the stub code in RTC memory */
 
 /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/