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Merge branch 'bugfix/increase_esp32h2_slow_clock_calibration_wdt_threshold_v5.1' into 'release/v5.1'

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fix(esp_system): increase esp32h2 slow clock calibration timeout watchdog threshold (backport v5.1)

See merge request espressif/esp-idf!26920
This commit is contained in:
Jiang Jiang Jian
2023-11-14 15:33:43 +08:00
parent cee24a6ce1 b31a07bc67
commit c21d2b254b
1 changed files with 3 additions and 3 deletions
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6
components/esp_system/port/soc/esp32h2/clk.c
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@ -55,13 +55,13 @@ static const char *TAG = "clk";
#ifdef CONFIG_BOOTLOADER_WDT_ENABLE
// WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
// If the frequency changes from 150kHz to 32kHz, then the timeout set for the WDT will increase 4.6 times.
// Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec).
// Therefore, for the time of frequency change, set a new lower timeout value (2 sec).
// This prevents excessive delay before resetting in case the supply voltage is drawdown.
// (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 1.6sec * 150/32 = 7.5 sec).
// (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 2 sec * 150/32 = 9.375 sec).
wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT};
uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
uint32_t stage_timeout_ticks = (uint32_t)(2000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
wdt_hal_feed(&rtc_wdt_ctx);
//Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same