mirror of
https://github.com/espressif/esp-idf.git
synced 2025-07-29 18:27:20 +02:00
feat(esp_rom): update rom files for eco3
This commit is contained in:
wanckl
@ -67,10 +67,6 @@ if(CONFIG_ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG OR CONFIG_ESP_ROM_HAS_CACHE_WRITEBAC
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list(APPEND sources "patches/esp_rom_cache_esp32s2_esp32s3.c")
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endif()
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if(CONFIG_ESP_ROM_CACHE_WB_INVLD_LOW_RANGE)
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list(APPEND sources "patches/esp_rom_cache_esp32c61.c")
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endif()
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if(CONFIG_ESP_ROM_HAS_CACHE_WRITEBACK_BUG)
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list(APPEND sources "patches/esp_rom_cache_writeback_esp32s3.S")
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endif()
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@ -107,10 +107,6 @@ config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
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bool
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default y
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config ESP_ROM_CACHE_WB_INVLD_LOW_RANGE
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bool
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default y
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config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
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bool
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default y
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@ -32,5 +32,4 @@
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#define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions
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#define ESP_ROM_USB_OTG_NUM (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
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#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
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#define ESP_ROM_CACHE_WB_INVLD_LOW_RANGE (1) // ROM `Cache_WriteBack_Addr` and `Cache_Invalidate_Addr` can only access low vaddr parts
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#define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access.
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@ -1,14 +1,10 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* ROM function interface esp32c61.rom.coexist.ld for esp32c61
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*
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*
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* Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457
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*
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* Compatible with ROM where ECO version equal or greater to 0.
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/* ROM function interface
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*
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* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
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*/
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@ -35,7 +31,7 @@ coex_hw_timer_set = 0x40000a64;
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coex_schm_interval_set = 0x40000a68;
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coex_schm_lock = 0x40000a6c;
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coex_schm_unlock = 0x40000a70;
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/*coex_status_get = 0x40000a74;*/
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coex_status_get = 0x40000a74;
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coex_wifi_release = 0x40000a78;
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esp_coex_ble_conn_dynamic_prio_get = 0x40000a7c;
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/* Data (.data, .bss, .rodata) */
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@ -1,14 +1,10 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* ROM function interface esp32c61.rom.ld for esp32c61
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*
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*
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* Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457
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*
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* Compatible with ROM where ECO version equal or greater to 0.
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/* ROM function interface
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*
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* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
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*/
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@ -54,8 +50,6 @@ software_reset_cpu = 0x40000098;
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ets_clk_assist_debug_clock_enable = 0x4000009c;
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clear_super_wdt_reset_flag = 0x400000a0;
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disable_default_watchdog = 0x400000a4;
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esp_rom_set_rtc_wake_addr = 0x400000a8;
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esp_rom_get_rtc_wake_addr = 0x400000ac;
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send_packet = 0x400000b0;
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recv_packet = 0x400000b4;
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GetUartDevice = 0x400000b8;
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@ -192,9 +186,9 @@ MMU_Set_Page_Mode = 0x40000624;
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MMU_Get_Page_Mode = 0x40000628;
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Cache_Sync_Items = 0x4000062c;
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Cache_Op_Addr = 0x40000630;
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/*Cache_Invalidate_Addr = 0x40000634; rom version API has issue that unable to access higher vaddr range, use IDF patch */
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Cache_Invalidate_Addr = 0x40000634;
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Cache_Clean_Addr = 0x40000638;
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/*Cache_WriteBack_Addr = 0x4000063c; rom version API has issue that unable to access higher vaddr range, use IDF patch */
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Cache_WriteBack_Addr = 0x4000063c;
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Cache_WriteBack_Invalidate_Addr = 0x40000640;
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Cache_Invalidate_All = 0x40000644;
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Cache_Clean_All = 0x40000648;
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@ -369,7 +363,6 @@ ets_efuse_jtag_disabled = 0x400007fc;
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ets_efuse_usb_print_is_disabled = 0x40000800;
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ets_efuse_usb_download_mode_disabled = 0x40000804;
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ets_efuse_usb_device_disabled = 0x40000808;
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ets_efuse_secure_boot_fast_wake_enabled = 0x4000080c;
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/***************************************
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@ -393,3 +386,60 @@ usb_serial_device_rx_one_char = 0x40000a20;
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usb_serial_device_rx_one_char_block = 0x40000a24;
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usb_serial_device_tx_flush = 0x40000a28;
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usb_serial_device_tx_one_char = 0x40000a2c;
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/***************************************
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Group lldesc
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***************************************/
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/* Functions */
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lldesc_build_chain = 0x400014dc;
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/***************************************
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Group sip
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***************************************/
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/* Functions */
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sip_after_tx_complete = 0x400014e0;
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sip_alloc_to_host_evt = 0x400014e4;
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sip_download_begin = 0x400014e8;
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sip_get_ptr = 0x400014ec;
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sip_get_state = 0x400014f0;
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sip_init_attach = 0x400014f4;
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sip_install_rx_ctrl_cb = 0x400014f8;
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sip_install_rx_data_cb = 0x400014fc;
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sip_is_active = 0x40001500;
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sip_post_init = 0x40001504;
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sip_reclaim_from_host_cmd = 0x40001508;
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sip_reclaim_tx_data_pkt = 0x4000150c;
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sip_send = 0x40001510;
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sip_to_host_chain_append = 0x40001514;
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sip_to_host_evt_send_done = 0x40001518;
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/***************************************
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Group slc
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***************************************/
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/* Functions */
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slc_add_credits = 0x4000151c;
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slc_enable = 0x40001520;
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slc_from_host_chain_fetch = 0x40001524;
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slc_from_host_chain_recycle = 0x40001528;
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slc_has_pkt_to_host = 0x4000152c;
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slc_init_attach = 0x40001530;
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slc_init_credit = 0x40001534;
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slc_reattach = 0x40001538;
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slc_send_to_host_chain = 0x4000153c;
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slc_set_host_io_max_window = 0x40001540;
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slc_to_host_chain_recycle = 0x40001544;
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/***************************************
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Group recovery_bootloader
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***************************************/
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/* Functions */
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ets_get_bootloader_offset = 0x40001548;
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ets_set_bootloader_offset = 0x4000154c;
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@ -1,14 +1,10 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* ROM function interface esp32c61.rom.net80211.ld for esp32c61
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*
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*
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* Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457
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*
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* Compatible with ROM where ECO version equal or greater to 0.
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/* ROM function interface
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*
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* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
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*/
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@ -40,7 +36,7 @@ ieee80211_encap_esfbuf = 0x40000ac8;
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ieee80211_is_tx_allowed = 0x40000acc;
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ieee80211_output_pending_eb = 0x40000ad0;
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ieee80211_output_process = 0x40000ad4;
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/*ieee80211_set_tx_desc = 0x40000ad8;*/
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ieee80211_set_tx_desc = 0x40000ad8;
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ieee80211_classify = 0x40000adc;
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ieee80211_copy_eb_header = 0x40000ae0;
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ieee80211_recycle_cache_eb = 0x40000ae4;
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@ -60,12 +56,12 @@ ieee80211_find_ext_elem = 0x40000b18;
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ieee80211_find_ie = 0x40000b1c;
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ieee80211_find_ext_ie = 0x40000b20;
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ieee80211_merge_mbssid_profile = 0x40000b24;
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/*ieee80211_encap_esfbuf_htc = 0x40000b28;*/
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ieee80211_encap_esfbuf_htc = 0x40000b28;
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wifi_get_macaddr = 0x40000b2c;
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wifi_rf_phy_disable = 0x40000b30;
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wifi_rf_phy_enable = 0x40000b34;
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wifi_is_started = 0x40000b38;
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/*sta_input = 0x40000b3c;*/
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sta_input = 0x40000b3c;
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sta_rx_eapol = 0x40000b40;
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sta_reset_beacon_timeout = 0x40000b44;
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sta_get_beacon_timeout = 0x40000b48;
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@ -21,293 +21,8 @@
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phy_param_addr = 0x4000104c;
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chip762_phyrom_version = 0x40001050;
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chip762_phyrom_version_num = 0x40001054;
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phy_get_rc_dout = 0x40001058;
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phy_rc_cal = 0x4000105c;
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phy_abs_temp = 0x40001060;
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phy_set_chan_cal_interp = 0x40001064;
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phy_loopback_mode_en = 0x40001068;
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phy_get_data_sat = 0x4000106c;
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phy_byte_to_word = 0x40001070;
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phy_bb_bss_cbw40 = 0x40001074;
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phy_set_chan_reg = 0x40001078;
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phy_i2c_master_reset = 0x4000107c;
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phy_chan14_mic_enable = 0x40001080;
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phy_chan14_mic_cfg = 0x40001084;
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phy_freq_module_resetn = 0x40001088;
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phy_freq_chan_en_sw = 0x4000108c;
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phy_write_chan_freq = 0x40001090;
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phy_get_freq_mem_param = 0x40001094;
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phy_get_freq_mem_addr = 0x40001098;
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phy_wr_rf_freq_mem = 0x4000109c;
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phy_read_rf_freq_mem = 0x400010a0;
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phy_freq_i2c_mem_write = 0x400010a4;
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phy_freq_reg_init = 0x400010a8;
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phy_freq_num_get_data = 0x400010ac;
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phy_freq_i2c_num_addr = 0x400010b0;
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phy_freq_i2c_write_set = 0x400010b4;
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phy_pll_dac_mem_update = 0x400010b8;
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phy_pll_cap_mem_update = 0x400010bc;
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phy_get_rf_freq_cap = 0x400010c0;
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phy_get_rf_freq_init = 0x400010c4;
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phy_freq_get_i2c_data = 0x400010c8;
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phy_freq_i2c_data_write = 0x400010cc;
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phy_set_chan_freq_hw_init = 0x400010d0;
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phy_en_hw_set_freq = 0x400010d4;
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phy_dis_hw_set_freq = 0x400010d8;
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phy_wait_freq_set_busy = 0x400010dc;
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phy_set_chan_freq_sw_start = 0x400010e0;
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phy_wait_i2c_sdm_stable = 0x400010e4;
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phy_reg_init = 0x400010e8;
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phy_xpd_rf = 0x400010ec;
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phy_close_rf = 0x400010f0;
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phy_get_mac_addr = 0x400010f4;
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phy_set_mac_data = 0x400010f8;
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phy_rfcal_data_sub = 0x400010fc;
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phy_rf_cal_data_recovery = 0x40001100;
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phy_rf_cal_data_backup = 0x40001104;
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phy_rfcal_data_check = 0x40001108;
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phy_pwdet_reg_init = 0x4000110c;
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phy_pwdet_sar2_init = 0x40001110;
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phy_en_pwdet = 0x40001114;
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phy_get_sar_sig_ref = 0x40001118;
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phy_pwdet_tone_start = 0x4000111c;
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phy_get_tone_sar_dout = 0x40001120;
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phy_get_fm_sar_dout = 0x40001124;
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phy_txtone_linear_pwr = 0x40001128;
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phy_linear_to_db = 0x4000112c;
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phy_get_power_db = 0x40001130;
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phy_meas_tone_pwr_db = 0x40001134;
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phy_pwdet_wait_idle = 0x40001138;
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phy_pkdet_vol_start = 0x4000113c;
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phy_read_sar_dout = 0x40001140;
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phy_read_sar2_code = 0x40001144;
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phy_get_sar2_vol = 0x40001148;
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phy_get_pll_vol = 0x4000114c;
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phy_tx_pwctrl_bg_init = 0x40001150;
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phy_set_most_tpw = 0x40001154;
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phy_get_most_tpw = 0x40001158;
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phy_tx_state_out = 0x4000115c;
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phy_ant_dft_cfg = 0x40001160;
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phy_ant_wifitx_cfg = 0x40001164;
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phy_ant_wifirx_cfg = 0x40001168;
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phy_ant_bttx_cfg = 0x4000116c;
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phy_ant_btrx_cfg = 0x40001170;
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phy_chan_dump_cfg = 0x40001174;
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phy_enable_low_rate = 0x40001178;
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phy_disable_low_rate = 0x4000117c;
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phy_is_low_rate_enabled = 0x40001180;
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phy_dig_reg_backup = 0x40001184;
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phy_chan_filt_set = 0x40001188;
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phy_rx11blr_cfg = 0x4000118c;
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phy_set_cca = 0x40001190;
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phy_set_rx_sense = 0x40001194;
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phy_rx_gain_force = 0x40001198;
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phy_mhz2ieee = 0x4000119c;
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phy_chan_to_freq = 0x400011a0;
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phy_restart_cal = 0x400011a4;
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phy_write_rfpll_sdm = 0x400011a8;
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phy_wait_rfpll_cal_end = 0x400011ac;
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phy_rfpll_set_freq = 0x400011b0;
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phy_set_rf_freq_offset = 0x400011b4;
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phy_set_rfpll_freq = 0x400011b8;
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phy_set_channel_rfpll_freq = 0x400011bc;
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phy_rfpll_cap_correct = 0x400011c0;
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phy_rfpll_cap_init_cal = 0x400011c4;
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phy_set_freq = 0x400011c8;
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phy_write_pll_cap = 0x400011cc;
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phy_read_pll_cap = 0x400011d0;
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phy_chip_set_chan_misc = 0x400011d4;
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phy_freq_set_reg = 0x400011d8;
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phy_rfpll_chgp_cal = 0x400011dc;
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phy_gen_rx_gain_table = 0x400011e0;
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phy_get_rxbb_dc = 0x400011e4;
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phy_wr_rx_gain_mem = 0x400011e8;
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phy_rfpll_cap_track = 0x400011ec;
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phy_param_track = 0x400011f0;
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phy_txpwr_correct = 0x400011f4;
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phy_txpwr_cal_track = 0x400011f8;
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phy_bt_track_tx_power = 0x400011fc;
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phy_wifi_track_tx_power = 0x40001200;
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phy_bt_txdc_cal = 0x40001204;
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phy_bt_txiq_cal = 0x40001208;
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phy_txdc_cal_pwdet = 0x4000120c;
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phy_txdc_cal = 0x40001210;
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phy_txiq_get_mis_pwr = 0x40001214;
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phy_txiq_cover = 0x40001218;
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phy_rfcal_txiq = 0x4000121c;
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phy_get_power_atten = 0x40001220;
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phy_pwdet_ref_code = 0x40001224;
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phy_pwdet_code_cal = 0x40001228;
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phy_rfcal_txcap = 0x4000122c;
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phy_tx_cap_init = 0x40001230;
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phy_rfcal_pwrctrl = 0x40001234;
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||||
phy_tx_pwctrl_init_cal = 0x40001238;
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||||
phy_tx_pwctrl_init = 0x4000123c;
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||||
phy_bt_tx_pwctrl_init = 0x40001240;
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phy_i2c_enter_critical_ = 0x40001244;
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phy_i2c_exit_critical_ = 0x40001248;
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phy_i2c_clk_sel = 0x4000124c;
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||||
phy_get_i2c_read_mask_ = 0x40001250;
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phy_get_i2c_mst0_mask = 0x40001254;
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phy_get_i2c_hostid_ = 0x40001258;
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||||
phy_chip_i2c_readReg_org = 0x4000125c;
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||||
phy_chip_i2c_readReg = 0x40001260;
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||||
phy_i2c_paral_set_mst0 = 0x40001264;
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||||
phy_i2c_paral_set_read = 0x40001268;
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||||
phy_i2c_paral_read = 0x4000126c;
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||||
phy_i2c_paral_write = 0x40001270;
|
||||
phy_i2c_paral_write_num = 0x40001274;
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||||
phy_i2c_paral_write_mask = 0x40001278;
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phy_i2c_readReg = 0x4000127c;
|
||||
phy_chip_i2c_writeReg = 0x40001280;
|
||||
phy_i2c_writeReg = 0x40001284;
|
||||
phy_i2c_readReg_Mask = 0x40001288;
|
||||
phy_i2c_writeReg_Mask = 0x4000128c;
|
||||
phy_set_txcap_reg = 0x40001290;
|
||||
phy_i2c_sar2_init_code = 0x40001294;
|
||||
phy_test_filter_band_set = 0x40001298;
|
||||
phy_filter_dcap_set = 0x4000129c;
|
||||
phy_i2c_init1 = 0x400012a0;
|
||||
phy_i2c_init2 = 0x400012a4;
|
||||
phy_bias_reg_set = 0x400012a8;
|
||||
phy_i2c_rc_cal_set = 0x400012ac;
|
||||
phy_i2c_bbpll_set = 0x400012b0;
|
||||
phy_adc_rate_set = 0x400012b4;
|
||||
phy_dac_rate_set = 0x400012b8;
|
||||
phy_encode_i2c_master = 0x400012bc;
|
||||
phy_i2c_master_fill = 0x400012c0;
|
||||
phy_i2c_master_mem_txcap = 0x400012c4;
|
||||
/* phy_i2c_master_cmd_mem_init = 0x400012c8; */
|
||||
/* phy_i2c_master_mem_cfg = 0x400012cc; */
|
||||
phy_pbus_force_mode = 0x400012d0;
|
||||
phy_pbus_rd_addr = 0x400012d4;
|
||||
phy_pbus_rd_shift = 0x400012d8;
|
||||
phy_pbus_force_test = 0x400012dc;
|
||||
phy_pbus_rd = 0x400012e0;
|
||||
phy_pbus_debugmode = 0x400012e4;
|
||||
phy_pbus_workmode = 0x400012e8;
|
||||
phy_pbus_set_rxgain = 0x400012ec;
|
||||
phy_pbus_xpd_rx_off = 0x400012f0;
|
||||
phy_pbus_xpd_rx_on = 0x400012f4;
|
||||
phy_pbus_xpd_tx_off = 0x400012f8;
|
||||
phy_pbus_xpd_tx_on = 0x400012fc;
|
||||
phy_pbus_set_dco = 0x40001300;
|
||||
phy_set_loopback_gain = 0x40001304;
|
||||
phy_txcal_debuge_mode_ = 0x40001308;
|
||||
phy_txcal_work_mode = 0x4000130c;
|
||||
phy_pbus_clear_reg = 0x40001310;
|
||||
phy_save_pbus_reg = 0x40001314;
|
||||
phy_write_pbus_mem = 0x40001318;
|
||||
phy_set_pbus_mem = 0x4000131c;
|
||||
phy_disable_agc = 0x40001320;
|
||||
phy_enable_agc = 0x40001324;
|
||||
phy_disable_cca = 0x40001328;
|
||||
phy_enable_cca = 0x4000132c;
|
||||
phy_write_gain_mem = 0x40001330;
|
||||
phy_bb_bss_cbw40_dig = 0x40001334;
|
||||
phy_mac_tx_chan_offset = 0x40001338;
|
||||
phy_rx_11b_opt = 0x4000133c;
|
||||
phy_tx_paon_set = 0x40001340;
|
||||
phy_i2cmst_reg_init = 0x40001344;
|
||||
phy_bt_gain_offset = 0x40001348;
|
||||
phy_fe_reg_init = 0x4000134c;
|
||||
phy_mac_enable_bb = 0x40001350;
|
||||
phy_bb_wdg_cfg = 0x40001354;
|
||||
phy_fe_txrx_reset = 0x40001358;
|
||||
phy_set_rx_comp_ = 0x4000135c;
|
||||
phy_agc_reg_init = 0x40001360;
|
||||
phy_btbb_wifi_bb_cfg2 = 0x40001364;
|
||||
phy_bb_reg_init = 0x40001368;
|
||||
phy_open_i2c_xpd = 0x4000136c;
|
||||
phy_force_txrx_off = 0x40001370;
|
||||
phy_txiq_set_reg = 0x40001374;
|
||||
phy_rxiq_set_reg = 0x40001378;
|
||||
phy_set_txclk_en = 0x4000137c;
|
||||
phy_set_rxclk_en = 0x40001380;
|
||||
phy_start_tx_tone_step = 0x40001384;
|
||||
phy_stop_tx_tone = 0x40001388;
|
||||
phy_bb_wdg_test_en = 0x4000138c;
|
||||
phy_noise_floor_auto_set = 0x40001390;
|
||||
phy_read_hw_noisefloor = 0x40001394;
|
||||
phy_iq_corr_enable = 0x40001398;
|
||||
phy_wifi_agc_sat_gain = 0x4000139c;
|
||||
phy_bbpll_cal = 0x400013a0;
|
||||
phy_ant_init = 0x400013a4;
|
||||
phy_wifi_fbw_sel = 0x400013a8;
|
||||
phy_bt_filter_reg = 0x400013ac;
|
||||
phy_rx_sense_set = 0x400013b0;
|
||||
phy_tx_state_set = 0x400013b4;
|
||||
phy_close_pa = 0x400013b8;
|
||||
phy_freq_correct = 0x400013bc;
|
||||
phy_set_pbus_reg = 0x400013c0;
|
||||
phy_wifi_rifs_mode_en = 0x400013c4;
|
||||
phy_nrx_freq_set = 0x400013c8;
|
||||
phy_fe_adc_on = 0x400013cc;
|
||||
phy_force_pwr_index = 0x400013d0;
|
||||
phy_fft_scale_force = 0x400013d4;
|
||||
phy_force_rx_gain = 0x400013d8;
|
||||
phy_wifi_enable_set = 0x400013dc;
|
||||
phy_bb_wdt_rst_enable = 0x400013e0;
|
||||
phy_bb_wdt_int_enable = 0x400013e4;
|
||||
phy_bb_wdt_timeout_clear = 0x400013e8;
|
||||
phy_bb_wdt_get_status = 0x400013ec;
|
||||
phy_iq_est_enable = 0x400013f0;
|
||||
phy_iq_est_disable = 0x400013f4;
|
||||
phy_dc_iq_est = 0x400013f8;
|
||||
phy_set_cal_rxdc = 0x400013fc;
|
||||
phy_rxiq_get_mis = 0x40001400;
|
||||
phy_rxiq_cover_mg_mp = 0x40001404;
|
||||
phy_rfcal_rxiq = 0x40001408;
|
||||
phy_get_rfcal_rxiq_data = 0x4000140c;
|
||||
phy_get_dco_comp = 0x40001410;
|
||||
phy_pbus_rx_dco_cal = 0x40001414;
|
||||
phy_rxdc_est_min = 0x40001418;
|
||||
phy_pbus_rx_dco_cal_1step = 0x4000141c;
|
||||
phy_get_iq_value = 0x40001420;
|
||||
phy_set_lb_txiq = 0x40001424;
|
||||
phy_set_rx_gain_cal_iq = 0x40001428;
|
||||
phy_set_rx_gain_cal_dc = 0x4000142c;
|
||||
phy_spur_reg_write_one_tone = 0x40001430;
|
||||
phy_spur_cal = 0x40001434;
|
||||
phy_spur_coef_cfg = 0x40001438;
|
||||
phy_bb_gain_index = 0x4000143c;
|
||||
phy_rfrx_gain_index = 0x40001440;
|
||||
phy_set_tsens_power_ = 0x40001444;
|
||||
phy_set_tsens_range_ = 0x40001448;
|
||||
phy_get_tsens_value_ = 0x4000144c;
|
||||
phy_tsens_read_init = 0x40001450;
|
||||
phy_code_to_temp = 0x40001454;
|
||||
phy_tsens_dac_to_index = 0x40001458;
|
||||
phy_tsens_dac_cal = 0x4000145c;
|
||||
phy_tsens_code_read = 0x40001460;
|
||||
phy_tsens_temp_read = 0x40001464;
|
||||
phy_tsens_temp_read_local = 0x40001468;
|
||||
phy_temp_to_power = 0x4000146c;
|
||||
phy_txbbgain_to_index = 0x40001470;
|
||||
phy_index_to_txbbgain = 0x40001474;
|
||||
phy_bt_index_to_bb = 0x40001478;
|
||||
phy_bt_bb_to_index = 0x4000147c;
|
||||
phy_bt_get_tx_gain = 0x40001480;
|
||||
phy_dig_gain_check = 0x40001484;
|
||||
phy_wifi_get_tx_gain = 0x40001488;
|
||||
phy_wifi_11g_rate_chg = 0x4000148c;
|
||||
phy_set_tx_gain_mem = 0x40001490;
|
||||
phy_get_rate_fcc_index = 0x40001494;
|
||||
phy_get_chan_target_power = 0x40001498;
|
||||
phy_get_tx_gain_value = 0x4000149c;
|
||||
phy_wifi_get_target_power = 0x400014a0;
|
||||
phy_wifi_get_tx_tab_ = 0x400014a4;
|
||||
phy_wifi_set_tx_gain = 0x400014a8;
|
||||
phy_bt_get_tx_tab_ = 0x400014ac;
|
||||
phy_bt_set_tx_gain = 0x400014b0;
|
||||
phy_bt_tx_gain_init = 0x400014b4;
|
||||
phy_rate_to_index = 0x400014b8;
|
||||
phy_get_target_pwr = 0x400014bc;
|
||||
phy_get_max_pwr = 0x400014c0;
|
||||
phy_get_pwr_index = 0x400014c4;
|
||||
phy_chip_set_chan_ana = 0x400014d4;
|
||||
phy_get_romfuncs = 0x400014d8;
|
||||
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
phy_param_rom = 0x4084fc6c;
|
||||
rom_phyFuns = 0x4084fb84;
|
||||
rom_phyFuns = 0x4084fc68;
|
||||
rom_phyFuns_eco2 = 0x4084fc68;
|
||||
|
||||
@ -1,14 +1,10 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/* ROM function interface esp32c61.rom.pp.ld for esp32c61
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
|
||||
/* ROM function interface
|
||||
*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*/
|
||||
@ -27,14 +23,14 @@ esf_buf_recycle = 0x40000b64;
|
||||
GetAccess = 0x40000b68;
|
||||
hal_mac_is_low_rate_enabled = 0x40000b6c;
|
||||
hal_mac_tx_get_blockack = 0x40000b70;
|
||||
/*hal_mac_tx_set_ppdu = 0x40000b74;*/
|
||||
hal_mac_tx_set_ppdu = 0x40000b74;
|
||||
hal_mac_tx_clr_mplen = 0x40000b78;
|
||||
hal_mac_get_txq_state = 0x40000b7c;
|
||||
hal_mac_clr_txq_state = 0x40000b80;
|
||||
hal_mac_get_txq_complete = 0x40000b84;
|
||||
hal_mac_deinit_twt_tx = 0x40000b88;
|
||||
hal_mac_is_dma_enable = 0x40000b8c;
|
||||
/*hal_he_get_bss_color = 0x40000b90;*/
|
||||
hal_he_get_bss_color = 0x40000b90;
|
||||
hal_he_set_ersu = 0x40000b94;
|
||||
hal_he_get_mplen_addr_start = 0x40000b98;
|
||||
hal_he_get_mplen_addr_end = 0x40000b9c;
|
||||
@ -53,11 +49,6 @@ hal_tsf_get_tbttstart = 0x40000bcc;
|
||||
hal_get_tsf_time = 0x40000bd0;
|
||||
hal_get_sta_tsf = 0x40000bd4;
|
||||
tsf_hal_get_tbtt_interval = 0x40000bd8;
|
||||
tsf_hal_get_time = 0x400014cc;
|
||||
/*pm_get_tbtt_count = 0x400014c8;*/
|
||||
tsf_hal_get_counter_value = 0x400014d0;
|
||||
dbg_hal_check_clr_mplen_bitmap = 0x40000bdc;
|
||||
dbg_hal_check_set_mplen_bitmap = 0x40000be0;
|
||||
ic_get_trc = 0x40000be4;
|
||||
ic_mac_deinit = 0x40000be8;
|
||||
ic_mac_init = 0x40000bec;
|
||||
@ -81,7 +72,7 @@ lmacRecycleMPDU = 0x40000c30;
|
||||
lmacRxDone = 0x40000c34;
|
||||
lmacSetTxFrame = 0x40000c38;
|
||||
lmacTxDone = 0x40000c3c;
|
||||
/*lmacTxFrame = 0x40000c40;*/
|
||||
lmacTxFrame = 0x40000c40;
|
||||
lmacDisableTransmit = 0x40000c44;
|
||||
lmacDiscardFrameExchangeSequence = 0x40000c48;
|
||||
lmacProcessCollision = 0x40000c4c;
|
||||
@ -105,7 +96,7 @@ mac_tx_set_plcp1 = 0x40000c90;
|
||||
mac_tx_set_plcp2 = 0x40000c94;
|
||||
mac_tx_set_len = 0x40000c98;
|
||||
mac_tx_set_htsig = 0x40000c9c;
|
||||
/*mac_tx_set_hesig = 0x40000ca0;*/
|
||||
mac_tx_set_hesig = 0x40000ca0;
|
||||
mac_tx_set_tb = 0x40000ca4;
|
||||
mac_tx_set_mplen = 0x40000ca8;
|
||||
mac_tx_set_txop_q = 0x40000cac;
|
||||
@ -116,14 +107,14 @@ pm_disable_sleep_delay_timer = 0x40000cbc;
|
||||
pm_dream = 0x40000cc0;
|
||||
pm_mac_wakeup = 0x40000cc4;
|
||||
pm_mac_sleep = 0x40000cc8;
|
||||
/*pm_enable_active_timer = 0x40000ccc;*/
|
||||
pm_enable_active_timer = 0x40000ccc;
|
||||
pm_enable_sleep_delay_timer = 0x40000cd0;
|
||||
pm_local_tsf_process = 0x40000cd4;
|
||||
//pm_set_beacon_filter = 0x40000cd8;
|
||||
/*pm_is_in_wifi_slice_threshold = 0x40000cdc;*/
|
||||
pm_set_beacon_filter = 0x40000cd8;
|
||||
pm_is_in_wifi_slice_threshold = 0x40000cdc;
|
||||
pm_is_waked = 0x40000ce0;
|
||||
//pm_keep_alive = 0x40000ce4;
|
||||
/*pm_on_beacon_rx = 0x40000ce8;*/
|
||||
pm_keep_alive = 0x40000ce4;
|
||||
pm_on_beacon_rx = 0x40000ce8;
|
||||
pm_on_data_rx = 0x40000cec;
|
||||
pm_on_data_tx = 0x40000cf0;
|
||||
pm_on_tbtt = 0x40000cf4;
|
||||
@ -133,38 +124,38 @@ pm_on_isr_set_twt_target = 0x40000d00;
|
||||
pm_on_isr_twt_wake = 0x40000d04;
|
||||
pm_on_tsf_timer = 0x40000d08;
|
||||
pm_on_twt_force_tx = 0x40000d0c;
|
||||
/*pm_parse_beacon = 0x40000d10;*/
|
||||
/*pm_process_tim = 0x40000d14;*/
|
||||
pm_parse_beacon = 0x40000d10;
|
||||
pm_process_tim = 0x40000d14;
|
||||
pm_rx_beacon_process = 0x40000d18;
|
||||
pm_rx_data_process = 0x40000d1c;
|
||||
pm_sleep = 0x40000d20;
|
||||
pm_sleep_for = 0x40000d24;
|
||||
/*pm_tbtt_process = 0x40000d28;*/
|
||||
pm_tbtt_process = 0x40000d28;
|
||||
pm_tx_data_done_process = 0x40000d2c;
|
||||
pm_allow_tx = 0x40000d30;
|
||||
pm_extend_tbtt_adaptive_servo = 0x40000d34;
|
||||
pm_scale_listen_interval = 0x40000d38;
|
||||
pm_parse_mbssid_element = 0x40000d3c;
|
||||
pm_disconnected_wake = 0x40000d40;
|
||||
/*pm_tx_data_process = 0x40000d44;*/
|
||||
pm_tx_data_process = 0x40000d44;
|
||||
pm_is_twt_awake = 0x40000d48;
|
||||
pm_enable_twt_keep_alive = 0x40000d4c;
|
||||
pm_twt_on_tsf_timer = 0x40000d50;
|
||||
/*pm_twt_process = 0x40000d54;*/
|
||||
pm_twt_process = 0x40000d54;
|
||||
pm_is_twt_start = 0x40000d58;
|
||||
pm_twt_set_target_wdev_time = 0x40000d5c;
|
||||
pm_twt_set_target_tsf = 0x40000d60;
|
||||
pm_enable_twt_keep_alive_timer = 0x40000d64;
|
||||
/*pm_mac_try_enable_modem_state = 0x40000d68;*/
|
||||
pm_mac_try_enable_modem_state = 0x40000d68;
|
||||
pm_beacon_monitor_tbtt_timeout_process = 0x40000d6c;
|
||||
pm_update_next_tbtt = 0x40000d70;
|
||||
pm_twt_disallow_tx = 0x40000d74;
|
||||
pm_clear_wakeup_signal = 0x40000d78;
|
||||
/*pm_mac_disable_tsf_tbtt_soc_wakeup = 0x40000d7c;
|
||||
pm_mac_disable_tsf_tbtt_soc_wakeup = 0x40000d7c;
|
||||
pm_mac_disable_tsf_tbtt_modem_wakeup = 0x40000d80;
|
||||
//pm_mac_enable_tsf_tbtt_soc_wakeup = 0x40000d84;
|
||||
//pm_mac_enable_tsf_tbtt_modem_wakeup = 0x40000d88;
|
||||
//pm_mac_modem_params_rt_update = 0x40000d8c;*/
|
||||
pm_mac_enable_tsf_tbtt_soc_wakeup = 0x40000d84;
|
||||
pm_mac_enable_tsf_tbtt_modem_wakeup = 0x40000d88;
|
||||
pm_mac_modem_params_rt_update = 0x40000d8c;
|
||||
pm_update_at_next_beacon = 0x40000d90;
|
||||
pm_get_null_max_tx_time = 0x40000d94;
|
||||
pm_coex_schm_overall_period_get = 0x40000d98;
|
||||
@ -184,17 +175,17 @@ ppEmptyDelimiterLength = 0x40000dcc;
|
||||
ppEnqueueRxq = 0x40000dd0;
|
||||
ppEnqueueTxDone = 0x40000dd4;
|
||||
ppGetTxframe = 0x40000dd8;
|
||||
/*ppMapTxQueue = 0x40000ddc;*/
|
||||
ppMapTxQueue = 0x40000ddc;
|
||||
ppProcTxSecFrame = 0x40000de0;
|
||||
ppProcessRxPktHdr = 0x40000de4;
|
||||
/*ppProcessTxQ = 0x40000de8;*/
|
||||
ppProcessTxQ = 0x40000de8;
|
||||
ppRecordBarRRC = 0x40000dec;
|
||||
ppRecycleAmpdu = 0x40000df0;
|
||||
ppRecycleRxPkt = 0x40000df4;
|
||||
ppResortTxAMPDU = 0x40000df8;
|
||||
ppResumeTxAMPDU = 0x40000dfc;
|
||||
ppRxFragmentProc = 0x40000e00;
|
||||
/*ppRxPkt = 0x40000e04;*/
|
||||
ppRxPkt = 0x40000e04;
|
||||
ppRxProtoProc = 0x40000e08;
|
||||
ppSearchTxQueue = 0x40000e0c;
|
||||
ppSearchTxframe = 0x40000e10;
|
||||
@ -214,7 +205,7 @@ ppMapWaitTxq = 0x40000e44;
|
||||
ppProcessWaitingQueue = 0x40000e48;
|
||||
ppDisableQueue = 0x40000e4c;
|
||||
ppCheckTxRTS = 0x40000e50;
|
||||
/*ppProcessLifeTime = 0x40000e54;*/
|
||||
ppProcessLifeTime = 0x40000e54;
|
||||
ppProcTxCallback = 0x40000e58;
|
||||
ppCalPreFecPaddingFactor = 0x40000e5c;
|
||||
ppCalDeliNum = 0x40000e60;
|
||||
@ -228,7 +219,7 @@ pp_coex_tx_release = 0x40000e7c;
|
||||
ppAdd2AMPDUTail = 0x40000e80;
|
||||
ppDirectRecycleAmpdu = 0x40000e84;
|
||||
ppRegressAmpdu = 0x40000e88;
|
||||
/*pp_timer_do_process = 0x40000e8c;*/
|
||||
pp_timer_do_process = 0x40000e8c;
|
||||
rcGetAmpduSched = 0x40000e90;
|
||||
rcUpdateRxDone = 0x40000e94;
|
||||
rc_get_trc = 0x40000e98;
|
||||
@ -238,7 +229,7 @@ rcampduuprate = 0x40000ea4;
|
||||
rcClearCurAMPDUSched = 0x40000ea8;
|
||||
rcClearCurSched = 0x40000eac;
|
||||
rcClearCurStat = 0x40000eb0;
|
||||
/* rcGetSched = 0x40000eb4;*/
|
||||
rcGetSched = 0x40000eb4;
|
||||
rcLowerSched = 0x40000eb8;
|
||||
rcSetTxAmpduLimit = 0x40000ebc;
|
||||
rcTxUpdatePer = 0x40000ec0;
|
||||
@ -278,7 +269,7 @@ wdev_mac_special_reg_store = 0x40000f44;
|
||||
wdev_mac_wakeup = 0x40000f48;
|
||||
wdev_mac_sleep = 0x40000f4c;
|
||||
wDev_ProcessFiq = 0x40000f50;
|
||||
/*wDev_ProcessRxSucData = 0x40000f54;*/
|
||||
wDev_ProcessRxSucData = 0x40000f54;
|
||||
wdevProcessRxSucDataAll = 0x40000f58;
|
||||
wdev_csi_len_align = 0x40000f5c;
|
||||
wDev_IndicateBeaconMemoryFrame = 0x40000f60;
|
||||
@ -290,8 +281,6 @@ wdev_process_tsf_timer = 0x40000f74;
|
||||
wdev_process_beacon_filter = 0x40000f78;
|
||||
wdev_process_mac_modem_beacon_miss = 0x40000f7c;
|
||||
config_is_cache_tx_buf_enabled = 0x40000f80;
|
||||
config_get_wifi_feature_capabilities = 0x40000f84;
|
||||
config_get_wifi_ampdu_tx_hetb_tid_limit = 0x40000f88;
|
||||
esp_test_disable_tx_statistics = 0x40000f8c;
|
||||
esp_test_enable_tx_statistics = 0x40000f90;
|
||||
esp_test_clr_tx_statistics = 0x40000f94;
|
||||
@ -451,3 +440,33 @@ g_pp_timer_info_ptr = 0x4084fc98;
|
||||
g_rts_threshold_bytes_ptr = 0x4084fc94;
|
||||
g_he_max_apep_length_tab_ptr = 0x4084fc90;
|
||||
s_tbttstart = 0x4084fc88;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group rom_pp
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
pm_get_tbtt_count = 0x400014c8;
|
||||
tsf_hal_get_time = 0x400014cc;
|
||||
tsf_hal_get_counter_value = 0x400014d0;
|
||||
|
||||
/***************************************
|
||||
Group rom_pp
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
pm_save_tbtt_info = 0x40001550;
|
||||
pm_beacon_offset_is_enabled = 0x40001554;
|
||||
pm_beacon_offset_is_sampling = 0x40001558;
|
||||
pm_beacon_offset_add_total_counter = 0x4000155c;
|
||||
pm_beacon_offset_add_loss_counter = 0x40001560;
|
||||
pm_beacon_offset_check = 0x40001564;
|
||||
pm_beacon_offset_get_average = 0x40001568;
|
||||
pm_beacon_offset_get_expect = 0x4000156c;
|
||||
pm_beacon_offset_get_params = 0x40001570;
|
||||
pm_beacon_monitor_tbtt_stop = 0x40001574;
|
||||
pm_enable_max_idle_timer = 0x40001578;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
s_pm_beacon_offset_ptr = 0x4084fc64;
|
||||
s_pm_beacon_offset_config_ptr = 0x4084fc60;
|
||||
|
||||
@ -1,14 +1,10 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/* ROM function interface esp32c61.rom.rvfp.ld for esp32c61
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
|
||||
/* ROM function interface
|
||||
*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*/
|
||||
@ -61,9 +57,10 @@ __muldf3 = 0x40000a14;
|
||||
__nedf2 = 0x40000a18;
|
||||
__subdf3 = 0x40000a1c;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group libgcc
|
||||
***************************************/
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
__divsf3 = 0x40000828;
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -9,9 +9,8 @@
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
|
||||
/* systimer_hal_init = 0x400003d0; */
|
||||
/* systimer_hal_deinit = 0x400003d4; */
|
||||
systimer_hal_init = 0x400003d0;
|
||||
systimer_hal_deinit = 0x400003d4;
|
||||
systimer_hal_set_tick_rate_ops = 0x400003d8;
|
||||
systimer_hal_get_counter_value = 0x400003dc;
|
||||
systimer_hal_get_time = 0x400003e0;
|
||||
|
||||
@ -9,8 +9,6 @@ entries:
|
||||
esp_rom_cache_esp32s2_esp32s3 (noflash)
|
||||
if ESP_ROM_HAS_CACHE_WRITEBACK_BUG = y:
|
||||
esp_rom_cache_writeback_esp32s3 (noflash)
|
||||
if ESP_ROM_CACHE_WB_INVLD_LOW_RANGE = y:
|
||||
esp_rom_cache_esp32c61 (noflash)
|
||||
if HEAP_TLSF_USE_ROM_IMPL = y && (ESP_ROM_TLSF_CHECK_PATCH = y || HEAP_TLSF_CHECK_PATCH = y):
|
||||
esp_rom_tlsf (noflash)
|
||||
if SOC_SYSTIMER_SUPPORTED = y:
|
||||
|
||||
@ -1,97 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_rom_caps.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/cache_reg.h"
|
||||
#include "soc/cache_struct.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/assert.h"
|
||||
#include "esp32c61/rom/cache.h"
|
||||
|
||||
#include "esp_rom_sys.h"
|
||||
|
||||
#define CACHE_MAX_SYNC_NUM ((CACHE_SYNC_SIZE + 1) >> 1)
|
||||
|
||||
/**
|
||||
* @brief Sync Cache items
|
||||
*
|
||||
* @param type sync type
|
||||
* @param addr address
|
||||
* @param bytes bytes to be synced
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void s_cache_sync_items(uint32_t type, uint32_t addr, uint32_t bytes)
|
||||
{
|
||||
REG_WRITE(CACHE_SYNC_ADDR_REG, addr);
|
||||
REG_SET_FIELD(CACHE_SYNC_SIZE_REG, CACHE_SYNC_SIZE, bytes);
|
||||
REG_SET_BIT(CACHE_SYNC_CTRL_REG, type);
|
||||
while (!REG_GET_BIT(CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE))
|
||||
;
|
||||
}
|
||||
|
||||
int Cache_Invalidate_Addr(uint32_t vaddr, uint32_t size)
|
||||
{
|
||||
uint32_t plus = 0;
|
||||
uint32_t cache_line_size = 32;
|
||||
uint32_t cache_max_sync_size = CACHE_MAX_SYNC_NUM;
|
||||
if (size == 0) {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
//aligned start address to cache line size
|
||||
plus = vaddr & (cache_line_size - 1);
|
||||
vaddr -= plus;
|
||||
//make the length fit the start address
|
||||
size += plus;
|
||||
//aligned the length to cache line size(0->0)
|
||||
size = (size + cache_line_size - 1) & ~(cache_line_size - 1);
|
||||
|
||||
while (size > 0) {
|
||||
//aligned to cache_max_sync_size, (0->cache_max_sync_size)
|
||||
uint32_t this_size = ((vaddr + cache_max_sync_size) & ~(cache_max_sync_size - 1)) - vaddr;
|
||||
if (this_size > size) {
|
||||
this_size = size;
|
||||
}
|
||||
s_cache_sync_items(CACHE_SYNC_INVALIDATE, vaddr, this_size);
|
||||
vaddr += this_size;
|
||||
size -= this_size;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int Cache_WriteBack_Addr(uint32_t vaddr, uint32_t size)
|
||||
{
|
||||
uint32_t plus = 0;
|
||||
uint32_t cache_line_size = 32;
|
||||
uint32_t cache_max_sync_size = CACHE_MAX_SYNC_NUM;
|
||||
if (size == 0) {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
//aligned start address to cache line size
|
||||
plus = vaddr & (cache_line_size - 1);
|
||||
vaddr -= plus;
|
||||
//make the length fit the start address
|
||||
size += plus;
|
||||
//aligned the length to cache line size(0->0)
|
||||
size = (size + cache_line_size - 1) & ~(cache_line_size - 1);
|
||||
|
||||
while (size > 0) {
|
||||
//aligned to cache_max_sync_size, (0->cache_max_sync_size)
|
||||
uint32_t this_size = ((vaddr + cache_max_sync_size) & ~(cache_max_sync_size - 1)) - vaddr;
|
||||
if (this_size > size) {
|
||||
this_size = size;
|
||||
}
|
||||
s_cache_sync_items(CACHE_SYNC_WRITEBACK, vaddr, this_size);
|
||||
vaddr += this_size;
|
||||
size -= this_size;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -64,7 +64,7 @@ void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t co
|
||||
}
|
||||
#endif // CONFIG_IDF_TARGET_ESP32C2 && (CONFIG_ESP32C2_REV_MIN_FULL < 200)
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4
|
||||
void systimer_hal_init(systimer_hal_context_t *hal)
|
||||
{
|
||||
hal->dev = &SYSTIMER;
|
||||
@ -78,6 +78,6 @@ void systimer_hal_deinit(systimer_hal_context_t *hal)
|
||||
systimer_ll_enable_clock(hal->dev, false);
|
||||
hal->dev = NULL;
|
||||
}
|
||||
#endif // CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4
|
||||
#endif // CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4
|
||||
|
||||
#endif // CONFIG_HAL_SYSTIMER_USE_ROM_IMPL
|
||||
|
||||
Reference in New Issue
Block a user