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Merge branch 'fix/esp32c5_rng_random_disable' into 'master'

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fix(bootloader): update random disable api for ESP32-C5/C6

Closes IDFGH-13185 and IDFGH-13368

See merge request espressif/esp-idf!32700
This commit is contained in:
Mahavir Jain
2024-08-12 12:28:13 +08:00
parent 3e30e302c7 f38f77a7fc
commit c3b58b9476
2 changed files with 0 additions and 6 deletions
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3
components/bootloader_support/src/bootloader_random_esp32c5.c
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@@ -94,9 +94,6 @@ void bootloader_random_disable(void)
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_EN_TOUT_ADDR, 0); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_EN_TOUT_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_EN_TOUT_ADDR, 0); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_EN_TOUT_ADDR, 0);
// Revert PMU_RF_PWC_REG to it's initial value
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
// disable ADC_CTRL_CLK (SAR ADC function clock) // disable ADC_CTRL_CLK (SAR ADC function clock)
REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000); REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);

3
components/bootloader_support/src/bootloader_random_esp32c6.c
View File

@@ -88,9 +88,6 @@ void bootloader_random_disable(void)
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
// Revert PMU_RF_PWC_REG to it's initial value
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
// disable ADC_CTRL_CLK (SAR ADC function clock) // disable ADC_CTRL_CLK (SAR ADC function clock)
REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000); REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);