Merge branch 'ci/backport_i2s_ci_fix_to_v5.3' into 'release/v5.3'

ci(i2s&parlio): backport i2s and parlio ci fix (v5.3)

See merge request espressif/esp-idf!34587

components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
@@ -279,22 +279,15 @@ static void test_i2s_external_clk_src(bool is_master, bool is_external)
         .slot_cfg = I2S_STD_MSB_SLOT_DEFAULT_CONFIG(16, I2S_SLOT_MODE_STEREO),
         .gpio_cfg = TEST_I2S_DEFAULT_GPIO(TEST_I2S_MCK_IO, is_master),
     };
+    std_cfg.clk_cfg.mclk_multiple = I2S_MCLK_MULTIPLE_512;
     if (is_external) {
         std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_EXTERNAL;
-        std_cfg.clk_cfg.ext_clk_freq_hz = 11289600;
+        std_cfg.clk_cfg.ext_clk_freq_hz = 22579200;
     }
     TEST_ESP_OK(i2s_channel_init_std_mode(tx_handle, &std_cfg));
-    if (is_master && !is_external) {
-        i2s_std_slot_config_t slot_cfg = I2S_STD_PHILIPS_SLOT_DEFAULT_CONFIG(16, I2S_SLOT_MODE_STEREO);
-        memcpy(&std_cfg.slot_cfg, &slot_cfg, sizeof(i2s_std_slot_config_t));
-    }
     TEST_ESP_OK(i2s_channel_init_std_mode(rx_handle, &std_cfg));
 
     if (is_master) {
-        if (!is_external) {
-            // Delay bclk to get compensate the data delay
-            I2S0.rx_timing.rx_bck_out_dm = 1;
-        }
         uint8_t mst_tx_data[4] = {0x12, 0x34, 0x56, 0x78};
         size_t w_bytes = 4;
         while (w_bytes == 4) {

components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c

@@ -178,6 +178,8 @@ static void pulse_delimiter_sender_task_i2s(void *args)
     }
 }
 
+#if CONFIG_IDF_TARGET_ESP32C6   // TODO: IDF-9806 fix the bit shift issue in other target
+
 static void cs_high(spi_transaction_t *trans)
 {
     gpio_set_level(TEST_VALID_GPIO, 1);
@@ -274,6 +276,7 @@ static void level_delimiter_sender_task_spi(void *args)
         vTaskDelay(portMAX_DELAY);
     }
 }
+#endif
 
 static bool test_delimiter(parlio_rx_delimiter_handle_t deli, bool free_running_clk, void (*sender_task_thread)(void *args))
 {
@@ -339,6 +342,7 @@ static bool test_delimiter(parlio_rx_delimiter_handle_t deli, bool free_running_
     return is_success;
 }
 
+#if CONFIG_IDF_TARGET_ESP32C6   // TODO: IDF-9806 fix the bit shift issue in other target
 // This test case uses level delimiter
 TEST_CASE("parallel_rx_unit_level_delimiter_test_via_spi", "[parlio_rx]")
 {
@@ -358,13 +362,14 @@ TEST_CASE("parallel_rx_unit_level_delimiter_test_via_spi", "[parlio_rx]")
     TEST_ESP_OK(parlio_del_rx_delimiter(deli));
     TEST_ASSERT(is_success);
 }
+#endif
 
 // This test case uses pulse delimiter
 TEST_CASE("parallel_rx_unit_pulse_delimiter_test_via_i2s", "[parlio_rx]")
 {
     parlio_rx_pulse_delimiter_config_t pls_deli_cfg = {
         .valid_sig_line_id = TEST_VALID_SIG,
-        .sample_edge = PARLIO_SAMPLE_EDGE_POS,
+        .sample_edge = PARLIO_SAMPLE_EDGE_NEG,
         .bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB,
         .eof_data_len = TEST_EOF_DATA_LEN,
         .timeout_ticks = 0,

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -1107,10 +1107,22 @@ config SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH
     int
     default 16
 
+config SOC_PARLIO_TX_CLK_SUPPORT_GATING
+    bool
+    default y
+
+config SOC_PARLIO_RX_CLK_SUPPORT_GATING
+    bool
+    default y
+
 config SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
     bool
     default y
 
+config SOC_PARLIO_TRANS_BIT_ALIGN
+    bool
+    default y
+
 config SOC_PARLIO_TX_SIZE_BY_DMA
     bool
     default y

components/soc/esp32p4/include/soc/soc_caps.h

@@ -420,7 +420,10 @@
 #define SOC_PARLIO_RX_UNITS_PER_GROUP        1U  /*!< number of RX units in each group */
 #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH    16  /*!< Number of data lines of the TX unit */
 #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH    16  /*!< Number of data lines of the RX unit */
+#define SOC_PARLIO_TX_CLK_SUPPORT_GATING     1  /*!< Support gating TX clock */
+#define SOC_PARLIO_RX_CLK_SUPPORT_GATING     1  /*!< Support gating RX clock */
 #define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT     1  /*!< Support output RX clock to a GPIO */
+#define SOC_PARLIO_TRANS_BIT_ALIGN           1  /*!< Support bit alignment in transaction */
 #define SOC_PARLIO_TX_SIZE_BY_DMA            1   /*!< Transaction length is controlled by DMA instead of indicated by register */
 
 /*--------------------------- MPI CAPS ---------------------------------------*/

examples/peripherals/.build-test-rules.yml

@@ -262,20 +262,12 @@ examples/peripherals/mcpwm/mcpwm_sync:
 examples/peripherals/parlio:
   disable:
     - if: SOC_PARLIO_SUPPORTED != 1
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: lack of runner
   depends_components:
     - esp_driver_parlio
 
 examples/peripherals/parlio/parlio_rx:
   disable:
     - if: SOC_PARLIO_SUPPORTED != 1
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: lack of runner
   depends_components:
     - esp_driver_parlio
 

examples/peripherals/parlio/parlio_rx/logic_analyzer/pytest_logic_analyzer.py

@@ -0,0 +1,22 @@
+# SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: CC0-1.0
+import pytest
+from pytest_embedded import Dut
+
+
+@pytest.mark.esp32c6
+@pytest.mark.esp32h2
+@pytest.mark.esp32p4
+@pytest.mark.generic
+@pytest.mark.parametrize(
+    'config',
+    [
+        'flash_stream',
+    ],
+    indirect=True,
+)
+def test_logic_analyzer_flash_stream(dut: Dut) -> None:
+    dut.expect(r'flash_fat: Probe data partition base addr: \w+ size: \w+')
+    dut.expect(r'flash_fat: flash FATFS mounted')
+    dut.expect(r'esp_probe: Dump data size reached the max dump size')
+    dut.expect(r'example: Probe finished! [0-9]+ \(\w+\) bytes dumped')

examples/peripherals/parlio/parlio_rx/logic_analyzer/sdkconfig.ci.flash_stream

@@ -0,0 +1 @@
+CONFIG_EXAMPLE_FLASH_STREAM=y