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change(hal): add union enum type for modem peripheral 32k source selection

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This commit is contained in:
wuzhenghui
2025-06-18 11:48:48 +08:00
parent 78baff95ec
commit c7f114e0a9
13 changed files with 65 additions and 92 deletions
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2
components/hal/esp32c5/include/hal/modem_lpcon_ll.h
View File

@@ -146,7 +146,7 @@ static inline void modem_lpcon_ll_set_clk_modem_aon_force(modem_lpcon_dev_t *hw,
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_select_modem_32k_clock_source(modem_lpcon_dev_t *hw, uint32_t src)
static inline void modem_lpcon_ll_select_modem_32k_clock_source(modem_lpcon_dev_t *hw, modem_clock_32k_clk_src_t src)
{
hw->modem_32k_clk_conf.clk_modem_32k_sel = src;
}

26
components/hal/esp32c5/modem_clock_hal.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,12 +13,6 @@
#include "hal/efuse_hal.h"
#include "hal/assert.h"
typedef enum {
MODEM_CLOCK_XTAL32K_CODE = 0,
MODEM_CLOCK_RC32K_CODE = 1,
MODEM_CLOCK_EXT32K_CODE = 2
} modem_clock_32k_clk_src_code_t;
void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap)
{
HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX);
@@ -154,15 +148,15 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t
break;
case MODEM_CLOCK_LPCLK_SRC_RC32K:
modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_RC32K);
break;
case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_XTAL32K);
break;
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_EXT32K);
break;
default:
HAL_ASSERT(0);
@@ -194,15 +188,15 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo
break;
case MODEM_CLOCK_LPCLK_SRC_RC32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_RC32K);
break;
case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_XTAL32K);
break;
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_EXT32K);
break;
default:
HAL_ASSERT(0);
@@ -234,15 +228,15 @@ void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, mo
break;
case MODEM_CLOCK_LPCLK_SRC_RC32K:
modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_RC32K);
break;
case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_XTAL32K);
break;
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_EXT32K);
break;
default:
HAL_ASSERT(0);

2
components/hal/esp32c6/include/hal/modem_lpcon_ll.h
View File

@@ -134,7 +134,7 @@ static inline uint32_t modem_lpcon_ll_get_wifi_lpclk_divisor_value(modem_lpcon_d
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_select_modem_32k_clock_source(modem_lpcon_dev_t *hw, uint32_t src)
static inline void modem_lpcon_ll_select_modem_32k_clock_source(modem_lpcon_dev_t *hw, modem_clock_32k_clk_src_t src)
{
hw->modem_32k_clk_conf.clk_modem_32k_sel = src;
}

26
components/hal/esp32c6/modem_clock_hal.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,12 +13,6 @@
#include "hal/efuse_hal.h"
#include "hal/assert.h"
typedef enum {
MODEM_CLOCK_XTAL32K_CODE = 0,
MODEM_CLOCK_RC32K_CODE = 1,
MODEM_CLOCK_EXT32K_CODE = 2
} modem_clock_32k_clk_src_code_t;
void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap)
{
HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX);
@@ -152,15 +146,15 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t
break;
case MODEM_CLOCK_LPCLK_SRC_RC32K:
modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_RC32K);
break;
case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_XTAL32K);
break;
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_EXT32K);
break;
default:
HAL_ASSERT(0);
@@ -192,15 +186,15 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo
break;
case MODEM_CLOCK_LPCLK_SRC_RC32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_RC32K);
break;
case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_XTAL32K);
break;
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_EXT32K);
break;
default:
HAL_ASSERT(0);
@@ -232,15 +226,15 @@ void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, mo
break;
case MODEM_CLOCK_LPCLK_SRC_RC32K:
modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_RC32K);
break;
case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_XTAL32K);
break;
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_EXT32K);
break;
default:
HAL_ASSERT(0);

2
components/hal/esp32c61/include/hal/modem_lpcon_ll.h
View File

@@ -146,7 +146,7 @@ static inline void modem_lpcon_ll_set_clk_modem_aon_force(modem_lpcon_dev_t *hw,
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_select_modem_32k_clock_source(modem_lpcon_dev_t *hw, uint32_t src)
static inline void modem_lpcon_ll_select_modem_32k_clock_source(modem_lpcon_dev_t *hw, modem_clock_32k_clk_src_t src)
{
hw->modem_32k_clk_conf.clk_modem_32k_sel = src;
}

26
components/hal/esp32c61/modem_clock_hal.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,12 +13,6 @@
#include "hal/efuse_hal.h"
#include "hal/assert.h"
typedef enum {
MODEM_CLOCK_XTAL32K_CODE = 0,
MODEM_CLOCK_RC32K_CODE = 1,
MODEM_CLOCK_EXT32K_CODE = 2
} modem_clock_32k_clk_src_code_t;
void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap)
{
HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX);
@@ -154,15 +148,15 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t
break;
case MODEM_CLOCK_LPCLK_SRC_RC32K:
modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_RC32K);
break;
case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_XTAL32K);
break;
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_EXT32K);
break;
default:
HAL_ASSERT(0);
@@ -194,15 +188,15 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo
break;
case MODEM_CLOCK_LPCLK_SRC_RC32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_RC32K);
break;
case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_XTAL32K);
break;
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_EXT32K);
break;
default:
HAL_ASSERT(0);
@@ -234,15 +228,15 @@ void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, mo
break;
case MODEM_CLOCK_LPCLK_SRC_RC32K:
modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_RC32K);
break;
case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_XTAL32K);
break;
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_32K_SRC_EXT32K);
break;
default:
HAL_ASSERT(0);

3
components/hal/esp32h2/include/hal/lp_clkrst_ll.h
View File

@@ -13,6 +13,7 @@
#include "soc/soc.h"
#include "soc/lp_clkrst_struct.h"
#include "soc/lpperi_struct.h"
#include "hal/modem_clock_types.h"
#ifdef __cplusplus
extern "C" {
@@ -55,7 +56,7 @@ static inline uint32_t lp_clkrst_ll_get_ble_rtc_timer_divisor_value(lp_clkrst_de
}
__attribute__((always_inline))
static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *hw, uint32_t src)
static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *hw, modem_clock_32k_clk_src_t src)
{
hw->lpperi.lp_bletimer_32k_sel = src;
}

20
components/hal/esp32h2/modem_clock_hal.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,12 +13,6 @@
#include "hal/modem_clock_types.h"
#include "hal/assert.h"
typedef enum {
MODEM_CLOCK_XTAL32K_CODE = 0,
MODEM_CLOCK_RC32K_CODE = 1,
MODEM_CLOCK_EXT32K_CODE = 2
} modem_clock_32k_clk_src_code_t;
void IRAM_ATTR modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable)
{
modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable);
@@ -68,15 +62,15 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t
break;
case MODEM_CLOCK_LPCLK_SRC_RC32K:
lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_RC32K);
break;
case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_XTAL32K);
break;
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_EXT32K);
break;
default:
HAL_ASSERT(0);
@@ -108,15 +102,15 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo
break;
case MODEM_CLOCK_LPCLK_SRC_RC32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_RC32K);
break;
case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_XTAL32K);
break;
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_EXT32K);
break;
default:
HAL_ASSERT(0);

3
components/hal/esp32h21/include/hal/lp_clkrst_ll.h
View File

@@ -13,6 +13,7 @@
#include "soc/soc.h"
#include "soc/lp_clkrst_struct.h"
#include "soc/lpperi_struct.h"
#include "hal/modem_clock_types.h"
#ifdef __cplusplus
extern "C" {
@@ -55,7 +56,7 @@ static inline uint32_t lp_clkrst_ll_get_ble_rtc_timer_divisor_value(lp_clkrst_de
}
__attribute__((always_inline))
static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *hw, uint32_t src)
static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *hw, modem_clock_32k_clk_src_t src)
{
hw->lpperi.clkrst_lp_bletimer_32k_sel = src;
}

18
components/hal/esp32h21/modem_clock_hal.c
View File

@@ -13,12 +13,6 @@
#include "hal/modem_clock_types.h"
#include "hal/assert.h"
typedef enum {
MODEM_CLOCK_XTAL32K_CODE = 0,
MODEM_CLOCK_RC32K_CODE = 1,
MODEM_CLOCK_EXT32K_CODE = 2
} modem_clock_32k_clk_src_code_t;
void IRAM_ATTR modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable)
{
modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable);
@@ -69,15 +63,15 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t
break;
case MODEM_CLOCK_LPCLK_SRC_RC32K:
lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_RC32K);
break;
case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_XTAL32K);
break;
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_EXT32K);
break;
default:
HAL_ASSERT(0);
@@ -109,15 +103,15 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo
break;
case MODEM_CLOCK_LPCLK_SRC_RC32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_RC32K);
break;
case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_XTAL32K);
break;
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_EXT32K);
break;
default:
HAL_ASSERT(0);

3
components/hal/esp32h4/include/hal/lp_clkrst_ll.h
View File

@@ -13,6 +13,7 @@
#include "soc/soc.h"
#include "soc/lp_clkrst_struct.h"
#include "soc/lpperi_struct.h"
#include "hal/modem_clock_types.h"
#ifdef __cplusplus
extern "C" {
@@ -55,7 +56,7 @@ static inline uint32_t lp_clkrst_ll_get_ble_rtc_timer_divisor_value(lp_clkrst_de
}
__attribute__((always_inline))
static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *hw, uint32_t src)
static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *hw, modem_clock_32k_clk_src_t src)
{
hw->lpperi.lp_bletimer_32k_sel = src;
}

18
components/hal/esp32h4/modem_clock_hal.c
View File

@@ -13,12 +13,6 @@
#include "hal/modem_clock_types.h"
#include "hal/assert.h"
typedef enum {
MODEM_CLOCK_XTAL32K_CODE = 0,
MODEM_CLOCK_RC32K_CODE = 1,
MODEM_CLOCK_EXT32K_CODE = 2
} modem_clock_32k_clk_src_code_t;
void IRAM_ATTR modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable)
{
modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable);
@@ -68,15 +62,15 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t
break;
case MODEM_CLOCK_LPCLK_SRC_RC32K:
lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_RC32K);
break;
case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_XTAL32K);
break;
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_EXT32K);
break;
default:
HAL_ASSERT(0);
@@ -108,15 +102,15 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo
break;
case MODEM_CLOCK_LPCLK_SRC_RC32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_RC32K);
break;
case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_XTAL32K);
break;
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_32K_SRC_EXT32K);
break;
default:
HAL_ASSERT(0);

8
components/hal/include/hal/modem_clock_types.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -35,6 +35,12 @@ typedef enum {
MODEM_CLOCK_LPCLK_SRC_MAX
} modem_clock_lpclk_src_t;
typedef enum {
MODEM_CLOCK_32K_SRC_XTAL32K = 0,
MODEM_CLOCK_32K_SRC_RC32K = 1,
MODEM_CLOCK_32K_SRC_EXT32K = 2
} modem_clock_32k_clk_src_t;
#ifdef __cplusplus
}
#endif