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refactor(usb): Include supported PHYs information in SoC

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This commit is contained in:
Tomas Rezucha
2025-01-22 13:19:22 +01:00
parent d12312bf76
commit cd7fab3bdc
4 changed files with 15 additions and 0 deletions
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2
components/soc/esp32p4/usb_dwc_periph.c
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@@ -42,6 +42,7 @@ const usb_dwc_info_t usb_dwc_info = {
.fsls_signals = NULL, .fsls_signals = NULL,
.otg_signals = NULL, .otg_signals = NULL,
.internal_phy_io = NULL, // HS PHY is not mapped to any GPIO .internal_phy_io = NULL, // HS PHY is not mapped to any GPIO
.supported_phys = USB_PHY_INST_UTMI_0,
.irq = ETS_USB_OTG_INTR_SOURCE, .irq = ETS_USB_OTG_INTR_SOURCE,
.irq_2nd_cpu = ETS_USB_OTG_ENDP_MULTI_PROC_INTR_SOURCE, .irq_2nd_cpu = ETS_USB_OTG_ENDP_MULTI_PROC_INTR_SOURCE,
}, },
@@ -50,6 +51,7 @@ const usb_dwc_info_t usb_dwc_info = {
.fsls_signals = NULL, .fsls_signals = NULL,
.otg_signals = &dwc_fs_otg_signals, .otg_signals = &dwc_fs_otg_signals,
.internal_phy_io = &internal_phy_io, .internal_phy_io = &internal_phy_io,
.supported_phys = USB_PHY_INST_FSLS_INTERN_0,
.irq = ETS_USB_OTG11_CH0_INTR_SOURCE, .irq = ETS_USB_OTG11_CH0_INTR_SOURCE,
.irq_2nd_cpu = -1, .irq_2nd_cpu = -1,
}, },

1
components/soc/esp32s2/usb_dwc_periph.c
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@@ -52,6 +52,7 @@ const usb_dwc_info_t usb_dwc_info = {
.fsls_signals = &fsls_signals, .fsls_signals = &fsls_signals,
.otg_signals = &otg_signals, .otg_signals = &otg_signals,
.internal_phy_io = &internal_phy_io, .internal_phy_io = &internal_phy_io,
.supported_phys = USB_PHY_INST_FSLS_INTERN_0,
.irq = ETS_USB_INTR_SOURCE, .irq = ETS_USB_INTR_SOURCE,
.irq_2nd_cpu = -1, .irq_2nd_cpu = -1,
}, },

1
components/soc/esp32s3/usb_dwc_periph.c
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@@ -52,6 +52,7 @@ const usb_dwc_info_t usb_dwc_info = {
.fsls_signals = &fsls_signals, .fsls_signals = &fsls_signals,
.otg_signals = &otg_signals, .otg_signals = &otg_signals,
.internal_phy_io = &internal_phy_io, .internal_phy_io = &internal_phy_io,
.supported_phys = USB_PHY_INST_FSLS_INTERN_0,
.irq = ETS_USB_INTR_SOURCE, .irq = ETS_USB_INTR_SOURCE,
.irq_2nd_cpu = -1, .irq_2nd_cpu = -1,
}, },

11
components/soc/include/soc/usb_dwc_periph.h
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@@ -16,6 +16,16 @@ extern "C" {
/* ---------------------------------- Types --------------------------------- */ /* ---------------------------------- Types --------------------------------- */
/**
* @brief USB PHY Instance Type
*/
typedef enum {
USB_PHY_INST_FSLS_INTERN_0 = (1 << 0),
USB_PHY_INST_FSLS_INTERN_1 = (1 << 1),
USB_PHY_INST_UTMI_0 = (1 << 2),
USB_PHY_INST_EXTERN = (1 << 3),
} usb_phy_inst_t;
/** /**
* @brief USB PHY FSLS Serial Interface Signals * @brief USB PHY FSLS Serial Interface Signals
* *
@@ -83,6 +93,7 @@ typedef struct {
const usb_fsls_serial_signal_conn_t * const fsls_signals; // Must be set if external PHY is supported by controller const usb_fsls_serial_signal_conn_t * const fsls_signals; // Must be set if external PHY is supported by controller
const usb_otg_signal_conn_t * const otg_signals; const usb_otg_signal_conn_t * const otg_signals;
const usb_internal_phy_io_t * const internal_phy_io; // Must be set for internal FSLS PHY(s) const usb_internal_phy_io_t * const internal_phy_io; // Must be set for internal FSLS PHY(s)
const usb_phy_inst_t supported_phys; // Bitmap of supported PHYs by this controller
const int irq; const int irq;
const int irq_2nd_cpu; // The USB-DWC can provide 2nd interrupt so each CPU can have its own interrupt line. Set to -1 if not supported const int irq_2nd_cpu; // The USB-DWC can provide 2nd interrupt so each CPU can have its own interrupt line. Set to -1 if not supported
} controllers [SOC_USB_OTG_PERIPH_NUM]; } controllers [SOC_USB_OTG_PERIPH_NUM];