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Merge branch 'feat/support_rmt_on_h4' into 'master'

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feat(rmt): support rmt on ESP32-H4

Closes IDF-12402

See merge request espressif/esp-idf!40523
This commit is contained in:
Chen Ji Chang
2025-07-25 19:41:24 +08:00
parent d1ea45202e d6a9a0f5d5
commit cfca52255e
29 changed files with 1259 additions and 158 deletions
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6
components/driver/deprecated/rmt_legacy.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -156,7 +156,7 @@ static void rmt_module_disable(void)
{
RMT_ENTER_CRITICAL();
if (rmt_contex.rmt_module_enabled == true) {
rmt_ll_mem_force_power_off(rmt_contex.hal.regs);
rmt_ll_mem_force_low_power(rmt_contex.hal.regs);
RMT_RCC_ATOMIC() {
rmt_ll_enable_bus_clock(0, false);
}
@@ -257,7 +257,7 @@ esp_err_t rmt_set_mem_pd(rmt_channel_t channel, bool pd_en)
ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
RMT_ENTER_CRITICAL();
if (pd_en) {
rmt_ll_mem_force_power_off(rmt_contex.hal.regs);
rmt_ll_mem_force_low_power(rmt_contex.hal.regs);
} else {
rmt_ll_mem_power_by_pmu(rmt_contex.hal.regs);
}

4
components/driver/test_apps/legacy_rmt_driver/README.md
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@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

4
components/esp_driver_rmt/test_apps/rmt/README.md
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@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

2
components/esp_driver_rmt/test_apps/rmt/main/test_rmt_tx.c
View File

@@ -708,7 +708,7 @@ TEST_CASE("rmt tx gpio switch test", "[rmt]")
printf("install tx channel\r\n");
rmt_channel_handle_t tx_channel = NULL;
TEST_ESP_OK(rmt_new_tx_channel(&tx_channel_cfg, &tx_channel));
printf("install bytes encoder\r\n");
printf("install copy encoder\r\n");
rmt_encoder_handle_t copy_encoder = NULL;
rmt_copy_encoder_config_t copy_encoder_config = {};
TEST_ESP_OK(rmt_new_copy_encoder(&copy_encoder_config, &copy_encoder));

31
components/hal/esp32/include/hal/rmt_ll.h
View File

@@ -41,6 +41,10 @@ typedef enum {
RMT_LL_MEM_OWNER_HW = 1,
} rmt_ll_mem_owner_t;
typedef enum {
RMT_LL_MEM_LP_MODE_SHUT_DOWN, // power down memory during low power stage
} rmt_ll_mem_lp_mode_t;
/**
* @brief Enable the bus clock for RMT module
*
@@ -82,17 +86,6 @@ static inline void rmt_ll_reset_register(int group_id)
rmt_ll_reset_register(__VA_ARGS__); \
} while(0)
/**
* @brief Enable clock gate for register and memory
*
* @param dev Peripheral instance address
* @param enable True to enable, False to disable
*/
static inline void rmt_ll_enable_periph_clock(rmt_dev_t *dev, bool enable)
{
dev->conf_ch[0].conf0.clk_en = enable; // register clock gating
}
/**
* @brief Force power on the RMT memory block, regardless of the outside PMU logic
*
@@ -104,11 +97,11 @@ static inline void rmt_ll_mem_force_power_on(rmt_dev_t *dev)
}
/**
* @brief Force power off the RMT memory block, regardless of the outside PMU logic
* @brief Force the RMT memory block into low power mode, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_force_power_off(rmt_dev_t *dev)
static inline void rmt_ll_mem_force_low_power(rmt_dev_t *dev)
{
dev->conf_ch[0].conf0.mem_pd = 1;
}
@@ -123,6 +116,18 @@ static inline void rmt_ll_mem_power_by_pmu(rmt_dev_t *dev)
dev->conf_ch[0].conf0.mem_pd = 0;
}
/**
* @brief Set low power mode for RMT memory block
*
* @param dev Peripheral instance address
* @param mode RMT memory low power mode in low power stage
*/
static inline void rmt_ll_mem_set_low_power_mode(rmt_dev_t *dev, rmt_ll_mem_lp_mode_t mode)
{
(void)dev;
HAL_ASSERT(mode == RMT_LL_MEM_LP_MODE_SHUT_DOWN);
}
/**
* @brief Enable APB accessing RMT memory in nonfifo mode
*

32
components/hal/esp32c3/include/hal/rmt_ll.h
View File

@@ -47,6 +47,10 @@ typedef enum {
RMT_LL_MEM_OWNER_HW = 1,
} rmt_ll_mem_owner_t;
typedef enum {
RMT_LL_MEM_LP_MODE_SHUT_DOWN, // power down memory during low power stage
} rmt_ll_mem_lp_mode_t;
/**
* @brief Enable the bus clock for RMT module
*
@@ -85,18 +89,6 @@ static inline void rmt_ll_reset_register(int group_id)
rmt_ll_reset_register(__VA_ARGS__); \
} while(0)
/**
* @brief Enable clock gate for register and memory
*
* @param dev Peripheral instance address
* @param enable True to enable, False to disable
*/
static inline void rmt_ll_enable_periph_clock(rmt_dev_t *dev, bool enable)
{
dev->sys_conf.clk_en = enable; // register clock gating
dev->sys_conf.mem_clk_force_on = enable; // memory clock gating
}
/**
* @brief Force power on the RMT memory block, regardless of the outside PMU logic
*
@@ -109,11 +101,11 @@ static inline void rmt_ll_mem_force_power_on(rmt_dev_t *dev)
}
/**
* @brief Force power off the RMT memory block, regardless of the outside PMU logic
* @brief Force the RMT memory block into low power mode, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_force_power_off(rmt_dev_t *dev)
static inline void rmt_ll_mem_force_low_power(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pd = 1;
dev->sys_conf.mem_force_pu = 0;
@@ -130,6 +122,18 @@ static inline void rmt_ll_mem_power_by_pmu(rmt_dev_t *dev)
dev->sys_conf.mem_force_pu = 0;
}
/**
* @brief Set low power mode for RMT memory block
*
* @param dev Peripheral instance address
* @param mode RMT memory low power mode in low power stage
*/
static inline void rmt_ll_mem_set_low_power_mode(rmt_dev_t *dev, rmt_ll_mem_lp_mode_t mode)
{
(void)dev;
HAL_ASSERT(mode == RMT_LL_MEM_LP_MODE_SHUT_DOWN);
}
/**
* @brief Enable APB accessing RMT memory in nonfifo mode
*

32
components/hal/esp32c5/include/hal/rmt_ll.h
View File

@@ -48,6 +48,10 @@ typedef enum {
RMT_LL_MEM_OWNER_HW = 1,
} rmt_ll_mem_owner_t;
typedef enum {
RMT_LL_MEM_LP_MODE_SHUT_DOWN, // power down memory during low power stage
} rmt_ll_mem_lp_mode_t;
/**
* @brief Enable the bus clock for RMT module
*
@@ -72,18 +76,6 @@ static inline void rmt_ll_reset_register(int group_id)
PCR.rmt_conf.rmt_rst_en = 0;
}
/**
* @brief Enable clock gate for register and memory
*
* @param dev Peripheral instance address
* @param enable True to enable, False to disable
*/
static inline void rmt_ll_enable_periph_clock(rmt_dev_t *dev, bool enable)
{
dev->sys_conf.clk_en = enable; // register clock gating
dev->sys_conf.mem_clk_force_on = enable; // memory clock gating
}
/**
* @brief Force power on the RMT memory block, regardless of the outside PMU logic
*
@@ -96,11 +88,11 @@ static inline void rmt_ll_mem_force_power_on(rmt_dev_t *dev)
}
/**
* @brief Force power off the RMT memory block, regardless of the outside PMU logic
* @brief Force the RMT memory block into low power mode, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_force_power_off(rmt_dev_t *dev)
static inline void rmt_ll_mem_force_low_power(rmt_dev_t *dev)
{
PCR.rmt_pd_ctrl.rmt_mem_force_pd = 1;
PCR.rmt_pd_ctrl.rmt_mem_force_pu = 0;
@@ -117,6 +109,18 @@ static inline void rmt_ll_mem_power_by_pmu(rmt_dev_t *dev)
PCR.rmt_pd_ctrl.rmt_mem_force_pu = 0;
}
/**
* @brief Set low power mode for RMT memory block
*
* @param dev Peripheral instance address
* @param mode RMT memory low power mode in low power stage
*/
static inline void rmt_ll_mem_set_low_power_mode(rmt_dev_t *dev, rmt_ll_mem_lp_mode_t mode)
{
(void)dev;
HAL_ASSERT(mode == RMT_LL_MEM_LP_MODE_SHUT_DOWN);
}
/**
* @brief Enable APB accessing RMT memory in nonfifo mode
*

32
components/hal/esp32c6/include/hal/rmt_ll.h
View File

@@ -48,6 +48,10 @@ typedef enum {
RMT_LL_MEM_OWNER_HW = 1,
} rmt_ll_mem_owner_t;
typedef enum {
RMT_LL_MEM_LP_MODE_SHUT_DOWN, // power down memory during low power stage
} rmt_ll_mem_lp_mode_t;
/**
* @brief Enable the bus clock for RMT module
*
@@ -72,18 +76,6 @@ static inline void rmt_ll_reset_register(int group_id)
PCR.rmt_conf.rmt_rst_en = 0;
}
/**
* @brief Enable clock gate for register and memory
*
* @param dev Peripheral instance address
* @param enable True to enable, False to disable
*/
static inline void rmt_ll_enable_periph_clock(rmt_dev_t *dev, bool enable)
{
dev->sys_conf.clk_en = enable; // register clock gating
dev->sys_conf.mem_clk_force_on = enable; // memory clock gating
}
/**
* @brief Force power on the RMT memory block, regardless of the outside PMU logic
*
@@ -96,11 +88,11 @@ static inline void rmt_ll_mem_force_power_on(rmt_dev_t *dev)
}
/**
* @brief Force power off the RMT memory block, regardless of the outside PMU logic
* @brief Force the RMT memory block into low power mode, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_force_power_off(rmt_dev_t *dev)
static inline void rmt_ll_mem_force_low_power(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pd = 1;
dev->sys_conf.mem_force_pu = 0;
@@ -117,6 +109,18 @@ static inline void rmt_ll_mem_power_by_pmu(rmt_dev_t *dev)
dev->sys_conf.mem_force_pu = 0;
}
/**
* @brief Set low power mode for RMT memory block
*
* @param dev Peripheral instance address
* @param mode RMT memory low power mode in low power stage
*/
static inline void rmt_ll_mem_set_low_power_mode(rmt_dev_t *dev, rmt_ll_mem_lp_mode_t mode)
{
(void)dev;
HAL_ASSERT(mode == RMT_LL_MEM_LP_MODE_SHUT_DOWN);
}
/**
* @brief Enable APB accessing RMT memory in nonfifo mode
*

32
components/hal/esp32h2/include/hal/rmt_ll.h
View File

@@ -48,6 +48,10 @@ typedef enum {
RMT_LL_MEM_OWNER_HW = 1,
} rmt_ll_mem_owner_t;
typedef enum {
RMT_LL_MEM_LP_MODE_SHUT_DOWN, // power down memory during low power stage
} rmt_ll_mem_lp_mode_t;
/**
* @brief Enable the bus clock for RMT module
*
@@ -72,18 +76,6 @@ static inline void rmt_ll_reset_register(int group_id)
PCR.rmt_conf.rmt_rst_en = 0;
}
/**
* @brief Enable clock gate for register and memory
*
* @param dev Peripheral instance address
* @param enable True to enable, False to disable
*/
static inline void rmt_ll_enable_periph_clock(rmt_dev_t *dev, bool enable)
{
dev->sys_conf.clk_en = enable; // register clock gating
dev->sys_conf.mem_clk_force_on = enable; // memory clock gating
}
/**
* @brief Force power on the RMT memory block, regardless of the outside PMU logic
*
@@ -96,11 +88,11 @@ static inline void rmt_ll_mem_force_power_on(rmt_dev_t *dev)
}
/**
* @brief Force power off the RMT memory block, regardless of the outside PMU logic
* @brief Force the RMT memory block into low power mode, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_force_power_off(rmt_dev_t *dev)
static inline void rmt_ll_mem_force_low_power(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pd = 1;
dev->sys_conf.mem_force_pu = 0;
@@ -117,6 +109,18 @@ static inline void rmt_ll_mem_power_by_pmu(rmt_dev_t *dev)
dev->sys_conf.mem_force_pu = 0;
}
/**
* @brief Set low power mode for RMT memory block
*
* @param dev Peripheral instance address
* @param mode RMT memory low power mode in low power stage
*/
static inline void rmt_ll_mem_set_low_power_mode(rmt_dev_t *dev, rmt_ll_mem_lp_mode_t mode)
{
(void)dev;
HAL_ASSERT(mode == RMT_LL_MEM_LP_MODE_SHUT_DOWN);
}
/**
* @brief Enable APB accessing RMT memory in nonfifo mode
*

910
components/hal/esp32h4/include/hal/rmt_ll.h Normal file
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@@ -0,0 +1,910 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @note TX and RX channels are index from 0 in the LL driver, i.e. tx_channel = [0,1], rx_channel = [0,1]
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include "hal/misc.h"
#include "hal/assert.h"
#include "hal/rmt_types.h"
#include "soc/rmt_struct.h"
#include "soc/pcr_struct.h"
#include "soc/retention_periph_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#define RMT_LL_EVENT_TX_DONE(channel) (1 << (channel))
#define RMT_LL_EVENT_TX_THRES(channel) (1 << ((channel) + 8))
#define RMT_LL_EVENT_TX_LOOP_END(channel) (1 << ((channel) + 12))
#define RMT_LL_EVENT_TX_ERROR(channel) (1 << ((channel) + 4))
#define RMT_LL_EVENT_RX_DONE(channel) (1 << ((channel) + 2))
#define RMT_LL_EVENT_RX_THRES(channel) (1 << ((channel) + 10))
#define RMT_LL_EVENT_RX_ERROR(channel) (1 << ((channel) + 6))
#define RMT_LL_EVENT_TX_MASK(channel) (RMT_LL_EVENT_TX_DONE(channel) | RMT_LL_EVENT_TX_THRES(channel) | RMT_LL_EVENT_TX_LOOP_END(channel))
#define RMT_LL_EVENT_RX_MASK(channel) (RMT_LL_EVENT_RX_DONE(channel) | RMT_LL_EVENT_RX_THRES(channel))
#define RMT_LL_MAX_LOOP_COUNT_PER_BATCH 1023
#define RMT_LL_MAX_FILTER_VALUE 255
#define RMT_LL_MAX_IDLE_VALUE 32767
// Maximum values due to limited register bit width
#define RMT_LL_CHANNEL_CLOCK_MAX_PRESCALE 256
#define RMT_LL_GROUP_CLOCK_MAX_INTEGER_PRESCALE 256
#define RMT_LL_GROUP_CLOCK_MAX_FRACTAL_PRESCALE 64
typedef enum {
RMT_LL_MEM_OWNER_SW = 0,
RMT_LL_MEM_OWNER_HW = 1,
} rmt_ll_mem_owner_t;
typedef enum {
RMT_LL_MEM_LP_MODE_DEEP_SLEEP, // memory will enter deep sleep during low power stage, keep memory data
RMT_LL_MEM_LP_MODE_LIGHT_SLEEP, // memory will enter light sleep during low power stage, keep memory data
RMT_LL_MEM_LP_MODE_SHUT_DOWN, // memory will be powered down during low power stage
RMT_LL_MEM_LP_MODE_DISABLE, // disable the low power stage
} rmt_ll_mem_lp_mode_t;
/**
* @brief Enable the bus clock for RMT module
*
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void rmt_ll_enable_bus_clock(int group_id, bool enable)
{
(void)group_id;
PCR.rmt_conf.rmt_clk_en = enable;
}
/**
* @brief Reset the RMT module
*
* @param group_id Group ID
*/
static inline void rmt_ll_reset_register(int group_id)
{
(void)group_id;
PCR.rmt_conf.rmt_rst_en = 1;
PCR.rmt_conf.rmt_rst_en = 0;
}
/**
* @brief Force power on the RMT memory block, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_force_power_on(rmt_dev_t *dev)
{
PCR.rmt_mem_lp_ctrl.rmt_mem_force_ctrl = 1;
PCR.rmt_mem_lp_ctrl.rmt_mem_lp_en = 0;
}
/**
* @brief Force the RMT memory block into low power mode, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_force_low_power(rmt_dev_t *dev)
{
PCR.rmt_mem_lp_ctrl.rmt_mem_force_ctrl = 1;
PCR.rmt_mem_lp_ctrl.rmt_mem_lp_en = 1;
}
/**
* @brief Power control the RMT memory block by the outside PMU logic
*
* @param dev Peripheral instance address
* @param mode RMT memory low power mode in low power stage
*/
static inline void rmt_ll_mem_power_by_pmu(rmt_dev_t *dev)
{
PCR.rmt_mem_lp_ctrl.rmt_mem_force_ctrl = 0;
PCR.rmt_mem_lp_ctrl.rmt_mem_lp_en = 0;
}
/**
* @brief Set low power mode for RMT memory block
*
* @param dev Peripheral instance address
* @param mode RMT memory low power mode in low power stage
*/
static inline void rmt_ll_mem_set_low_power_mode(rmt_dev_t *dev, rmt_ll_mem_lp_mode_t mode)
{
PCR.rmt_mem_lp_ctrl.rmt_mem_lp_mode = mode;
}
/**
* @brief Enable APB accessing RMT memory in nonfifo mode
*
* @param dev Peripheral instance address
* @param enable True to enable, False to disable
*/
static inline void rmt_ll_enable_mem_access_nonfifo(rmt_dev_t *dev, bool enable)
{
dev->sys_conf.apb_fifo_mask = enable;
}
/**
* @brief Set clock source and divider for RMT channel group
*
* @param dev Peripheral instance address
* @param channel not used as clock source is set for all channels
* @param src Clock source
* @param divider_integral Integral part of the divider
* @param divider_denominator Denominator part of the divider
* @param divider_numerator Numerator part of the divider
*/
static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, rmt_clock_source_t src,
uint32_t divider_integral, uint32_t divider_denominator, uint32_t divider_numerator)
{
// Formula: rmt_sclk = module_clock_src / (1 + div_num + div_a / div_b)
(void)channel; // the source clock is set for all channels
HAL_ASSERT(divider_integral >= 1);
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.rmt_sclk_conf, rmt_sclk_div_num, divider_integral - 1);
PCR.rmt_sclk_conf.rmt_sclk_div_a = divider_numerator;
PCR.rmt_sclk_conf.rmt_sclk_div_b = divider_denominator;
switch (src) {
case RMT_CLK_SRC_RC_FAST:
PCR.rmt_sclk_conf.rmt_sclk_sel = 1;
break;
case RMT_CLK_SRC_XTAL:
PCR.rmt_sclk_conf.rmt_sclk_sel = 0;
break;
default:
HAL_ASSERT(false);
break;
}
}
/**
* @brief Enable RMT peripheral source clock
*
* @param dev Peripheral instance address
* @param en True to enable, False to disable
*/
static inline void rmt_ll_enable_group_clock(rmt_dev_t *dev, bool en)
{
(void)dev;
PCR.rmt_sclk_conf.rmt_sclk_en = en;
}
////////////////////////////////////////TX Channel Specific/////////////////////////////////////////////////////////////
/**
* @brief Reset clock divider for TX channels by mask
*
* @param dev Peripheral instance address
* @param channel_mask Mask of TX channels
*/
static inline void rmt_ll_tx_reset_channels_clock_div(rmt_dev_t *dev, uint32_t channel_mask)
{
// write 1 to reset
dev->ref_cnt_rst.val |= channel_mask & 0x03;
}
/**
* @brief Set TX channel clock divider
*
* @param dev Peripheral instance address
* @param channel RMT TX channel number
* @param div Division value
*/
static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
{
HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range");
// limit the maximum divider to 256
if (div >= 256) {
div = 0; // 0 means 256 division
}
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chnconf0[channel], div_cnt_chn, div);
}
/**
* @brief Reset RMT reading pointer for TX channel
*
* @param dev Peripheral instance address
* @param channel RMT TX channel number
*/
__attribute__((always_inline))
static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->chnconf0[channel].mem_rd_rst_chn = 1;
dev->chnconf0[channel].mem_rd_rst_chn = 0;
dev->chnconf0[channel].apb_mem_rst_chn = 1;
dev->chnconf0[channel].apb_mem_rst_chn = 0;
}
/**
* @brief Start transmitting for TX channel
*
* @param dev Peripheral instance address
* @param channel RMT TX channel number
*/
__attribute__((always_inline))
static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel)
{
// update other configuration registers before start transmitting
dev->chnconf0[channel].conf_update_chn = 1;
dev->chnconf0[channel].tx_start_chn = 1;
}
/**
* @brief Stop transmitting for TX channel
*
* @param dev Peripheral instance address
* @param channel RMT TX channel number
*/
__attribute__((always_inline))
static inline void rmt_ll_tx_stop(rmt_dev_t *dev, uint32_t channel)
{
dev->chnconf0[channel].tx_stop_chn = 1;
// stop won't take place until configurations updated
dev->chnconf0[channel].conf_update_chn = 1;
}
/**
* @brief Set memory block number for TX channel
*
* @param dev Peripheral instance address
* @param channel RMT TX channel number
* @param block_num memory block number
*/
static inline void rmt_ll_tx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
{
dev->chnconf0[channel].mem_size_chn = block_num;
}
/**
* @brief Enable TX wrap
*
* @param dev Peripheral instance address
* @param channel RMT TX channel number
* @param enable True to enable, False to disable
*/
static inline void rmt_ll_tx_enable_wrap(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chnconf0[channel].mem_tx_wrap_en_chn = enable;
}
/**
* @brief Enable transmitting in a loop
*
* @param dev Peripheral instance address
* @param channel RMT TX channel number
* @param enable True to enable, False to disable
*/
__attribute__((always_inline))
static inline void rmt_ll_tx_enable_loop(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chnconf0[channel].tx_conti_mode_chn = enable;
}
/**
* @brief Set loop count for TX channel
*
* @param dev Peripheral instance address
* @param channel RMT TX channel number
* @param count TX loop count
*/
__attribute__((always_inline))
static inline void rmt_ll_tx_set_loop_count(rmt_dev_t *dev, uint32_t channel, uint32_t count)
{
HAL_ASSERT(count <= RMT_LL_MAX_LOOP_COUNT_PER_BATCH && "loop count out of range");
dev->chn_tx_lim[channel].tx_loop_num_chn = count;
}
/**
* @brief Reset loop count for TX channel
*
* @param dev Peripheral instance address
* @param channel RMT TX channel number
*/
__attribute__((always_inline))
static inline void rmt_ll_tx_reset_loop_count(rmt_dev_t *dev, uint32_t channel)
{
dev->chn_tx_lim[channel].loop_count_reset_chn = 1;
dev->chn_tx_lim[channel].loop_count_reset_chn = 0;
}
/**
* @brief Enable loop count for TX channel
*
* @param dev Peripheral instance address
* @param channel RMT TX channel number
* @param enable True to enable, False to disable
*/
__attribute__((always_inline))
static inline void rmt_ll_tx_enable_loop_count(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chn_tx_lim[channel].tx_loop_cnt_en_chn = enable;
}
/**
* @brief Enable loop stop at count value automatically
*
* @param dev Peripheral instance address
* @param channel RMT TX channel number
* @param enable True to enable, False to disable
*/
__attribute__((always_inline))
static inline void rmt_ll_tx_enable_loop_autostop(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chn_tx_lim[channel].loop_stop_en_chn = enable;
}
/**
* @brief Enable transmit multiple channels synchronously
*
* @param dev Peripheral instance address
* @param enable True to enable, False to disable
*/
static inline void rmt_ll_tx_enable_sync(rmt_dev_t *dev, bool enable)
{
dev->tx_sim.tx_sim_en = enable;
}
/**
* @brief Clear the TX channels synchronous group
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_tx_clear_sync_group(rmt_dev_t *dev)
{
dev->tx_sim.val &= ~(0x03);
}
/**
* @brief Add TX channels to the synchronous group
*
* @param dev Peripheral instance address
* @param channel_mask Mask of TX channels to be added to the synchronous group
*/
static inline void rmt_ll_tx_sync_group_add_channels(rmt_dev_t *dev, uint32_t channel_mask)
{
dev->tx_sim.val |= (channel_mask & 0x03);
}
/**
* @brief Remove TX channels from the synchronous group
*
* @param dev Peripheral instance address
* @param channel_mask Mask of TX channels to be removed from the synchronous group
*/
static inline void rmt_ll_tx_sync_group_remove_channels(rmt_dev_t *dev, uint32_t channel_mask)
{
dev->tx_sim.val &= ~channel_mask;
}
/**
* @brief Fix the output level when TX channel is in IDLE state
*
* @param dev Peripheral instance address
* @param channel RMT TX channel number
* @param level IDLE level (1 => high, 0 => low)
* @param enable True to fix the IDLE level, otherwise the IDLE level is determined by EOF encoder
*/
__attribute__((always_inline))
static inline void rmt_ll_tx_fix_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level, bool enable)
{
dev->chnconf0[channel].idle_out_en_chn = enable;
dev->chnconf0[channel].idle_out_lv_chn = level;
}
/**
* @brief Set the amount of RMT symbols that can trigger the limitation interrupt
*
* @param dev Peripheral instance address
* @param channel RMT TX channel number
* @param limit Specify the number of symbols
*/
static inline void rmt_ll_tx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
{
dev->chn_tx_lim[channel].tx_lim_chn = limit;
}
/**
* @brief Set high and low duration of carrier signal
*
* @param dev Peripheral instance address
* @param channel RMT TX channel number
* @param high_ticks Duration of high level
* @param low_ticks Duration of low level
*/
static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
{
HAL_ASSERT(high_ticks >= 1 && high_ticks <= 65536 && low_ticks >= 1 && low_ticks <= 65536 && "out of range high/low ticks");
// ticks=0 means 65536 in hardware
if (high_ticks >= 65536) {
high_ticks = 0;
}
if (low_ticks >= 65536) {
low_ticks = 0;
}
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chncarrier_duty[channel], carrier_high_chn, high_ticks);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chncarrier_duty[channel], carrier_low_chn, low_ticks);
}
/**
* @brief Enable modulating carrier signal to TX channel
*
* @param dev Peripheral instance address
* @param channel RMT TX channel number
* @param enable True to enable, False to disable
*/
static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chnconf0[channel].carrier_en_chn = enable;
}
/**
* @brief Set on high or low to modulate the carrier signal
*
* @param dev Peripheral instance address
* @param channel RMT TX channel number
* @param level Which level to modulate on (0=>low level, 1=>high level)
*/
static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{
dev->chnconf0[channel].carrier_out_lv_chn = level;
}
/**
* @brief Enable to always output carrier signal, regardless of a valid data transmission
*
* @param dev Peripheral instance address
* @param channel RMT TX channel number
* @param enable True to output carrier signal in all RMT state, False to only output carrier signal for effective data
*/
static inline void rmt_ll_tx_enable_carrier_always_on(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chnconf0[channel].carrier_eff_en_chn = !enable;
}
////////////////////////////////////////RX Channel Specific/////////////////////////////////////////////////////////////
/**
* @brief Reset clock divider for RX channels by mask
*
* @param dev Peripheral instance address
* @param channel_mask Mask of RX channels
*/
static inline void rmt_ll_rx_reset_channels_clock_div(rmt_dev_t *dev, uint32_t channel_mask)
{
// write 1 to reset
dev->ref_cnt_rst.val |= ((channel_mask & 0x03) << 2);
}
/**
* @brief Set RX channel clock divider
*
* @param dev Peripheral instance address
* @param channel RMT RX channel number
* @param div Division value
*/
static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
{
HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range");
// limit the maximum divider to 256
if (div >= 256) {
div = 0; // 0 means 256 division
}
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chmconf[channel].conf0, div_cnt_chm, div);
}
/**
* @brief Reset RMT writing pointer for RX channel
*
* @param dev Peripheral instance address
* @param channel RMT RX channel number
*/
__attribute__((always_inline))
static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->chmconf[channel].conf1.mem_wr_rst_chm = 1;
dev->chmconf[channel].conf1.mem_wr_rst_chm = 0;
dev->chmconf[channel].conf1.apb_mem_rst_chm = 1;
dev->chmconf[channel].conf1.apb_mem_rst_chm = 0;
}
/**
* @brief Enable receiving for RX channel
*
* @param dev Peripheral instance address
* @param channel RMT RX channel number
* @param enable True to enable, False to disable
*/
__attribute__((always_inline))
static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chmconf[channel].conf1.rx_en_chm = enable;
// rx won't be enabled until configurations updated
dev->chmconf[channel].conf1.conf_update_chm = 1;
}
/**
* @brief Set memory block number for RX channel
*
* @param dev Peripheral instance address
* @param channel RMT RX channel number
* @param block_num memory block number
*/
static inline void rmt_ll_rx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
{
dev->chmconf[channel].conf0.mem_size_chm = block_num;
}
/**
* @brief Set the time length for RX channel before going into IDLE state
*
* @param dev Peripheral instance address
* @param channel RMT RX channel number
* @param thres Time length threshold
*/
__attribute__((always_inline))
static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
{
dev->chmconf[channel].conf0.idle_thres_chm = thres;
}
/**
* @brief Set RMT memory owner for RX channel
*
* @param dev Peripheral instance address
* @param channel RMT RX channel number
* @param owner Memory owner
*/
__attribute__((always_inline))
static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, rmt_ll_mem_owner_t owner)
{
dev->chmconf[channel].conf1.mem_owner_chm = owner;
}
/**
* @brief Enable filter for RX channel
*
* @param dev Peripheral instance address
* @param channel RMT RX chanenl number
* @param enable True to enable, False to disable
*/
__attribute__((always_inline))
static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chmconf[channel].conf1.rx_filter_en_chm = enable;
}
/**
* @brief Set RX channel filter threshold (i.e. the maximum width of one pulse signal that would be treated as a noise)
*
* @param dev Peripheral instance address
* @param channel RMT RX channel number
* @param thres Filter threshold
*/
__attribute__((always_inline))
static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chmconf[channel].conf1, rx_filter_thres_chm, thres);
}
/**
* @brief Get RMT memory write cursor offset
*
* @param dev Peripheral instance address
* @param channel RMT RX channel number
* @return writer offset
*/
__attribute__((always_inline))
static inline uint32_t rmt_ll_rx_get_memory_writer_offset(rmt_dev_t *dev, uint32_t channel)
{
return dev->chmstatus[channel].mem_waddr_ex_chm - (channel + 2) * 48;
}
/**
* @brief Set the amount of RMT symbols that can trigger the limitation interrupt
*
* @param dev Peripheral instance address
* @param channel RMT RX channel number
* @param limit Specify the number of symbols
*/
static inline void rmt_ll_rx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
{
dev->chm_rx_lim[channel].rx_lim_chm = limit;
}
/**
* @brief Set high and low duration of carrier signal
*
* @param dev dev Peripheral instance address
* @param channel RMT TX channel number
* @param high_ticks Duration of high level
* @param low_ticks Duration of low level
*/
static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
{
HAL_ASSERT(high_ticks >= 1 && high_ticks <= 65536 && low_ticks >= 1 && low_ticks <= 65536 && "out of range high/low ticks");
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chm_rx_carrier_rm[channel], carrier_high_thres_chm, high_ticks - 1);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chm_rx_carrier_rm[channel], carrier_low_thres_chm, low_ticks - 1);
}
/**
* @brief Enable demodulating the carrier on RX channel
*
* @param dev Peripheral instance address
* @param channel RMT RX channel number
* @param enable True to enable, False to disable
*/
static inline void rmt_ll_rx_enable_carrier_demodulation(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chmconf[channel].conf0.carrier_en_chm = enable;
}
/**
* @brief Set on high or low to demodulate the carrier signal
*
* @param dev Peripheral instance address
* @param channel RMT RX channel number
* @param level Which level to demodulate (0=>low level, 1=>high level)
*/
static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{
dev->chmconf[channel].conf0.carrier_out_lv_chm = level;
}
/**
* @brief Enable RX wrap
*
* @param dev Peripheral instance address
* @param channel RMT RX channel number
* @param enable True to enable, False to disable
*/
static inline void rmt_ll_rx_enable_wrap(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chmconf[channel].conf1.mem_rx_wrap_en_chm = enable;
}
//////////////////////////////////////////Interrupt Specific////////////////////////////////////////////////////////////
/**
* @brief Enable RMT interrupt for specific event mask
*
* @param dev Peripheral instance address
* @param mask Event mask
* @param enable True to enable, False to disable
*/
__attribute__((always_inline))
static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool enable)
{
if (enable) {
dev->int_ena.val |= mask;
} else {
dev->int_ena.val &= ~mask;
}
}
/**
* @brief Clear RMT interrupt status by mask
*
* @param dev Peripheral instance address
* @param mask Interrupt status mask
*/
__attribute__((always_inline))
static inline void rmt_ll_clear_interrupt_status(rmt_dev_t *dev, uint32_t mask)
{
dev->int_clr.val = mask;
}
/**
* @brief Get interrupt status register address
*
* @param dev Peripheral instance address
* @return Register address
*/
static inline volatile void *rmt_ll_get_interrupt_status_reg(rmt_dev_t *dev)
{
return &dev->int_st;
}
/**
* @brief Get interrupt status for TX channel
*
* @param dev Peripheral instance address
* @param channel RMT TX channel number
* @return Interrupt status
*/
__attribute__((always_inline))
static inline uint32_t rmt_ll_tx_get_interrupt_status(rmt_dev_t *dev, uint32_t channel)
{
return dev->int_st.val & RMT_LL_EVENT_TX_MASK(channel);
}
/**
* @brief Get interrupt raw status for TX channel
*
* @param dev Peripheral instance address
* @param channel RMT TX channel number
* @return Interrupt raw status
*/
static inline uint32_t rmt_ll_tx_get_interrupt_status_raw(rmt_dev_t *dev, uint32_t channel)
{
return dev->int_raw.val & (RMT_LL_EVENT_TX_MASK(channel) | RMT_LL_EVENT_TX_ERROR(channel));
}
/**
* @brief Get interrupt raw status for RX channel
*
* @param dev Peripheral instance address
* @param channel RMT RX channel number
* @return Interrupt raw status
*/
static inline uint32_t rmt_ll_rx_get_interrupt_status_raw(rmt_dev_t *dev, uint32_t channel)
{
return dev->int_raw.val & (RMT_LL_EVENT_RX_MASK(channel) | RMT_LL_EVENT_RX_ERROR(channel));
}
/**
* @brief Get interrupt status for RX channel
*
* @param dev Peripheral instance address
* @param channel RMT RX channel number
* @return Interrupt status
*/
__attribute__((always_inline))
static inline uint32_t rmt_ll_rx_get_interrupt_status(rmt_dev_t *dev, uint32_t channel)
{
return dev->int_st.val & RMT_LL_EVENT_RX_MASK(channel);
}
//////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
/////////////////////////////The following functions are only used by the legacy driver/////////////////////////////////
/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
__attribute__((always_inline))
static inline uint32_t rmt_ll_tx_get_status_word(rmt_dev_t *dev, uint32_t channel)
{
return dev->chnstatus[channel].val;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_rx_get_status_word(rmt_dev_t *dev, uint32_t channel)
{
return dev->chmstatus[channel].val;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
{
uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->chnconf0[channel], div_cnt_chn);
return div == 0 ? 256 : div;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
{
uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->chmconf[channel].conf0, div_cnt_chm);
return div == 0 ? 256 : div;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel)
{
return dev->chmconf[channel].conf0.idle_thres_chm;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
{
return dev->chnconf0[channel].mem_size_chn;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
{
return dev->chmconf[channel].conf0.mem_size_chm;
}
__attribute__((always_inline))
static inline bool rmt_ll_tx_is_loop_enabled(rmt_dev_t *dev, uint32_t channel)
{
return dev->chnconf0[channel].tx_conti_mode_chn;
}
__attribute__((always_inline))
static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel)
{
rmt_clock_source_t clk_src = RMT_CLK_SRC_XTAL;
switch (PCR.rmt_sclk_conf.rmt_sclk_sel) {
case 1:
clk_src = RMT_CLK_SRC_RC_FAST;
break;
case 0:
clk_src = RMT_CLK_SRC_XTAL;
break;
}
return clk_src;
}
__attribute__((always_inline))
static inline bool rmt_ll_tx_is_idle_enabled(rmt_dev_t *dev, uint32_t channel)
{
return dev->chnconf0[channel].idle_out_en_chn;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel)
{
return dev->chnconf0[channel].idle_out_lv_chn;
}
static inline bool rmt_ll_is_mem_force_powered_down(rmt_dev_t *dev)
{
return PCR.rmt_mem_lp_ctrl.rmt_mem_lp_en;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel)
{
return dev->chmconf[channel].conf1.mem_owner_chm;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t channel)
{
return dev->chm_rx_lim[channel].rx_lim_chm;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev)
{
return dev->int_st.val & 0x03;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev)
{
return (dev->int_st.val >> 2) & 0x03;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev)
{
return (dev->int_st.val >> 4) & 0x03;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev)
{
return (dev->int_st.val >> 6) & 0x03;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev)
{
return (dev->int_st.val >> 8) & 0x03;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_get_rx_thres_interrupt_status(rmt_dev_t *dev)
{
return (dev->int_st.val >> 10) & 0x03;
}
__attribute__((always_inline))
static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev)
{
return (dev->int_st.val >> 12) & 0x03;
}
#ifdef __cplusplus
}
#endif

32
components/hal/esp32p4/include/hal/rmt_ll.h
View File

@@ -47,6 +47,10 @@ typedef enum {
RMT_LL_MEM_OWNER_HW = 1,
} rmt_ll_mem_owner_t;
typedef enum {
RMT_LL_MEM_LP_MODE_SHUT_DOWN,
} rmt_ll_mem_lp_mode_t;
/**
* @brief Enable the bus clock for RMT module
*
@@ -147,18 +151,6 @@ static inline void rmt_ll_enable_group_clock(rmt_dev_t *dev, bool en)
rmt_ll_enable_group_clock(__VA_ARGS__); \
} while(0)
/**
* @brief Enable clock gate for register and memory
*
* @param dev Peripheral instance address
* @param enable True to enable, False to disable
*/
static inline void rmt_ll_enable_periph_clock(rmt_dev_t *dev, bool enable)
{
dev->sys_conf.clk_en = enable; // register clock gating
dev->sys_conf.mem_clk_force_on = enable; // memory clock gating
}
/**
* @brief Force power on the RMT memory block, regardless of the outside PMU logic
*
@@ -171,11 +163,11 @@ static inline void rmt_ll_mem_force_power_on(rmt_dev_t *dev)
}
/**
* @brief Force power off the RMT memory block, regardless of the outside PMU logic
* @brief Force the RMT memory block into low power mode, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_force_power_off(rmt_dev_t *dev)
static inline void rmt_ll_mem_force_low_power(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pd = 1;
dev->sys_conf.mem_force_pu = 0;
@@ -192,6 +184,18 @@ static inline void rmt_ll_mem_power_by_pmu(rmt_dev_t *dev)
dev->sys_conf.mem_force_pu = 0;
}
/**
* @brief Set low power mode for RMT memory block
*
* @param dev Peripheral instance address
* @param mode RMT memory low power mode in low power stage
*/
static inline void rmt_ll_mem_set_low_power_mode(rmt_dev_t *dev, rmt_ll_mem_lp_mode_t mode)
{
(void)dev;
HAL_ASSERT(mode == RMT_LL_MEM_LP_MODE_SHUT_DOWN);
}
/**
* @brief Enable APB accessing RMT memory in nonfifo mode
*

32
components/hal/esp32s2/include/hal/rmt_ll.h
View File

@@ -42,6 +42,10 @@ typedef enum {
RMT_LL_MEM_OWNER_HW = 1,
} rmt_ll_mem_owner_t;
typedef enum {
RMT_LL_MEM_LP_MODE_SHUT_DOWN, // power down memory during low power stage
} rmt_ll_mem_lp_mode_t;
/**
* @brief Enable the bus clock for RMT module
*
@@ -83,18 +87,6 @@ static inline void rmt_ll_reset_register(int group_id)
rmt_ll_reset_register(__VA_ARGS__); \
} while(0)
/**
* @brief Enable clock gate for register and memory
*
* @param dev Peripheral instance address
* @param enable True to enable, False to disable
*/
static inline void rmt_ll_enable_periph_clock(rmt_dev_t *dev, bool enable)
{
dev->apb_conf.clk_en = enable; // register clock gating
dev->apb_conf.mem_clk_force_on = enable; // memory clock gating
}
/**
* @brief Force power on the RMT memory block, regardless of the outside PMU logic
*
@@ -107,11 +99,11 @@ static inline void rmt_ll_mem_force_power_on(rmt_dev_t *dev)
}
/**
* @brief Force power off the RMT memory block, regardless of the outside PMU logic
* @brief Force the RMT memory block into low power mode, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_force_power_off(rmt_dev_t *dev)
static inline void rmt_ll_mem_force_low_power(rmt_dev_t *dev)
{
dev->apb_conf.mem_force_pd = 1;
dev->apb_conf.mem_force_pu = 0;
@@ -128,6 +120,18 @@ static inline void rmt_ll_mem_power_by_pmu(rmt_dev_t *dev)
dev->apb_conf.mem_force_pu = 0;
}
/**
* @brief Set low power mode for RMT memory block
*
* @param dev Peripheral instance address
* @param mode RMT memory low power mode in low power stage
*/
static inline void rmt_ll_mem_set_low_power_mode(rmt_dev_t *dev, rmt_ll_mem_lp_mode_t mode)
{
(void)dev;
HAL_ASSERT(mode == RMT_LL_MEM_LP_MODE_SHUT_DOWN);
}
/**
* @brief Enable APB accessing RMT memory in nonfifo mode
*

32
components/hal/esp32s3/include/hal/rmt_ll.h
View File

@@ -47,6 +47,10 @@ typedef enum {
RMT_LL_MEM_OWNER_HW = 1,
} rmt_ll_mem_owner_t;
typedef enum {
RMT_LL_MEM_LP_MODE_SHUT_DOWN, // power down memory during low power stage
} rmt_ll_mem_lp_mode_t;
/**
* @brief Enable the bus clock for RMT module
*
@@ -85,18 +89,6 @@ static inline void rmt_ll_reset_register(int group_id)
rmt_ll_reset_register(__VA_ARGS__); \
} while(0)
/**
* @brief Enable clock gate for register and memory
*
* @param dev Peripheral instance address
* @param enable True to enable, False to disable
*/
static inline void rmt_ll_enable_periph_clock(rmt_dev_t *dev, bool enable)
{
dev->sys_conf.clk_en = enable; // register clock gating
dev->sys_conf.mem_clk_force_on = enable; // memory clock gating
}
/**
* @brief Force power on the RMT memory block, regardless of the outside PMU logic
*
@@ -109,11 +101,11 @@ static inline void rmt_ll_mem_force_power_on(rmt_dev_t *dev)
}
/**
* @brief Force power off the RMT memory block, regardless of the outside PMU logic
* @brief Force the RMT memory block into low power mode, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void rmt_ll_mem_force_power_off(rmt_dev_t *dev)
static inline void rmt_ll_mem_force_low_power(rmt_dev_t *dev)
{
dev->sys_conf.mem_force_pd = 1;
dev->sys_conf.mem_force_pu = 0;
@@ -130,6 +122,18 @@ static inline void rmt_ll_mem_power_by_pmu(rmt_dev_t *dev)
dev->sys_conf.mem_force_pu = 0;
}
/**
* @brief Set low power mode for RMT memory block
*
* @param dev Peripheral instance address
* @param mode RMT memory low power mode in low power stage
*/
static inline void rmt_ll_mem_set_low_power_mode(rmt_dev_t *dev, rmt_ll_mem_lp_mode_t mode)
{
(void)dev;
HAL_ASSERT(mode == RMT_LL_MEM_LP_MODE_SHUT_DOWN);
}
/**
* @brief Enable APB accessing RMT memory in nonfifo mode
*

5
components/hal/rmt_hal.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,6 +11,7 @@ void rmt_hal_init(rmt_hal_context_t *hal)
{
hal->regs = &RMT;
rmt_ll_mem_power_by_pmu(hal->regs);
rmt_ll_mem_set_low_power_mode(hal->regs, RMT_LL_MEM_LP_MODE_SHUT_DOWN); // power down memory during low power stage
rmt_ll_enable_mem_access_nonfifo(hal->regs, true); // APB access the RMTMEM in nonfifo mode
rmt_ll_enable_interrupt(hal->regs, UINT32_MAX, false); // disable all interrupt events
rmt_ll_clear_interrupt_status(hal->regs, UINT32_MAX); // clear all pending events
@@ -23,7 +24,7 @@ void rmt_hal_deinit(rmt_hal_context_t *hal)
{
rmt_ll_enable_interrupt(hal->regs, UINT32_MAX, false); // disable all interrupt events
rmt_ll_clear_interrupt_status(hal->regs, UINT32_MAX); // clear all pending events
rmt_ll_mem_force_power_off(hal->regs); // power off RMTMEM power domain forcefully
rmt_ll_mem_force_low_power(hal->regs); // power off RMTMEM power domain forcefully
hal->regs = NULL;
}

2
components/soc/esp32c5/include/soc/clk_tree_defs.h
View File

@@ -206,7 +206,7 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of RMT
*/
#define SOC_RMT_CLKS {/*SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST,*/ SOC_MOD_CLK_XTAL}
#define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
/**
* @brief Type of RMT clock source

64
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
View File

@@ -39,6 +39,10 @@ config SOC_I2S_SUPPORTED
bool
default y
config SOC_RMT_SUPPORTED
bool
default y
config SOC_I2C_SUPPORTED
bool
default y
@@ -423,6 +427,66 @@ config SOC_MMU_DI_VADDR_SHARED
bool
default y
config SOC_RMT_GROUPS
int
default 1
config SOC_RMT_TX_CANDIDATES_PER_GROUP
int
default 2
config SOC_RMT_RX_CANDIDATES_PER_GROUP
int
default 2
config SOC_RMT_CHANNELS_PER_GROUP
int
default 4
config SOC_RMT_MEM_WORDS_PER_CHANNEL
int
default 48
config SOC_RMT_SUPPORT_RX_PINGPONG
bool
default y
config SOC_RMT_SUPPORT_RX_DEMODULATION
bool
default y
config SOC_RMT_SUPPORT_TX_ASYNC_STOP
bool
default y
config SOC_RMT_SUPPORT_TX_LOOP_COUNT
bool
default y
config SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP
bool
default y
config SOC_RMT_SUPPORT_TX_SYNCHRO
bool
default y
config SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY
bool
default y
config SOC_RMT_SUPPORT_XTAL
bool
default y
config SOC_RMT_SUPPORT_RC_FAST
bool
default y
config SOC_RMT_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 3

24
components/soc/esp32h4/include/soc/clk_tree_defs.h
View File

@@ -199,6 +199,30 @@ typedef enum {
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Timer group clock source default choice is PLL_F48M */
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of RMT
*/
#define SOC_RMT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of RMT clock source
*/
typedef enum {
RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
} soc_periph_rmt_clk_src_t;
/**
* @brief Type of RMT clock source, reserved for the legacy RMT driver
*/
typedef enum {
RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< RMT source clock default choice is XTAL */
} soc_periph_rmt_clk_src_legacy_t;
///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
/**

31
components/soc/esp32h4/include/soc/soc_caps.h
View File

@@ -55,7 +55,7 @@
#define SOC_EFUSE_SUPPORTED 1 // TODO: [ESP32H4] IDF-12268
// #define SOC_RTC_MEM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12313
#define SOC_I2S_SUPPORTED 1
// #define SOC_RMT_SUPPORTED 1 // TODO: [ESP32H4] IDF-12402
#define SOC_RMT_SUPPORTED 1
// #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12348
// #define SOC_GPSPI_SUPPORTED 1 // TODO: [ESP32H4] IDF-12362 IDF-12364 IDF-12366
// #define SOC_LEDC_SUPPORTED 1 // TODO: [ESP32H4] IDF-12343
@@ -320,20 +320,21 @@
// #define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
/*--------------------------- RMT CAPS ---------------------------------------*/
// #define SOC_RMT_GROUPS 1U /*!< One RMT group */
// #define SOC_RMT_TX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Transmit */
// #define SOC_RMT_RX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Receive */
// #define SOC_RMT_CHANNELS_PER_GROUP 4 /*!< Total 4 channels */
// #define SOC_RMT_MEM_WORDS_PER_CHANNEL 48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
// #define SOC_RMT_SUPPORT_RX_PINGPONG 1 /*!< Support Ping-Pong mode on RX path */
// #define SOC_RMT_SUPPORT_RX_DEMODULATION 1 /*!< Support signal demodulation on RX path (i.e. remove carrier) */
// #define SOC_RMT_SUPPORT_TX_ASYNC_STOP 1 /*!< Support stop transmission asynchronously */
// #define SOC_RMT_SUPPORT_TX_LOOP_COUNT 1 /*!< Support transmit specified number of cycles in loop mode */
// #define SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1 /*!< Hardware support of auto-stop in loop mode */
// #define SOC_RMT_SUPPORT_TX_SYNCHRO 1 /*!< Support coordinate a group of TX channels to start simultaneously */
// #define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 /*!< TX carrier can be modulated to data phase only */
// #define SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */
// #define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST as the RMT clock source */
#define SOC_RMT_GROUPS 1U /*!< One RMT group */
#define SOC_RMT_TX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Transmit */
#define SOC_RMT_RX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Receive */
#define SOC_RMT_CHANNELS_PER_GROUP 4 /*!< Total 4 channels */
#define SOC_RMT_MEM_WORDS_PER_CHANNEL 48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
#define SOC_RMT_SUPPORT_RX_PINGPONG 1 /*!< Support Ping-Pong mode on RX path */
#define SOC_RMT_SUPPORT_RX_DEMODULATION 1 /*!< Support signal demodulation on RX path (i.e. remove carrier) */
#define SOC_RMT_SUPPORT_TX_ASYNC_STOP 1 /*!< Support stop transmission asynchronously */
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT 1 /*!< Support transmit specified number of cycles in loop mode */
#define SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1 /*!< Hardware support of auto-stop in loop mode */
#define SOC_RMT_SUPPORT_TX_SYNCHRO 1 /*!< Support coordinate a group of TX channels to start simultaneously */
#define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 /*!< TX carrier can be modulated to data phase only */
#define SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */
#define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST as the RMT clock source */
#define SOC_RMT_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up RMT registers before sleep */
/*-------------------------- MCPWM CAPS --------------------------------------*/
// #define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)

1
components/soc/esp32h4/ld/esp32h4.peripherals.ld
View File

@@ -24,6 +24,7 @@ PROVIDE ( LEDC = 0x6001B000 );
PROVIDE ( TWAI0 = 0x6001C000 );
PROVIDE ( USB_SERIAL_JTAG = 0x6001D000 );
PROVIDE ( RMT = 0x6001E000 );
PROVIDE ( RMTMEM = 0x6001E400 );
PROVIDE ( AHB_DMA = 0x6001F000 );
PROVIDE ( PAU = 0x60020000 );
PROVIDE ( SOC_ETM = 0x60021000 );

10
components/soc/esp32h4/register/soc/rmt_struct.h
View File

@@ -778,13 +778,13 @@ typedef union {
} rmt_date_reg_t;
typedef struct {
typedef struct rmt_dev_t {
volatile rmt_chndata_reg_t chndata[4];
volatile rmt_chnconf0_reg_t chnconf0[2];
volatile rmt_chmconf0_reg_t ch2conf0;
volatile rmt_chmconf1_reg_t ch2conf1;
volatile rmt_chmconf0_reg_t ch3conf0;
volatile rmt_chmconf1_reg_t ch3conf1;
volatile struct {
rmt_chmconf0_reg_t conf0;
rmt_chmconf1_reg_t conf1;
} chmconf[2];
volatile rmt_chnstatus_reg_t chnstatus[2];
volatile rmt_chmstatus_reg_t chmstatus[2];
volatile rmt_int_raw_reg_t int_raw;

67
components/soc/esp32h4/rmt_periph.c Normal file
View File

@@ -0,0 +1,67 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/rmt_periph.h"
#include "soc/rmt_reg.h"
#include "soc/gpio_sig_map.h"
const rmt_signal_conn_t rmt_periph_signals = {
.groups = {
[0] = {
.irq = ETS_RMT_INTR_SOURCE,
.channels = {
[0] = {
.tx_sig = RMT_SIG_OUT0_IDX,
.rx_sig = -1
},
[1] = {
.tx_sig = RMT_SIG_OUT1_IDX,
.rx_sig = -1
},
[2] = {
.tx_sig = -1,
.rx_sig = RMT_SIG_IN0_IDX
},
[3] = {
.tx_sig = -1,
.rx_sig = RMT_SIG_IN1_IDX
},
}
}
}
};
/**
* RMT Registers to be saved during sleep retention
* - Channel configuration registers, e.g.: RMT_CH0CONF0_REG, RMT_CH3CONF0_REG, RMT_CH3CONF1_REG, RMT_CH0_TX_LIM_REG, RMT_CH3_RX_LIM_REG
* - TX synchronization registers, e.g.: RMT_TX_SIM_REG
* - Interrupt enable registers, e.g.: RMT_INT_ENA_REG
* - Carrier duty registers, e.g.: RMT_CH0CARRIER_DUTY_REG, RMT_CH3_RX_CARRIER_RM_REG
* - Global configuration registers, e.g.: RMT_SYS_CONF_REG
*/
#define RMT_RETENTION_REGS_CNT 17
#define RMT_RETENTION_REGS_BASE (DR_REG_RMT_BASE + 0x10)
static const uint32_t rmt_regs_map[4] = {0xffd03f, 0x0, 0x0, 0x0};
static const regdma_entries_config_t rmt_regdma_entries[] = {
// backup stage: save configuration registers
// restore stage: restore the configuration registers
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_RMT_LINK(0x00),
RMT_RETENTION_REGS_BASE, RMT_RETENTION_REGS_BASE,
RMT_RETENTION_REGS_CNT, 0, 0,
rmt_regs_map[0], rmt_regs_map[1],
rmt_regs_map[2], rmt_regs_map[3]),
.owner = ENTRY(0) | ENTRY(2),
},
};
const rmt_reg_retention_info_t rmt_reg_retention_info[SOC_RMT_GROUPS] = {
[0] = {
.module = SLEEP_RETENTION_MODULE_RMT0,
.regdma_entry_array = rmt_regdma_entries,
.array_size = ARRAY_SIZE(rmt_regdma_entries)
},
};

4
examples/get-started/blink/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
# Blink Example

4
examples/peripherals/rmt/dshot_esc/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
# RMT Infinite Loop Transmit Example -- Dshot ESC (Electronic Speed Controller)
(See the README.md file in the upper level 'examples' directory for more information about examples.)

4
examples/peripherals/rmt/ir_nec_transceiver/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
# IR NEC Encoding and Decoding Example
(See the README.md file in the upper level 'examples' directory for more information about examples.)

4
examples/peripherals/rmt/led_strip/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
# RMT Transmit Example -- LED Strip
(See the README.md file in the upper level 'examples' directory for more information about examples.)

4
examples/peripherals/rmt/led_strip_simple_encoder/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
# RMT Transmit Example -- LED Strip
(See the README.md file in the upper level 'examples' directory for more information about examples.)

4
examples/peripherals/rmt/musical_buzzer/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
# RMT Transmit Loop Count Example -- Musical Buzzer

4
examples/peripherals/rmt/onewire/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
# Advanced RMT Transmit & Receive Example -- Simulate 1-Wire Bus

4
examples/peripherals/rmt/stepper_motor/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- |
# RMT Based Stepper Motor Smooth Controller